Methods and systems for transistors with combined source and well contacts

Abstract

This application relates to methods and systems for transistors having combined source and well contacts. A metal-oxide-semiconductor (MOS) transistor includes: a substrate including a well region; an insulating layer coupled to the substrate; and a source including a source region, a source contact passing through the insulating layer and the source region, and an ohmic contact disposed in the well region. The MOS transistor further includes: a gate region including a gate insulating layer and a gate contact; and a drain including a drain region and a drain contact passing through the insulating layer to the drain region. The MOS transistor may be an LDMOS transistor, such as an LNDMOS or LPDMOS transistor.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 736,524, filed on December 19, 2024, entitled “METHOD AND SYSTEM FOR TRANSISTOR WITH COMBINED SOURCE AND WELL CONTACT,” the disclosure of which is hereby incorporated in its entirety. Technical Field

[0003] This application relates to methods and systems for transistors having combined source and well contacts. Background Technology

[0004] Transistors are widely used in various electronic devices. Metal-oxide-semiconductor (MOS) transistors are commonly used. Laterally diffused MOS (LDMOS) transistors offer high power density and linearity, high breakdown voltage, and other advantages. Despite advancements in MOS and LDMOS transistors, there is still a need in this field for improved methods and systems related to transistor design and fabrication. Summary of the Invention

[0005] Embodiments of this disclosure relate to transistor architectures and fabrication processes. More specifically, embodiments of the invention provide methods and systems for LDMOS transistors having combined source and well connections. In a particular embodiment, the transistor array includes LDMOS transistors; compared to conventional transistors, the LDMOS transistors provide electrical connections to both the source and the body (i.e., the well), thereby reducing a specific on-resistance. Embodiments of the invention are applicable to both LDMOS transistors and MOS transistors.

[0006] As described more fully herein, embodiments of the present invention provide methods and structures for improving the performance of n-type LDMOS transistors using combined source-well connections achieved by vertical etching through several device layers and junctions.

[0007] According to an embodiment of the present invention, a metal-oxide-semiconductor (MOS) transistor is provided. The MOS transistor includes: a substrate having a well region; an insulating layer coupled to the substrate; and a source having a source region, a source contact passing through the insulating layer and the source region, and an ohmic contact disposed in the well region. The MOS transistor further includes: a gate region having a gate insulating layer and a gate contact; and a drain having a drain region and a drain contact passing through the insulating layer to the drain region.

[0008] According to one embodiment of the present invention, a transistor array is provided. The transistor array includes a plurality of metal-oxide-semiconductor (MOS) transistors forming the transistor array, each of the plurality of MOS transistors including: a source region having a source contact; a well or well contact adjacent to the source region; a gate region having a gate contact; and a drain region having a drain contact. The source contact electrically connects the source region and the well contact. The well contact may be disposed below the source region, and the source contact may extend through the source region to the well contact. Each of the plurality of MOS transistors may be an LDMOS transistor. In some embodiments, the transistor array includes a first metal interconnect electrically connecting each of the plurality of source contacts and a second metal interconnect electrically connecting each of the plurality of drain contacts.

[0009] According to a specific embodiment of the present invention, a method for fabricating an n-type laterally diffused metal-oxide-semiconductor (LNDMOS) device is provided. The method includes: providing a substrate including a well region, forming a gate structure on the substrate, and performing a first ion implantation process to form a source region and a drain region. The method further includes forming a silicide layer on the substrate and forming an insulating layer on the silicide layer. The method further includes etching a first opening through the insulating layer to the silicide layer, and extending the first opening to pass through the source region to the well region. The method further includes: performing a second ion implantation process to form an ohmic contact, forming a source contact in the first opening, performing a chemical mechanical polishing (CMP) process to planarize the source contact, etching a second opening through the insulating layer to the silicide layer, and forming a drain contact in the second opening.

[0010] According to another specific embodiment of the present invention, a method for fabricating a p-type laterally diffused metal-oxide-semiconductor (LPDMOS) device is provided. The method includes: providing a substrate (e.g., an n-type substrate) including an n-type well region; forming a gate structure on the substrate; and performing a first ion implantation process to form a source region and a drain region. The method further includes forming a silicide layer on the substrate and forming an insulating layer on the silicide layer. The method further includes: etching a first opening through the insulating layer to the silicide layer, and extending the first opening to pass through the source region into the n-type well region. The method further includes: performing a second ion implantation process to form an ohmic contact (e.g., an ohmic contact leading to the well); forming a source contact in the first opening; performing a chemical mechanical polishing (CMP) process to planarize the source contact; etching a second opening through the insulating layer to the silicide layer; and forming a drain contact in the second opening.

[0011] In some embodiments, fabricating the LPDMOS device may include: etching a third opening through the insulating layer to the silicide layer and forming a second source contact in the third opening. Etching the second opening and the third opening may be performed simultaneously. Forming the source contact in the first opening may be performed before forming the second source contact. In some embodiments, forming the source contact includes depositing a contact liner in the first opening and depositing a contact plug on the contact liner to fill the first opening. Extending the first opening may form a tapered region in the insulating layer. Performing the CMP process may remove the tapered region. Performing the CMP process may similarly remove the upper portion of the insulating layer. The first opening may extend through the silicide layer and lead to the well region. Forming the drain contact may be performed after forming the source contact.

[0012] The present invention achieves numerous benefits compared to conventional techniques. For example, embodiments of the invention provide direct contacts to the body (i.e., the well), which reduces the specific on-resistance (RSP) of the device by reducing the size of the source / well junction region. Additionally, some embodiments reduce the polysilicon-to-polysilicon spacing because they utilize photolithography processes with reduced layer alignment tolerance and improved morphology. Furthermore, compared to conventional methods where only a fraction of the source interconnect is incorporated into the well interconnect, embodiments of the present invention improve LDMOS robustness and safe operating area (SOA) by integrating the well interconnect into each source interconnect in some implementations. Moreover, the fabrication methods discussed herein improve and simplify the photolithography process by eliminating the use of resist pillars and cracks, thereby enabling the source region to be fully n+ without the challenges of conventional photolithography caused by resist pillars and cracks. Using these photolithography processes reduces the process complexity, variability, concerns, risks, and concurrency issues associated with conventional processes. These and other embodiments of the invention, along with their many advantages and features, are described in more detail below in conjunction with the accompanying drawings. Attached Figure Description

[0013] Figure 1A This is a simplified cross-sectional view of an LDMOS transistor with combined source and well contacts according to an embodiment of the present invention.

[0014] Figure 1B This is a simplified cross-sectional view of an LDMOS transistor with a second source contact according to an embodiment of the present invention.

[0015] Figure 2A This is a simplified plan view of an LDMOS transistor array having a source region including source contacts leading to the source and the well, according to an embodiment of the present invention.

[0016] Figure 2B It is a product of an embodiment of the present invention. Figure 2A The diagram illustrates a simplified planar view of the LDMOS transistor array with the source contact and the second source contact.

[0017] Figure 2C This is a simplified plan view of an LDMOS transistor array having a source region including a shared source contact leading to the source and the well, according to an embodiment of the present invention.

[0018] Figure 3 This is a simplified flowchart of a method for fabricating an n-type LDMOS transistor according to an embodiment of the present invention, wherein the n-type LDMOS transistor has a source region including source contacts leading to the source and the well.

[0019] Figures 4A to 15This is a simplified cross-sectional view illustrating the various stages of fabricating an LDMOS transistor according to an embodiment of the present invention, the LDMOS transistor having a source region including source contacts leading to the source and the well.

[0020] Figure 16A This is a simplified cross-sectional view illustrating the source contact and gate region of an n-type LDMOS transistor according to an embodiment of the present invention.

[0021] Figure 16B This is a simplified cross-sectional view illustrating the source contact and gate region of a p-type LDMOS transistor according to an embodiment of the present invention.

[0022] In the drawings and detailed description, identical or similar components are designated by the same reference numerals. Several embodiments of this disclosure will be readily understood from the following detailed description with reference to the accompanying drawings. Detailed Implementation

[0023] Embodiments of this disclosure relate to transistor architectures and fabrication processes. More specifically, embodiments of the invention provide methods and systems for LDMOS transistors having combined source and well connections. In a particular embodiment, the transistor array includes LDMOS transistors; compared to conventional transistors, the LDMOS transistors provide electrical connections to both the source and the body (i.e., the well), thereby reducing a specific on-resistance. Embodiments of the invention are applicable to both LDMOS transistors and MOS transistors.

[0024] Figure 1A This is a simplified cross-sectional view of an LDMOS transistor 100 with combined source and well contacts according to an embodiment of the present invention. As discussed more fully below, embodiments of the present invention provide a transistor architecture or structure with different tungsten plug connectors on the source and drain. The drain plug connector may extend to the silicide layer. The source plug connector extends through the source junction doping and into the transistor well region to a depth deeper than the silicide surface, thereby forming a combined source and well connection.

[0025] refer to Figure 1AThe source region 104 and drain region 106 are supported by a substrate 102 (e.g., a silicon substrate). The substrate 102 includes a well region 103, for example, a p-doped layer formed by ion implantation and annealing processes. In n-type LDMOS devices, although other formation methods are included within the scope of this invention, the source region 104 and drain region 106 are typically formed using ion implantation processes for forming n+ regions. A silicide layer 108 is present in contact with the source region 104 and drain region 106. The silicide layer 108 may be a cobalt silicide layer, a titanium silicide layer, etc. A gate region 130 is formed between the source region 104 and drain region 106 and includes a lightly doped drain-source (LDD) 134 and a gate oxide insulating layer 138 extending below the gate contact 132.

[0026] Source contact 120, comprising source contact liner 122 and source contact plug 124, is electrically separated from drain contact 140, comprising drain contact liner 142 and drain contact plug 144, by insulating layer 110. Source contact 120 extends through source region 104 (i.e., to a location below source region 104) into well region 103 and is connected to substrate 102 via ohmic contact 148 (also referred to as well contact). Thus, source contact 120 provides a combined source-well connection because it electrically connects both source region 104 and well region 103 via ohmic contact 148. Source region 104 may be positioned at a first predetermined distance 147 from substrate 102, while ohmic contact 148 is positioned at a second predetermined distance 149 from said substrate, less than the first predetermined distance 147. It should be noted that this contact extends through the source implant and stops in the trap before reaching the substrate.

[0027] It should be noted that the n-type LDMOS device illustrated in Figure 1 differs from conventional devices because the source contacts 120 exist in the same plane as the source regions 104, i.e., between the portions of the source regions 104 as measured in a horizontal plane. In conventional devices, the p+ implant region would exist between the portions of the source regions 104 and be electrically contacted with the well region 103 via ohmic contacts 148. In contrast, embodiments of the present invention utilize source contacts extending through the source regions 104 to contact the well region 103 via ohmic contacts 148, thereby providing metal rather than semiconductor material between the portions of the source regions. Thus, in the substrate plane 105 (i.e., the plane parallel to the processed surface of the substrate), the source regions comprise both semiconductor material (i.e., source regions 104) and metal (the portions of source contacts 120 present in the substrate plane 105), because the source contacts 120 extend through the source regions 104 into the well region 103.

[0028] Refer again Figure 1AThe drain contact 140 passes through the insulating layer 110 and the drain contact liner 142 is therefore in electrical contact with the silicide layer 108 and the drain region 106. Thus, the drain contact 140, including the drain contact plug 144 and the drain contact liner 142, provides electrical connectivity to the drain region 106.

[0029] The embodiment contrasts with a fabrication process involving defining small regions for the p+ source / drain implant (which requires sufficient spacing between polysilicon lines to define resist pillars to shield the n+ source / drain implant where p+ contacts leading to the trap (i.e., the body) will be located, and then a crack for the p+ source / drain implant is defined in the n+ photoresist).

[0030] Although embodiments of the present invention are described with respect to n-type LDMOS transistors, this is not required and includes other transistor architectures, including p-type LDMOS transistors and MOS transistors (e.g., n-type MOS (NMOS) and p-type MOS (PMOS)) transistors).

[0031] Figure 1B This is a simplified cross-sectional view of an LDMOS transistor with a second source contact according to an embodiment of the present invention. Figure 1B The LDMOS transistor 150 illustrated in the figure is... Figure 1A The LDMOS transistor 100 illustrated herein shares common components, and the description provided for LDMOS transistor 100 applies, where appropriate, to LDMOS transistor 150. Reference Figure 1B The second source contact 160, including the second source contact liner 162 and the second source contact plug 164, is electrically separated from the drain contact 140, including the drain contact liner 142 and the drain contact plug 144, by the insulating layer 110. Figure 1A Compared to the source contact 120 illustrated in the figure, the second source contact 160 passes through the insulating layer 110 like the drain contact 140, but terminates at the silicide layer 108, where the second source contact liner 162 is thus in electrical contact with the silicide layer 108 and the source region 104.

[0032] Such as about Figure 2B To describe more fully, embodiments of the present invention can be utilized Figure 1A The source contact 120 and the diagram in the figure are illustrated. Figure 1B The second source contact 160 is illustrated in the diagram. In some architectures, all source contacts are implemented using source contact 120, while in other architectures, one-third of the source contacts are implemented using source contact 120 and the remaining source contacts are implemented using the second source contact 160.

[0033] Figure 2AThis is a simplified plan view of an LDMOS transistor array having a source region including source contacts leading to the source and the well, according to an embodiment of the present invention. Figure 2A Therefore, the diagram illustrates the surface areas of the source contact 210 and the drain contact 212, each of which is disposed within an insulating layer (such as...). Figure 1A and 1B The image shown is 110. Figure 2A In this example, the LDMOS transistor array 200 contains five transistors, but this is merely exemplary, and the LDMOS transistor array 200 may contain a larger number of LDMOS transistors. As an example, the source contact 210 and drain contact 212 of the transistor are illustrated. Therefore, the LDMOS transistor array 200 includes a source column 202 and a set of drain columns 204 separated by polysilicon lines 206, wherein the polysilicon lines 206 form the polysilicon layer of the LDMOS transistor.

[0034] exist Figure 2A In the LDMOS transistor array 200 illustrated in the diagram, each of the source contacts of the LDMOS transistors uses... Figure 1A This is implemented using the source contact 120 illustrated in the diagram. Therefore, each source contact extends through the source region and into the well region 103, thereby providing a combined source-well connection that electrically connects both the source and well regions of the transistor. Therefore, Figure 2A The cross section A-A' in the middle corresponds to Figure 1A The cross-section is illustrated in the diagram.

[0035] Figure 2A The diagram illustrates multiple metal interconnect layers that electrically connect the contacts. Drain metal interconnect 208 provides electrical connectivity between drain contacts 212. Source metal interconnect 209 provides electrical connectivity between source contacts 210. Because each source contact 210 is electrically connected to the well region, the device efficiency is improved compared to designs where the source contacts are electrically connected via metal interconnects.

[0036] Figure 2B It is a product of an embodiment of the present invention. Figure 2A The diagram illustrates a simplified planar view of the LDMOS transistor array with the source contact and the second source contact. Figure 2B The LDMOS transistor array 220 illustrated in the figure is... Figure 2A The LDMOS transistor array 200 illustrated herein shares common components, and the description provided for the LDMOS transistor array 200 is applicable to the LDMOS transistor array 220 where appropriate.

[0037] refer to Figure 2BA subgroup of transistors constituting the LDMOS transistor array 220 provides source contacts that electrically connect the doped source region to the well region via source contacts that pass through the insulating layer and through the doped source region to the well region. This is consistent with... Figure 2A In contrast to the LDMOS transistor array 200 illustrated in the figure, in which all source contacts are electrically connected to the well region via the doped source region.

[0038] like Figure 2B The diagram illustrates that, every other transistor, using the implementation as Figure 1B The second source contact 222 of the second source contact 160 illustrated in the figure is consistent with the implementation of... Figure 1A The transistors of source contact 120 and source contact 210 are alternately illustrated in the diagram. Therefore, an array of transistors is provided that alternately uses source contact 210 and second source contact 222. Figure 2B The cross section A-A' in the middle corresponds to Figure 1A The cross-section illustrated in the figure, and Figure 2B The cross section B-B' in the middle corresponds to Figure 1B The cross-section is illustrated in the diagram.

[0039] In other embodiments, the layout of the source contact 210 and the second source contact 222 is altered, wherein several contacts of each type are utilized in a manner adjacent to each other. Therefore, Figure 2B The layout illustrated herein is merely exemplary, and embodiments of the invention are not limited to this specific layout. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0040] Therefore, embodiments of the present invention provide that some of the source contacts (e.g., source contact 210) are electrically connected to the well region via the doped source region, while other source contacts (e.g., second source contact 222) only contact the LDMOS transistor array via the doped source region.

[0041] Figure 2C This is a simplified plan view of an LDMOS transistor array having a source region including a shared source contact leading to the source and the well, according to an embodiment of the present invention. Figure 2C The LDMOS transistor array 240 illustrated in the figure and Figure 2A The LDMOS transistor array 200 illustrated herein shares common components, and the description provided for LDMOS transistor array 200 applies where appropriate to LDMOS transistor array 240. Figure 2C In the embodiment illustrated in the figure, the source contact 242 is implemented as a crack, i.e., a rectangular feature in the plan view, rather than as shown in the figure. Figure 2A and 2BThe diagram illustrates a hole. The crack diagram illustrates that the surface area of ​​the source contact 242 can have a larger surface area than the surface area of ​​the drain contact 212. The number of drain contacts corresponding to each of the source contacts 242 can be varied as appropriate for a particular application. Therefore, embodiments of the invention utilize rectangular and square features, as well as features in the form of cracks and holes. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0042] Figure 3 This is a simplified flowchart of a method for fabricating an n-type LDMOS transistor according to an embodiment of the present invention, wherein the n-type LDMOS transistor has a source region including source contacts leading to the source and the well.

[0043] In short, and as about Figure 3 The described process involves two separate masking, etching, and filling processes for contact etching. The drain contact etching process uses a plasma-oxide etching tool that stops etching on the silicon / silicide layer. The source contact etching process uses a plasma-oxide etching tool that stops etching on the silicon / silicide layer. The wafer is then transferred to a transformer-coupled plasma (TCP) etching tool, which uses chlorine-based chemicals (e.g., Cl2 / BCl3) to etch through the silicide layer and the p-type body region beneath the n+ source / drain regions. The same mask can be used during both the plasma-oxide etching tool and the TCP etching tool.

[0044] The wafer is then implanted with a low-energy, high-dose p+ implant to reduce contact resistance, followed by filling with titanium and titanium nitride (Ti / TiN) contact liners and tungsten to form ohmic contacts. A photoresist stripping process is used before or after the implantation process. As described more fully below, the tungsten polishing time is extended to remove surface oxide tapering caused by the additional silicon etching process. The initial dielectric thickness is increased to account for tungsten polishing removal. The wafer is then processed using a standard contact etching process, photoresist stripping is performed, and then filled with Ti / TiN contact liners and tungsten to form ohmic contacts. Note that drain contacts can be formed before or after source contacts. Figure 3 In the illustrated embodiments, although not required by the embodiments of the present invention, the drain contact is formed after the source contact.

[0045] refer to Figure 3 Method 300 includes providing a substrate (302) and forming a gate structure (304) including spacers and LDD regions. The gate structure can be formed by performing a hot wet or dry oxidation process. Polysilicon is deposited, patterned, and etched to perform low-doped (LDD) implantation, and nitride or oxide spacers are formed on the sidewalls of the polysilicon.

[0046] Method 300 further includes performing a first ion implantation process to form source and drain regions (306). The same n+ implant can be used to form the source and drain regions. Method 300 further includes forming a silicide layer (308) and forming an insulating layer (310) on the silicide layer. The silicide layer can be formed by the following steps: depositing a silicide metal on a clean surface, heating the wafer using a rapid thermal processing (RTP) process to form a silicide on the exposed silicon surface, selectively removing unreacted metal in a wet etching process, and then heating the wafer again to complete the formation of the silicide. The silicide layer may include cobalt, platinum, titanium, or other materials used in semiconductor manufacturing, such as silicide metals.

[0047] Method 300 further includes etching a first opening (312) through the insulating layer to the silicide layer, extending the first opening (314), and performing a second ion implantation process to form an ohmic contact (316) leading to the well region. Extending the first opening (314) may include using an additional etching process to extend the first opening through the silicide layer and the source region into the well. Extending the first opening (314) may form a tapered region in the insulating layer as a photoresist mask is etched. (See below for more details.) Figure 12 As discussed, this tapered region can be removed during a subsequent planarization process after removing the upper portion of the insulating layer. The first opening extends through the silicide layer into the substrate.

[0048] In some embodiments, a second ion implantation process is performed at high doses and low energy to produce a suitable p-type doping density in the trap region.

[0049] Additionally, method 300 includes forming a source contact (318) in a first opening, performing a chemical mechanical polishing (CMP) process to planarize the source contact and remove the tapered portion (320), etching a second opening (322) through the insulating layer to the silicide layer, and forming a drain contact (324) in the second opening. The drain contact may be formed before or after the source contact. The source contact may include a contact liner and a contact plug, for example, a Ti / TiN contact liner deposited in the first opening, followed by a tungsten plug deposited on the contact liner to fill the first opening.

[0050] In some embodiments, method 300 further includes etching a second opening through the insulating layer to the silicide layer and forming a second source contact in the second opening. Etching the second opening (i.e., for forming the second source contact) and further etching the second opening (i.e., for forming the drain contact) can be performed simultaneously, which may also be referred to as etching a third opening. Therefore, as... Figure 1B and 2BThe illustration shows that a transistor array may include two types of transistors: a combined source-well connector that uses both the source and well regions of the transistors in the array to electrically connect them, and a standard source contact connected to the silicide layer and the source region. Depending on the implementation, the source contact may be formed before the second source contact is formed, or the second source contact may be formed before the source contact is formed.

[0051] This embodiment contrasts with conventional fabrication processes that utilize two photolithography steps prior to the implantation process to mask the n+ source / drain (e.g., using photoresist pillars) and separately form the p+ source (e.g., using crack openings in the photoresist layer). Those skilled in the art will appreciate that variable height topography and photoresist dimensions present challenges during fabrication. Therefore, Figure 2A The polysilicon line 206 illustrated in the diagram is typically spaced significantly apart from the source array 202 and the drain array 204. As discussed more fully below, embodiments of the invention reduce the complexity associated with conventional designs and the wide spacing between polysilicon lines by forming deep contacts that extend through the n+ source region to the p+ well and make electrical contact with both the n+ source region and the p+ well.

[0052] It should be understood that Figure 3 The specific steps illustrated herein provide a specific method for fabricating an n-type LDMOS transistor according to an embodiment of the present invention, the n-type LDMOS transistor having a source region including source contacts leading to a source and a well. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments of this disclosure may perform the steps outlined above in a different order. Furthermore, Figure 3 The individual steps illustrated herein may contain multiple sub-steps that can be executed in various sequences appropriate for each individual step. Furthermore, depending on the specific application, additional steps may be added or removed. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0053] Figures 4A to 15 This is a simplified cross-sectional view illustrating the various stages of fabricating an LDMOS transistor according to an embodiment of the present invention, the LDMOS transistor having a source region including source contacts leading to the source and the well.

[0054] Figure 4A This is a simplified cross-sectional view of an LDMOS transistor at a first fabrication stage according to an embodiment of the present invention. As shown in FIG. 4, a substrate 402 (e.g., a silicon substrate) is provided. The substrate 402 includes a well 403, for example, a p-doped layer formed by an ion implantation and annealing process.

[0055] Figure 4B This is a simplified cross-sectional view of an LDMOS transistor at the second fabrication stage according to an embodiment of the present invention. Figure 4B As shown, a gate structure 404, also known as a gate region, is formed on the substrate 402 and the well 403.

[0056] Figure 5 This is a simplified cross-sectional view of an LDMOS transistor at the third fabrication stage according to an embodiment of the present invention. Figure 5 The diagram illustrates how the source region 502 (which can also be called the doped source region) and the drain region 504 (which can also be called the doped drain region) are formed using an ion implantation process.

[0057] Figure 6 This is a simplified cross-sectional view of an LDMOS transistor at the fourth fabrication stage according to an embodiment of the present invention. Figure 6 As shown, substrate 402 is processed to form a silicide layer 610 (also known as an insulating layer). The silicide layer 610 may be a cobalt silicide layer, a titanium silicide layer, etc.

[0058] Figure 7 This is a simplified cross-sectional view of an LDMOS transistor at the fifth fabrication stage according to an embodiment of the present invention. Figure 7 The diagram illustrates the formation of an insulating layer 710. The insulating layer 710 may be a silicon dioxide layer approximately 1 μm thick, formed using plasma-enhanced chemical vapor deposition (PECVD) and oxide CMP processes. In other embodiments, other insulating materials, including Si, may be used. x N y SiO x N y Wait. The initial thickness of the insulating layer 710 is greater than the following text regarding... Figure 12 A more comprehensive description of the final thickness, Figure 12 The process of removing the upper portion of the insulating layer 710 during the planarization process is described.

[0059] Figure 8A This is a simplified cross-sectional view of an LDMOS transistor at the sixth fabrication stage according to an embodiment of the present invention. (Reference) Figure 8A A photoresist layer is deposited and patterned to form a photoresist mask 802. During subsequent processing, an opening 803 in the photoresist mask 802 will be used to form a first opening suitable for use during source contact formation.

[0060] Figure 8B This is a simplified cross-sectional view of an LDMOS transistor at the seventh fabrication stage according to an embodiment of the present invention. Figure 8BThe illustration shows a first opening 804 formed through the insulating layer 710 to the silicide layer 610 using a first etching process, for example, implemented using a plasma oxide etching tool. In some embodiments, the silicide layer 610 acts as an etching stop during the etching process, while in other embodiments, etching is terminated at the silicide layer 610 using timing of the etching or other suitable process monitoring techniques. Many variations, modifications, and alternatives will be recognized by those skilled in the art.

[0061] Figure 9A This is a simplified cross-sectional view of an LDMOS transistor at the eighth fabrication stage according to an embodiment of the present invention. Figure 9A In the cross-sectional view illustrated, the wafer is transferred to a TCP etching tool and a second etching process is used to etch through the silicide layer 610 and the source region 502 into the substrate 402. During this second etching process, which extends the first opening 902, the photoresist is consumed and etched, resulting in a tapered profile 904 forming near the top of the insulating layer 710 as the photoresist is etched. As discussed more fully below, the tapered profile will result in the formation of a metal edge disposed within the tapered profile during metal (tungsten) deposition. To remove this tapered metal profile, additional polishing is performed and as... Figure 7 The thickness of the deposited insulating layer, as illustrated in the diagram, is thus reduced. It should be noted that while the operation of extending the first opening through the silicide layer 610 into the underlying silicon is deep enough to allow etching through the n+ source region and into the well region, it does not result in extension into the well region (i.e., the p-type well) or below the body region.

[0062] Figure 9B This is a simplified cross-sectional view of an LDMOS transistor at the ninth fabrication stage according to an embodiment of the present invention, illustrated herein. Figure 8A The removal of photoresist mask 802 is illustrated in the figure.

[0063] Figure 10 This is a simplified cross-sectional view of an LDMOS transistor at the tenth fabrication stage according to an embodiment of the present invention. Figure 10 In the process illustrated herein, a second ion implantation process is used to form an ohmic contact 1002 that leads to a well region 403 in the substrate 402. In some embodiments, the second ion implantation process is performed with sufficiently low energy to avoid penetrating the dielectric film, but with a sufficiently high dose to form a low-resistance contact suitable for leading to the ohmic contact in the well region. According to some embodiments, regarding Figure 9B The ninth production stage discussed can be found in the section on Figure 10 This occurs after the tenth production stage discussed.

[0064] A high-dose implant provides an ohmic contact leading to the trap, as described more fully herein. In some embodiments, a low-energy, high-dose p+ implant is used, and the silicide layer 610 is used as an implant mask. In these embodiments, the photoresist mask 802 used during the etching process to further shape the first opening 902 is removed, for example, after the etching process using a tool comprising both an etching chamber and a photoresist stripping chamber. In these embodiments, the low-energy implant allows the use of the silicide layer 610 as an implant mask and the stripping of the photoresist prior to the ion implantation process.

[0065] In other embodiments, the photoresist is stripped off after the ion implantation process. For example, if a higher-energy implantation process is used, then... Figure 9A The etching process shown in the document and Figure 10 The ion implantation process shown in the diagram involves the presence of a photoresist mask 802 during both stages. The photoresist mask 802 is then stripped after the ion implantation process. Those skilled in the art will recognize numerous variations, modifications, and alternatives.

[0066] Figure 11A This is a simplified cross-sectional view of an LDMOS transistor at the eleventh fabrication stage according to an embodiment of the present invention. Figure 11A In the process, a deposition process is used to form a source contact liner 1110 in the first opening 902 and cover the wafer. The source contact liner 1110 is related to... Figure 11B and 12 The source contact plugs discussed are formed together. Figure 1A The source contact 120 is illustrated in the diagram.

[0067] Figure 11B This is a simplified cross-sectional view of an LDMOS transistor at the twelfth fabrication stage according to an embodiment of the present invention. Figure 11B The diagram illustrates that tungsten deposition not only forms the source contact plug 1112, but also deposits a tungsten layer 1114 covering the wafer. To remove the tungsten layer 1114 and planarize the wafer, methods such as those described above are employed. Figure 12 The CMP process discussed. It should be noted that embodiments of the invention utilize a source contact plug 1112 passing through the source region 502, thereby providing metallic material between the portions of the source region 502. (See also: Regarding...) Figure 1A As discussed, in conventional devices, the p+ implant region would exist between the portions of the source region 502 and be in electrical contact with the well region 403. In contrast, embodiments of the present invention utilize source contacts comprising a source contact liner 1110 extending through the source region 502 and a source contact plug 1112 to contact the well region 403, thereby providing metal between the portions of the source region.

[0068] Figure 12 This is a simplified cross-sectional view of an LDMOS transistor at the thirteenth fabrication stage according to an embodiment of the present invention. (Reference) Figure 12 CMP process removal Figure 11B The tungsten layer 1114 and a portion of the deposited insulating layer illustrated herein are used to create a polished insulating layer 1212 with a polished surface 1214 and a planarized source contact 1216. (See also: Regarding...) Figure 7 As mentioned, Figure 7 The thickness of the silicide layer 610 illustrated in the diagram is reduced during the CMP process, which removes the edges of the tungsten to produce a polished insulating layer 1212. Therefore, in Figure 12 Following the CMP process shown, a substrate with planarized source contacts 1216 is provided.

[0069] Figure 13A This is a simplified cross-sectional view of the LDMOS transistor at the fourteenth manufacturing stage. Figure 13B This is a simplified cross-sectional view of the LDMOS transistor at the fifteenth manufacturing stage, and Figure 13C This is a simplified cross-sectional view of an LDMOS transistor at the sixteenth fabrication stage according to an embodiment of the present invention. Figure 13A As shown, a photoresist layer is deposited and patterned to form the drain contact mask 1302. Using, as... Figure 13B The drain contact mask 1302 shown in the figure is etched through a polished insulating layer 1212 to a silicide layer 610 that can act as an etch stop, creating a second opening 1304 (which may be referred to as a drain opening). Figure 13C As shown, the drain contact mask 1302 can be removed after etching the second opening 1304.

[0070] Figure 14A This is a simplified cross-sectional view of the LDMOS transistor at the seventeenth manufacturing stage, and Figure 14B This is a simplified cross-sectional view of an LDMOS transistor at the eighteenth fabrication stage according to an embodiment of the present invention. Figures 14A to 14B The process flow illustrated in the diagram is used to form the drain contact. (Reference) Figure 14A Ti / TiN liner 1410 is deposited in the second opening 1304. Figure 14B The illustration shows the deposition of a tungsten plug 1412 on a Ti / TiN liner 1410 to fill the second opening 1304. During the deposition of the tungsten plug 1412, a tungsten layer 1414 can be formed and subsequently removed using a CMP process.

[0071] Figure 15 This is a simplified cross-sectional view of an LDMOS transistor at the nineteenth fabrication stage according to an embodiment of the present invention. (Reference) Figure 15The tungsten layer 1414 formed on the Ti / TiN liner and the Ti / TiN liner 1410 formed on the photoresist are removed using a CMP process to form the drain contact 1510.

[0072] In some embodiments, Figures 8A to 12 The second opening 1304 and the drain contact 1510 are formed prior to the fabrication steps shown, thereby forming the drain contact 1510 before forming the source contact 1210. In other embodiments, the process flow shown above is used to form the source contact 1210 before the drain contact 1510. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0073] Figure 16A This is a simplified cross-sectional view illustrating the source contact and gate region of an n-type LDMOS transistor according to an embodiment of the present invention. Figure 16A The diagram illustrates that the n-type LDMOS transistor 1600 includes a source region 502 and a well region 403 electrically connected by a source contact 1210 passing through an insulating layer 1212 and a silicide layer 610. The substrate 402 and the gate structure 404 are also illustrated.

[0074] exist Figure 16A In the n-type LDMOS transistor illustrated in the figure, the well region 403 is p-type, the ohmic contact 1002 is p-type, the source region 502 is heavily doped n-type (i.e., n+), and the lightly doped drain 1602 is n-type.

[0075] Figure 16B This is a simplified cross-sectional view illustrating the source contact and gate region of a p-type LDMOS transistor according to an embodiment of the present invention. Figure 16B The diagram illustrates that the p-type LDMOS transistor 1650 includes a source region 1616 and a well region 1613 electrically connected by a source contact 1210 passing through an insulating layer 1212 and a silicide layer 610. The substrate 1612 and gate structure 404 are also illustrated. Although different dopant types are used, Figure 16B The p-type LDMOS transistor 1650 illustrated in the figure can be fabricated in a similar manner to the fabrication stages of the n-type LDMOS transistor described with respect to Figures 4 to 15. Figure 16A In the p-type LDMOS transistor 1650 illustrated in the figure, the well 1613 is n-type, the highly doped well contact 1614 is n-type, the source region 1616 is heavily doped p-type (i.e., p+), and the lightly doped drain 1618 is p-type.

[0076] It should be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes based thereon are intended to be suggested to those skilled in the art and are intended to be included within the spirit and scope of this application and the appended claims.

[0077] Upon reading this disclosure, those skilled in the art will immediately understand additional alternative structural and functional designs for systems and processes using the principles disclosed herein for motion-based content navigation. Therefore, while specific embodiments and applications have been illustrated and described, it should be understood that the disclosed embodiments are not limited to the precise constructions and components disclosed herein. Various modifications, alterations, and variations to the arrangement, operation, and details of the methods and apparatus disclosed herein, as will be apparent to those skilled in the art, may be made without departing from the spirit and scope defined in the appended claims.

Claims

1. A metal-oxide-semiconductor (MOS) transistor, comprising: Substrate containing a well region; An insulating layer coupled to the substrate; The source pole, which includes: Source region; The source contact passes through the insulating layer and the source region to the well region; as well as Ohmic contacts, which are disposed in the well region; The gate region includes a gate insulating layer and a gate contact; and The drain electrode includes: Drain region; and The drain contact passes through the insulating layer to the drain region.

2. The MOS transistor of claim 1, wherein the source region further includes a second source contact extending through the insulating layer to the source region.

3. The MOS transistor according to claim 1, wherein the source region is positioned at a first predetermined distance from the substrate, and the ohmic contact is positioned at a second predetermined distance from the substrate that is less than the first predetermined distance.

4. The MOS transistor according to claim 1, wherein the source region is n-type.

5. The MOS transistor of claim 1, wherein the source contact electrically connects the source region to the well region.

6. The MOS transistor of claim 1, further comprising a silicide layer disposed between the source region and the insulating layer and between the drain region and the insulating layer.

7. The MOS transistor according to claim 1, wherein: The source contact includes a source contact surface region disposed on the insulating layer; and The drain contact includes a drain contact surface area disposed on the insulating layer.

8. The MOS transistor of claim 7, further comprising a polysilicon layer.

9. The MOS transistor according to claim 1, wherein the source contact comprises: The contact lining comprises titanium and titanium nitride; as well as Source contact plug, which contains tungsten.

10. A transistor array comprising: The plurality of metal-oxide-semiconductor (MOS) transistors forming the transistor array, each of the plurality of MOS transistors comprising: The source region has source contacts; A well contact adjacent to the source region, wherein the source contact is electrically connected to the source region and the well contact; Gate region, having gate contacts; and The drain region has drain contacts.

11. The transistor array of claim 10, wherein each of the plurality of MOS transistors comprises a laterally diffused MOS LDMOS transistor.

12. The transistor array of claim 10, further comprising a metal interconnect layer electrically connecting the source contacts.

13. A method for fabricating a laterally diffused metal-oxide-semiconductor (LNDMOS) device, the method comprising: Provide a substrate containing a well region; A gate structure is formed on the substrate; Perform the first ion implantation process to form the source and drain regions; A silicide layer is formed on the substrate; An insulating layer is formed on the silicide layer; Etch a first opening through the insulating layer to the silicide layer; The first opening is extended to pass through the source region and into the well region; A second ion implantation process is performed to form an ohmic contact leading to the trap region; A source contact is formed in the first opening; Perform a chemical mechanical polishing (CMP) process to planarize the source contacts; A second opening is etched through the insulating layer to the silicide layer; and A drain contact is formed in the second opening.

14. The method of claim 13, wherein etching the second opening further comprises: Etching is performed through the insulating layer to the silicide layer to form contact openings; and A second source contact is formed in the contact opening.

15. The method of claim 14, wherein: Etching the second opening and etching through the insulating layer to the silicide layer are performed simultaneously; and The formation of the source contact is performed before the formation of the second source contact.

16. The method of claim 13, wherein forming the source contact comprises: Deposit contact lining in the first opening; and A contact plug is deposited on the contact liner to fill the first opening.

17. The method of claim 13, wherein: Etching the first opening will form a tapered region in the insulating layer; and Performing the CMP process includes removing the tapered region.

18. The method of claim 13, wherein extending the first opening extends through the silicide layer, the source region, and into the well region.

19. The method of claim 13, wherein performing the CMP process removes the upper portion of the insulating layer.

20. The method of claim 13, wherein forming the drain contact is performed after forming the source contact.

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