Floating-point operand multiplier using a lower-precision floating-point number decomposition of the operands

Abstract

The invention relates to a binary input decomposition circuit (UPCK) for a binary arithmetic operator, the input number having an FP32 floating-point format. The decomposition circuit is wired to decompose the input number (X) into a pair of high and low components (Xh, Xl) in an internal format with a 9-bit exponent and a 12-bit significand. The circuit directly connects the bits of the significand (Xhm) of the high component to a circuit providing the value of the implicit bit and the most significant bits of the fractional mantissa of the input number. The circuit directly connects the bits of the significand (Xlm) of the low component to the remaining bits of the fractional mantissa. The exponent (Xhe) of the high component is set to the exponent of the input number (X) plus 12. The exponent (Xle) of the low component remains unchanged from the input number (X). Figure for the abstract: Fig. 1