Electronic device including a memory cell

Abstract

Electronic device comprising a memory cell. This description relates to an electronic device comprising a memory cell (10) comprising: - a first semiconductor box (12), of a first type of conductivity; - a second semiconductor box (14), of the first type of conductivity; - a first layer (18) on a lower face of the first and second boxes; - an insulated conductive wall (16) separating the first and second boxes; - a third semiconductor box (22) of the second type of conductivity located in the first box; - a fourth semiconductor box (24) of the second type of conductivity located in the second box; and - a stack of layers extending above the first and second boxes and the wall, the stack comprising a second insulating layer (27), a third floating grid layer (26), a fourth insulating layer (29) and a fifth control grid layer (28).Figure for the summary: Fig. 2A.

Description

Title of the invention: Electronic device comprising a memory cell technical field

[0001] This description relates generally to electronic devices and more specifically to devices comprising a memory cell and their methods of use. Previous technique

[0002] There are many types of memory cells. There are memory cells called eSTM (embedded Select in Trench Memory). An eSTM memory cell is a rewritable memory cell typically used in flash memory circuits. There are also memory cells called EEPROM (Electrically-Erasable Programmable Read-Only Memory). An EEPROM memory cell is a type of non-volatile memory. Summary of the invention

[0003] One embodiment provides an electronic device comprising a memory cell, the memory cell comprising: - a first semiconductor casing, doped with a first type of conductivity; - a second semiconductor chamber, doped with the same type of conductivity as the first chamber; - a first layer in contact with an underside of the first and second boxes; - an insulated conductive wall separating the first and second boxes; - a third semiconductor chamber located in the first chamber, the third chamber being doped with a second type of conductivity opposite to the first type of conductivity; - a fourth semiconductor cell located within the second cell, the fourth cell being doped with the second type of conductivity; and - a stack of layers extending above the first and second boxes and the wall, the stack comprising a second insulating layer, a third layer forming a floating grid, a fourth insulating layer and a fifth layer forming a control grid.

[0004] One embodiment provides a method for using an electronic device comprising a memory cell, the memory cell comprising: - a first semiconductor casing, doped with a first type of conductivity; - a second semiconductor chamber, doped with the same type of conductivity as the first chamber; - a first layer in contact with an underside of the first and second boxes; - an insulated conductive wall separating the first and second boxes; - a third semiconductor chamber located in the first chamber, the third chamber being doped with a second type of conductivity opposite to the first type of conductivity; - a fourth semiconductor cell located within the second cell, the fourth cell being doped with the second type of conductivity; and - a stack of layers extending above the first and second boxes and the wall, the stack comprising a second insulating layer, a third layer forming a floating grid, a fourth insulating layer and a fifth layer forming a control grid, the process includes a step of reading 'data contained in the cell', a step of writing the data into the cell and a step of erasing the cell.

[0005] According to one embodiment, the fourth compartment separates the second compartment from the second layer.

[0006] According to one embodiment, during the writing or erasing step, the cell is polarized in such a way that charges, electrons or holes, are injected into the third layer from the fourth chamber through the second layer by tunneling.

[0007] According to one embodiment, the fourth box is separated from the wall by a portion of the second box.

[0008] According to one embodiment, during the writing or erasing step, the cell is polarized in such a way that charges, electrons or holes, are injected into the third layer from the second box through the second layer by tunneling.

[0009] According to one embodiment, the conductive insulating wall comprises a conductive core and an insulating envelope.

[0010] According to one embodiment, a portion of the envelope is covered with an insulating region made of a material different from the material of the envelope, the region separating the fourth box from the wall, the second box being in contact with the wall.

[0011] According to one embodiment, the core extends from the lower face of the second layer to a level in the first layer.

[0012] According to one embodiment, the core is separated from the second layer by a portion of the envelope.

[0013] According to one embodiment, the second layer comprises a first part having a first thickness and a second part having a second thickness, less than the first thickness, the first part being located opposite the first box and the second part being located opposite the second box.

[0014] According to one embodiment, the thickness of the first part is at least one and a half times greater than the thickness of the second part.

[0015] According to one embodiment, during the reading step, the cell is polarized so as to form a current between the first layer and the third box.

[0016] According to one embodiment, during the writing or erasing step, the cell is polarized in such a way that a current is formed between the first layer and the third cell, charges, electrons or holes, being injected into the third layer by injecting hot carriers through the second layer.

[0017] According to one embodiment, during the writing or erasing step, the cell is polarized in such a way that a current is formed between the first layer and the fourth cell, charges, electrons or holes, being injected into the third layer by injecting hot carriers through the second layer. Brief description of the drawings

[0018] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0019] [Fig.1] represents views A, B, C and D of an embodiment of a memory cell;

[0020] [Fig.2A] and [Fig.2B] represent operating modes of the cell of [Fig.1];

[0021] [Fig.3] represents another embodiment of a memory cell;

[0022] [Fig.4] represents another embodiment of a memory cell;

[0023] [Fig.5] represents another embodiment of a memory cell;

[0024] Fig. 6A, Fig. 6B and Fig. 6C represent modes of operation of the cell of [Fig.5];

[0025] Figure 7 represents another embodiment of a memory cell; and

[0026] [Fig.8] represents one mode of operation of the cell of [Fig.7]. Description of the implementation methods

[0027] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0028] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0029] Unless otherwise specified, when referring to two elements connected between them, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or linked through one or more other elements.

[0030] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0031] Unless otherwise specified, the expressions "approximately", "about", "Sensibly" and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0032] [Fig. 1] represents views A, B, C and D of an embodiment of a memory cell 10. More specifically, [Fig. 1] includes: a cross-sectional view A along a plane AA of views B and C; a top view B according to a plane BB of views A and D; a top view C along a plane CC of views A and D; and a cross-sectional view D along a plane DD of views B and C.

[0033] Planes BB and CC are parallel to each other and orthogonal to planes AA and DD. Plane AA is orthogonal to planes BB, CC, and DD. Similarly, plane DD is orthogonal to planes AA, BB, and CC. Plane AA corresponds to the direction of a bit row in a matrix of identical or similar elementary cells. Plane DD corresponds to the direction of a word row in the matrix.

[0034] The memory cell 10 comprises a housing 12. The housing 12 is made of a semiconductor material, for example silicon. The housing 12 is doped with a first type of conductivity, for example type P. The housing 12 is, for example, doped with boron. The concentration of dopants in the housing 12 is, for example, between 10¹⁴ and 5 x 10¹⁵ atoms·cm³.

[0035] The cell 10 further comprises a compartment 14. The compartment 14 is made of a semiconductor material, for example silicon. The compartment 14 is doped with the first type of conductivity, that is to say, the same type of conductivity as the compartment 12, for example, type P. The compartment 14 is, for example, doped with boron. The concentration of dopants in the compartment 14 is, for example, between 10¹⁴ and 5 x 10¹⁵ atoms·cm³.

[0036] The cell 10 further comprises a wall 16 separating the compartments 12 and 14. The wall 16 comprises, for example, a core 16a, for example made of a metal or a semiconductor material, preferably polycrystalline silicon, and an insulating envelope 16b surrounding the core 16a, for example made of silicon dioxide. In particular, the insulating envelope 16b separates the core 16a from the compartments 12 and 14. Preferably, the compartments 12 and 14 are completely separated by the wall 16. The wall 16 preferably extends at least over the entire height of the compartments 12 and 14. Thus, the compartments 12 and 14 are preferably not in contact with each other. The compartments 12 and 14 are preferably in contact with the wall 16.

[0037] Preferably, the compartments 12 and 14 have coplanar lower faces. Preferably, the cell 10 comprises a layer 18 on which the lower faces of the compartments 12 and 14 rest. In this example, the lower faces of the compartments 12 and 14 are in contact with the upper face of the layer 18. The layer 18 is preferably made of a semiconductor material, for example silicon, for example silicon doped with a second type of conductivity opposite to the first type of conductivity, for example type N. The layer 18 rests, for example, on a substrate 20 doped with the first type of conductivity, for example type P. The substrate 20 is, for example, made of a semiconductor material, for example boron-doped.

[0038] Preferably, the lower face of the wall 16 is located in the layer 18. The wall 16 crosses, preferably partially, the layer 18. Preferably, a part of the wall 16, including at least a part of the core 16a, is laterally surrounded by the layer 18. Preferably, the wall 16 does not cross, even partially, the substrate 20.

[0039] The cell 10 comprises a compartment 22 located in an upper part of the compartment 12. The compartment 22 is made of a semiconductor material, for example, silicon. The compartment 22 is doped with the second type of conductivity, for example, type N (N+). The compartment 22 is doped with the type of conductivity opposite to that of the compartment 12. The compartment 22 is, for example, doped with phosphorus. The concentration of dopants in the compartment 22 is, for example, between 10 and 10 atoms.cm³.

[0040] The enclosure 22 is separated from the wall 16 by a portion of the enclosure 12. In other words, a portion of the enclosure 12 is located between the enclosure 22 and the wall 16. The wall 16 and the enclosure 22 are thus not in contact with each other. The enclosure 22 extends from the upper face of the enclosure 12. The upper face of the enclosure 22 is preferably coplanar with the upper face of the wall 16 and with the upper face of the portion of the enclosure 12 located between the enclosure 22 and the wall 16.

[0041] Similarly, the cell 10 includes a box 24 located in an upper part of the box 14. The box 24 is made of a semiconductor material, for example silicon. The box 24 is doped with the second type of conductivity, for example of type N (N+). Cell 24 is doped with a conductivity type opposite to that of cell 14. For example, cell 24 is doped with phosphorus. The concentration of dopants in cell 24 is, for example, between 10¹⁸ and 10²⁰ atoms / cm³.

[0042] The box 24 preferably extends above the box 14. The box 24 therefore extends onto, and preferably in contact with, the upper face of the box 14. The box 24 is in contact with the wall 16. The box 24 extends from the upper face of the box 12 and the wall 18. The upper face of the box 24 is preferably coplanar with the upper face of the wall 16. Preferably, the box 14 does not extend to the level of the upper face of the wall 16. Thus, an upper part of the wall 16 is in contact with the box 12 and the box 24, and a lower part of the wall 16 is in contact with the box 12 and the box 14.

[0043] Plan CC of view C illustrates the upper faces of the boxes 12, 22, 24 and of the wall 16. In plan CC, the cell thus comprises from left to right box 22, box 12, wall 16, and box 24.

[0044] The doping type, or conductivity, of chamber 12 is the same as the doping type of chamber 14. Similarly, the doping type of chamber 22 is the same as the doping type of chamber 24. Furthermore, the doping type of chamber 22 is the opposite of the doping type of chamber 12. The doping type of chamber 24 is the opposite of the doping type of chamber 14. Thus, chambers 22 and 14 have opposite doping types, and chambers 24 and 12 have opposite doping types.

[0045] The cell 10 is separated from neighboring cells belonging to different rows by insulating walls 25. The insulating walls 25 are, for example, made of silicon oxide. The insulating walls 25 preferably extend from the plane of the upper faces of the boxes 22 and 24, i.e., the CC plane. The walls 25 preferably extend along the entire cell in the direction of the rows. Thus, the walls 25 extend along the boxes 22, 24, 12, and 14. The walls 25 are preferably traversed by the wall 16. Preferably, the walls 25 extend to a height less than the height of the wall 16, that is, a height less than the distance between the CC plane and the layer 18. Thus, the walls 25 preferably do not extend over the entire height of the boxes 12 and 14. This allows the boxes 12 and 14 of a cell 10 to be electrically connected to neighboring cells 10.The walls 25 are preferably separated from layer 18 by a part of box 12 or box 14. Preferably, the walls 25 extend over a height greater than the height of boxes 22 and 24.

[0046] The cell 10 further comprises a stack of an insulating layer 27, a layer 26 of a metal or a semiconductor material, for example polycrystalline silicon, an insulating layer 29 and a layer 28 of a metal or a semiconductor material, for example polycrystalline silicon. For example, layer 27 is silicon oxide and layer 29 is a stack of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. Preferably, layers 26 and 28 are made of the same material, for example polycrystalline silicon.

[0047] Layer 27 rests on the upper face of the boxes 12, 22 and 24. Layer 26 rests on layer 27. Preferably, layer 26 has horizontal dimensions smaller than the horizontal dimensions of layer 27, i.e. smaller dimensions in the bit and word line directions. Preferably, layer 27 extends continuously over the entire upper face of box 12 and at least partially over the upper face of boxes 22 and 24. Layer 27 preferably does not extend into contact with box 14. Box 14 is preferably completely separated from layer 27 by box 24. Layer 27 extends, in the direction of the columns, over the entire width of boxes 22 and 24. Preferably, layer 27 extends from one of the walls 25, preferably from a lateral face of one of the walls 25, to the other wall 25 of the cell, preferably to a lateral face of the other wall 25.Layer 27 extends, preferably, in the direction of the matrix line, from wall 16. Layer 27 separates layer 26 from boxes 12 and 24.

[0048] The layer 27 comprises two parts 27a and 27b. Parts 27a and 27b preferably each have a substantially constant thickness. Part 27a corresponds, for example, to a high-voltage oxide, i.e., an insulating layer configured to withstand a high voltage, for example, greater than 10 V. Part 27b corresponds to a tunneling oxide, i.e., an insulating layer configured to allow charges to pass through it, according to the tunneling effect. Part 27a has a thickness greater than the thickness of part 27b. Preferably, the thickness of part 27a is at least one and a half times, and preferably at least twice, the thickness of part 27b. For example, the thickness of part 27a is greater than 10 nm, for example, greater than or equal to 15 nm. For example, the thickness of part 27b is greater than 5 nm, for example greater than or equal to 8 nm. For example, the thickness of part 24b is approximately equal to 8 nm.For example, the thickness of part 24a is approximately equal to 15 nm or 22 nm.

[0049] Part 27a extends over boxes 12 and 22. Part 27b extends over box 24. Preferably, part 27a does not extend over box 24. Preferably, part 27b does not extend over boxes 12 and 22. The separation between parts 24a and 24b is preferably located on wall 16.

[0050] Preferably, layer 26 extends continuously along the entire upper face of the boxes 12 and 14. Layer 26 extends, in the direction of the columns, across the entire width of the boxes 22 and 24. Preferably, layer 26 extends from a from walls 25 to another wall 25 of the cell. Layer 26 extends, preferably, in the direction of the matrix line, from box 22 to box 24.

[0051] Layer 29 preferably completely covers layer 26. Preferably, layer 29 covers the top face of layer 26 and the lateral faces of layer 26, for example, the lateral faces of layer 26 in the direction of the matrix columns. Preferably, layer 29 has a dimension, in the direction of the matrix rows, substantially equal to the dimension of layer 26 in the row direction.

[0052] Layer 28 preferably completely covers layer 29. Layer 28 is separated from layer 26 by layer 29. Preferably, layer 28 has a dimension, in the direction of the lines, substantially equal to the dimension of layer 26 in the direction of the lines.

[0053] Preferably, layer 28 is common to several cells in the same column, preferably to all cells in a column. Thus, layer 28 preferably covers the layers 26 of several cells in the same column, and covers the walls 25 separating said cells.

[0054] The cell further comprises contact elements 30 and 32, for example, conductive vias. Elements 30 and 32 are, for example, made of a metal. Element 30 is in contact with the housing 22 and element 32 is in contact with the housing 24. Elements 30 and 32 are not in contact with layers 26 and 28. Element 30 is preferably not in contact with the housing 12. Element 32 is preferably not in contact with the housing 14. Elements 30 and 32 are each connected to a connecting element forming a bit line.

[0055] Cell 10 consists of two MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). One N-channel transistor is formed by layer 18, box 12, and box 22, with layers 26, 27, 28, and 29 forming the gate. The other P-channel transistor is formed by box 12, box 14, and box 24, with layers 26, 27, 28, and 29 forming the gate.

[0056] Layer 18 is preferably common to all memory cells of the type of cell 10 in the same cell matrix.

[0057] The wall 16 is preferably common to all cells in the column of the matrix. The wall 16 extends from one cell to a neighboring cell by passing through the insulating walls 25.

[0058] The cell matrix row comprises, for example, adjacent cells that are symmetrical to each other along a plane of symmetry parallel to plane DD and located, for example, to the left of view A. The cells 12 and 22 then extend to the left in view A so as to form shapes similar to the shapes shown in [Fig.1]. Similarly, box 24 and box 14 are, for example, common with a neighboring cell on the same line of the matrix located towards the right of view A.

[0059] Preferably, the cells 22 of the same row of the matrix are connected to each other via the elements 30 and possibly other connecting elements not shown. Similarly, the cells 24 of the same row of the matrix are connected to each other via the elements 32 and possibly other connecting elements not shown.

[0060] Furthermore, the box 12 and the box 14 are preferably common to all the cells in the column of the matrix. The boxes 12 and 14 extend under the walls 25. For example, the boxes 12 and 14 are each connected by an end-of-line contact to a voltage application node.

[0061] Fig. 2A and Fig. 2B represent operating modes of the cell in Fig. 1.

[0062] Figure 2A represents an operating mode of the cell in Figure 1. More specifically, Figure 2A represents an EEPROM-type operating mode. Figure 2A includes three arrows 34, 36, 38 illustrating, respectively, a cell writing step, a cell erasure step, and a cell reading step.

[0063] During the cell writing stage, the different parts of the cell are polarized in such a way that electrons, stored in the chamber 24, are injected into the layer 26 through the part 27b by tunneling. For example, the chambers 12, 22, 14, and 24 are set to a reference potential, for example, ground. For example, the layer 18 is set to a reference potential, for example, ground. For example, the layer 28 is set to a positive potential, for example, approximately 14V. The core 16a is, for example, set to a reference potential, for example, ground.

[0064] During the cell erasure step, the different parts of the cell are polarized in such a way that the electrons stored in layer 26, preferably all the electrons that were injected during the writing step, are injected into the box 24 through part 27b by tunneling.

[0065] The placement of the box 24, i.e. the fact that the box 24 extends to the wall 16, allows the use of various potential values ​​for the erasure step.

[0066] Thus, according to a first example of an erasure step, the cells 12, 22, 14, 24 are brought to a reference potential, for example, ground. For example, layer 18 is brought to a reference potential, for example, ground. For example, layer 28 is brought to a negative potential, for example, substantially equal to -14V. Core 16a is, for example, brought to a reference potential, for example, ground.

[0067] According to a second example of an erasure step, the cells 12, 22, 14 are brought to a reference potential, for example, ground. For example, layer 18 is brought to a reference potential, for example ground. For example, layer 28 is set to a negative potential, for example approximately -7 V. For example, cell 24 is set to a positive potential, for example approximately 7 V. Core 16a is for example set to a reference potential, for example ground.

[0068] During the cell reading step, the different parts of the cell are biased to create a current between layer 18 and cell 22. The value of the current determines the value of the data stored in the cell. For example, cells 12, 14, and 24 are set to the same reference potential, for example, ground. Layer 18 is also set to the same reference potential. Cell 22 is set to a potential higher than that of layer 18. Cell 22 is preferably set to a positive potential, for example, a potential between 0 V and 1 V, for example, approximately 0.7 V. Furthermore, layer 28 is set to a potential lower than that of cell 22, preferably to the reference potential GND. Wall 16 is set to a potential higher than the potential to which box 22 is set. For example, wall 16 is set to a potential between 1 V and 5 V.

[0069] Figure 2B represents an operating mode of the cell in Figure 1. More specifically, Figure 2B represents an eSTM-type operating mode. Figure 2B includes three arrows 40, 42, 44 illustrating, respectively, a cell writing step, a cell erasure step, and a cell reading step.

[0070] The read and erase steps, illustrated by arrows 42 and 44, are for example identical to the read and erase steps of the operating mode described in relation to [Fig.2A].

[0071] During the cell writing step, the different parts of the cell are polarized in such a way that, during the writing step, a current, represented by arrow 40, is formed between layer 18 and cell 22, along wall 16 and layer 26. The potentials of cell 22, layers 28 and 18, and wall 16 are such that a hot carrier injection phenomenon occurs. Thus, carriers, here electrons e-, enter layer 26 through layer 27 and remain trapped there. For example, cells 12, 14, and 24 are respectively set to a reference potential, for example, ground. For example, cell 22 is set to a potential approximately equal to 4.5 V. For example, layer 18 is set to a reference potential, for example, ground. For example, layer 28 is set to a potential approximately equal to 10 V.

[0072] Fig. 3 represents another embodiment of a memory cell 46.

[0073] Memory cell 46 comprises the elements of cell 10 of [Fig. 1]. These elements will not be described again in detail.

[0074] The memory cell 46 differs from the memory cell 10 of [Fig.1] in that the cell 46 includes an insulating region 48. The region 48 is located between the box 24 and the wall 16, more precisely between the box 24 and the envelope 16b. The box 24 is thus separated, preferably entirely, from the wall 16 by the region 48. The region 48 preferably extends from the level of the top face of the box 24 to a level located in the box 14. The region 48 extends over the entire height of the box 24. A portion of the box 14 is, for example, separated from the wall 16 by the region 48. Preferably, the region 48 does not extend over the entire height of the box 14. Thus, a portion of the box 14 is not separated from the wall 16 by the region 48 and is preferably in contact with the envelope 16b.

[0075] Region 48 is preferably made of a different material from the material of the envelope 16b. Region 48 is for example made of silicon nitride.

[0076] Region 48 corresponds for example to a shallow insulating trench (STI - Shallow Trench Isolation) which has been partially engraved to form wall 16.

[0077] Figure 4 represents another embodiment of a memory cell 50.

[0078] Memory cell 50 comprises the elements of cell 10 of [Fig. 1]. These elements will not be described again in detail.

[0079] The memory cell 50 differs from the memory cell 10 of [Fig. 1] in that the cell 50 comprises an insulating region 52. The region 52 is located between the core 16a and the layer 27. The core 16a is thus separated from the layer 27 by the region 52. The upper face of the core 16a is, for example, located at a level between the level of the upper face of the box 24 and the level of the lower face of the box 24. The upper face of the core 16a is separated, by the region 52, from the lower face of the layer 27, i.e., separated from the upper face of the boxes 12 and 24, by a distance of less than 15 nm, for example, less than 10 nm. A portion of the box 24 is thus separated from the box 12 by the region 52. The region 52 is, for example, made of the material of the casing 16b. Region 52, for example, is part of envelope 16b.

[0080] The features of figures 3 and 4 can be combined so as to form a cell comprising the elements of the cell of [Fig.1], region 48 and region 52.

[0081] Figure 5 represents another embodiment of a memory cell 54.

[0082] Memory cell 54 comprises the elements of cell 10 of [Fig. 1]. These elements will not be described again in detail.

[0083] Cell 54 differs from cell 10 in that the box 24 is separated from the wall 16 by a portion of the box 14. In other words, a portion of the box 14 is located between the box 24 and the wall 16. The wall 16 and the box 24 are thus not in contact with each other. Preferably, the layer 26 is located opposite the portion of the box 14 separating the box 24 and the wall 16. Preferably, the layer 26 is not located opposite the box 24.

[0084] Fig. 6A, Fig. 6B and Fig. 6C represent operating modes of the cell in Fig. 5.

[0085] Figure 6A represents an operating mode of the cell in Figure 5. More specifically, Figure 6A represents an EEPROM-type operating mode. Figure 6A includes three arrows 34, 36, 38 illustrating, respectively, a cell writing step, a cell erasure step, and a cell reading step.

[0086] The operating mode of cell 54 illustrated in [Fig. 6A] is identical to the operating mode of cell 10 illustrated in [Fig. 2A]. The operating mode differs only in that, in the absence of the portion of the box 24 in contact with the wall 16, the erasure step cannot be performed with certain polarization values. Thus, in the operating mode of [Fig. 6A], the erasure step can be performed as described in relation to [Fig. 2A], with boxes 14 and 24 being polarized to a reference potential, for example, ground, and layer 28 being polarized to a negative potential, for example, less than -10 V, for example, approximately -14 V. It is not possible, however, to negatively polarize box 14, except by reversing the conductivity types, i.e., if 14 is type N and box 24 is type P.

[0087] Figure 6B represents an operating mode of the cell in Figure 5. More specifically, Figure 6B represents an eSTM-type operating mode. Figure 6B includes three arrows 40, 42, 44 illustrating, respectively, a cell writing step, a cell erasure step, and a cell reading step.

[0088] The operating mode of cell 54 illustrated by [Fig.6A] is identical to the operating mode of cell 10 illustrated by [Fig.2A].

[0089] Fig. 6C represents one mode of operation of the cell of Fig. 5.

[0090] The [Fig.6C] includes an arrow 58 illustrating the writing and erasure steps of a first variant of the operating mode of the [Fig.6C].

[0091] During the writing and erasing steps of the first variant, the different parts of the cell are polarized in such a way that a current, represented by arrow 58, is formed between layer 18 and box 22, along wall 16 and layer 26. The potentials of box 22, layers 28 and 18, and wall 16 are such that a hot carrier injection phenomenon occurs. Thus, carriers—electrons e- during the writing step and holes e+ during the erasing step—enter layer 26 through layer 27, and more precisely through part 27a of layer 27. For example, boxes 12, 14, and 24 are respectively placed at a reference potential, for example ground. For example, the 22 box is set to a positive potential, for example approximately equal to 4.5 V. For example, layer 18 is set to a reference potential, for example ground. For example, layer 28 is set to a positive potential during the writing stage, for example approximately equal to 10 V, and to a negative potential during the erasure stage, for example approximately equal to -10 V.

[0092] The [Fig.6C] includes an arrow 60 illustrating the writing and erasing steps of a second variant of the operating mode of the [Fig.6C].

[0093] The second variant differs from the first variant in that carriers, electrons e- during the writing step and holes e+ during the erasure step, enter layer 26 through layer 27, and more precisely through part 27b of layer 27 and not through part 27a of layer 27. The potentials applied in the second variant are, for example, the same as the potentials applied in the first variant, with the exception of the potential applied to the box 22 and the potential applied to the box 24. In the second variant, the potential applied to the box 22 is preferably a reference potential, for example ground, and the potential applied to the box 24 is a positive potential, for example approximately equal to 4.5 V.As an alternative, the potentials applied in the second variant are different from the potentials applied in the first variant, the difference in thickness of layer 27 affecting the cell coupling factors.

[0094] Figure 6C includes an arrow 56 illustrating the cell reading step 54. The reading step is, for example, identical to the reading steps described previously. The reading step is applicable to both variants of the operating mode.

[0095] Figure 7 represents another embodiment of a memory cell 62.

[0096] Memory cell 62 comprises the elements of cell 54 of [Fig.5]. These elements will not be described again in detail.

[0097] Cell 62 differs from cell 54 in that layer 27 does not include parts 27a and 27b. In other words, the portions of layer 27 covering compartments 12 and 14 preferably have a constant thickness and are substantially the same thickness. The portions of layer 27 covering compartments 12, 14, 22, and 24 preferably have a constant thickness and are substantially the same thickness. Layer 27 preferably has a constant thickness.

[0098] Fig. 8 represents one mode of operation of the cell of Fig. 7.

[0099] The operating mode of cell 62 is identical to the operating mode described in relation to [Fig.6C].

[0100] Thus, [Fig. 6C] includes an arrow 58 illustrating the writing and erasing steps of a first variant of the operating mode of the [Fig.8], identical to the first variation described in relation to [Fig.6C], and an arrow 60 illustrating the writing and erasure steps of a second variant of the operating mode of [Fig.8], identical to the second variation described in relation to [Fig.6C].

[0101] One advantage of these embodiments is that it is possible to use the same memory cells to implement various modes of operation. Thus, the same cells can be used for eSTM-type memories and EEPROM-type memories.

[0102] Another advantage of the described embodiments is that they allow for cell-by-cell programming.

[0103] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to those skilled in the art. In particular, the features of the embodiments in Figures 3 and 4 can be applied to the embodiments in Figures 5 and 7.

[0104] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. An electronic device comprising a memory cell, the memory cell (10, 46, 50, 54, 62) comprising: - a first semiconductor cell (12), doped with a first type of conductivity; - a second semiconductor cell (14), doped with the same type of conductivity as the first cell (12); - a first layer (18) in contact with a lower face of the first (12) and second (14) cells; - an insulated conductive wall (16) separating the first (12) and second (14) cells; - a third semiconductor cell (22) located in the first cell (12), the third cell (22) being doped with a second type of conductivity opposite to the first type of conductivity; - a fourth semiconductor cell (24) located in the second cell (14), the fourth cell (24) being doped with the second type of conductivity;and - a stack of layers extending over the first (12) and second (14) boxes and the wall (16), the stack comprising a second insulating layer (27), a third layer (26) constituting a floating grid, a fourth insulating layer (29) and a fifth layer (28) constituting a control grid.;

2. Device according to claim 1, wherein the fourth box (24) separates the second box (14) from the second layer (27).

3. Device according to claim 1, wherein the fourth box (24) is separated from the wall by a portion of the second box (14).

4. Device according to any one of claims 1 to 3, wherein the conductive insulating wall (16) comprises a conductive core (16a) and an insulating envelope (16b).

5. Device or method according to claim 4, wherein a portion of the envelope (16b) is covered with an insulating region (48) of a material different from the material of the envelope (16b), the region (48) separating the fourth box (24) from the wall (16), the second box (14) being in contact with the wall (16).

6. Device according to claim 4 or 5, wherein the core (16a) extends from the lower face of the second layer (27) to a level in the first layer (18).

7. Device according to any one of claims 4 to 6, wherein the core (16a) is separated from the second layer (27) by a portion (52) of the envelope (16b).

8. Device according to any one of claims 1 to 7, wherein the second layer (27) comprises a first part (27a) having a first thickness and a second part (27b) having a second thickness, less than the first thickness, the first part (27a) being located opposite the first box (12) and the second part (27b) being located opposite the second box (14).

9. Device according to claim 8, wherein the thickness of the first part (27a) is at least one and a half times greater than the thickness of the second part (27b).

10. A method of using an electronic device comprising a memory cell, the memory cell (10, 46, 50, 54, 62) comprising: - a first semiconductor cell (12), doped with a first type of conductivity; - a second semiconductor cell (14), doped with the same type of conductivity as the first cell (12); - a first layer (18) in contact with a lower face of the first (12) and second (14) cells; - an insulated conductive wall (16) separating the first (12) and second (14) cells; - a third semiconductor cell (22) located in the first cell (12), the third cell (22) being doped with a second type of conductivity opposite to the first type of conductivity; - a fourth semiconductor cell (24) located in the second cell (14), the fourth cell (24) being doped with the second type of conductivity;and - a stack of layers extending above the first (12) and second (14) boxes and the wall (16), the stack comprising a second insulating layer (27), a third layer (26) constituting a floating grid, a fourth insulating layer (29) and a fifth layer (28) constituting a control grid, the method comprising a step of reading data contained in the cell, a step of writing the data into the cell and a step of erasing the cell.;

11. Method of use according to claim 10 applied to a device according to any one of claims 1 to 9.

12. A method according to claim 11 in relation to claim 2, wherein during the writing or erasing step, the cell is polarized in such a way that charges, electrons or holes, are injected into the third layer (26) from the fourth chamber (24) through the second layer (27) by tunneling.

13. A method according to claim 11 in relation to claim 3, wherein during the writing or erasing step, the cell is polarized in such a way that charges, electrons or holes, are injected into the third layer (26) from the second box (14) through the second layer (27) by tunneling.

14. A method according to any one of claims 10 to 13, wherein during the reading step, the cell is polarized so as to form a current between the first layer (18) and the third box (22).

15. A method according to any one of claims 10 to 14, wherein during the writing or erasing step, the cell is polarized in such a way that a current is formed between the first layer (18) and the third box (22), charges, electrons or holes, being injected into the third layer (26) by injecting hot carriers through the second layer (27).

16. A method according to any one of claims 10 to 15, wherein during the writing or erasing step, the cell is polarized in such a way that a current is formed between the first layer (18) and the fourth box (24), charges, electrons or holes, being injected into the third layer (26) by injecting hot carriers through the second layer (27).