Method for manufacturing optoelectronic circuits comprising light-emitting diodes
The method of forming optoelectronic circuits with wire-shaped LEDs in parallel bands addresses the high cost issue of mask redesign by enabling reuse of photolithography masks, ensuring efficient LED operation and uniformity in manufacturing processes.
Patent Information
- Authority / Receiving Office
- FR · FR
- Patent Type
- Applications
- Current Assignee / Owner
- ALEDIA INC
- Filing Date
- 2024-12-19
- Publication Date
- 2026-06-26
AI Technical Summary
Existing methods for manufacturing optoelectronic circuits with light-emitting diodes require redesigning new masks during photolithography steps for each new light intensity and consumption requirement, leading to significant manufacturing costs.
A method involving the formation of an optoelectronic plate with micrometric or nanometric, wire-shaped, conical or truncated conical LEDs distributed in parallel bands, allowing cutting to form optoelectronic circuits without altering the LEDs, enabling the reuse of existing photolithography masks.
Reduces manufacturing costs by allowing the reuse of photolithography masks and enables efficient operation of LEDs near peak efficiency without the need for new mask designs, while maintaining uniformity in growth, deposition, and etching steps.
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Abstract
Description
Title of the invention: Method for manufacturing optoelectronic circuits comprising light-emitting diodes. Technical field
[0001] This description relates generally to methods for manufacturing optoelectronic circuits comprising light-emitting diodes. Prior art
[0002] An example of a method for manufacturing optoelectronic circuits comprising light-emitting diodes includes manufacturing several copies of the optoelectronic circuit on a plate and cutting the plate to separate the optoelectronic circuits.
[0003] Figure 1 shows the evolution of the efficiency of a light-emitting diode (LED) as a function of the current density J2D, expressed in A / cm², flowing through the LED. The efficiency corresponds to the ratio between the optical power, expressed in mW, of the radiation emitted by the LED and the electrical power, expressed in W, consumed by the LED. The curve exhibits an efficiency peak obtained for a given current density, which depends essentially on the growth process of the semiconductor materials composing the LED and is difficult to modify.
[0004] It is desirable to operate a light-emitting diode (LED) near its peak efficiency to increase the efficiency of the optoelectronic circuit comprising the LED. This requires operating the LED at a given current density.
[0005] A compromise must therefore be found during the design of the light-emitting diode, in particular during the determination of the dimensions of the light-emitting diode, so that the light-emitting diode operates at the given current density while satisfying the light intensity and consumption requirements of the optoelectronic circuit.
[0006] The design of each new optoelectronic circuit with new light intensity and consumption requirements may therefore require the design of a new light-emitting diode, and thus the design and manufacture of new masks used during photolithography steps during the manufacture of the light-emitting diode, which presents a significant cost.
[0007] It would be desirable to be able to design a new light-emitting diode without having to define new masks used during photolithography steps during the manufacturing of the light-emitting diode and while ensuring the operation of the light-emitting diode near its peak operating level. Summary of the invention
[0008] An embodiment overcomes all or part of the drawbacks of known methods of manufacturing optoelectronic circuits comprising light-emitting diodes.
[0009] One embodiment provides for a method of manufacturing optoelectronic circuits comprising the following steps: a) forming an optoelectronic plate comprising a substrate having one face and, on the face, wire, conical, or truncated conical light-emitting diodes of micrometric or nanometric size and distributed according to first parallel and distinct bands; and b) cutting the substrate to delimit optoelectronic circuits each comprising a part of one of the first bands.
[0010] Advantageously, the design of a new optoelectronic circuit consists of moving the cutting lines in step b) to vary the number of LEDs in the optoelectronic circuit and thus the maximum light intensity that can be emitted by the optoelectronic circuit. Since the LEDs are three-dimensional, wire-shaped, conical, or frustoconical LEDs of micrometer or nanometer size, the cutting in step b) advantageously does not damage the three-dimensional LEDs remaining on the optoelectronic circuit. An advantage is that the manufacturing process steps up to the cutting step b) do not depend on the dimensions of the optoelectronic circuits and are therefore the same regardless of their dimensions.Advantageously, the masks used in photolithography steps for forming light-emitting diodes do not need to be modified for the design of a new optoelectronic circuit. The manufacturing cost of a new optoelectronic circuit is therefore advantageously reduced.
[0011] According to one embodiment, step a) further comprises the following steps: - formation of the light-emitting diodes over the entire face; and - removal of the light-emitting diodes outside the first bands.
[0012] This advantageously improves the uniformity of the growth, deposition and etching steps implemented during the manufacture of light-emitting diodes and thus improves the uniformity of the characteristics of the light-emitting diodes distributed over the entire surface of the substrate.
[0013] According to one embodiment, step a) includes the formation of second electrically conductive bands parallel to the first bands, each second band forming a first electrode of the light-emitting diodes of at least one of the first bands.
[0014] According to one embodiment, two of the first strips are interposed between each pair of adjacent second strips.
[0015] According to one embodiment, step a) comprises the formation of third electrically conductive strips parallel to the first strips, each third strip forming a second electrode of the light-emitting diodes (LEDs) of at least one of the first strips. This advantageously allows for testing the proper functioning of the LEDs of a first LED strip before step b) of cutting, using the second and third conductive strips adjacent to the first LED strip to power the LEDs.This also advantageously allows for testing the proper functioning of the LEDs in an electronic circuit after step b) of cutting, using the second and third conductive strips adjacent to the cut portion of the first LED strip to power the LEDs.
[0016] According to one embodiment, a single second strip or two adjacent third strips are interposed between each pair of adjacent first strips.
[0017] According to one embodiment, the method further comprises cutting the optoelectronic plate along first cutting lines parallel to the first strips and located between the first strips and cutting the optoelectronic plate along second cutting lines orthogonal to the first cutting lines.
[0018] According to one embodiment, the first cutting lines among the first cutting lines extend onto the second strips.
[0019] According to one embodiment, first cutting lines among the first cutting lines extend between each pair of adjacent third strips.
[0020] According to one embodiment, each first strip of light-emitting diodes comprises rows of at least two light-emitting diodes perpendicular to the direction of the first strips.
[0021] One embodiment also provides for an optoelectronic plate comprising a substrate having one face and, on the face, wire, conical, or truncated conical light-emitting diodes of micrometric or nanometric size and distributed according to first parallel and distinct bands.
[0022] According to one embodiment, each first strip of light-emitting diodes comprises rows of at least two light-emitting diodes perpendicular to the direction of the first strips.
[0023] According to one embodiment, the optoelectronic plate comprises second electrically conductive bands parallel to the first bands, each second band forming a first electrode of the light-emitting diodes of at least one of the first bands.
[0024] According to one embodiment, the optoelectronic plate comprises third bands that are electrically conductive and parallel to the first bands, each third band forming a second electrode of the light-emitting diodes of at least one of the first bands. Brief description of the drawings
[0025] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:
[0026] the [Fig.1], described previously, is a curve showing the evolution of the efficiency of a light-emitting diode as a function of the current density through the light-emitting diode;
[0027] [Fig.2A], [Fig.2B], [Fig.3A], [Fig.3B], [Fig.4A], [Fig.4B], [Fig.5], [Fig.6], [Fig.7], [Fig.8A], [Fig.8B], [Fig.9], [Fig.1OA], [Fig.1OB], [Fig.11A], [Fig.11B], [Fig.12A], [Fig.12B], [Fig.13] and [Fig.14] represent partial and schematic cross-sectional or top views of structures obtained at successive stages of an embodiment of a process for manufacturing optoelectronic circuits;
[0028] Figures 15 and 16 are figures analogous respectively to Figures 13 and 14 which illustrate structures obtained at successive stages of another embodiment of a process for manufacturing optoelectronic circuits;
[0029] Figures 17 and 18 are figures analogous respectively to Figures 13 and 14, which illustrate structures obtained at successive stages of another embodiment of a process for manufacturing optoelectronic circuits; and
[0030] [Fig. 19] and [Fig. 20] are partial and schematic cross-sectional views, respectively, of embodiments of a three-dimensional light-emitting diode. Description of the implementation methods
[0031] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the Different embodiments may have the same references and may have identical structural, dimensional and material properties.
[0032] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.
[0033] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.
[0034] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.
[0035] Unless otherwise specified, the expressions "approximately", "roughly", "about", and "on the order of" mean to the nearest 10% or 10°, preferably to the nearest 5% or 5°. Furthermore, the terms "insulator" and "conductor" are taken to mean "electrically insulating" and "electrically conductive", respectively.
[0036] Successive steps of an embodiment of a method for manufacturing an optoelectronic circuit will now be described in relation to [Fig.2A], [Fig.2B], [Fig.3A], [Fig.3B], [Fig.4A], [Fig.4B], [Fig.5], [Fig.6], [Fig.7], [Fig.8A], [Fig.8B], [Fig.9], [Fig.1OA], [Fig.1OB], [Fig.11A], [Fig.11B], [Fig.12A], [Fig.12B], [Fig.13] and [Fig.14],
[0037] Fig. 2A and Fig. 2B represent respectively a partial and schematic side sectional view and top view of the structure obtained after the formation of three-dimensional LEDs on a semiconductor substrate 10.
[0038] In [Fig. 2A], a structure is shown comprising, from bottom to top in [Fig. 2A]: - the semiconductor substrate 10 comprising a top face 22; - germination pads 24 promoting the growth of wires and arranged on the face 22; - a stack of insulating layers 26, 28, 30 covering the germination pads 24 and traversed by openings 32 leading to the germination pads 24; and - three-dimensional LEDs in wire, conical or truncated conical shape, each LED being in contact with one of the germination pads 24, through one of the openings 32.
[0039] Each light-emitting diode LED comprises a wire-shaped, conical or frustoconical semiconductor element and a casing, not shown, comprising a A stack of semiconductor layers covering at least part of the semiconductor wire element. The shell includes, in particular, an active layer, which is the layer from which the majority of the electromagnetic radiation emitted by the light-emitting diode (LED) is generated.
[0040] According to one embodiment, as can be seen in [Fig.2B], the LEDs are distributed over the entire substrate 10.
[0041] Figures 3A and 3B respectively represent a partial and schematic side view and top view of the structure obtained after the formation of a layer 34 covering the LEDs on BLED portions of the upper face 22 where the LEDs are to be retained, and after the LEDs have been removed from the rest of face 22 of the substrate 10 so that LEDs remain only on the BLED portions of face 22. In one embodiment, the LEDs are removed from the rest of face 22 of the substrate 10 by a mechanical process. In one embodiment, the BLED portions of face 22 are in the form of parallel bands. In one embodiment, the width of each BLED band is between 5 µm and 20 µm.According to one embodiment, for each BLED strip, there are from 1 to 10, preferably from 1 to 4, light-emitting diodes (LEDs) depending on the width of the BLED strip.
[0042] Figures 4A and 4B respectively represent a partial and schematic side sectional view and top view of the structure obtained after the removal of layer 34 and the etching, on portions of the surface 22, of the stack of insulating layers 26, 28, 30, the remaining LEDs, the germination pads 24, and the substrate 10 from face 22 over a portion of the substrate's thickness to form openings 36. In one embodiment, each opening 36 comprises a portion 38 which, in top view, has the form of a straight band interposed between two pairs of BLED strips, and a terminal portion 40. In one embodiment, two BLED strips of LEDs are interposed between two adjacent openings 36. Subsequently, a pair of BLED strips that are not separated by an opening 36 are called adjacent BLED strips.
[0043] Fig. 5 represents a partial, schematic, side-sectional view of the structure obtained after the deposition of an insulating layer 42 over the entire structure of Fig. 4A, and in particular over the LEDs and in the openings 36, and the removal of part of the insulating layer 42 to expose an upper portion of each LED.
[0044] Figure 6 shows a partial, schematic, lateral cross-sectional view of the structure obtained after the deposition of a conductive layer for each BLED strip. and transparent 44 forming a top electrode, covering the shell of all the LEDs in the BLED strip, and in direct physical contact with the shell of all the LEDs in the BLED strip, and extending, furthermore, over the insulating layer 42 between the LEDs in the BLED strip.
[0045] Fig. 7 represents a partial and schematic lateral cross-sectional view of the structure obtained after the removal of the insulating layer 42 in each opening 36 to expose the upper face 22 of the substrate 10.
[0046] Figures 8A and 8B respectively represent a partial and schematic side view and top view of the structure obtained after the deposition, for each aperture 36, of a conductive layer 46 covering the aperture 36, and, for each BLED strip, of a conductive layer 48 covering the electrode layer 44 between the LEDs but not extending onto the LEDs. In one embodiment, each conductive layer 46 has, in top view, substantially the same shape as the corresponding aperture 36. The conductive layer 48, which is located between the LEDs, notably acts as a mirror reflecting the light emitted by the LEDs and advantageously increases light extraction.According to one embodiment, each conductive layer 48 covers, in top view, substantially the entire corresponding BLED strip. Furthermore, the conductive layers 48 covering two adjacent BLED strips can extend laterally between the adjacent BLED strips. In Figures 8A and 8B, the conductive layers 48 covering two adjacent BLED strips are shown separated laterally by an opening 49. Alternatively, the conductive layers 48 covering two adjacent BLED strips can be contiguous. Moreover, as shown in the top view in [Fig. 8B], the conductive layers 48 covering two adjacent BLED strips extend at one end by a common terminal portion 50.
[0047] Fig. 9 represents a partial and schematic lateral cross-sectional view of the structure obtained after the deposition of an encapsulation layer 52 over the entire structure.
[0048] Figures 10A and 10B respectively represent a partial and schematic side sectional view and top view of the structure obtained after the formation of the first and second pre-cut grooves 54, 56, followed by the application of a protective layer 58 covering the entire structure. Each first and second groove 54, 56 extends down to the substrate 10 and over a portion of the substrate 10's thickness. In one embodiment, the first and second grooves 54, 56 are parallel to the BLED strips. In another embodiment, the first and second grooves 54, 56 extend substantially over the same length as the BLED strips. According to one embodiment, the first grooves 54 extend substantially in the middle of the openings 36 and the second grooves 56 extend substantially between each pair of adjacent BLED strips, substantially in the middle of each opening 49.
[0049] The [Fig. 11 A] and the [Fig. Figures 1 IB represent, respectively, a partial and schematic side sectional view and top view of the structure obtained after etching openings 60 in the protective layer 58 and in the encapsulation layer 52 until each conductive layer 46 and each opening 54 is exposed, openings 62 in the protective layer 58 and in the encapsulation layer 52 until a portion of each conductive layer 48 is exposed, and openings 64 in the protective layer 58 and in the encapsulation layer 52 until another portion of each conductive layer 48 is exposed. The openings 60 are within the limits of the openings 36. In one embodiment, each opening 60 comprises a portion 66 which, in top view, has the shape of a straight band, the portion 66 extending into a terminal portion 68. The openings 62 are located on either side of each second groove 56.According to one embodiment, the openings 62 are parallel to the BLED strips. According to another embodiment, the openings 62 extend substantially over the same length as the BLED strips. The openings 64 are located in the terminal portions 50.
[0050] Fig. 12A and Fig. 12B respectively represent a partial and schematic side sectional view and top view of the structure obtained after the deposition of a conductive layer 70, also called conductive strip 70, covering the conductive layer 46 in each opening 60, of a conductive layer 72, also called conductive strip 72, covering the conductive layer 48 in each opening 62, and of a conductive layer 74 covering the conductive layer 48 in each opening 64. The conductive layer 70 forms a first contact (one of the anode contact or the cathode contact) of the light-emitting diodes LEDs located on the nearest BLED strip. The conductive layer 72 forms a second contact (other than the anode contact or the cathode contact) of the LED light-emitting diodes located on the two closest BLED strips between which the conductive layer 72 is interposed.The conductive layer 74 is electrically connected to the conductive layers 72 which are connected to the same conductive layer 48. An optoelectronic plate 75 is then obtained.
[0051] Testing operations for the light-emitting diodes can be implemented at this stage. A test operation may include applying a first test tip to one of the conductive layers 74 and a second test tip to one of the terminal portions 70 closest to the conductive layer 74, and the application of a voltage between the first and second test probes. The LEDs, located in the BLED strip whose cathode and anode correspond to the conductive layers 70 and 74 in contact with the first and second test probes in good working order, light up. This advantageously allows for a rapid test of the proper functioning of the LEDs, in particular a rapid measurement of their efficiency.
[0052] Figure 13 is a partial, schematic top view illustrating the structure obtained after the formation of the first and second cutting lines 76, 78 for separating optoelectronic circuits 80 in the optoelectronic wafer 75. The first cutting lines 76 extend along the first grooves 54 and the second grooves 56 and delimit the BLED strips of light-emitting diodes (LEDs). The positions of the first cutting lines 76 are always the same and do not depend on the intended applications. The second cutting lines 78 are perpendicular to the first cutting lines 76. The first cutting lines 76 can be obtained by thinning the substrate 10 from the face opposite the face 22 until reaching the grooves 54 and 56.
[0053] The positions of the second cutting lines 78 depend on the intended applications, with the possible exception of those located closest to the conductive layers 74 and those located furthest from the conductive layers 74. The positions of the second cutting lines 78 determine the number of LEDs present on the optoelectronic circuits 80. The second cutting lines 76 and 78 can be made by laser cutting, dry etching, or sawing. According to one embodiment, the length of the LED strip per optoelectronic circuit 80 can vary between 5 µm and 200 µm.
[0054] Advantageously, the design of a new optoelectronic circuit 80 consists of moving the second cutting lines 78 to vary the number of LEDs in the optoelectronic circuit 80 and therefore the maximum luminous intensity that can be emitted by the optoelectronic circuit 80. Since LEDs are three-dimensional LEDs that are wire-shaped, conical, or truncated conical, and of micrometric or nanometric size, the creation of the second cutting lines 78 does not, advantageously, damage the three-dimensional LEDs remaining on the optoelectronic circuit 80.
[0055] Advantageously, test operations can be carried out before the separation of the optoelectronic circuits 80. The determination of the proper condition of the LEDs can therefore be carried out before the formation of the optoelectronic circuits 80. Further test operations can be carried out after the first and second cutting line formation step 76, 78, since the conductive layers 70 and 72 form contact pads allowing the electrical supply of the LEDs of each optoelectronic circuit 80.
[0056] Figure 14 is a partial, schematic, side-sectional view of the structure obtained after transferring the optoelectronic circuits 80 onto a substrate 82, for example, a printed circuit board. The transfer operation can be a bulk transfer process or a pick-and-place process.
[0057] One advantage is that the manufacturing process steps described above up to the cutting step illustrated in [Fig. 13] do not depend on the dimensions of the optoelectronic circuits 80 and are therefore the same regardless of the dimensions of the optoelectronic circuits 80. Advantageously, the masks used during photolithography steps for the formation of the LEDs therefore do not need to be modified for the design of a new optoelectronic circuit 80. The manufacturing cost of a new optoelectronic circuit 80 is thus advantageously reduced.
[0058] Fig. 15 is a figure analogous to Fig. 12A and illustrates an optoelectronic plate 85 which includes all the elements of the optoelectronic plate 75 except that the openings 36, the openings 60, and the conductive layers 70 are not present.
[0059] Figure 16 is a partial, schematic, side-sectional view of the structure obtained after thinning the substrate 10, cutting optoelectronic circuits 90 from the optoelectronic wafer 85, forming conductive pads 92 on the face of the substrate 10 opposite the face 22, and transferring the optoelectronic circuits 90 onto a support 94, for example, a printed circuit board. The conductive layer 72 forms a first contact (either the anode or cathode contact) of the LEDs. The conductive pad 92 forms a second contact (either the anode or cathode contact) of the LEDs.
[0060] Fig. 17 is a figure analogous to Fig. 12A and illustrates an optoelectronic plate 95 which includes all the elements of the optoelectronic plate 75 except that the openings 36, the openings 60 and 62, and the conductive layers 70 and 72 are not present.
[0061] Figure 18 is a partial, schematic, side-sectional view of the structure obtained after thinning the substrate 10, cutting optoelectronic circuits 100 in the optoelectronic wafer 95, and, for each optoelectronic circuit 100, forming an insulating wall 101 separating the substrate 10 into first and second semiconductor portions 102, 103, and forming a laterally isolated via 104, also called a TSV (through-silicon via), passing through the first The semiconductor portion 102, extending through its entire thickness and with one end connected to the conductive layer 48, forms a conductive pad 105 on the face of the first semiconductor portion 102 opposite face 22 and in contact with the via 104. A conductive pad 106 is also formed on the face of the second semiconductor portion 103 opposite face 22. The optoelectronic circuits 100 are then transferred to a substrate 108, for example, a printed circuit board. The contact pad 105 forms a first contact (either the anode or cathode contact) of the LEDs. The conductive pad 106 forms a second contact (either the anode or cathode contact) of the LEDs.
[0062] Fig. 19 represents an embodiment of the three-dimensional light-emitting diode LED.
[0063] The LED light-emitting diode comprises, from bottom to top in [Fig. 19]: - a three-dimensional semiconductor element 110 in the form of a wire, conical, or truncated cone of nanometric or micrometric size, also referred to as a wire hereafter, which in the present embodiment corresponds to a wire of axis D, comprising for example a lower portion, doped with a first type of conductivity, for example of type N, in contact with the nucleation pad 24, and an upper portion, doped with the first type of conductivity or not intentionally doped; - an active region 112 covering the upper portion of wire 110; and - a semiconductor layer 114 of a second type of conductivity opposite to the first type of conductivity, covering the active region 112.
[0064] In [Fig. 19], the LED is said to be in radial configuration, or in core / shell configuration, since the active region 112 is formed at the periphery of the three-dimensional semiconductor element 110.
[0065] Fig. 20 represents another embodiment of the three-dimensional LED in which the active region 112 covers only the end of the wire 110 opposite the nucleation point 24 and does not cover the lateral faces of the wire 110. In Fig. 20, the LED is said to be in axial configuration, since the active region 110 is formed along the axis D of the three-dimensional semiconductor element 110.
[0066] The substrate 10 may be a single-piece structure or a layer covering a support made of another material. The substrate 10 is, for example, a semiconductor substrate, preferably a semiconductor substrate compatible with the manufacturing processes used in microelectronics, for example, a silicon substrate, a germanium substrate, or an alloy of these compounds. The substrate 10 may be made of a doped semiconductor material.
[0067] The germination pads 24, also called germination islands, are made of a material that promotes the growth of the wires 110. As an alternative, the pads of germination 24 can be replaced by a germination layer covering face 22 of substrate 10.
[0068] By way of example, the material composing the germination pads 24 may be a nitride, a carbide or a boride of a transition metal from column IV, V or VI of the periodic table of elements or a combination of these compounds. For example, the germination pads 24 may be made of boron (B), boron nitride (BN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), hafnium (Hf), hafnium nitride (HfN), niobium (Nb), niobium nitride (NbN), zirconium (Zr), zirconium borate (ZrB2), zirconium nitride (ZrN), silicon carbide (SiC), tantalum nitride and carbide (TaCN), gallium magnesium nitride (MgGaN), tungsten (W), tungsten nitride (WN), or a combination thereof. The germination pads 24 may be doped with the same type of conductivity as the substrate 10 or with the opposite type of conductivity.
[0069] Each insulating layer 26, 28, 30, 42 can be made of a dielectric material, for example silicon oxide (SiO2), silicon nitride (SixNy, where x is about equal to 3 and y is about equal to 4, for example Si3N4), aluminium oxide (Al2O3), hafnium oxide (HfO2), or titanium oxide (TiO2).
[0070] The wires 110 can be, at least in part, formed from at least one semiconductor material. The semiconductor material can be silicon, germanium, silicon carbide, a III-V compound, an ILVI compound, or a combination of these compounds.
[0071] The wires 110 can be, at least in part, formed from semiconductor materials consisting predominantly of a III-V compound, for example, IIILN compounds. Examples of Group III elements include gallium (Ga), indium (In), or aluminum (Al). Examples of IIILN compounds are GaN, AIN, InN, InGaN, AlGaN, or AlInGaN. Other Group V elements can also be used, for example, phosphorus or arsenic. In general, the elements in the IILV compound can be combined in different mole fractions.
[0072] The wires 110 can be, at least in part, formed from semiconductor materials consisting predominantly of an ILVI compound. Examples of Group II elements include Group IIA elements, notably beryllium (Be) and magnesium (Mg), and Group IIB elements, notably zinc (Zn) and cadmium (Cd). Examples of Group VI elements include Group VIA elements, notably oxygen (O) and tellurium (Te). Examples of ILVI compounds are ZnO, ZnMgO, CdZnO, or CdZnMgO. Generally, the elements in the ILVI compound can be combined in different mole fractions.
[0073] The wires 110 may include a dopant. By way of example, for III-V compounds, the dopant may be chosen from the group comprising a P-type dopant from Group II, for example, magnesium (Mg), zinc (Zn), cadmium (Cd) or mercury (Hg), a P-type dopant from Group IV, for example carbon (C) or an N-type dopant from Group IV, for example silicon (Si), germanium (Ge), selenium (Se), sulfur (S), terbium (Tb), zinc (Zn), or tin (Sn).
[0074] The cross-section of the wires 110 can have various shapes, such as, for example, an oval, circular, or polygonal shape, including triangular, rectangular, square, or hexagonal shapes. Thus, it is understood that when the "diameter" in a cross-section of a wire or a layer deposited on that wire is mentioned here, it refers to a quantity associated with the surface area of the structure in that cross-section, corresponding, for example, to the diameter of the disk having the same surface area as the cross-section of the wire. The average diameter of each wire 110 can be between 50 nm and 2.5 pm. The height of each wire 110 can be between 250 nm and 20 pm, preferably between 1 pm and 10 pm.
[0075] The axes of two adjacent wires 110 may be separated from 0.05 pm to 10 pm and preferably from 1.5 pm to 4 pm. For example, the wires 110 may be regularly distributed. For example, the wires 110 may be distributed according to a hexagonal lattice.
[0076] The active region 112 is the layer from which the majority of the radiation supplied by the light-emitting diode LED is emitted. By way of example, the active region 112 may include confinement means, such as multiple quantum wells.
[0077] The semiconductor layer 114 can correspond to a single semiconductor layer or to a stack of semiconductor layers and allows the formation of a PN or PIN junction with the active region 112. The stack of semiconductor layers can include an electron-blocking layer formed of a ternary alloy, for example in gallium aluminum nitride (AlGaN) or indium aluminum nitride (AlInN) in contact with the active layer and an additional layer, to ensure good electrical contact between the electrode 44 and the active region 112, for example in gallium nitride (GaN) in contact with the electron-blocking layer and with the electrode 44.
[0078] The electrode 44 is adapted to polarize the active layer of each wire 110 and allow the passage of electromagnetic radiation emitted by the light-emitting diodes (LEDs). The material forming the electrode 44 can be a transparent and conductive material such as indium tin oxide (ITO), aluminum-doped zinc oxide, or gallium. By way of example, the electrode layer 44 has a thickness between 10 nm and 150 nm depending on the optical and electrical characteristics of the layer 44.
[0079] The conductive layer 46, 48, 70, 72 may be a single layer or a stack of two or more layers. The conductive layer 46, 48, 70, 72 may also be adapted to reflect at least part of the radiation emitted by the light-emitting diodes (LEDs). By way of example, the conductive layer 46, 48, 70, 72 may be a single metallic layer. According to another example, the conductive layer 46, 48, 70, 72 may be a stack of conductive layers comprising, for example, a metallic layer for current transmission and layers acting as anchoring or protective layers. The metallic layer of the conductive layer 46, 48, 70, 72 can be formed on an anchoring layer, for example in titanium or in a conductive metal nitride, such as titanium nitride (TiN) or tantalum nitride (TaN).For example, the material composing the metallic layer of the conductive layer 46, 48, 70, 72 (single-layer or multi-layer) can be aluminum, an aluminum-based alloy, in particular AlSiz, AlxCuy (for example with x equal to 0.95 and y equal to 0.05), silver, gold, nickel, chromium, rhodium, ruthenium, palladium, or an alloy of two or more of these compounds. For example, the conductive layer 46, 48, 70, 72 (single-layer or multi-layer) has a thickness between 100 nm and 2000 nm.
[0080] The maximum thickness of the encapsulation layer 52 is between 200 nm and 5 pm, for example, about 1 pm, so that the encapsulation layer 52 completely covers the electrode 44 at the top of the LEDs. The encapsulation layer 52 is made of an insulating material that is at least partially transparent. The encapsulation layer 52 may be made of an inorganic material that is at least partially transparent.
[0081] The germination plots 24 can be obtained by a chemical vapor deposition (CVD) or metal-organic chemical vapor deposition (MOCVD) process, also known as metal-organic vapor phase epitaxy (or MOVPE). However, processes such as molecular-beam epitaxy (MBE), gas-source MBE (GSMBE), metal-organic MBE (MOMBE), plasma-assisted MBE (PAMBE), atomic layer epitaxy (ALE), hydride vapor phase epitaxy (HVPE) may be used, or an atomic layer deposition (ALD) process.In addition, processes such as evaporation or reactive sputtering can be used.
[0082] The process for growing the wires 110, the active regions 112, and the semiconductor layers 114 can be a CVD, MOCVD, MBE, GSMBE, PAMBE, ALE, or HVPE type process. In addition, electrochemical processes can be used, for example, chemical bath deposition (CBD), hydrothermal processes, liquid aerosol pyrolysis, or electrodeposition.
[0083] The conductive layers 46, 48, 70, 72 for example by physical vapor deposition (PVD) on the whole structure and etching of this layer to expose each wire 26.
[0084] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.
[0085] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.
Claims
Demands
1. A method for manufacturing optoelectronic circuits (80; 90; 100) comprising the following steps: a) forming an optoelectronic wafer (75; 85; 95) comprising a substrate (10) having a face (22) and, on the face (22), wire, conical, or truncated conical light-emitting diodes (LEDs) of micrometer or nanometer size and distributed according to first parallel and distinct bands (BLEDs); and b) cutting the substrate (10) to delimit optoelectronic circuits (80; 90; 100) each comprising a portion of one of the first bands (BLEDs).
2. A method according to claim 1, wherein step a) further comprises the following steps: - formation of light-emitting diodes (LEDs) over the entire face (22); and - removal of light-emitting diodes (LEDs) outside the first bands (BLED).
3. A method according to claim 1 or 2, wherein step a) comprises the formation of second strips (70) electrically conductive and parallel to the first strips (BLED), each second strip (70) forming a first electrode of the light-emitting diodes (LEDs) of at least one of the first strips (BLED).
4. Method according to claim 3, wherein two of the first bands (BLED) are interposed between each pair of adjacent second bands (70).
5. A method according to any one of claims 3 or 4, wherein step a) comprises the formation of third bands (72) that are electrically conductive and parallel to the first bands (BLED), each third band (72) forming a second electrode of the light-emitting diodes (LEDs) of at least one of the first bands (BLED).
6. Method according to claim 5, wherein a single second band (70) or two adjacent third bands (72) are interposed between each pair of adjacent first bands (BLED).
7. A method according to any one of claims 1 to 6, further comprising cutting the optoelectronic plate (75; 85; 95) along first cutting lines (76) parallel to the first strips (BLED) and located between the first strips (BLED) and cutting the optoelectronic plate (75; 85; 95) along second cutting lines (78) orthogonal to the first cutting lines (76).
8. A method according to claim 7 in its dependence on claim 4, wherein first cutting lines (76) among the first cutting lines (76) extend over second strips (70).
9. A method according to claim 7 in its dependence on claim 6, wherein first cutting lines (76) among the first cutting lines (76) extend between each pair of adjacent third strips (72).
10. A method according to any one of claims 1 to 9, wherein each first strip (BLED) of light-emitting diodes (LEDs) comprises rows of at least two light-emitting diodes (LEDs) perpendicular to the direction of the first strips (BLEDs).
11. Optoelectronic plate (75; 85; 95) comprising a substrate (10) having a face (22) and, on the face (22), wire, conical, or truncated conical light-emitting diodes (LEDs) of micrometric or nanometric size and distributed according to first parallel and distinct bands (BLEDs).
12. Optoelectronic plate (75; 85; 95) according to claim 11, wherein each first strip (BLED) of light-emitting diodes (LEDs) comprises rows of at least two light-emitting diodes (LEDs) perpendicular to the direction of the first strips (BLEDs).
13. Optoelectronic plate (75; 85; 95) according to claim 11 or 12, comprising second bands (70) electrically conductive and parallel to the first bands (BLED), each second band (70) forming a first electrode of the light-emitting diodes (LEDs) of at least one of the first bands (BLED).
14. Optoelectronic plate (75; 85; 95) according to claim 13, comprising electrically conductive third bands (72) and parallel to the first bands (BLED), each third band (72) forming a second electrode of the light-emitting diodes (LED) of at least one of the first bands (BLED).