MICROELECTRONIC DEVICE COMPRISING A NON-CLONABLE PHYSICAL FUNCTION AND ASSOCIATED MANUFACTURING METHOD

Abstract

The present invention relates to a microelectronic device (10) comprising a plurality of resistive memory points, a first part of said resistive memory points being resistive memory points configured to form a so-called "PUF" zone (11) of the device (10), a second part of said resistive memory points being configured to form a so-called "memory" zone (12) of the device, each resistive memory point comprising a first electrode layer (131), a second electrode layer (134), and an active resistive memory layer (133) included between the first (131) and second (134) electrode layers, said microelectronic device (10) being characterized in that each resistive memory point of the PUF zone (11) comprises a carbon layer (132) of a thickness greater than or equal to 3 nanometers which extends between the first electrode layer (131) and the active layer (133). Figure to be published with the abbreviation: Figure 2A.

Description

Title of the invention: MICROELECTRONIC DEVICE COMPRISING A NON-CLONABLE PHYSICAL FUNCTION AND ASSOCIATED MANUFACTURING METHOD FIELD OF INVENTION

[0001] The present invention relates generally to the field of microelectronics. More particularly, it relates to the field of microelectronic devices comprising a non-clonable physical function.

[0002] One object of the invention is a microelectronic device comprising a non-clonable physical function and a storage memory. Another object of the invention is the method for obtaining the device according to the invention. STATE OF THE ART

[0003] Counterfeiting of integrated electronic circuits, or "chips," is a major problem today. Combating chip counterfeiting is a key issue for the microelectronics industry.

[0004] To combat counterfeiting, solutions are sought to authenticate a circuit in order to distinguish whether it is a legitimate circuit (i.e., one that has successfully authenticated) or a counterfeit circuit (i.e., one that has failed). One method consists of using a unique identifier for each circuit and maintaining a database of legitimate identifiers. However, it turns out that it is very easy to emulate—to replay—a valid identifier using a hardware or software virus. Therefore, a unique identifier is not a viable solution because it does not protect against replay attacks.

[0005] Another mechanism, very widely used in the field of information security, is the so-called "challenge-response" mechanism. This mechanism allows authentication to be performed while protecting against replay attacks. A user who wants to authenticate a device using this mechanism must perform the following steps: • the user generates a random number N, N being the challenge; • the user sends N to the circuit; • the circuit calculates R=F(N) from a secret function F, R being the answer; • the circuit responds R to the user; • The user compares R with the expected answer and, if there is a tie, authentication is successful.

[0006] For the challenge-response method to be applicable to a given device, the manufacturer must perform an "enrollment" step at the factory exit, consisting of building a database containing legitimate challenge-response pairs for the given device. Specifically, for each integrated circuit, the tester will generate a certain number of challenges N, send them to the circuit, retrieve each response R, and record the pairs NR in a database. Throughout the chip's lifecycle, a user can authenticate the integrated circuit by performing the following steps: • he requests a database challenge N from the manufacturer; • the chip calculates the response R=F(N); • the user or manufacturer compares this response with the one stored in the database; • The "challenge-response" pair is removed from the database to prevent any replay.

[0007] This authentication takes place via a secure protocol between the database and the integrated circuit. The authentication solution relies on one essential element: the function F. This function must be unique to each chip and unclonable. It is referred to as a physical unclonable function, or "Personal Unclonable Function" (PUF), because an attacker must not be able to physically recreate the function; otherwise, they would be able to create a legitimate clone of the PUF and therefore of the circuit.

[0008] A PUF function must therefore possess several characteristics including a manufacturing process enabling very high inter-chip variability and low intra-chip variability.

[0009] Existing PUF functions are based on random physical elements. For example, one of the very first PUFs (non-silicon) is based on air bubbles found in molten plastic.

[0010] Several techniques have been proposed for obtaining PUFs in the field of microelectronics. Examples include techniques acting at the integrated circuit package level such as "coating" PUFs or "magnetic" PUFs based on the random distribution of resistive or magnetic particles.

[0011] Other techniques operate at the component level and are essentially based on the dispersion of physical characteristics. Among the integrated circuits with a PUF function known to those skilled in the art, we can mention those that exploit signal propagation times, such as ring circuits or arbiter circuits. Alternatively, it is possible to exploit instabilities at startup, for example in Static Random-Access Memory or SRAM devices.

[0012] A known implementation of PUF technology in the field of resistive memories is described in the publication "Error-free Physically Unclonable Function (PUF) with programmed ReRAM using reliable resistance states by Novel ID-Generation method" (Tseng et al. - International Conference on Solid State Devices and Materials 2017). This implementation is based on the use of an array of rewritable non-volatile resistive ReRAM memories, such as memories with a metal oxide active region (OxRAM or "Oxide Resistive RAM" in English terminology). These memories are resistive in type, meaning that they can exhibit at least two resistive states, corresponding to a high resistance state (HRS for "High Resistance State") and a low resistance state (LRS for "Low Resistance State"), under the application of a voltage.The voltage required to transition from an HRS state to an LRS state corresponds to the formation of a conductive filament connecting the two electrodes of each resistive memory location and is also called the "forming" voltage when referring to the initial voltage applied to form the memory location. Subsequently, the voltage is called the "set" voltage to transition the memory from an HRS state to an LRS state.

[0013] The method known to the person skilled in the art consists of applying a given range of tensions and, due to the dispersion of the physical parameters of the memory points, a random matrix of formed and unformed memory points is obtained.

[0014] Although this method makes it possible to obtain a PUF function in a ReRAM memory plane, its implementation is complicated due to the very narrow interrupt window for memory point formation. This risks significantly reducing the randomness of the PUF device, thereby increasing the risk of counterfeiting.

[0015] There is therefore a need to provide a microelectronic device integrating a PUF function and a storage memory function which is reliable and simple to implement, while being very difficult to counterfeit. Summary of the invention

[0016] The invention aims to solve at least partially the problems mentioned above by proposing a microelectronic device comprising two parts of different composition, one intended for the PUF part of the device and ensuring a high dispersion of the physical parameters of the memory points, the other intended for the storage memory part of the device and ensuring the highest possible repeatability of memory performance and ensuring the least possible performance dispersion.

[0017] To this end, a first object of the invention is a microelectronic device comprising a plurality of resistive memory points, a first part of said resistive memory points being resistive memory points configured to provide a non-clonable physical function, the resistive memory points of said first part forming a so-called "PUF" zone of the device, a second part of said resistive memory points being configured to provide a memory function to the microelectronic device, the resistive memory points of the second part forming a so-called "memory" zone of the device, each resistive memory point comprising a first electrode layer, a second electrode layer, and an active resistive memory layer included between the first and second electrode layers, said microelectronic device being characterized in that each resistive memory point of the first part forming the PUF zone comprises a carbon layer of thickness greater than or equal to 3 nanometers which extends between the first electrode layer and the active layer.

[0018] The portion of the medium corresponding to the PUF memory points is understood to be the part of the device intended to provide the PUF function. This part of the device is also called the PUF area or the PUF portion of the device. The storage memory is also called the memory area or the non-PUF area of ​​the device.

[0019] By integrating a carbon layer with a thickness greater than or equal to 3 nanometers between the first electrode layer and the active layer of the resistive memory dots in the PUF region, the microelectronic device according to the invention makes it possible to increase the dispersion of resistances before and after forming. This increased dispersion is essential for generating robust and non-clonable PUF functions, making each device unique and difficult to clone. Indeed, greater dispersion means that resistance values ​​are less predictable and less likely to be replicated. This is made possible by the presence of the carbon layer in the PUF region, which results in higher variability in the electrical properties of the memory dots. This carbon layer is not found in the memory region.

[0020] The device according to the invention further allows the forming voltage window to be widened for the use of a ReRAM memory plane as a PUF device. Therefore, by applying a forming voltage within this widened window, it is possible to obtain the formation of approximately half of the resistive memory points in the PUF area, resulting in good response diversity in the PUF area of ​​the device.

[0021] In other words, the invention makes it possible to widen the forming tension curve window by lowering its slope. This will allow us to target 50% formed memory points and 50% unformed memory points within a matrix, and thus obtain good PUF diversity.

[0022] The device according to the invention makes it possible to avoid the lengthy step of searching for the forming voltage disclosed, for example, in the article by Tseng and co-authors, "Error-free Physically Unclonable Function (PUF) with programmed ReRAM using reliable resistance states by Novel ID-Generation method." Indeed, thanks to the invention, the The dispersion of forming voltages in the PUF zone is very high, which facilitates the search for the forming voltage needed to obtain the formation condition of approximately 50% of the resistive memory points in the PUF zone.

[0023] In addition to the characteristics mentioned in the preceding paragraphs, the microelectronic device according to the invention may have one or more additional characteristics from among the following, considered individually or in all technically possible combinations: • The active layer is an active oxide layer. • the carbon layer has a thickness less than or equal to 5 nanometers. • each resistive memory point of the second part forming the area memory does not include a carbon layer of thickness greater than or equal to 3 nanometers between the first electrode layer and the active layer. • Each resistive memory point in the second part forming the memory area does not include a carbon layer between the first electrode layer and the active layer. • Each resistive memory point is unformed. • the first electrode layer is made of titanium nitride, doped silicon, doped polysilicon, tungsten, tungsten nitride, molybdenum nitride, tantalum nitride, cobalt silicide, nickel silicide, palladium silicide, platinum silicide, titanium silicide, other silicides, nickel, platinum, iridium, ruthenium, or any combination thereof; the second electrode layer is made of titanium nitride, doped silicon, doped polysilicon, tungsten, tungsten nitride, molybdenum nitride, tantalum nitride, cobalt silicide, nickel silicide, palladium silicide, platinum silicide, titanium silicide, in other silicides, in nickel, in platinum, in iridium, in ruthenium, or any combination and the active layer comprises at least one layer in hafnium.

[0024] Another object of the invention is a method for manufacturing a microelectronic device comprising a plurality of resistive memory points, a first part of said resistive memory points being resistive memory points configured to provide a non-clonable physical function, the resistive memory points of said first part forming a so-called "PUF" area of ​​the device, a second part of said resistive memory points being configured to provide a memory function to the microelectronic device, the resistive memory points of the second part forming a so-called "memory" area of ​​the device, said manufacturing method being characterized in that it comprises: • Provision of a support comprising a first layer of electrode; • Deposition of a carbon layer on the first electrode layer; • Removal of the carbon layer in the memory area; • Deposition of an active resistive memory layer; • Deposition of at least a second electrode layer; • Etching of the second electrode layer, the active layer and the first electrode layer so as to define the plurality of resistive memory points.

[0025] In addition to the characteristics mentioned in the preceding paragraphs, the manufacturing process according to another aspect of the invention may have one or more complementary characteristics from among the following, considered individually or in all technically possible combinations: • that the removal of the carbon layer in the memory area includes: • deposition of a protective layer configured to protect the PUF area of ​​the device; • etching the device's memory area to remove the carbon layer in the device's memory area. • The engraving in the device's memory area is a plasma engraving. • The process further includes a step of encapsulating the memory points using at least one dielectric layer. • The process according to the invention includes a step of re-establishing contact on the two electrodes.

[0026] Advantageously, the device according to the invention comprises resistive memory points in the memory portion having very low dispersion of physical properties, ensuring good operation as a storage memory. LIST OF FIGURES

[0027] Other features and advantages of the invention will become clear from the description given below, by way of example and not limitation, with reference to the accompanying figures, among which: • [Fig.1] schematically illustrates a microelectronic device according to the invention. • [Fig.2A] and [Fig.2B] schematically illustrate memory points seen in cross-section of memory points of a microelectronic device according to the invention. • [Fig.3] schematically illustrates resistance dispersions before and after forming in a prior art device. • [Fig.4] schematically illustrates resistance dispersions before and after forming in devices according to the invention. • [Fig.5] schematically illustrates a comparison of resistance dispersions before and after annealing in devices according to the invention. • [Fig.6] schematically illustrates a manufacturing process for a microelectronic device according to the invention. DETAILED DESCRIPTION OF THE INVENTION

[0028] The present invention aims to amplify the resistance dispersion of the PUF areas of resistive memories. This increased dispersion is essential for generating robust and non-clonable PUF functions, making each device unique and difficult to clone. Simultaneously, the memory area of ​​the device, lacking this carbon layer, maintains low resistance dispersion, thus ensuring stable and repeatable performance of the storage memories.

[0029] Fig. 1 represents an example of a microelectronic device 10 according to the invention.

[0030] The device 10 according to the invention comprises a zone 11 comprising a plurality of resistive memory points intended to provide a PUF function and a zone 12 comprising a plurality of resistive memory points intended to provide a memory function.

[0031] Figures 2A and 2B each show an example of a memory point of a microelectronic device 10 according to the invention, viewed in cross-section. As can be seen in Figures 2A and 2B, each memory point is in the form of a stack of layers extending along a z-axis. Layers 131 to 134 form the individual layers of each stack. The individual layers extend parallel to each other (and parallel to a substrate, not shown, on which each memory point rests). The z-axis is perpendicular to the plane of the individual layers of the stack forming each memory point.

[0032] In [Fig.2A] a memory point 13 of the PUF 11 area is shown, and in [Fig.2B] a memory point 14 of the memory area 12 is shown.

[0033] The memory point 13 is a memory point of the PUF area 11 and comprises a first electrode 131, a second electrode 134, a carbon layer 132 and an active layer 133, the carbon layer 132 and the active layer 133 being arranged between the first electrode 131 and the second electrode 134.

[0034] The first electrode 131 forms a lower electrode of the memory point 13. The second electrode 134 forms an upper electrode of the memory point 13. By convention, the terms "lower" and "upper" are used with respect to the substrate on which each memory point is fabricated. Thus, a lower layer of each memory point will designate a layer close to the substrate, while an upper layer will designate a layer opposite and farther from the substrate.

[0035] The first electrode 131 is formed of a conductive and inert material. This conductive material is, in particular, neutral with respect to oxygen atoms. The first electrode 2 comprises, for example, a metallic material. Here, it comprises titanium nitride (TiN). Alternatively, the first electrode 133 may be made of titanium nitride, doped silicon, doped polysilicon, tungsten, tungsten nitride, molybdenum nitride, tantalum nitride, cobalt silicide, nickel silicide, palladium silicide, platinum silicide, titanium silicide, other silicides, nickel, platinum, iridium, ruthenium, or other suitable materials, or any suitable combination of the preceding materials.

[0036] The first electrode 131 has, for example, a thickness between 5 and 200 nanometers (nm).

[0037] According to the invention, and as previously stated, the memory point 13 comprises a carbon layer 132. This carbon layer 132, present only in the memory points 13 of the PUF zone 11, allows for increased resistance dispersion in the memory points 13 of the PUF zone 11. The carbon layer 132 is disposed on the first electrode 131, i.e. in contact with the first electrode 131.

[0038] The carbon layer has a thickness greater than or equal to 3 nanometers. Preferably, the carbon 132 layer also has a thickness less than or equal to 5 nanometers.

[0039] The active layer 133 is disposed on the carbon layer 132, i.e. in contact with the carbon layer 132. The active layer 133 is a layer of active material, preferably of active oxide.

[0040] The active layer 133 comprises a metal oxide or a semiconductor oxide. Preferably, the active layer 133 is based on hafnium dioxide HfO2. In this description, the expression "based on" means that the layer in question comprises more than 50% of the element mentioned after this expression (for example, here it means that the active layer 133 comprises more than 50% hafnium dioxide). The active layer 133 may also be a bilayer, with a layer of hafnium and a layer of another material, for example, aluminum dioxide Al2O3, tantalum dioxide Ta2O5, zirconium dioxide ZrO2, titanium dioxide TiO2, hafnium oxide denoted HfOx with x>=1.8, or any other suitable material.

[0041] Alternatively, the active layer 133 may comprise tantalum(V) oxide Ta2O5 or any other known metal oxide to make such an active layer.

[0042] The active layer 133 has, for example, a thickness of at least 3nm and is preferably between 3 and 10 nm.

[0043] In another embodiment, the active layer 133 may comprise a layer of active material as described above, and an additional layer of dielectric oxide.

[0044] The dielectric oxide layer is adapted to serve as a support for the formation of an electrically conductive filament, which passes completely through the active layer to electrically connect the first electrode 131 to the second electrode 134. This electrically conductive filament can be broken and then reformed several times successively during successive write and reset cycles of the memory point. In practice, this conductive filament is produced for the first time during a kind of controlled electrical breakdown of the active layer (according to a common operation known as "forming").

[0045] The dielectric oxide layer comprises, for example, a metal oxide or a semiconductor oxide. Preferably, it is aluminum oxide Al₂O₃. Alternatively, it may also be silicon dioxide SiO₂.

[0046] The dielectric oxide layer has, for example, a thickness between 0.2 and 2 nm.

[0047] As shown in [Fig. 2A], the second electrode 134 (or upper electrode) is arranged on the active layer 133. It is, for example, in the form of a bilayer structure. It comprises, for example, a first conductive layer 1341 and a second conductive layer 1342.

[0048] The second conductive layer 1342 is disposed on the first conductive layer 1341. The second conductive layer 1342 is formed of a conductive material comprising a transition metal. This conductive material is, for example, titanium nitride (TiN). Alternatively, the second electrode 134 may be made of titanium nitride, doped silicon, doped polysilicon, tungsten, tungsten nitride, molybdenum nitride, tantalum nitride, cobalt silicide, nickel silicide, palladium silicide, platinum silicide, titanium silicide, other silicides, nickel, platinum, iridium, ruthenium, or other suitable materials, or any suitable combination of the preceding materials.

[0049] The second conductive layer 1342 has a thickness between 5 and 200 nm.

[0050] The second conductive layer 1342 comprises, for example, a plurality of conductive layers.

[0051] The second conductive layer 1342 plays both the role of a protective layer (preventing in particular total oxidation of the first conductive layer 1341), and the role of a contact layer allowing the memory point 13 to be electrically connected to its electronic control and reading circuit.

[0052] The first conductive layer 1341 is disposed on the active layer 133. It is in direct contact with the active layer 133.

[0053] The first conductive layer 1341 has the particularity of being a layer adapted to create oxygen gaps in the active layer 133 when this first conductive layer 1341 is in contact with the active layer 133. According to the commonly used Anglo-Saxon term of origin, the first conductive layer is an "Oxygen scavenging layer".

[0054] The first conductive layer 1341 comprises a metallic conductive material. Preferably, it comprises titanium Ti, tantalum Ta or hafnium Hf.

[0055] For example, when the second conductive layer 1342 comprises titanium nitride, the first conductive layer 1341 is formed of a conductive material chosen from titanium Ti or hafnium Hf.

[0056] Alternatively, when the second conductive layer 1342 comprises tantalum nitride, the first conductive layer 1341 is formed of a conductive material selected from tantalum Ta or hafnium Hf.

[0057] Alternatively, when the second conductive layer 1342 comprises tungsten, the first conductive layer 1341 is formed of a conductive material chosen from titanium Ti, tantalum Ta or hafnium Hf.

[0058] For example, the thickness of the first conductive layer 1341 is between 3 and 20 nm.

[0059] The memory point 14 shown in [Fig. 2B] is a memory point of the memory area 12 and comprises a first electrode 131, a second electrode 134, and an active layer 133 arranged between the first electrode 131 and the second electrode 134. Thus, the description of the layers 131, 133, and 134 of the memory point 13 also applies to the memory point 14. Unlike the memory point 13, the memory point 14 does not include a carbon layer 132. Thus, none of the memory points 14 of the memory area 12 include a carbon layer 132, unlike the memory points 13 of the PUF area 11, which all include a carbon layer 132. This makes it possible to obtain a device 10 that simultaneously includes a PUF function and a storage memory function.

[0060] Tests were carried out to obtain resistance dispersions with and without a carbon layer. The results of these tests are shown in Figures 3 and 4.

[0061] Fig. 3 shows a schematic representation of the cumulative distribution of the resistance values ​​obtained, illustrated by an empirical cumulative distribution function (ECDF), for a memory point in the memory area, i.e. without a carbon 132 layer.

[0062] Figure 4 shows two schematic representations of the cumulative distribution of the resistance values ​​obtained, illustrated by a cumulative distribution function empirical (ECDF), on the left for a memory point in the PUF 11 area comprising a 3 nanometer thick layer of carbon 132 and on the right for a memory point in the PUF 11 area comprising a 5 nanometer thick layer of carbon 132.

[0063] In each of the representations of Figures 3 and 4, the curve “BF” represents the cumulative distribution of the resistances of the memory points of the device 10 according to the invention after forming, that is to say after application of a forming voltage, therefore when the memory points are formed.

[0064] In each of the representations of Figures 3 and 4, the curve “AF” represents the cumulative distribution of the resistances of the memory points of the device 10 according to the invention before forming, that is to say before application of a forming voltage, therefore when the memory points are not formed.

[0065] The stacks used had a top electrode 134 made of titanium nitride TiN, a bottom electrode of titanium Ti of 5 nm coated with titanium nitride TiN and an active layer of silicon-doped hafnium HfO2 of 5 nm.

[0066] As shown in Figure 4, the resistance before AF forming in the left-hand portion (with the 3-nanometer C layer) is much more dispersed than in Figure 3 (without the C layer), since the resistance distribution ranges from 5 × 10² Ohms to 10¹⁰ Ohms, whereas in Figure 3, the resistance distribution ranges from 10⁷ Ohms to 10¹⁰ Ohms. Similarly, the resistance before AF forming in the right-hand portion (with the 5-nanometer C layer) is much more dispersed than in Figure 3 (without the C layer), since the resistance distribution ranges from 10 Ohms to 10¹³ Ohms.

[0067] To use the PUF function, it is then sufficient to apply a low voltage to a memory point, for example on the order of 0.1 to 0.2 Volts, and read the associated resistance. This voltage must be low enough not to change the state of the memory point, that is to say, not to cause a transition between the resistive states (HRS for "High Resistive State" and LRS for "Low Resistive State").

[0068] As shown in Figure 4, the resistance after forming BF in the right part (with the 5 nanometer C layer) is much more dispersed than in Figure 3 (without C layer), since the resistance distribution goes from 10 Ohms to 13 Ohms while in Figure 3, the resistance distribution after forming extends from 10 Ohms to 5*104 Ohms.

[0069] Thus, the invention even allows the PUF function of the device 10 to be used before the memory points have been formed, that is, before forming, therefore before the application of a forming voltage, a forming voltage being, for example, on the order of 1 to 5V. Indeed, before forming, as represented by the AF BF curves, the resistances are also very dispersed, a particularly remarkable fact in the case of a carbon-132 layer with a thickness of 5 nanometers. It is therefore possible, thanks to this increased dispersion, by using the PUF function of the microelectronic device 10 before and after forming, contrary to the prior art, in which the dispersion of resistances before forming is too concentrated.

[0070] It has also been noted, as shown in [Fig.5], that the dispersions obtained change shortly after annealing at 150° Celsius for 1 hour.

[0071] The present invention also relates to a manufacturing method 20 for a microelectronic device 10. Figure 6 represents, in the form of a flowchart, an example of a manufacturing method according to the invention.

[0072] The method 20 according to the invention includes a step 21 of providing a support comprising a first electrode layer 131. The first electrode layer 131 is the first layer of resistive memory points. The support is common to the PUF zone 11 and the memory zone 12 of the device 10. In one embodiment, step 201 comprises the deposition of the first electrode layer 131, for example by PVD (Physical Vapor Deposition). The first electrode layer 131 may, for example, be in the form of vias, or be etched simultaneously with the top electrode, the active layer, and the bottom electrode.

[0073] According to the invention, the process 20 comprises a second step 22 of depositing a layer of carbon 132 onto the first electrode layer 131. The deposition is preferably carried out by PVD. This layer of carbon 132 is, for example, deposited over the entire support provided in step 201.

[0074] The deposited carbon layer has a thickness greater than or equal to 3 nanometers. The carbon 132 layer deposited in step 22, for example, has a thickness less than or equal to 5 nanometers.

[0075] The method 20 according to the invention includes a step 23 for removing the carbon layer 132 from the memory area 12 of the device 10. For this purpose, the PUF area 11 is protected. Thus, step 23 includes a substep 23a for protecting the portion of the support corresponding to the PUF area of ​​the device 10. Advantageously, this protection step then allows the carbon layer to be selectively removed from the memory area 12 during a substep 23b.

[0076] According to one embodiment, substep 23a is a lithography step comprising spreading a resin, exposing it to light using a mask, and removing, or "stripping" according to English terminology, the resin after an etch has been made in substep 23b. Advantageously, substep 23a makes it possible to cover with a layer of resin the PUF 11 area for which the carbon layer does not need to be removed during the etching substep 23b.

[0077] The removal of the carbon 132 layer is carried out by etching in substep 23b. According to one embodiment, the etching substep 23b in the area Memory 12 of device 10 is etched using plasma etching. The resin is then removed. Thus, at the end of step 23, a carbon 132 layer is present only in the portion of the substrate corresponding to the PUF 11 area of ​​device 10, and is absent from the portion of the substrate corresponding to the memory 12 area of ​​device 10.

[0078] The method 20 according to the invention further comprises a step 24 of depositing the active layer 133 on the entire support, i.e., on the lower electrode layer 131 in the part of the support corresponding to the memory area 12, and on the carbon layer 132 in the part of the support corresponding to the PUF area 11. According to one embodiment this step comprises the deposition of a hafnium HfO2 layer, for example by atomic layer deposition (ALD) or by PVD.

[0079] The method 20 according to the invention further comprises a step 25 of depositing a second layer of electrode 134, for example by PVD. In one embodiment, this step comprises the deposition of a layer of Ti or TiN or both.

[0080] The method 20 according to the invention further comprises a step 26 of etching the second electrode layer 134, the active layer 133, the carbon layer 132 when present, and then the first electrode layer 131, so as to define the plurality of resistive memory points.

[0081] Advantageously, this step makes it possible to obtain the resistive memory points of the PUF 11 area and the resistive memory points of the memory area 12.

[0082] The method 20 according to the invention further comprises an encapsulation step 27 of the memory points using a dielectric layer.

[0083] According to one embodiment, the encapsulation step 27 comprises encapsulation in several dielectric layers. Examples of dielectric materials used in step 27 are SiN and SiO2.

[0084] During steps 24 of deposition of the active layer 133, 25 of the second electrode layer 134 or upper electrode, and then 26 of definition of the memory points, the two PUF 11 and memory 12 areas are treated identically, with the deposition of the materials constituting the active layer 133, for example HfO2, the upper electrode 134, for example Ti, TiN, and the definition of the patterns constituting the memory points throughout the cell. According to one embodiment, a SiN-type dielectric serving as a hard mask can also be used during the lithography step.

[0085] Finally, according to one embodiment, vias can be used to resume contacts on the memory points of the PUF 11 area and the memory area 12.

Claims

Demands

1. A microelectronic device (10) comprising a plurality of resistive memory points, a first part of said resistive memory points being resistive memory points configured to provide a non-clonable physical function, the resistive memory points of said first part forming a so-called "PUF" area (11) of the device (10), a second part of said resistive memory points being configured to provide a memory function to the microelectronic device (10), the resistive memory points of the second part forming a so-called "memory" area (12) of the device, each resistive memory point comprising a first electrode layer (131), a second electrode layer (134), and an active resistive memory layer (133) included between the first (131) and second (134) electrode layers,said microelectronic device (10) being characterized in that each resistive memory point of the first part forming the PUF zone (11) comprises a carbon layer (132) of thickness greater than or equal to 3 nanometers which extends between the first electrode layer (131) and the active layer (133).

2. Microelectronic device (10) according to claim 1 characterized in that the active layer (133) is an oxide-based layer.

3. Microelectronic device (10) according to any one of the preceding claims characterized in that the carbon layer (132) has a thickness less than or equal to 5 nanometers.

4. Microelectronic device (200) according to any one of the preceding claims characterized in that each resistive memory point of the second part forming the memory area does not include a carbon layer between the first electrode layer (131) and the active layer (133).

5. Microelectronic device (200) according to any one of the preceding claims characterized in that each resistive memory point is unformed.

6. Microelectronic device (200) according to any one of the preceding claims, characterized in that the first (131) electrode layer is made of titanium nitride, doped silicon, doped polysilicon, tungsten, tungsten nitride, molybdenum nitride, tantalum nitride, cobalt silicide, nickel silicide, in palladium silicide, platinum silicide, titanium silicide, other silicides, nickel, platinum, iridium, ruthenium, or any combination, the second (134) electrode layer is titanium nitride, doped silicon, doped polysilicon, tungsten, tungsten nitride, molybdenum nitride, tantalum nitride, cobalt silicide, nickel silicide, palladium silicide, platinum silicide, titanium silicide, other silicides, nickel, platinum, iridium, ruthenium, or any combination and in that the active layer (133) comprises at least one hafnium layer.

7. A manufacturing method (20) for a microelectronic device (10) comprising a plurality of resistive memory points, a first part of said resistive memory points being resistive memory points configured to provide a non-clonable physical function, the resistive memory points of said first part forming a so-called "PUF" area (11) of the device (10), a second part of said resistive memory points being configured to provide a memory function to the microelectronic device (10), the resistive memory points of the second part forming a so-called "memory" area (12) of the device (10), said manufacturing method (20) being characterized in that it comprises: - Providing (21) a support comprising a first electrode layer (131); - Depositing (22) a carbon layer (132) on the first electrode layer (131); - Removal (23) of the carbon layer (132) in the memory area (12);- Deposition (24) of an active layer (133) of resistive memory; - Deposition (25) of at least a second electrode layer (134); - Etching (26) of the second electrode layer, the active layer and the first electrode layer so as to define the plurality of resistive memory points.

8. A method (20) for manufacturing a microelectronic device (10) according to the preceding claim, characterized in that the removal (23) of the carbon layer in the memory area comprises: - deposition (23a) of a protective layer configured to protect the PUF area (11) of the device (10); - etching (23b) of the memory area (12) of the device (10) to remove the carbon layer (132) in the memory area (12) of the device (10).

9. Method (20) of manufacturing a microelectronic device (10) according to the preceding claim characterized in that the etching (23b) in the memory area (12) of the device (10) is a plasma etching.

10. A method (20) for manufacturing a microelectronic device (10) according to any one of the preceding claims characterized in that it further comprises a step of encapsulating the memory points using at least one dielectric layer.

Images