Wide input range probabilistic bit device

Abstract

The invention relates to a probabilistic (p-bit) bit generator (D1) comprising: a magnetic tunnel junction (MTJ) having a resistance that fluctuates between at least two distinct resistive states (P, AP) depending on its magnetization; a biasing circuit (POL) configured to inject a control current (Ic) through the magnetic tunnel junction, which varies according to a first input voltage (Vin1); the biasing circuit (POL) comprising: a control transistor (T1) mounted in series with the magnetic tunnel junction between two power supply nodes and comprising an insulating layer (BOX) embedded in a semiconductor substrate (2) forming a back gate (G2, T1); control means (CONT) configured to apply the first input voltage (Vin1) to said back gate; a detection circuit (DET) configured to generate a detection signal (s1) that varies according to the resistive state of the magnetic tunnel junction. Figure for the abstract: Fig. 2a

Description

Title of the invention: Wide input range probabilistic bit device

[0001] The invention relates to a probabilistic bit device based on a stochastic unit consisting of a magnetic tunnel junction. More particularly, the invention relates to a specific control architecture for the stochastic unit that allows the input range of the probabilistic bit device to be extended.

[0002] A probabilistic bit generator is a device that generates a series of bits (binary outputs of type 0 or 1) randomly based on physical or quantum phenomena, thus ensuring a specific level of randomness or entropy. Unlike classical devices that produce deterministic results, this type of device produces a 0 or a 1 according to a probability that can be adjusted to suit the application's needs. This type of probabilistic output is essential in fields such as cryptography, probabilistic algorithms, and simulations, where the generation of random binary values ​​guarantees the security or representativeness of calculations.This means that instead of consistently producing a 0 or a 1 in a deterministic manner, the device generates a series of bits over a predetermined period in which the distribution between 0s and 1s can be controlled or predefined via input parameters. For example, one could define a probability of 0.7 for obtaining a 1 and 0.3 for obtaining a 0, which would produce a distribution in a series of bits (bit word) where approximately 70% of the bits are 1s and 30% are 0s. This probabilistic distribution distinguishes the probabilistic bit generator from pseudo-random number generators, as it relies on sources of physical uncertainty (such as quantum, thermal, or magnetic noise), producing genuine randomness at the bit level.

[0003] Probabilistic bit-generating devices based on magnetic tunnel junctions present a promising solution for exploiting fluctuations in the magnetic polarization state in such a structure. Figure 1a illustrates the electrical diagram of a prior art probabilistic bit generator D0. The probabilistic bit generator D0 comprises a magnetic tunnel junction MTJ, a control transistor T0, and a comparator COMP. The magnetic tunnel junction MTJ is a magnetoresistive pillar comprising a stack of layers 11, 12, 13. The stack includes a first ferromagnetic reference layer 11 in which the direction of the magnetic polarization is fixed and uniform. The stack further includes a second ferromagnetic layer 13 in which the direction of the The magnetic polarization is variable. The stack also includes a barrier layer 12 of oxide confined between the first and second ferromagnetic layers 11, 13. The barrier layer 12 plays a crucial role in magnetoresistive tunneling, allowing electrons to pass through by quantum tunneling. The first ferromagnetic layer 11 serves as a reference for detecting changes in magnetization in the free ferromagnetic layer 13. The operating principle of the magnetoresistive MTJ pillar is based on the change in electrical resistance as a function of the magnetic polarization orientation of the free ferromagnetic layer 13 relative to that of the reference ferromagnetic layer 11. When the magnetizations of the free and reference layers 11, 13 are parallel, the electrical resistance is low, and this is referred to as a low-resistance state P.When the magnetizations are antiparallel, the electrical resistance is high, and this is referred to as a high AP resistive state. The design of the magnetic tunnel junction (MTJ) is such that the magnetic moments of the layers fluctuate between different orientations under the influence of thermal fluctuations, even in the absence of an external magnetic field. These fluctuations are sufficiently large compared to the energy barrier separating the two resistive states that the magnetization is no longer stable in a fixed direction. This is referred to as "fluctuation regime" or a "superparamagnetic" state, unlike magnetoresistive memories where the magnetic layers retain their orientation after programming.Indeed, in a magnetoresistive memory, the energy barrier between the two resistive states is beyond the reach of thermal energy with an amplitude greater than 40xkbT, where kb is the Boltzmann constant and T is the operating temperature of the memory. The operation of the MTJ superparamagnetic tunnel junction is illustrated by the energy diagram in [Fig. 1b], which shows a first resistive state P and a second resistive state AP separated by an energy barrier AE less than or equal to ten times the thermal energy kbT, where kb is the Boltzmann constant and T is the operating temperature of the DO generator. The respective probability of generating 0 bits (high resistive state or vice versa, depending on the chosen convention) and 1 bits (low resistive state or vice versa, depending on the chosen convention) by the MTJ magnetic tunnel junction depends on the intensity of the bias current flowing through it. The current intensity is regulated by the control transistor To, which is connected in series with the magnetic tunnel junction MTJ between a power supply node providing the supply voltage VDD and ground GND. The comparator COMP is configured to compare the voltage drop across the magnetic tunnel junction with a reference voltage VreF, in order to continuously determine the random resistive state of said magnetic tunnel junction.

[0004] The bias current le is controlled by the input voltage Vin applied to the gate of the control transistor To. The control transistor To is a CMOS transistor. The input voltage Vin is advantageously chosen to operate in linear or ohmic mode. Increasing the input voltage Vin increases the bias current le. Increasing the bias current le increases the probability P(l) of having a high resistive state AP (equivalent to a "1" bit according to the chosen convention). Conversely, decreasing the bias current le increases the probability P(0) of having a low resistive state P (equivalent to a "0" bit according to the chosen convention). In this context, a major technical problem is encountered, namely limiting the input dynamic range for controlling the distribution of "1"s and "0"s in the generated bit sequence.Let Vinmin be the control voltage required to obtain the distribution of P(0) = 99% and P(l) = l%, where P(0) is the probability of having a 0 bit and P(1) is the probability of having a 1 bit. Let Vinmax be the control voltage required to obtain the distribution of P(0) = l% and P(l) = 99%. The dynamic range of the input voltage Vn is thus defined by Vinmax - Vinmin. In state-of-the-art solutions, the input dynamic range is very limited, with an amplitude less than or equal to 0.2V. This drastically limits the stability and accuracy of the probabilistic bit generator.

[0005] To overcome the limitations of existing solutions, the invention proposes a probabilistic bit generator in which the tunnel junction is controlled by a voltage on the back gate of a transistor on SOI so as to broaden the input dynamic range and thus have better control over the probability of obtaining a high or low resistive state. The generator according to the invention makes it possible to achieve dynamic ranges on the order of IV, which represents a 5-fold increase compared to the dynamic ranges observed for prior art solutions. Summary / Claims

[0006] The invention relates to a probabilistic bit generator comprising: - a magnetic tunnel junction having a resistance that fluctuates between at least two distinct resistive states depending on its magnetization; - a biasing circuit configured to inject a control current through the magnetic tunnel junction, which varies according to a first input voltage; the biasing circuit comprising: • a control transistor mounted in series with the magnetic tunnel junction between two power nodes and comprising an insulating layer buried in a semiconductor substrate forming a back gate; - control means configured to apply the first input voltage to said rear grid; - a detection circuit configured to generate a detection signal that varies according to the resistive state of the magnetic tunnel junction.

[0007] According to a particular aspect of the invention, the magnetic tunnel junction is a super-paramagnetic tunnel junction.

[0008] According to a particular aspect of the invention, the control transistor is a "totally deserted silicon-on-insulator" transistor.

[0009] According to a particular aspect of the invention, the detection circuit is a comparator having a first input connected to a first end of the magnetic tunnel junction and a second input intended to receive a reference voltage and an output node to generate the detection signal.

[0010] According to a particular aspect of the invention, the generator further comprises a computing circuit configured to generate a probabilistic bit from the detection signal by sampling or by averaging calculation by determining the proportion of each resistive state of the magnetic tunnel junction during a predetermined period.

[0011] According to a particular aspect of the invention, the magnetic tunnel junction comprises: - a first ferromagnetic reference layer in which the direction of the magnetic polarization is fixed; - a second ferromagnetic layer in which the direction of magnetic polarization is variable; - a tunnel barrier layer of oxide confined between the first and second ferromagnetic layers.

[0012] According to a particular aspect of the invention, the thickness of the second layer is less than 10 nm.

[0013] According to a particular aspect of the invention, the diameter of the magnetic tunnel junction is less than 100 nm.

[0014] According to a particular aspect of the invention, the control transistor is mounted as a diode.

[0015] According to a particular aspect of the invention, the biasing circuit is a current mirror comprising a first power supply branch coupled to a second power supply branch comprising at least the control transistor and the magnetic tunnel junction mounted in series.

[0016] According to a particular aspect of the invention, the first power supply branch comprising a second control transistor having a second buried insulating layer forming an associated back gate, the control means being configured to apply a second input voltage to the back gate of the second control transistor.

[0017] Other features and advantages of the present invention will become more apparent from the following description in relation to the following accompanying drawings.

[0018] Figure [1a] illustrates a state-of-the-art probabilistic bit DO generator. This figure has already been described.

[0019] Figure 1b illustrates an energy diagram of the probabilistic bit generator D0 according to the state of the art. This figure has already been described.

[0020] Figure [Fig. 2a] illustrates a probabilistic bit DI generator according to a first embodiment of the invention.

[0021] Fig. 2b illustrates cross-sectional views of the implementation of four different FDSOI-type transistors.

[0022] Figure [Fig. 3] illustrates a probabilistic bit DI generator according to a second embodiment of the invention.

[0023] Figure 4 illustrates a probabilistic bit DI generator according to a third embodiment of the invention.

[0024] Figure 5 illustrates a probabilistic bit DI generator according to a fourth embodiment of the invention.

[0025] Figure 6 illustrates the probability of a high logic state “1” as a function of the input voltage for the generator according to the invention compared to a generator according to the prior art.

[0026] Figure 2a illustrates a probabilistic bit DI generator according to a first embodiment of the invention. The p-bit probabilistic bit DI generator comprises a magnetic tunnel junction MTJ, a biasing circuit POL, a detection circuit DET, and a computing circuit CALC. The magnetic tunnel junction MTJ is dimensioned to operate in a fluctuating regime in response to thermal agitation. The magnetic tunnel junction MTJ is formed by a stack of layers. The stack comprises a first reference ferromagnetic layer 11 in which the direction of the magnetic polarization is fixed and uniform. The stack further comprises a second ferromagnetic layer 13 in which the direction of the magnetic polarization is variable. The stack further comprises a barrier oxide layer 12 confined between the first and second ferromagnetic layers 11, 13.The diameter (or diagonal, depending on the shape) of the MTJ magnetic tunnel junction is less than 100 nm. More advantageously, the thickness of the second layer 13 is less than 10 nm. This allows the energy barrier separating the first resistive state P and the second resistive state AP to be lowered to a value less than or equal to ten times the thermal energy kbT, thus enabling the realization of a super-paramagnetic MTJ tunnel junction. As a reminder, a super-paramagnetic tunnel junction exhibits a fluctuating resistive state where the magnetization is unstable under thermal influence.

[0027] The POL biasing circuit is configured to inject a control current through the MTJ magnetic tunnel junction so as to control the distribution between the two resistive states of the MTJ super-paramagnetic tunnel junction. The POL biasing circuit is formed by a control transistor Ti mounted in series with the MTJ magnetic tunnel junction between a power supply node providing the supply voltage VDD and electrical ground GND. The control transistor Ti is implemented on an insulating layer embedded in the substrate using SOI technology, an acronym for Silicon-on-Insulator, and more advantageously on an FDSOI (Fully Depleted Silicon-on-Insulator) substrate. For a better understanding of the invention, [Fig.Figure 2a illustrates cross-sectional views of the implementation of four different FDSOI transistors. Diagram 101 is a Regular VT (RVT) NMOS transistor. Diagram 102 is a Regular VT (RVT) PMOS FDSOI transistor. Diagram 103 is a Low VT (LVT) NMOS FDSOI transistor. Diagram 104 is a Low VT (RVT) PMOS FDSOI transistor. The transistor 11 in the scheme 101 of type NMOS-RVT according to the FDSOI technology is made on a substrate 2 based on P-doped semiconductor. A layer of insulating dielectric material, generally an oxide denoted BOX, separates the assembly composed of the N-doped regions forming the drain D and the source S and the region of the semiconductor 3 containing the conduction channel from the rest of the substrate 2.A control gate G1 is obtained by superimposing an oxide layer and a metallic layer on region 3 of the conduction channel, similar to the gate of a MOS transistor on a bulk semiconductor substrate. Lateral oxide insulation trenches (STI) are added to each side of transistor 11 to provide electrical isolation for the component. Layers of conductive material, usually metallic, are deposited on the gate G1, the drain D, and the source S to allow electrical connection to these terminals. Additionally, a further terminal G2 is added by depositing a metallic layer on the region bounded by two lateral insulation trenches (STI) adjacent to transistor 11. Applying an electrical voltage to terminal G2 biases the buried oxide layer BOX, which acts as a back gate. This allows the threshold voltage Vth of transistor 1 to be varied.This operation is commonly referred to by the English term "back-biasing." The PMOS-RVT transistor 12 in schematic 102 has exactly the same structure as the one in schematic 101, except for the doping distribution, since it is a PMOS transistor. Substrate 2 is N-doped, while drain D and source S are P-doped. Regarding the NMOS-LVT transistor 13, the only difference with the transistor... 11 of diagram 101 is the inversion of the doping type of the N-doped substrate 2. Regarding the PMOS-LVT type transistor 14, the only difference with the transistor 12 of diagram 102 is the inversion of the doping type of the P-doped substrate 2. In general, the invention can be realized by SOI type transistors or by any transistor having an insulating layer buried in the substrate whose conductance can be controlled via a back gate connected to the buried insulating layer.

[0028] In the probabilistic bit DI generator according to the invention, increasing the bias current induces an increase in the probability P(l) of having a high resistive state AP (equivalent to a "1" bit). Conversely, decreasing the bias current induces an increase in the probability P(0) of having a low resistive state P (equivalent to a "0" bit). The control of the bias current le is achieved by applying an input voltage Vinl to the rear gate G2,n of the control transistor Ti. The DI generator includes control means CONT configured to apply the variable input voltage Vinl to the rear gate G2,n and a fixed bias voltage VpoL to the front gate Gl,Ti of the control transistor Tb. The bias voltage VpoL is chosen such that the control transistor operates in ohmic mode to ensure linear behavior of the generator.Applying the input voltage Vinl to the back gate G2,n modifies the threshold voltage V* of the transistor Ti, allowing finer control of the control current variation le and thus more precise control of the distribution within the probabilistic p-bit. In the control transistor Tb, the back gate is formed by the buried dielectric layer BOX, controlled by the terminal G2,Ti. The buried dielectric layer BOX has a much lower capacitance compared to the front gate G1jTi of the transistor TL. The thickness of the buried insulating layer BOX is less than or equal to 25 nm.The reduced capacitance allows for more precise control of the back-gate bias G2,n, which in turn allows for precise adjustment of the threshold voltage Vth of the control transistor Tb II. Consequently, by adjusting the back-gate voltage G2,n, it becomes possible to obtain finer control of the positive slope of the sigmoid response at the output of the probabilistic bit generator, thus improving the overall sensitivity of the device. This results in a much wider input dynamic range Vin >max - Vin min with an amplitude up to IV.

[0029] The control transistor Ti can be an NMOS or PMOS type transistor. The control transistor Ti can be an LVT or RVT type FDSOI transistor.

[0030] The DET detection circuit is configured to generate a detection signal that varies according to the resistive state of the magnetic tunnel junction MTJ. The DET detection circuit includes a comparator COMP to compare the voltage drop across the magnetic tunnel junction MTJ with respect to a predetermined reference voltage VRFF. The magnetic tunnel junction MTJ and the control transistor Ti form a voltage divider. The comparator COMP has a first input connected to the common node between the magnetic tunnel junction MTJ and the control transistor Ti; and a second input receiving the reference voltage VreF. When the magnetic tunnel junction MTJ is in a high resistive state AP, the voltage received by the first input of the comparator is less than the reference voltage V^ and the comparator generates an output voltage equal to VDD, equivalent to a bit equal to "1". When the magnetic tunnel junction MTJ is in a low resistive state P, the voltage received by the first input of the comparator is greater than the reference voltage VRuCt and the comparator generates an output voltage equal to 0, equivalent to a bit equal to "0".

[0031] Alternatively, the DET detection circuit includes an inverter instead of the COMP comparator. The inverter includes an input connected to the common node between the magnetic tunnel junction MTJ and the control transistor Th. When the magnetic tunnel junction MTJ is in a high resistive state AP, the voltage received by the inverter is less than its switching threshold voltage. The inverter generates an output signal equal to VDD, equivalent to a bit equal to "1". When the magnetic tunnel junction MTJ is in a low resistive state P, the voltage received by the inverter is greater than its switching threshold voltage, and the inverter generates an output voltage equal to 0, equivalent to a bit equal to "0".

[0032] The CALC computer circuit is configured to generate a probabilistic bit from the detection signal by determining the proportion of each resistive state of the magnetic tunnel junction MTJ during a predetermined period. The computer circuit is configured to calculate the distribution between bits in a logic high state "1" and bits in a logic low state "0" in a bit sequence corresponding to the detection signal for a predetermined duration. For example, the CALC computer circuit is configured to sample the detection output every 1 ns for a period of 1 Ops. The number of bits in "1" (or bits in "0") is calculated during the period of 1 Ops, which corresponds to a sample of 10,000 logic bits to determine the proportion of bits in "1" and "0" that corresponds to the probabilistic bit p-bit = (P(1),P(0)).

[0033] Alternatively, the CALC computer circuit is configured to calculate the average of the detection signal over the duration of the period. The average is proportional to the number of bits equal to "1" during the sampled period.

[0034] Figure 3 illustrates a probabilistic bit DI generator according to a second embodiment of the invention. The second embodiment retains the same technical characteristics and advantages detailed for the first embodiment. The second embodiment differs from the first in that the control transistor Ti is mounted as a diode. Mounting the control transistor Ti as a diode, while maintaining the application of the input voltage Vini, improves the stability and linearity of the DI generator according to the invention.

[0035] Figure 4 illustrates a probabilistic bit DI generator according to a third embodiment of the invention. The third embodiment retains the same technical characteristics and advantages detailed for the first embodiment. In the DI generator according to the third embodiment, the biasing circuit POL is implemented by a current mirror capable of copying a reference current in another branch of the circuit with high accuracy. The current mirror comprises a first supply branch BA1 coupled to a second supply branch BA2. The first branch includes a PMOS transistor T3 mounted in series with an NMOS transistor T2 configured as a diode. Transistor T3 receives a bias voltage VP0L on its front gate GljT3 to set the current Iref. The front gate GljT2 is connected to that of the control transistor T1 to couple the two supply branches BA1, BA2.The rear gate G2 of the control transistor T1 receives the input voltage Vini generated by the control circuit CONT, which allows for more precise modulation of the current intensity flowing through the second power supply branch BA2 over a wider dynamic input range up to IV.

[0036] Figure 5 illustrates a probabilistic bit DI generator according to a fourth embodiment of the invention. The fourth embodiment retains the same technical characteristics and advantages detailed for the third embodiment. In the DI generator according to the fourth embodiment, the transistor T2 of the first branch also receives on its rear gate G2jT2 a second input voltage Vin2 generated by the control circuit CONT. This allows for dual control of the probability of bits in the logic high state "1" in the generated bit sequence. This embodiment has the advantage of facilitating the recovery of an operating point of the circuit when the bias voltage VpoL fluctuates by symmetrically adjusting the two transistors T1, T2 of the current mirror.

[0037] Fig. 6 illustrates the probability of a high logic state "1" as a function of the input voltage for the generator according to the invention on curve (601) compared to a generator according to the state of the art on curve (602).

[0038] On curve (602), the probability is almost zero for input voltage values ​​Vin between 0V and 0.4V. The probability is greater than 0.9 from an input voltage Vin of 0.6V. The observed input dynamic range for a generator according to the state of the art is thus equal to 0.2V. The slope of variation between the state P(l)=l% and P(l)=99% is steep, which limits the possibility of controlling the probability of output. On curve (601), the probability is almost zero for input voltage values ​​Vin i between 0V and 0.1V. The probability is greater than 0.9 from an input voltage Vin i of 1.1V. The observed input dynamic range for a generator according to the invention is thus equal to 0.1V. The slope of variation between the state P(l)=l% and P(1)=99% has been reduced, allowing for more precise control of the output probability.

[0039] The probabilistic bit generator according to the invention exploits the stochastic properties of a magnetic tunnel junction (MTJ) to produce random or pseudo-random bits with a controlled distribution. Unlike conventional generators, it uses a solid-state (SOI) transistor, and more advantageously an FDSOI transistor, to precisely adjust the control current of the MTJ, thus modulating the probability of obtaining a high or low resistive state. This mechanism allows for bit generation directly influenced by variations in the input voltage, offering a compact, precise, and energy-efficient solution, particularly well-suited to embedded technologies. This innovation improves dynamic range and stability compared to existing solutions, thereby expanding applications in cryptography, artificial intelligence, and neuromorphic systems.

Claims

Demands

1. Probabilistic bit (p-bit) generator (Dl) comprising: - a magnetic tunnel junction (MTJ) having a resistance that fluctuates between at least two distinct resistive states (P, AP) according to its magnetization; - a biasing circuit (POL) configured to inject a control current (le) through the magnetic tunnel junction (MTJ) which varies according to a first input voltage (Vini); the biasing circuit (POL) comprising: • a control transistor (Ti) mounted in series with the magnetic tunnel junction (MTJ) between two power supply nodes (VDD, GND) and comprising an insulating layer (BOX) embedded in a semiconductor substrate (2) forming a back gate (G2,T1); - control means (CONT) configured to apply the first input voltage (Vini) to said back gate (G2,T1);- a detection circuit (DET) configured to generate a detection signal (si) that varies according to the resistive state of the magnetic tunnel junction (MTJ).;

2. Probabilistic bit (p-bit) generator (Dl) according to claim 1 wherein the magnetic tunnel junction (MTJ) is a super-paramagnetic tunnel junction.

3. Probabilistic bit (p-bit) generator according to any one of claims 1 or 2 wherein the control transistor (Tl) is a "silicon-on-insulator-fully-deserted" transistor.

4. Probabilistic bit (p-bit) generator (Dl) according to any one of claims 1 to 3 wherein the detection circuit (DET) is a comparator (COMP) having a first input connected to a first end of the magnetic tunnel junction (MTJ) and a second input for receiving a reference voltage (Vref) and an output node for generating the detection signal (si).

5. Probabilistic bit (p-bit) generator (Dl) according to any one of claims 1 to 4 further comprising a computing circuit (CALC) configured to generate a probabilistic bit from the detection signal (if) by sampling or by averaging calculation by determining the proportion of each resistive state of the magnetic tunnel junction (MTJ) during a predetermined period.

6. Probabilistic bit (p-bit) generator (Dl) according to any one of claims 1 to 5 wherein the magnetic tunnel junction (MTJ) comprises: - a first ferromagnetic reference layer (11) in which the direction of the magnetic polarization is fixed; - a second ferromagnetic layer (13) in which the direction of the magnetic polarization is variable; - a tunnel barrier layer (12) of oxide confined between the first and second ferromagnetic layers (11,13).

7. Probabilistic bit (p-bit) generator (Dl) according to claim 6 wherein the thickness of the second layer (13) is less than 10

8. nm. Probabilistic bit (p-bit) generator (Dl) according to any one of claims 6 or 7 wherein the diameter of the magnetic tunnel junction (MTJ) is less than 100 nm.

9. Probabilistic bit (p-bit) generator (Dl) according to any one of claims 1 to 8 wherein the control transistor (Tl) is mounted as a diode.

10. Probabilistic bit (p-bit) generator (Dl) according to any one of claims 1 to 8 wherein the biasing circuit (POL) is a current mirror comprising a first power supply branch (BAI) coupled to a second power supply branch comprising at least the control transistor (Tl) and the magnetic tunnel junction (MTJ) mounted in series.

11. Probabilistic bit (p-bit) generator (Dl) according to claim 10 wherein the first power supply branch (BAI) includes a second control transistor (T2) having a second buried insulating layer forming an associated back gate (G2,T2), the control means (CONT) being configured to apply a second input voltage (Vin2) to the back gate (G2,T2) of the second control transistor (T2).

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