Drive circuit,display panel,and display apparatus

Abstract

Provided are a drive circuit, a display panel, and a display apparatus. The drive circuit comprises a first output circuit (11) and a first pull-up node control circuit (12). The first output circuit (11) is separately and electrically connected to a pull-up node (PU), a first high-voltage input end (VH1) and a driving signal output end (O1), and is used for, under the control of the potential of the pull-up node (PU), controlling connection between the first high-voltage input end (VH1) and driving signal output end (O1). The first pull-up node control circuit (12) is separately and electrically connected to a pull-down node (PD), a second high-voltage input end (VH2) and the pull-up node (PU), and is used for, under the control of the potential of the pull-down node (PD), controlling connection between the pull-up node (PU) and the second high-voltage input end (VH2). The first high-voltage input end (VH1) is different from the second high-voltage input end (VH2). The drive circuit uses at least two high-voltage input ends to flexibly control the potential of each node.

Description

Driving circuit, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving circuit, a display panel, and a display device. Background Art

[0002] Active-matrix organic light-emitting diode (AMOLED) display devices are widely used in various products due to their advantages such as flexibility, high contrast and low power consumption.

[0003] In related art, an AMOLED display device typically includes an AMOLED display panel and a gate drive circuit. The AMOLED display panel includes multiple rows of pixels. The gate drive circuit includes multiple cascaded shift register units. Each shift register unit is coupled to a row of pixels and is used to transmit a gate drive signal to that row of pixels to drive that row of pixels to emit light. The multiple cascaded shift register units can achieve row-by-row scanning and drive of the multiple rows of pixels, allowing the AMOLED display panel to display an image.

[0004] However, the related shift register units use the same voltage input terminal, and the potential of each node cannot be flexibly set.

[0005] Public content

[0006] In one aspect, an embodiment of the present disclosure provides a driving circuit including a first output circuit and a first pull-up node control circuit;

[0007] The first output circuit is electrically connected to the pull-up node, the first high voltage input terminal and the drive signal output terminal respectively, and is used to control the connection between the first high voltage input terminal and the drive signal output terminal under the control of the potential of the pull-up node;

[0008] The first pull-up node control circuit is electrically connected to the pull-down node, the second high voltage input terminal and the pull-up node respectively, and is used to control the connection between the pull-up node and the second high voltage input terminal under the control of the potential of the pull-down node;

[0009] The first high voltage input terminal and the second high voltage input terminal are different.

[0010] Optionally, the driving circuit according to at least one embodiment of the present disclosure may further include a first pull-down node control circuit;

[0011] The first pull-down node control circuit is electrically connected to the pull-down node, the third high voltage input terminal and the pull-down control terminal respectively, and is used to control the connection between the third high voltage input terminal and the pull-down node under the control of the pull-down control signal provided by the pull-down control terminal;

[0012] The third high voltage input terminal is different from at least one of the first high voltage input terminal and the second high voltage input terminal.

[0013] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a first node control circuit and a fourth high voltage input terminal;

[0014] The first node control circuit is electrically connected to the first node, the first control terminal, and the fourth high voltage input terminal, respectively, and is configured to control the connection between the first node and the fourth high voltage input terminal under the control of the potential of the first control terminal; the first control terminal is the first control node or the second control node;

[0015] The fourth high voltage input terminal is different from at least one of the first high voltage input terminal and the second high voltage input terminal.

[0016] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a second output circuit, a second pull-down node control circuit, and a first control node control circuit;

[0017] The second output circuit is electrically connected to the pull-down node, the drive signal output terminal and the first low voltage input terminal respectively, and is used to control the connection between the drive signal output terminal and the first low voltage input terminal under the control of the potential of the pull-down node;

[0018] The second pull-down node control circuit is electrically connected to the third control node, the pull-down node, and the second low-voltage input terminal, respectively, and is configured to control the connection between the third control node and the pull-down node under the control of a low-voltage signal provided by the second low-voltage input terminal;

[0019] The first control node control circuit is electrically connected to the first clock signal terminal, the third low voltage input terminal and the first control node respectively, and is used to control the first control node to be electrically connected to the third low voltage input terminal under the control of the first clock signal provided by the first clock signal terminal;

[0020] At least two of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal are different from each other.

[0021] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a second control node control circuit;

[0022] The second control node control circuit is electrically connected to the fourth low voltage input terminal, the first control node and the second control node respectively, and is used to control the connection between the first control node and the second control node under the control of the low voltage signal provided by the fourth low voltage input terminal.

[0023] Optionally, the fourth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal.

[0024] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a third pull-down node control circuit;

[0025] The third pull-down node control circuit is electrically connected to the first node and the second clock signal terminal, respectively, and is used to control the connection and disconnection between the first node and the second clock signal terminal. Optionally, the third pull-down node control circuit is further electrically connected to the pull-down node, the second node, the third node, the fifth low-voltage input terminal, the first clock signal terminal, and the start signal terminal, and controls the connection between the first node and the second clock signal terminal under the control of the potential of the second node, controls the potential of the second node according to the potential of the first node, controls the connection between the start signal terminal and the third node under the control of the first clock signal provided by the first clock signal terminal, controls the connection between the third node and the second node under the control of the low-voltage signal provided by the fifth low-voltage input terminal, and controls the connection between the second node and the pull-down node under the control of the potential of the second node.

[0026] Optionally, the fifth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal.

[0027] Optionally, the first output circuit includes a first transistor, the first pull-up node control circuit includes a second transistor, and the first pull-down node control circuit includes a third transistor;

[0028] The control electrode of the first transistor is electrically connected to the pull-up node, the first electrode of the first transistor is electrically connected to the first high voltage input terminal, and the second electrode of the first transistor is electrically connected to the drive signal output terminal;

[0029] The control electrode of the second transistor is electrically connected to the pull-down node, the first electrode of the second transistor is electrically connected to the second high voltage input terminal, and the second electrode of the second transistor is electrically connected to the pull-up node;

[0030] The control electrode of the third transistor is electrically connected to the pull-down control terminal, the first electrode of the third transistor is electrically connected to the third high voltage input terminal, and the second electrode of the third transistor is electrically connected to the pull-down node;

[0031] The first high voltage input terminal is a first high voltage terminal, and the second high voltage input terminal and the third high voltage input terminal are second high voltage terminals; or,

[0032] The first high voltage input terminal is the second high voltage terminal, and the second high voltage input terminal and the third high voltage input terminal are the first high voltage terminal; or,

[0033] The first high voltage input terminal is a first high voltage terminal, the second high voltage input terminal is a second high voltage terminal, and the third high voltage input terminal is a third high voltage terminal; or,

[0034] The first high voltage input terminal and the third high voltage input terminal are first high voltage terminals, and the second high voltage input terminal is a second high voltage terminal.

[0035] Optionally, the first node control circuit includes a fourth transistor;

[0036] The control electrode of the fourth transistor is electrically connected to the first control node, the first electrode of the fourth transistor is electrically connected to the fourth high voltage input terminal, and the second electrode of the fourth transistor is electrically connected to the first node;

[0037] The first high voltage input terminal, the third high voltage input terminal and the fourth high voltage input terminal are first high voltage terminals, and the second high voltage input terminal is a second high voltage terminal; or,

[0038] The first high voltage input terminal and the fourth high voltage input terminal are first high voltage terminals, and the second high voltage input terminal and the third high voltage input terminal are second high voltage terminals; or,

[0039] The first high voltage input terminal and the third high voltage input terminal are first high voltage terminals, and the second high voltage input terminal and the fourth high voltage input terminal are second high voltage terminals; or,

[0040] The first high voltage input terminal is a first high voltage terminal, and the second high voltage input terminal, the third high voltage input terminal, and the fourth high voltage input terminal are second high voltage terminals.

[0041] Optionally, the second output circuit includes a fifth transistor, the second pull-down node control circuit includes a sixth transistor, and the first control node control circuit includes a seventh transistor;

[0042] The control electrode of the fifth transistor is electrically connected to the pull-down node, the first electrode of the fifth transistor is electrically connected to the drive signal output terminal, and the second electrode of the fifth transistor is electrically connected to the first low voltage input terminal;

[0043] The control electrode of the sixth transistor is electrically connected to the second low voltage input terminal, the first electrode of the sixth transistor is electrically connected to the third control node, and the second electrode of the sixth transistor is electrically connected to the pull-down node;

[0044] The control electrode of the seventh transistor is electrically connected to the first clock signal terminal, the first electrode of the seventh transistor is electrically connected to the third low voltage input terminal, and the second electrode of the seventh transistor is electrically connected to the first control node;

[0045] The first low voltage input terminal and the second low voltage input terminal are first low voltage terminals, and the third low voltage input terminal is a second low voltage terminal; or,

[0046] The first low voltage input terminal is a first low voltage terminal, and the second low voltage input terminal and the third low voltage input terminal are second low voltage terminals.

[0047] Optionally, the second control node control circuit includes an eighth transistor;

[0048] The control electrode of the eighth transistor is electrically connected to the fourth low voltage input terminal, the first electrode of the eighth transistor is electrically connected to the first control node, and the second electrode of the eighth transistor is electrically connected to the second control node;

[0049] The fourth low voltage input terminal is the first low voltage terminal or the second low voltage terminal.

[0050] Optionally, the third pull-down node control circuit includes a first capacitor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor;

[0051] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the second node;

[0052] The control electrode of the ninth transistor is electrically connected to the second node, the first electrode of the ninth transistor is electrically connected to the first node, and the second electrode of the ninth transistor is electrically connected to the second clock signal terminal;

[0053] The control electrode of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is electrically connected to the pull-down node, and the second electrode of the tenth transistor is electrically connected to the second node;

[0054] The control electrode of the eleventh transistor is electrically connected to the fifth low voltage input terminal, the first electrode of the eleventh transistor is electrically connected to the third node, and the second electrode of the eleventh transistor is electrically connected to the second node;

[0055] The control electrode of the twelfth transistor is electrically connected to the first clock signal terminal, the first electrode of the twelfth transistor is electrically connected to the start signal terminal, and the second electrode of the twelfth transistor is electrically connected to the third node.

[0056] Optionally, the fifth low voltage input terminal is the first low voltage terminal or the second low voltage terminal.

[0057] Optionally, the driving circuit includes a first control node control circuit, a third control node control circuit and a second pull-up node control circuit;

[0058] The first control node control circuit is electrically connected to the first control node, and is also electrically connected to a third control node, and is configured to control the connection between the first control node and the first clock signal terminal under the control of the potential of the third control node;

[0059] The third control node control circuit is electrically connected to the first clock signal terminal, the start signal terminal and the third control node respectively, and is used to control the start signal terminal to be electrically connected to the third control node under the control of the first clock signal provided by the first clock signal terminal;

[0060] The second pull-up node control circuit is also electrically connected to the first control node or the second control node, the fourth control node, the second clock signal terminal and the first high voltage input terminal, respectively, and is used to control the potential of the fourth control node according to the potential of the second control node, and under the control of the potential of the first control node or the potential of the second control node, control the connection between the second clock signal terminal and the fourth control node, and under the control of the second clock signal provided by the second clock signal terminal, control the connection between the fourth control node and the pull-up node, and maintain the potential of the pull-up node.

[0061] Optionally, the first control node control circuit includes a thirteenth transistor, the third control node control circuit includes a fourteenth transistor, and the second pull-up node control circuit includes a second capacitor, a third capacitor, a fifteenth transistor, and a sixteenth transistor;

[0062] The control electrode of the thirteenth transistor is electrically connected to the third control node, the first electrode of the thirteenth transistor is electrically connected to the first control node, and the second electrode of the thirteenth transistor is electrically connected to the first clock signal terminal;

[0063] The control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourteenth transistor is electrically connected to the start signal terminal, and the second electrode of the fourteenth transistor is electrically connected to the third control node;

[0064] A first end of the second capacitor is electrically connected to the second control node, and a second end of the second capacitor is electrically connected to the fourth control node;

[0065] A first end of the third capacitor is electrically connected to the pull-up node, and a second end of the third capacitor is electrically connected to the first high voltage input terminal;

[0066] The control electrode of the fifteenth transistor is electrically connected to the second control node, the first electrode of the fifteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifteenth transistor is electrically connected to the fourth control node;

[0067] The control electrode of the sixteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixteenth transistor is electrically connected to the fourth control node, and the second electrode of the sixteenth transistor is electrically connected to the pull-up node.

[0068] In a second aspect, an embodiment of the present disclosure further provides a driving circuit, the driving circuit comprising a second output circuit, a second pull-down node control circuit, and a first control node control circuit;

[0069] The second output circuit is electrically connected to the pull-down node, the drive signal output terminal and the first low voltage input terminal respectively, and is used to control the connection between the drive signal output terminal and the first low voltage input terminal under the control of the potential of the pull-down node;

[0070] The second pull-down node control circuit is electrically connected to the third control node, the pull-down node, and the second low-voltage input terminal, respectively, and is configured to control the connection between the third control node and the pull-down node under the control of a low-voltage signal provided by the second low-voltage input terminal;

[0071] The first control node control circuit is electrically connected to the first clock signal terminal, the third low voltage input terminal and the first control node respectively, and is used to control the first control node to be electrically connected to the third low voltage input terminal under the control of the first clock signal provided by the first clock signal terminal;

[0072] At least two of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal are different from each other.

[0073] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a second control node control circuit;

[0074] The second control node control circuit is electrically connected to the fourth low voltage input terminal, the first control node, and the second control node, respectively, and is configured to control the communication between the first control node and the second control node under the control of a low voltage signal provided by the fourth low voltage input terminal;

[0075] The fourth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal.

[0076] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a third pull-down node control circuit;

[0077] The third pull-down node control circuit is electrically connected to the first node and the second clock signal terminal respectively, and is used to control the connection and disconnection between the first node and the second clock signal terminal;

[0078] The third pull-down node control circuit is further electrically connected to the second node, the third node, the fifth low-voltage input terminal, the first clock signal terminal, and the start signal terminal, respectively. Under the control of the potential of the second node, the third pull-down node control circuit controls the first node to be connected to the second clock signal terminal. According to the potential of the first node, the third pull-down node control circuit controls the potential of the second node to be connected to the third node. Under the control of the first clock signal provided by the first clock signal terminal, the third pull-down node control circuit controls the second node to be connected to the second node. Under the control of the low-voltage signal provided by the fifth low-voltage input terminal, the third pull-down node control circuit controls the second node to be connected to the pull-down node.

[0079] The fifth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, the third low voltage input terminal, and the fourth low voltage input terminal.

[0080] In a third aspect, an embodiment of the present disclosure provides a display panel, comprising the aforementioned driving circuit; the display panel further comprises a display driving chip;

[0081] The first high voltage input terminal is electrically connected to the first high voltage line, and the second high voltage input terminal is electrically connected to the second high voltage line; the first high voltage line and the second high voltage line are respectively electrically connected to different pins of the display driver chip, and the display driver chip is used to provide a first high voltage signal for the first high voltage line, and the display driver chip is used to provide a second high voltage signal for the second high voltage line.

[0082] In a fourth aspect, an embodiment of the present disclosure provides a display panel, comprising the aforementioned driving circuit; the display panel further comprises a display driving chip;

[0083] The first low voltage input terminal is electrically connected to the first low voltage line, the second low voltage input terminal is electrically connected to the second low voltage line, and the third low voltage input terminal is electrically connected to the third low voltage line. The first low voltage line, the second low voltage line, and the third low voltage line are electrically connected to different pins of the display driver chip, respectively. The display driver chip is used to provide a first low voltage signal for the first low voltage line, a second low voltage signal for the second low voltage line, and a third low voltage signal for the third low voltage line; or

[0084] The first low voltage input terminal is electrically connected to the first low voltage line, the second low voltage input terminal and the third low voltage input terminal are both electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal to the first low voltage line and provide a second low voltage signal to the second low voltage line; or

[0085] The first low voltage input terminal and the second low voltage input terminal are both electrically connected to the first low voltage line, the third low voltage input terminal is electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal to the first low voltage line and provide a second low voltage signal to the second low voltage line; or

[0086] The first low voltage input terminal and the third low voltage input terminal are both electrically connected to the first low voltage line, the second low voltage input terminal is electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are respectively electrically connected to different pins of the display driver chip, and the display driver chip is used to provide a first low voltage signal for the first low voltage line and provide a second low voltage signal for the second low voltage line.

[0087] In a fifth aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0088] FIG1 is a structural diagram of a driving circuit according to an embodiment of the present disclosure;

[0089] FIG2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0090] FIG3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0091] FIG4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0092] FIG5 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0093] FIG6 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0094] FIG7 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0095] FIG8 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0096] FIG9 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0097] FIG10 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0098] FIG11 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0099] FIG12 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0100] FIG13 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0101] FIG14 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0102] FIG15 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0103] FIG16 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0104] FIG17 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0105] FIG18 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0106] FIG19 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0107] FIG20 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0108] FIG21 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0109] FIG22 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0110] FIG23 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0111] FIG24 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0112] FIG25 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0113] FIG26 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0114] FIG27 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0115] FIG28 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0116] FIG29 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0117] FIG30 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0118] FIG31 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0119] FIG32 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0120] FIG33 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0121] FIG34 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0122] FIG35 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0123] FIG36 is a structural diagram of a display panel according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0124] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0125] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0126] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the gate electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0127] As shown in FIG1 , the driving circuit according to the embodiment of the present disclosure includes a first output circuit 11 and a first pull-up node control circuit 12 ;

[0128] The first output circuit 11 is electrically connected to the pull-up node PU, the first high voltage input terminal VH1 and the drive signal output terminal O1 respectively, and is used to control the connection between the first high voltage input terminal VH1 and the drive signal output terminal O1 under the control of the potential of the pull-up node PU;

[0129] The first pull-up node control circuit 12 is electrically connected to the pull-down node PD, the second high voltage input terminal VH2 and the pull-up node PU respectively, and is used to control the connection between the pull-up node PU and the second high voltage input terminal VH2 under the control of the potential of the pull-down node PD;

[0130] The first high voltage input terminal VH1 and the second high voltage input terminal VH2 are different.

[0131] The driving circuit described in the embodiment of the present disclosure adopts two high voltage input terminals to flexibly control the potential of each node.

[0132] In at least one embodiment of the present disclosure, two high voltage input terminals being different may mean that the voltage values ​​of the high voltage signals respectively provided by the two high voltage input terminals are different.

[0133] In at least one embodiment of the driving circuit shown in FIG. 1 , the first high voltage input terminal VH1 electrically connected to the first output circuit 11 and the second high voltage input terminal VH2 electrically connected to the first pull-up node control circuit 12 are different.

[0134] In a specific implementation, when the transistor included in the first output circuit 11 is a p-type transistor, the voltage value of the high voltage signal provided by the first high voltage input terminal can be set to be lower than the voltage value of the high voltage signal provided by the second high voltage input terminal, so that when the transistor included in the first pull-up node control circuit 12 is turned on, the transistor included in the first output circuit 11 can be better turned off;

[0135] When the transistor included in the first output circuit 11 is an n-type transistor, the voltage value of the high voltage signal provided by the first high voltage input terminal can be set to be greater than the voltage value of the high voltage signal provided by the second high voltage input terminal, so that when the transistor included in the first pull-up node control circuit 12 is turned on, the transistor included in the first output circuit 11 can be turned off better;

[0136] But it is not limited to this.

[0137] In at least one embodiment of the present disclosure, VH1 may provide a first high voltage signal VGH, and VH2 may provide a second high voltage signal VGH2; or, VH1 may provide a second high voltage signal VGH2, and VH2 may provide a first high voltage signal VGH; but the present invention is not limited thereto.

[0138] In at least one embodiment of the present disclosure, the voltage value of the high voltage signal provided by each high voltage input terminal can be a positive value; the voltage value of the first high voltage signal VGH can be greater than the voltage value of the second high voltage signal VGH2, or the voltage value of the first high voltage signal VGH can be less than the voltage value of the second high voltage signal VGH2.

[0139] In at least one embodiment of the present disclosure, the voltage value of the first high voltage signal VGH may be greater than or equal to 7V and less than or equal to 12V. For example, the voltage value of VGH may be approximately 9.5V.

[0140] As shown in FIG2 , based on the embodiment of the driving circuit shown in FIG1 , the driving circuit according to at least one embodiment of the present disclosure further includes a first pull-down node control circuit 21 ;

[0141] The first pull-down node control circuit 21 is electrically connected to the pull-down node PD, the third high voltage input terminal VH3 and the pull-down control terminal VEL, respectively, and is used to control the connection between the third high voltage input terminal VH3 and the pull-down node PD under the control of the pull-down control signal provided by the pull-down control terminal VEL;

[0142] The third high voltage input terminal VH3 is different from at least one of the first high voltage input terminal VH1 and the second high voltage input terminal VH2.

[0143] In at least one embodiment of the present disclosure, the driving circuit may further include a first pull-down node control circuit 21, which controls the connection between the third high voltage input terminal VH3 and the pull-down node PD under the control of a pull-down control signal, and the third high voltage input terminal VH3 is different from the first high voltage input terminal VH1; and / or the third high voltage input terminal VH3 is different from the second high voltage input terminal VH2.

[0144] In a specific implementation, the pull-down control terminal VEL may write the high voltage signal provided by the third high voltage input terminal VH3 into the pull-down node PD before normal display, but the present invention is not limited thereto.

[0145] In at least one embodiment of the present disclosure, the third high voltage input terminal VH3 may provide the first high voltage signal VGH or the second high voltage signal VGH2 , but the present invention is not limited thereto.

[0146] The driving circuit according to at least one embodiment of the present disclosure further includes a first node control circuit and a fourth high voltage input terminal;

[0147] The first node control circuit is electrically connected to the first node, the first control terminal, and the fourth high voltage input terminal, respectively, and is configured to control the connection between the first node and the fourth high voltage input terminal under the control of the potential of the first control terminal; the first control terminal is the first control node or the second control node;

[0148] The fourth high voltage input terminal is different from at least one of the first high voltage input terminal and the second high voltage input terminal.

[0149] In at least one embodiment of the present disclosure, the first node control circuit can be used to control the potential of the first node, and the fourth high voltage input terminal electrically connected to the first node control circuit can be different from at least one of the first high voltage input terminal, the second high voltage input terminal, and the third high voltage input terminal.

[0150] As shown in FIG3 , based on at least one embodiment of the driving circuit shown in FIG2 , the driving circuit according to at least one embodiment of the present disclosure further includes a first node control circuit 31 and a fourth high voltage input terminal VH4 ;

[0151] The first node control circuit 31 is electrically connected to the first node N1, the first control node Ct1 and the fourth high voltage input terminal VH4 respectively, and is used to control the connection between the first node N1 and the fourth high voltage input terminal VH4 under the control of the potential of the first control node Ct1.

[0152] In at least one embodiment of the driving circuit shown in FIG. 3 , the fourth high voltage input terminal VH4 can provide the first high voltage signal VGH or the second high voltage signal VGH2 , but the present invention is not limited thereto.

[0153] In at least one embodiment of the present disclosure, the first high voltage input terminal VH1, the second high voltage input terminal VH2, the third high voltage input terminal VH3, and the fourth high voltage input terminal VH4 are not completely the same, specifically as follows:

[0154] VH1 and VH2 are not identical; or,

[0155] VH1 and VH3 are not identical; or,

[0156] VH1 and VH4 are not identical; or,

[0157] VH2 and VH3 are not identical; or,

[0158] VH2 and VH4 are not identical; or,

[0159] VH3 and VH4 are not identical; or,

[0160] VH1, VH2 and VH3 are different from each other; or,

[0161] VH1, VH2 and VH4 are different from each other; or,

[0162] VH1, VH3 and VH4 are different from each other; or,

[0163] VH2, VH3 and VH4 are different from each other; or,

[0164] VH1, VH2, VH3 and VH4 are different from each other.

[0165] The driving circuit according to at least one embodiment of the present disclosure further includes a second output circuit, a second pull-down node control circuit, and a first control node control circuit;

[0166] The second output circuit is electrically connected to the pull-down node, the drive signal output terminal and the first low voltage input terminal respectively, and is used to control the connection between the drive signal output terminal and the first low voltage input terminal under the control of the potential of the pull-down node;

[0167] The second pull-down node control circuit is electrically connected to the third control node, the pull-down node, and the second low-voltage input terminal, respectively, and is configured to control the connection between the third control node and the pull-down node under the control of a low-voltage signal provided by the second low-voltage input terminal;

[0168] The first control node control circuit is electrically connected to the first clock signal terminal, the third low voltage input terminal and the first control node respectively, and is used to control the first control node to be electrically connected to the third low voltage input terminal under the control of the first clock signal provided by the first clock signal terminal;

[0169] At least two of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal are different from each other.

[0170] In at least one embodiment of the present disclosure, the two low voltage input terminals being different may mean that the voltage values ​​of the low voltage signals respectively provided by the two low voltage input terminals are different.

[0171] As shown in FIG4 , based on at least one embodiment of the driving circuit shown in FIG3 , the driving circuit according to at least one embodiment of the present disclosure further includes a second output circuit 41 , a second pull-down node control circuit 42 , and a first control node control circuit 43 ;

[0172] The second output circuit 41 is electrically connected to the pull-down node PD, the drive signal output terminal O1, and the first low voltage input terminal VL1, respectively, and is used to control the connection between the drive signal output terminal O1 and the first low voltage input terminal VL1 under the control of the potential of the pull-down node PD;

[0173] The second pull-down node control circuit 42 is electrically connected to the third control node Ct3, the pull-down node PD, and the second low voltage input terminal VL2, respectively, and is configured to control the connection between the third control node Ct3 and the pull-down node PD under the control of the low voltage signal provided by the second low voltage input terminal VL2;

[0174] The first control node control circuit 43 is electrically connected to the first clock signal terminal CK, the third low voltage input terminal VL3 and the first control node Ct1 respectively, and is used to control the first control node Ct1 to be electrically connected to the third low voltage input terminal VL3 under the control of the first clock signal provided by the first clock signal terminal CK;

[0175] At least two of the first low voltage input terminal VL1 , the second low voltage input terminal VL2 , and the third low voltage input terminal VL3 are different from each other.

[0176] In at least one embodiment of the driving circuit shown in FIG4 , the first low voltage input terminal VL1 provides the first low voltage signal VGL, the second low voltage input terminal VL2 provides the first low voltage signal VGL, and the third low voltage input terminal VL3 provides the second low voltage signal VL2; or

[0177] The first low voltage input terminal VL1 provides the second low voltage signal VGL2 , the second low voltage input terminal VL2 provides the first low voltage signal VGL, and the third low voltage input terminal VL3 provides the first low voltage signal VGL; or,

[0178] The first low voltage input terminal VL1 provides a first low voltage signal VGL, the second low voltage input terminal VL2 provides a second low voltage signal VGL2, and the third low voltage input terminal VL3 provides a second low voltage signal VGL2;

[0179] But it is not limited to this.

[0180] In at least one embodiment of the present disclosure, the first low voltage input terminal VL1 , the second low voltage input terminal VL2 , and the third low voltage input terminal VL3 may also be the same, but not limited thereto.

[0181] In at least one embodiment of the present disclosure, the voltage value of the low voltage signal provided by each low voltage input terminal can be a negative value; the voltage value of the first low voltage signal VGL can be greater than the voltage value of the second low voltage signal VGL2, or the voltage value of the first low voltage signal VGL can be less than the voltage value of the second low voltage signal VGL2.

[0182] In at least one embodiment of the present disclosure, the voltage value of the first low voltage signal VGL may be greater than or equal to -11V and less than or equal to -6V. For example, the voltage value of VGL may be approximately -8.5V, but is not limited thereto.

[0183] As shown in FIG5 , based on at least one embodiment of the driving circuit shown in FIG4 , the driving circuit according to at least one embodiment of the present disclosure further includes a second control node control circuit 51 ;

[0184] The second control node control circuit 51 is electrically connected to the fourth low voltage input terminal VL4, the first control node Ct1 and the second control node Ct2, respectively, and is used to control the connection between the first control node Ct1 and the second control node Ct2 under the control of the low voltage signal provided by the fourth low voltage input terminal VL4.

[0185] In at least one embodiment of the present disclosure, the fourth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal.

[0186] In at least one embodiment of the present disclosure, the fourth low voltage input terminal VL4 can provide the first low voltage signal VGL or the second low voltage signal VGL2 , but is not limited thereto.

[0187] As shown in FIG6 , based on at least one embodiment of the driving circuit shown in FIG5 , the driving circuit according to at least one embodiment of the present disclosure further includes a third pull-down node control circuit 61 ;

[0188] The third pull-down node control circuit 61 is electrically connected to the first node N1 and the second clock signal terminal CB respectively, and is used to control the connection between the first node N1 and the second clock signal terminal CB.

[0189] In a specific implementation, the driving circuit may further include a third pull-down node control circuit 61 for controlling the potential of the pull-down node PD.

[0190] As shown in Figure 6, the third pull-down node control circuit 61 is also electrically connected to the pull-down node PD, the second node N2, the third node N3, the fifth low voltage input terminal VL5, the first clock signal terminal CK and the start signal terminal STV, respectively. Under the control of the potential of the second node N2, the first node N1 is controlled to be connected to the second clock signal terminal CB. According to the potential of the first node N1, the potential of the second node N2 is controlled. Under the control of the first clock signal provided by the first clock signal terminal CK, the start signal terminal STV is controlled to be connected to the third node N3. Under the control of the low voltage signal provided by the fifth low voltage input terminal VL5, the third node N3 is controlled to be connected to the second node N2. Under the control of the potential of the second node N2, the second node N2 is controlled to be connected to the pull-down node PD.

[0191] In at least one embodiment of the present disclosure, the fifth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal.

[0192] In at least one embodiment of the present disclosure, the fifth low voltage input terminal can provide the first low voltage signal VGL or the second low voltage signal VGL2, but is not limited thereto. In actual operation, the fifth low voltage input terminal can also provide other low voltage signals.

[0193] In at least one embodiment of the present disclosure, VL1, VL2, VL3, VL4, and VL5 are not identical; specifically, as follows:

[0194] VL1 and VL2 are not the same; or,

[0195] VL1 and VL3 are not the same; or,

[0196] VL1 and VL4 are not the same; or,

[0197] VL1 and VL5 are not the same; or,

[0198] VL2 and VL3 are not the same; or,

[0199] VL2 and VL4 are not the same; or,

[0200] VL2 and VL5 are not the same; or,

[0201] VL3 and VL4 are not the same; or,

[0202] VL3 and VL5 are not the same; or

[0203] VL4 and VL5 are not the same; or

[0204] VL1, VL2 and VL3 are different from each other; or;

[0205] VL1, VL2 and VL4 are different from each other; or,

[0206] VL1, VL2 and VL5 are different from each other; or,

[0207] VL1, VL3 and VL4 are different from each other; or,

[0208] VL1, VL3 and VL5 are different from each other; or,

[0209] VL1, VL4 and VL5 are different from each other; or,

[0210] VL2, VL3 and VL4 are different from each other; or,

[0211] VL2, VL3 and VL5 are different from each other; or,

[0212] VL2, VL4 and VL5 are different from each other; or;

[0213] VL1, VL2, VL3 and VL4 are different from each other; or,

[0214] VL1, VL2, VL3 and VL5 are different from each other; or,

[0215] VL1, VL3, VL4 and VL5 are different from each other; or,

[0216] VL2, VL3, VL4 and VL5 are different from each other; or,

[0217] VL1, VL2, VL3, VL4 and VL5 are different from each other.

[0218] Optionally, the first output circuit includes a first transistor, the first pull-up node control circuit includes a second transistor, and the first pull-down node control circuit includes a third transistor;

[0219] The control electrode of the first transistor is electrically connected to the pull-up node, the first electrode of the first transistor is electrically connected to the first high voltage input terminal, and the second electrode of the first transistor is electrically connected to the drive signal output terminal;

[0220] The control electrode of the second transistor is electrically connected to the pull-down node, the first electrode of the second transistor is electrically connected to the second high voltage input terminal, and the second electrode of the second transistor is electrically connected to the pull-up node;

[0221] The control electrode of the third transistor is electrically connected to the pull-down control terminal, the first electrode of the third transistor is electrically connected to the third high voltage input terminal, and the second electrode of the third transistor is electrically connected to the pull-down node;

[0222] The first high voltage input terminal is a first high voltage terminal, and the second high voltage input terminal and the third high voltage input terminal are second high voltage terminals; or,

[0223] The first high voltage input terminal is the second high voltage terminal, and the second high voltage input terminal and the third high voltage input terminal are the first high voltage terminal; or,

[0224] The first high voltage input terminal is a first high voltage terminal, the second high voltage input terminal is a second high voltage terminal, and the third high voltage input terminal is a third high voltage terminal; or,

[0225] The first high voltage input terminal and the third high voltage input terminal are first high voltage terminals, and the second high voltage input terminal is a second high voltage terminal.

[0226] In at least one embodiment of the present disclosure, the first high voltage terminal may be used to provide a first high voltage signal, and the second high voltage terminal may be used to provide a second high voltage signal.

[0227] Optionally, the first node control circuit includes a fourth transistor;

[0228] The control electrode of the fourth transistor is electrically connected to the first control node, the first electrode of the fourth transistor is electrically connected to the fourth high voltage input terminal, and the second electrode of the fourth transistor is electrically connected to the first node;

[0229] The first high voltage input terminal, the third high voltage input terminal and the fourth high voltage input terminal are first high voltage terminals, and the second high voltage input terminal is a second high voltage terminal; or,

[0230] The first high voltage input terminal and the fourth high voltage input terminal are first high voltage terminals, and the second high voltage input terminal and the third high voltage input terminal are second high voltage terminals; or,

[0231] The first high voltage input terminal and the third high voltage input terminal are first high voltage terminals, and the second high voltage input terminal and the fourth high voltage input terminal are second high voltage terminals; or,

[0232] The first high voltage input terminal is a first high voltage terminal, and the second high voltage input terminal, the third high voltage input terminal, and the fourth high voltage input terminal are second high voltage terminals.

[0233] Optionally, the second output circuit includes a fifth transistor, the second pull-down node control circuit includes a sixth transistor, and the first control node control circuit includes a seventh transistor;

[0234] The control electrode of the fifth transistor is electrically connected to the pull-down node, the first electrode of the fifth transistor is electrically connected to the drive signal output terminal, and the second electrode of the fifth transistor is electrically connected to the first low voltage input terminal;

[0235] The control electrode of the sixth transistor is electrically connected to the second low voltage input terminal, the first electrode of the sixth transistor is electrically connected to the third control node, and the second electrode of the sixth transistor is electrically connected to the pull-down node;

[0236] The control electrode of the seventh transistor is electrically connected to the first clock signal terminal, the first electrode of the seventh transistor is electrically connected to the third low voltage input terminal, and the second electrode of the seventh transistor is electrically connected to the first control node;

[0237] The first low voltage input terminal and the second low voltage input terminal are first low voltage terminals; the third low voltage input terminal is a second low voltage terminal; or,

[0238] The first low voltage input terminal is a first low voltage terminal, and the second low voltage input terminal and the third low voltage input terminal are second low voltage terminals.

[0239] In at least one embodiment of the present disclosure, the first low voltage terminal may be used to provide a first low voltage signal, and the second low voltage terminal may be used to provide a second low voltage signal.

[0240] Optionally, the second control node control circuit includes an eighth transistor;

[0241] The control electrode of the eighth transistor is electrically connected to the fourth low voltage input terminal, the first electrode of the eighth transistor is electrically connected to the first control node, and the second electrode of the eighth transistor is electrically connected to the second control node;

[0242] The fourth low voltage input terminal is the first low voltage terminal or the second low voltage terminal.

[0243] Optionally, the third pull-down node control circuit includes a first capacitor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor;

[0244] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the second node;

[0245] The control electrode of the ninth transistor is electrically connected to the second node, the first electrode of the ninth transistor is electrically connected to the first node, and the second electrode of the ninth transistor is electrically connected to the second clock signal terminal;

[0246] The control electrode of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is electrically connected to the pull-down node, and the second electrode of the tenth transistor is electrically connected to the second node;

[0247] The control electrode of the eleventh transistor is electrically connected to the fifth low voltage input terminal, the first electrode of the eleventh transistor is electrically connected to the third node, and the second electrode of the eleventh transistor is electrically connected to the second node;

[0248] The control electrode of the twelfth transistor is electrically connected to the first clock signal terminal, the first electrode of the twelfth transistor is electrically connected to the start signal terminal, and the second electrode of the twelfth transistor is electrically connected to the third node.

[0249] In at least one embodiment of the present disclosure, the fifth low voltage input terminal is the first low voltage terminal or the second low voltage terminal, but is not limited thereto.

[0250] Optionally, the driving circuit includes a first control node control circuit, a third control node control circuit and a second pull-up node control circuit;

[0251] The first control node control circuit is electrically connected to the first control node, and is also electrically connected to a third control node, and is configured to control the connection between the first control node and the first clock signal terminal under the control of the potential of the third control node;

[0252] The third control node control circuit is electrically connected to the first clock signal terminal, the start signal terminal, and the third control node, respectively, and is configured to control the start signal terminal to be electrically connected to the third control node under the control of the first clock signal provided by the first clock signal terminal;

[0253] The second pull-up node control circuit is also electrically connected to the first control node or the second control node, the fourth control node, the second clock signal terminal and the first high voltage input terminal, respectively, and is used to control the potential of the fourth control node according to the potential of the second control node, and under the control of the potential of the first control node or the potential of the second control node, control the connection between the second clock signal terminal and the fourth control node, and under the control of the second clock signal provided by the second clock signal terminal, control the connection between the fourth control node and the pull-up node, and maintain the potential of the pull-up node.

[0254] In at least one embodiment of the present disclosure, as shown in FIG7 , based on at least one embodiment of the driving circuit shown in FIG6 , the driving circuit includes a third control node control circuit 72 and a second pull-up node control circuit 73 ;

[0255] The first control node control circuit 43 is further electrically connected to the third control node Ct3, and is configured to control the connection between the first control node Ct1 and the first clock signal terminal CK under the control of the potential of the third control node Ct3;

[0256] The third control node control circuit 72 is electrically connected to the first clock signal terminal CK, the start signal terminal STV and the third control node Ct3 respectively, and is used to control the start signal terminal STV to be electrically connected to the third control node Ct3 under the control of the first clock signal provided by the first clock signal terminal CK;

[0257] The second pull-up node control circuit 73 is also electrically connected to the second control node Ct2, the fourth control node Ct4, the second clock signal terminal CB and the first high voltage input terminal VH1, respectively, and is used to control the potential of the fourth control node Ct4 according to the potential of the second control node Ct2, and under the control of the potential of the second control node Ct2, control the connection between the second clock signal terminal CB and the fourth control node Ct4, and under the control of the second clock signal provided by the second clock signal terminal CB, control the connection between the fourth control node Ct4 and the pull-up node PU, and is used to maintain the potential of the pull-up node PU.

[0258] Optionally, the first control node control circuit includes a thirteenth transistor, the third control node control circuit includes a fourteenth transistor, and the second pull-up node control circuit includes a second capacitor, a third capacitor, a fifteenth transistor, and a sixteenth transistor;

[0259] The control electrode of the thirteenth transistor is electrically connected to the third control node, the first electrode of the thirteenth transistor is electrically connected to the first control node, and the second electrode of the thirteenth transistor is electrically connected to the first clock signal terminal;

[0260] The control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourteenth transistor is electrically connected to the start signal terminal, and the second electrode of the fourteenth transistor is electrically connected to the third control node;

[0261] A first end of the second capacitor is electrically connected to the second control node, and a second end of the second capacitor is electrically connected to the fourth control node;

[0262] A first end of the third capacitor is electrically connected to the pull-up node, and a second end of the third capacitor is electrically connected to the first high voltage input terminal;

[0263] The control electrode of the fifteenth transistor is electrically connected to the second control node, the first electrode of the fifteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifteenth transistor is electrically connected to the fourth control node;

[0264] The control electrode of the sixteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixteenth transistor is electrically connected to the fourth control node, and the second electrode of the sixteenth transistor is electrically connected to the pull-up node.

[0265] As shown in FIG8 , based on at least one embodiment of the driving circuit shown in FIG7 , the first output circuit includes a first transistor T1, the first pull-up node control circuit includes a second transistor T2, and the first pull-down node control circuit includes a third transistor T3;

[0266] The gate of the first transistor T1 is electrically connected to the pull-up node PU, the source of the first transistor T1 is electrically connected to the first high voltage input terminal VH1, and the drain of the first transistor T1 is electrically connected to the drive signal output terminal O1;

[0267] The gate of the second transistor T2 is electrically connected to the pull-down node PD, the source of the second transistor T2 is electrically connected to the second high voltage input terminal VH2, and the drain of the second transistor T2 is electrically connected to the pull-up node PU;

[0268] The gate of the third transistor T3 is electrically connected to the pull-down control terminal VEL, the source of the third transistor T3 is electrically connected to the third high voltage input terminal VH3, and the drain of the third transistor T3 is electrically connected to the pull-down node PD;

[0269] The first node control circuit includes a fourth transistor T4;

[0270] The gate of the fourth transistor T4 is electrically connected to the first control node Ct1, the source of the fourth transistor T4 is electrically connected to the fourth high voltage input terminal VH4, and the drain of the fourth transistor T4 is electrically connected to the first node N1;

[0271] The second output circuit includes a fifth transistor T5, the second pull-down node control circuit includes a sixth transistor T6, and the first control node control circuit includes a seventh transistor T7;

[0272] The gate of the fifth transistor T5 is electrically connected to the pull-down node PD, the source of the fifth transistor T5 is electrically connected to the driving signal output terminal O1, and the drain of the fifth transistor T5 is electrically connected to the first low voltage input terminal VL1;

[0273] The gate of the sixth transistor T6 is electrically connected to the second low voltage input terminal VL2, the source of the sixth transistor T6 is electrically connected to the third control node Ct3, and the drain of the sixth transistor T6 is electrically connected to the pull-down node PD;

[0274] The gate of the seventh transistor T7 is electrically connected to the first clock signal terminal CK, the source of the seventh transistor T7 is electrically connected to the third low voltage input terminal VL3, and the drain of the seventh transistor T7 is electrically connected to the first control node Ct1;

[0275] The second control node control circuit includes an eighth transistor T8;

[0276] The gate of the eighth transistor T8 is electrically connected to the fourth low voltage input terminal VL4, the source of the eighth transistor T8 is electrically connected to the first control node Ct1, and the drain of the eighth transistor T8 is electrically connected to the second control node Ct2;

[0277] The third pull-down node control circuit includes a first capacitor C1, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12;

[0278] A first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the second node N2;

[0279] The gate of the ninth transistor T9 is electrically connected to the second node N2, the source of the ninth transistor T9 is electrically connected to the first node N1, and the drain of the ninth transistor T9 is electrically connected to the second clock signal terminal CB;

[0280] The gate of the tenth transistor T10 is electrically connected to the second node N2, the source of the tenth transistor T10 is electrically connected to the pull-down node PD, and the drain of the tenth transistor T10 is electrically connected to the second node N2;

[0281] The gate of the eleventh transistor T11 is electrically connected to the fifth low voltage input terminal VL5, the source of the eleventh transistor T11 is electrically connected to the third node N3, and the drain of the eleventh transistor T11 is electrically connected to the second node N2;

[0282] The gate of the twelfth transistor T12 is electrically connected to the first clock signal terminal CK, the source of the twelfth transistor T12 is electrically connected to the start signal terminal STV, and the drain of the twelfth transistor T12 is electrically connected to the third node N3;

[0283] The first control node control circuit includes a thirteenth transistor T13, the third control node control circuit includes a fourteenth transistor T14, and the second pull-up node control circuit includes a second capacitor C2, a third capacitor C3, a fifteenth transistor T15, and a sixteenth transistor T16;

[0284] The gate of the thirteenth transistor T13 is electrically connected to the third control node Ct3, the source of the thirteenth transistor T13 is electrically connected to the first control node Ct1, and the drain of the thirteenth transistor T13 is electrically connected to the first clock signal terminal CK;

[0285] The gate of the fourteenth transistor T14 is electrically connected to the first clock signal terminal CK, the source of the fourteenth transistor T14 is electrically connected to the start signal terminal STV, and the drain of the fourteenth transistor T14 is electrically connected to the third control node Ct3;

[0286] A first end of the second capacitor C2 is electrically connected to the second control node Ct2, and a second end of the second capacitor C2 is electrically connected to the fourth control node Ct4;

[0287] A first end of the third capacitor C3 is electrically connected to the pull-up node PU, and a second end of the third capacitor C3 is electrically connected to the first high voltage input terminal VH1;

[0288] The gate of the fifteenth transistor T15 is electrically connected to the second control node Ct2, the source of the fifteenth transistor T15 is electrically connected to the second clock signal terminal CB, and the drain of the fifteenth transistor T15 is electrically connected to the fourth control node Ct4;

[0289] A gate of the sixteenth transistor T16 is electrically connected to the second clock signal terminal CB, a source of the sixteenth transistor T16 is electrically connected to the fourth control node Ct4, and a drain of the sixteenth transistor T16 is electrically connected to the pull-up node PU.

[0290] In at least one embodiment shown in FIG. 8 , all transistors are p-type transistors, but the present invention is not limited thereto.

[0291] When at least one embodiment of the driving circuit of the present disclosure as shown in FIG8 is in operation, due to the parasitic capacitance between the data line, the scan line and the light-emitting control line, the data signal on the data line often fluctuates. Therefore, the scan signal and the light-emitting control signal will be coupled and changed by the change of the data signal, resulting in brightness deviation problems such as crosstalk. Therefore, at least one embodiment of the driving circuit of the present disclosure as shown in FIG8 is provided with a diode-connected T10 between PD and N2, which can stabilize the potential of PD at a low level in the operation mode of a charge pump, thereby ensuring the relative stability of the output signal and preventing the occurrence of brightness deviation caused by coupling crosstalk.

[0292] The difference between at least one embodiment of the driving circuit shown in FIG. 9 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 8 of the present disclosure is that T8 is connected between the source of T13 and the gate of T4 .

[0293] As shown in FIG10 , in at least one embodiment of the driving circuit shown in FIG8 , VH1 provides a first high voltage signal VGH, VH2 provides a second high voltage signal VGH2, VH3 provides a second high voltage signal VGH2, VH4 provides a first high voltage signal VGH, and VL1, VL2, VL3, VL4, and VL5 all provide a first low voltage signal VGL.

[0294] As shown in FIG11 , in at least one embodiment of the driving circuit shown in FIG8 , VH1 provides a second high voltage signal VGH2, VH2 provides a first high voltage signal VGH, VH3 provides a first high voltage signal VGH, VH4 provides a first high voltage signal VGH, and VL1, VL2, VL3, VL4, and VL5 all provide a first low voltage signal VGL.

[0295] As shown in FIG12 , in at least one embodiment of the driving circuit shown in FIG8 , VH1 provides a first high voltage signal VGH, VH2 provides a second high voltage signal VGH2, VH3 provides a second high voltage signal VGH2, VH4 provides a first high voltage signal VGH, VL1, VL2, VL4 and VL5 all provide a first low voltage signal VGL, and VL3 provides a second low voltage signal VGL2.

[0296] In at least one embodiment of the driver circuit shown in FIG. 12 of the present disclosure, during operation, the VGL connected to T5 is used only for output, is not subject to interference from other transistors, and simplifies wiring. Furthermore, because p-type transistors experience threshold voltage loss when transmitting low-level signals, the voltage value of VGL2 can be set slightly lower than the voltage value of VGL. For example, when the voltage value of VGL is -6V, the voltage value of VGL2 can be -6.5V, but this is not a limitation.

[0297] As shown in FIG13 , in at least one embodiment of the driving circuit shown in FIG8 , VH1 provides a second high voltage signal VGH2, VH2 provides a first high voltage signal VGH, VH3 provides a first high voltage signal VGH, VH4 provides a first high voltage signal VGH, VL1, VL2, VL4 and VL5 all provide a first low voltage signal VGL, and VL3 provides a second low voltage signal VGL2.

[0298] As shown in FIG14 , in at least one embodiment of the driving circuit shown in FIG8 , VH1 provides a first high voltage signal VGH, VH2 provides a second high voltage signal VGH2, VH3 provides a second high voltage signal VGH2, VH4 provides a first high voltage signal VGH, VL1 provides a second low voltage signal VGL2, and VL2, VL3, VL4, and VL5 all provide a first low voltage signal VGL.

[0299] As shown in FIG15 , in at least one embodiment of the driving circuit shown in FIG8 , VH1 provides a second high voltage signal VGH2, VH2 provides a first high voltage signal VGH, VH3 provides a first high voltage signal VGH, VH4 provides a first high voltage signal VGH, VL1 provides a second low voltage signal VGL2, and VL2, VL3, VL4, and VL5 all provide a first low voltage signal VGL.

[0300] As shown in FIG16 , in at least one embodiment of the driving circuit shown in FIG8 , VH1 provides a first high voltage signal VGH, VH2 provides a second high voltage signal VGH2, VH3 provides a first high voltage signal VGH, VH4 provides a first high voltage signal VGH, and VL1, VL2, VL3, VL4, and VL5 all provide a first low voltage signal VGL.

[0301] As shown in FIG17 , in at least one embodiment of the driving circuit shown in FIG8 , VH1 provides a first high voltage signal VGH, VH2 provides a second high voltage signal VGH2, VH3 provides a second high voltage signal VGH2, VH4 provides a first high voltage signal VGH, and VL1, VL2, VL3, VL4, and VL5 all provide a first low voltage signal VGL.

[0302] As shown in FIG18 , in at least one embodiment of the driving circuit shown in FIG8 , VH1 provides a first high voltage signal VGH, VH2 provides a second high voltage signal VGH2, VH3 provides a first high voltage signal VGH, VH4 provides a second high voltage signal VGH2, and VL1, VL2, VL3, VL4, and VL5 all provide a first low voltage signal VGL.

[0303] As shown in FIG19 , in at least one embodiment of the driving circuit shown in FIG8 , VH1 provides a first high voltage signal VGH, VH2 provides a second high voltage signal VGH2, VH3 provides a second high voltage signal VGH2, VH4 provides a second high voltage signal VGH2, and VL1, VL2, VL3, VL4, and VL5 all provide a first low voltage signal VGL.

[0304] As shown in Figure 20, in at least one embodiment of the driving circuit shown in Figure 8, VH1 provides a first high voltage signal VGH, VH2 provides a second high voltage signal VGH2, VH3 provides a first high voltage signal VGH1, VH4 provides a first high voltage signal VGH, VL3 provides a second low voltage signal VGL2, and VL1, VL2, VL4 and VL5 all provide a first low voltage signal VGL.

[0305] As shown in Figure 21, in at least one embodiment of the driving circuit shown in Figure 8, VH1 provides a first high voltage signal VGH, VH2 provides a second high voltage signal VGH2, VH3 provides a second high voltage signal VGH2, VH4 provides a first high voltage signal VGH, VL3 provides a second low voltage signal VGL2, and VL1, VL2, VL4 and VL5 all provide a first low voltage signal VGL.

[0306] As shown in Figure 22, in at least one embodiment of the driving circuit shown in Figure 8, VH1 provides a first high voltage signal VGH, VH2 provides a second high voltage signal VGH2, VH3 provides a first high voltage signal VGH, VH4 provides a second high voltage signal VGH2, VL3 provides a second low voltage signal VGL2, and VL1, VL2, VL4 and VL5 all provide a first low voltage signal VGL.

[0307] As shown in Figure 23, in at least one embodiment of the driving circuit shown in Figure 8, VH1 provides a first high voltage signal VGH, VH2 provides a second high voltage signal VGH2, VH3 provides a second high voltage signal VGH2, VH4 provides a second high voltage signal VGH2, VL3 provides a second low voltage signal VGL2, and VL1, VL2, VL4 and VL5 all provide a first low voltage signal VGL.

[0308] As shown in Figure 24, in at least one embodiment of the driving circuit shown in Figure 8, VH1 provides a first high voltage signal VGH, VH2 provides a second high voltage signal VGH2, VH3 provides a first high voltage signal VGH, VH4 provides a first high voltage signal VGH, VL3 provides a second low voltage signal VGL2, VL2 provides a second low voltage signal VGL2, and VL1, VL4 and VL5 all provide a first low voltage signal VGL.

[0309] As shown in Figure 25, in at least one embodiment of the driving circuit shown in Figure 8, VH1 provides a first high voltage signal VGH, VH2 provides a second high voltage signal VGH2, VH3 provides a second high voltage signal VGH2, VH4 provides a first high voltage signal VGH, VL3 provides a second low voltage signal VGL2, VL2 provides a second low voltage signal VGL2, and VL1, VL4 and VL5 all provide a first low voltage signal VGL.

[0310] As shown in Figure 26, in at least one embodiment of the driving circuit shown in Figure 8, VH1 provides a first high voltage signal VGH, VH2 provides a second high voltage signal VGH2, VH3 provides a first high voltage signal VGH, VH4 provides a second high voltage signal VGH2, VL3 provides a second low voltage signal VGL2, VL2 provides a second low voltage signal VGL2, and VL1, VL4 and VL5 all provide a first low voltage signal VGL.

[0311] As shown in Figure 27, in at least one embodiment of the driving circuit shown in Figure 8, VH1 provides a first high voltage signal VGH, VH2 provides a second high voltage signal VGH2, VH3 provides a second high voltage signal VGH2, VH4 provides a second high voltage signal VGH2, VL3 provides a second low voltage signal VGL2, VL2 provides a second low voltage signal VGL2, and VL1, VL4 and VL5 all provide a first low voltage signal VGL.

[0312] As shown in Figure 28, in at least one embodiment of the driving circuit shown in Figure 9, VH1 provides a first high voltage signal VGH, VH2 provides a second high voltage signal VGH2, VH3 provides a first high voltage signal VGH, VH4 provides a first high voltage signal VGH, VL3 provides a second low voltage signal VGL2, VL2 provides a first low voltage signal VGL, and VL1, VL4 and VL5 all provide a first low voltage signal VGL.

[0313] As shown in Figure 29, in at least one embodiment of the driving circuit shown in Figure 9, VH1 provides a first high voltage signal VGH, VH2 provides a second high voltage signal VGH2, VH3 provides a second high voltage signal VGH2, VH4 provides a first high voltage signal VGH, VL3 provides a second low voltage signal VGL2, VL2 provides a first low voltage signal VGL, and VL1, VL4 and VL5 all provide a first low voltage signal VGL.

[0314] As shown in Figure 30, in at least one embodiment of the driving circuit shown in Figure 9, VH1 provides a first high voltage signal VGH, VH2 provides a second high voltage signal VGH2, VH3 provides a first high voltage signal VGH, VH4 provides a second high voltage signal VGH2, VL3 provides a second low voltage signal VGL2, VL2 provides a first low voltage signal VGL, and VL1, VL4 and VL5 all provide a first low voltage signal VGL.

[0315] As shown in Figure 31, in at least one embodiment of the driving circuit shown in Figure 9, VH1 provides a first high voltage signal VGH, VH2 provides a second high voltage signal VGH2, VH3 provides a second high voltage signal VGH2, VH4 provides a second high voltage signal VGH2, VL3 provides a second low voltage signal VGL2, VL2 provides a first low voltage signal VGL, and VL1, VL4 and VL5 all provide a first low voltage signal VGL.

[0316] The display panel according to at least one embodiment of the present disclosure includes the above-mentioned driving circuit; the display panel also includes a display driving chip;

[0317] The first high voltage input terminal is electrically connected to the first high voltage line, and the second high voltage input terminal is electrically connected to the second high voltage line; the first high voltage line and the second high voltage line are respectively electrically connected to different pins of the display driver chip, and the display driver chip is used to provide a first high voltage signal for the first high voltage line, and the display driver chip is used to provide a second high voltage signal for the second high voltage line.

[0318] In the display panel described in the embodiment of the present disclosure, the first high voltage input terminal is electrically connected to the first high voltage line, the second high voltage input terminal is electrically connected to the second high voltage line, the first high voltage line is electrically connected to the first pin of the display driver chip, and the second high voltage line is electrically connected to the second pin of the display driver chip. The display driver chip provides a first high voltage signal to the first high voltage line through the first pin, and the display driver chip provides a second high voltage signal to the second high voltage line through the second pin.

[0319] As shown in FIG32 , the display panel includes a display driver chip 320 ;

[0320] The first high voltage input terminal VH1 is electrically connected to the first high voltage line LH1, and the second high voltage input terminal VH2 is electrically connected to the second high voltage line LH2;

[0321] The first high voltage line LH1 is electrically connected to the first pin P1 of the display driver chip 320 , and the second high voltage line LH2 is electrically connected to the second pin P2 of the display driver chip 320 ;

[0322] The display driver chip 320 is used to provide a first high voltage signal to the first high voltage line LH1 , and the display driver chip 320 is used to provide a second high voltage signal to the second high voltage line LH2 .

[0323] The driving circuit according to at least one embodiment of the present disclosure includes a second output circuit, a second pull-down node control circuit, and a first control node control circuit;

[0324] The second output circuit is electrically connected to the pull-down node, the drive signal output terminal and the first low voltage input terminal respectively, and is used to control the connection between the drive signal output terminal and the first low voltage input terminal under the control of the potential of the pull-down node;

[0325] The second pull-down node control circuit is electrically connected to the third control node, the pull-down node, and the second low-voltage input terminal, respectively, and is configured to control the connection between the third control node and the pull-down node under the control of a low-voltage signal provided by the second low-voltage input terminal;

[0326] The first control node control circuit is electrically connected to the first clock signal terminal, the third low voltage input terminal and the first control node respectively, and is used to control the first control node to be electrically connected to the third low voltage input terminal under the control of the first clock signal provided by the first clock signal terminal;

[0327] At least two of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal are different from each other.

[0328] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a second control node control circuit;

[0329] The second control node control circuit is electrically connected to the fourth low voltage input terminal, the first control node, and the second control node, respectively, and is configured to control the communication between the first control node and the second control node under the control of a low voltage signal provided by the fourth low voltage input terminal;

[0330] The fourth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal.

[0331] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a third pull-down node control circuit;

[0332] The third pull-down node control circuit is electrically connected to the first node and the second clock signal terminal respectively, and is used to control the connection and disconnection between the first node and the second clock signal terminal;

[0333] The third pull-down node control circuit is further electrically connected to the second node, the third node, the fifth low-voltage input terminal, the first clock signal terminal, and the start signal terminal, respectively. Under the control of the potential of the second node, the third pull-down node control circuit controls the first node to be connected to the second clock signal terminal. According to the potential of the first node, the third pull-down node control circuit controls the potential of the second node to be connected to the third node. Under the control of the first clock signal provided by the first clock signal terminal, the third pull-down node control circuit controls the second node to be connected to the second node. Under the control of the low-voltage signal provided by the fifth low-voltage input terminal, the third pull-down node control circuit controls the second node to be connected to the pull-down node.

[0334] The fifth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, the third low voltage input terminal, and the fourth low voltage input terminal.

[0335] The display panel according to at least one embodiment of the present disclosure includes the above-mentioned driving circuit; the display panel also includes a display driving chip;

[0336] The first low voltage input terminal is electrically connected to the first low voltage line, the second low voltage input terminal is electrically connected to the second low voltage line, and the third low voltage input terminal is electrically connected to the third low voltage line. The first low voltage line, the second low voltage line, and the third low voltage line are electrically connected to different pins of the display driver chip, respectively. The display driver chip is used to provide a first low voltage signal for the first low voltage line, a second low voltage signal for the second low voltage line, and a third low voltage signal for the third low voltage line; or

[0337] The first low voltage input terminal is electrically connected to the first low voltage line, the second low voltage input terminal and the third low voltage input terminal are both electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal to the first low voltage line and provide a second low voltage signal to the second low voltage line; or

[0338] The first low voltage input terminal and the second low voltage input terminal are both electrically connected to the first low voltage line, the third low voltage input terminal is electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal to the first low voltage line and provide a second low voltage signal to the second low voltage line; or

[0339] The first low voltage input terminal and the third low voltage input terminal are both electrically connected to the first low voltage line, the second low voltage input terminal is electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are respectively electrically connected to different pins of the display driver chip, and the display driver chip is used to provide a first low voltage signal for the first low voltage line and provide a second low voltage signal for the second low voltage line.

[0340] As shown in FIG33 , the display panel includes a display driver chip 320 ;

[0341] The first low voltage input terminal VL1 is electrically connected to the first low voltage line Ld1, the second low voltage input terminal VL2 is electrically connected to the second low voltage line Ld2, and the third low voltage input terminal VL3 is electrically connected to the third low voltage line Ld3. The first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320, the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320, and the third low voltage line Ld3 is electrically connected to the third pin P3 of the display driver chip 320.

[0342] The display driver chip 320 is configured to provide a first low voltage signal to the first low voltage line Ld1 , a second low voltage signal to the second low voltage line Ld2 , and a third low voltage signal to the third low voltage line Ld3 .

[0343] As shown in FIG34 , the display panel includes a display driver chip 320 ;

[0344] The first low voltage input terminal VL1 is electrically connected to the first low voltage line Ld1, and the second low voltage input terminal VL2 and the third low voltage input terminal VL3 are both electrically connected to the second low voltage line Ld2;

[0345] The first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320 , and the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320 ;

[0346] The display driver chip 320 is configured to provide a first low voltage signal to the first low voltage line Ld1 and a second low voltage signal to the second low voltage line Ld2 .

[0347] As shown in FIG35 , the display panel includes a display driver chip 320 ;

[0348] The first low voltage input terminal VL1 and the second low voltage input terminal VL2 are both electrically connected to the first low voltage line Ld1, and the third low voltage input terminal VL3 is electrically connected to the second low voltage line Ld2;

[0349] The first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320 , and the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320 ;

[0350] The display driver chip 320 is configured to provide a first low voltage signal to the first low voltage line Ld1 and a second low voltage signal to the second low voltage line Ld2 .

[0351] As shown in FIG36 , the display panel includes a display driver chip 320 ;

[0352] The first low voltage input terminal VL1 and the third low voltage input terminal VL3 are both electrically connected to the first low voltage line Ld1, and the second low voltage input terminal VL2 is electrically connected to the second low voltage line Ld2;

[0353] The first low voltage line Ld1 is electrically connected to the first pin P1 of the display driver chip 320 , and the second low voltage line Ld2 is electrically connected to the second pin P2 of the display driver chip 320 ;

[0354] The display driver chip 320 is configured to provide a first low voltage signal to the first low voltage line Ld1 and a second low voltage signal to the second low voltage line Ld2 .

[0355] The display device described in the embodiment of the present disclosure includes the above-mentioned driving circuit.

[0356] The display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0357] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A driving circuit comprising a first output circuit and a first pull-up node control circuit; The first output circuit is electrically connected to the pull-up node, the first high voltage input terminal and the drive signal output terminal respectively, and is used to control the connection between the first high voltage input terminal and the drive signal output terminal under the control of the potential of the pull-up node; The first pull-up node control circuit is electrically connected to the pull-down node, the second high voltage input terminal and the pull-up node respectively, and is used to control the connection between the pull-up node and the second high voltage input terminal under the control of the potential of the pull-down node; The first high voltage input terminal and the second high voltage input terminal are different.

2. The driving circuit according to claim 1, wherein: Also included is a first pull-down node control circuit; The first pull-down node control circuit is electrically connected to the pull-down node, the third high voltage input terminal and the pull-down control terminal respectively, and is used to control the connection between the third high voltage input terminal and the pull-down node under the control of the pull-down control signal provided by the pull-down control terminal; The third high voltage input terminal is different from at least one of the first high voltage input terminal and the second high voltage input terminal.

3. The driving circuit according to claim 1, wherein: Also includes a first node control circuit and a fourth high voltage input terminal; The first node control circuit is electrically connected to the first node, the first control terminal, and the fourth high voltage input terminal, respectively, and is configured to control the connection between the first node and the fourth high voltage input terminal under the control of the potential of the first control terminal; the first control terminal is the first control node or the second control node; The fourth high voltage input terminal is different from at least one of the first high voltage input terminal and the second high voltage input terminal.

4. The driving circuit according to claim 1, wherein: Also included is a second output circuit, a second pull-down node control circuit, and a first control node control circuit; The second output circuit is electrically connected to the pull-down node, the drive signal output terminal and the first low voltage input terminal respectively, and is used to control the connection between the drive signal output terminal and the first low voltage input terminal under the control of the potential of the pull-down node; The second pull-down node control circuit is electrically connected to the third control node, the pull-down node, and the second low-voltage input terminal, respectively, and is configured to control the connection between the third control node and the pull-down node under the control of a low-voltage signal provided by the second low-voltage input terminal; The first control node control circuit is electrically connected to the first clock signal terminal, the third low voltage input terminal and the first control node respectively, and is used to control the first control node to be electrically connected to the third low voltage input terminal under the control of the first clock signal provided by the first clock signal terminal; At least two of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal are different from each other.

5. The driving circuit according to claim 4, wherein: Also included is a second control node control circuit; The second control node control circuit is electrically connected to the fourth low voltage input terminal, the first control node and the second control node respectively, and is used to control the connection between the first control node and the second control node under the control of the low voltage signal provided by the fourth low voltage input terminal.

6. The driving circuit according to claim 5, wherein: The fourth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal.

7. The driving circuit according to claim 4, wherein: Also included is a third pull-down node control circuit; The third pull-down node control circuit is electrically connected to the first node and the second clock signal terminal respectively, and is used to control the connection and disconnection between the first node and the second clock signal terminal.

8. The driving circuit according to claim 7, wherein: The third pull-down node control circuit is also electrically connected to the pull-down node, the second node, the third node, the fifth low voltage input terminal, the first clock signal terminal and the start signal terminal, respectively. Under the control of the potential of the second node, the first node is controlled to be connected to the second clock signal terminal. According to the potential of the first node, the potential of the second node is controlled. Under the control of the first clock signal provided by the first clock signal terminal, the start signal terminal is controlled to be connected to the third node. Under the control of the low voltage signal provided by the fifth low voltage input terminal, the third node is controlled to be connected to the second node. Under the control of the potential of the second node, the second node is controlled to be connected to the pull-down node.

9. The driving circuit according to claim 8, wherein: The fifth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal.

10. The driving circuit according to claim 3, wherein: The first output circuit includes a first transistor, the first pull-up node control circuit includes a second transistor, and the first pull-down node control circuit includes a third transistor; The control electrode of the first transistor is electrically connected to the pull-up node, the first electrode of the first transistor is electrically connected to the first high voltage input terminal, and the second electrode of the first transistor is electrically connected to the drive signal output terminal; The control electrode of the second transistor is electrically connected to the pull-down node, the first electrode of the second transistor is electrically connected to the second high voltage input terminal, and the second electrode of the second transistor is electrically connected to the pull-up node; The control electrode of the third transistor is electrically connected to the pull-down control terminal, the first electrode of the third transistor is electrically connected to the third high voltage input terminal, and the second electrode of the third transistor is electrically connected to the pull-down node; The first high voltage input terminal is a first high voltage terminal, and the second high voltage input terminal and the third high voltage input terminal are second high voltage terminals; or, The first high voltage input terminal is the second high voltage terminal, and the second high voltage input terminal and the third high voltage input terminal are the first high voltage terminal; or, The first high voltage input terminal is a first high voltage terminal, the second high voltage input terminal is a second high voltage terminal, and the third high voltage input terminal is a third high voltage terminal; or, The first high voltage input terminal and the third high voltage input terminal are first high voltage terminals, and the second high voltage input terminal is a second high voltage terminal.

11. The driving circuit according to claim 10, wherein: The first node control circuit includes a fourth transistor; The control electrode of the fourth transistor is electrically connected to the first control node, the first electrode of the fourth transistor is electrically connected to the fourth high voltage input terminal, and the second electrode of the fourth transistor is electrically connected to the first node; The first high voltage input terminal, the third high voltage input terminal and the fourth high voltage input terminal are first high voltage terminals, and the second high voltage input terminal is a second high voltage terminal; or, The first high voltage input terminal and the fourth high voltage input terminal are first high voltage terminals, and the second high voltage input terminal and the third high voltage input terminal are second high voltage terminals; or, The first high voltage input terminal and the third high voltage input terminal are first high voltage terminals, and the second high voltage input terminal and the fourth high voltage input terminal are second high voltage terminals; or, The first high voltage input terminal is a first high voltage terminal, and the second high voltage input terminal, the third high voltage input terminal, and the fourth high voltage input terminal are second high voltage terminals.

12. The driving circuit according to claim 4, wherein: The second output circuit includes a fifth transistor, the second pull-down node control circuit includes a sixth transistor, and the first control node control circuit includes a seventh transistor; The control electrode of the fifth transistor is electrically connected to the pull-down node, the first electrode of the fifth transistor is electrically connected to the drive signal output terminal, and the second electrode of the fifth transistor is electrically connected to the first low voltage input terminal; The control electrode of the sixth transistor is electrically connected to the second low voltage input terminal, the first electrode of the sixth transistor is electrically connected to the third control node, and the second electrode of the sixth transistor is electrically connected to the pull-down node; The control electrode of the seventh transistor is electrically connected to the first clock signal terminal, the first electrode of the seventh transistor is electrically connected to the third low voltage input terminal, and the second electrode of the seventh transistor is electrically connected to the first control node; The first low voltage input terminal and the second low voltage input terminal are first low voltage terminals, and the third low voltage input terminal is a second low voltage terminal; or, The first low voltage input terminal is a first low voltage terminal, and the second low voltage input terminal and the third low voltage input terminal are second low voltage terminals.

13. The driving circuit according to claim 5, wherein: The second control node control circuit includes an eighth transistor; The control electrode of the eighth transistor is electrically connected to the fourth low voltage input terminal, the first electrode of the eighth transistor is electrically connected to the first control node, and the second electrode of the eighth transistor is electrically connected to the second control node; The fourth low voltage input terminal is the first low voltage terminal or the second low voltage terminal.

14. The driving circuit according to claim 7, wherein: The third pull-down node control circuit includes a first capacitor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the second node; The control electrode of the ninth transistor is electrically connected to the second node, the first electrode of the ninth transistor is electrically connected to the first node, and the second electrode of the ninth transistor is electrically connected to the second clock signal terminal; The control electrode of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is electrically connected to the pull-down node, and the second electrode of the tenth transistor is electrically connected to the second node; The control electrode of the eleventh transistor is electrically connected to the fifth low voltage input terminal, the first electrode of the eleventh transistor is electrically connected to the third node, and the second electrode of the eleventh transistor is electrically connected to the second node; The control electrode of the twelfth transistor is electrically connected to the first clock signal terminal, the first electrode of the twelfth transistor is electrically connected to the start signal terminal, and the second electrode of the twelfth transistor is electrically connected to the third node.

15. The driving circuit according to claim 14, wherein: The fifth low voltage input terminal is the first low voltage terminal or the second low voltage terminal.

16. The driving circuit according to any one of claims 4 to 15, wherein: The driving circuit includes a first control node control circuit, a third control node control circuit and a second pull-up node control circuit; The first control node control circuit is electrically connected to the first control node, and is also electrically connected to a third control node, and is configured to control the connection between the first control node and the first clock signal terminal under the control of the potential of the third control node; The third control node control circuit is electrically connected to the first clock signal terminal, the start signal terminal and the third control node respectively, and is used to control the start signal terminal to be electrically connected to the third control node under the control of the first clock signal provided by the first clock signal terminal; The second pull-up node control circuit is also electrically connected to the first control node or the second control node, the fourth control node, the second clock signal terminal and the first high voltage input terminal, respectively, and is used to control the potential of the fourth control node according to the potential of the second control node, and under the control of the potential of the first control node or the potential of the second control node, control the connection between the second clock signal terminal and the fourth control node, and under the control of the second clock signal provided by the second clock signal terminal, control the connection between the fourth control node and the pull-up node, and maintain the potential of the pull-up node.

17. The driving circuit according to claim 16, wherein: The first control node control circuit includes a thirteenth transistor, the third control node control circuit includes a fourteenth transistor, and the second pull-up node control circuit includes a second capacitor, a third capacitor, a fifteenth transistor, and a sixteenth transistor; The control electrode of the thirteenth transistor is electrically connected to the third control node, the first electrode of the thirteenth transistor is electrically connected to the first control node, and the second electrode of the thirteenth transistor is electrically connected to the first clock signal terminal; The control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourteenth transistor is electrically connected to the start signal terminal, and the second electrode of the fourteenth transistor is electrically connected to the third control node; A first end of the second capacitor is electrically connected to the second control node, and a second end of the second capacitor is electrically connected to the fourth control node; A first end of the third capacitor is electrically connected to the pull-up node, and a second end of the third capacitor is electrically connected to the first high voltage input terminal; The control electrode of the fifteenth transistor is electrically connected to the second control node, the first electrode of the fifteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifteenth transistor is electrically connected to the fourth control node; The control electrode of the sixteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixteenth transistor is electrically connected to the fourth control node, and the second electrode of the sixteenth transistor is electrically connected to the pull-up node.

18. A driving circuit, comprising a second output circuit, a second pull-down node control circuit, and a first control node control circuit; The second output circuit is electrically connected to the pull-down node, the drive signal output terminal and the first low voltage input terminal respectively, and is used to control the connection between the drive signal output terminal and the first low voltage input terminal under the control of the potential of the pull-down node; The second pull-down node control circuit is electrically connected to the third control node, the pull-down node, and the second low-voltage input terminal, respectively, and is configured to control the connection between the third control node and the pull-down node under the control of a low-voltage signal provided by the second low-voltage input terminal; The first control node control circuit is electrically connected to the first clock signal terminal, the third low voltage input terminal and the first control node respectively, and is used to control the first control node to be electrically connected to the third low voltage input terminal under the control of the first clock signal provided by the first clock signal terminal; At least two of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal are different from each other.

19. The driving circuit according to claim 18, wherein: Also included is a second control node control circuit; The second control node control circuit is electrically connected to the fourth low voltage input terminal, the first control node, and the second control node, respectively, and is configured to control the communication between the first control node and the second control node under the control of a low voltage signal provided by the fourth low voltage input terminal; The fourth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, and the third low voltage input terminal.

20. The driving circuit according to claim 19, wherein: Also included is a third pull-down node control circuit; The third pull-down node control circuit is electrically connected to the first node and the second clock signal terminal respectively, and is used to control the connection and disconnection between the first node and the second clock signal terminal; The third pull-down node control circuit is further electrically connected to the second node, the third node, the fifth low-voltage input terminal, the first clock signal terminal, and the start signal terminal, respectively. Under the control of the potential of the second node, the third pull-down node control circuit controls the first node to be connected to the second clock signal terminal. According to the potential of the first node, the third pull-down node control circuit controls the potential of the second node to be connected to the third node. Under the control of the first clock signal provided by the first clock signal terminal, the third pull-down node control circuit controls the second node to be connected to the second node. Under the control of the low-voltage signal provided by the fifth low-voltage input terminal, the third pull-down node control circuit controls the second node to be connected to the pull-down node. The fifth low voltage input terminal is different from at least one of the first low voltage input terminal, the second low voltage input terminal, the third low voltage input terminal, and the fourth low voltage input terminal.

21. A display panel comprising the driving circuit according to any one of claims 1 to 20; the display panel further comprising a display driver chip; The first high voltage input terminal is electrically connected to the first high voltage line, and the second high voltage input terminal is electrically connected to the second high voltage line; the first high voltage line and the second high voltage line are respectively electrically connected to different pins of the display driver chip, and the display driver chip is used to provide a first high voltage signal for the first high voltage line, and the display driver chip is used to provide a second high voltage signal for the second high voltage line.

22. A display panel comprising the driving circuit according to any one of claims 18 to 20; the display panel further comprising a display driver chip; The first low voltage input terminal is electrically connected to the first low voltage line, the second low voltage input terminal is electrically connected to the second low voltage line, and the third low voltage input terminal is electrically connected to the third low voltage line. The first low voltage line, the second low voltage line, and the third low voltage line are electrically connected to different pins of the display driver chip, respectively. The display driver chip is used to provide a first low voltage signal for the first low voltage line, a second low voltage signal for the second low voltage line, and a third low voltage signal for the third low voltage line. or, The first low voltage input terminal is electrically connected to the first low voltage line, the second low voltage input terminal and the third low voltage input terminal are both electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal to the first low voltage line and provide a second low voltage signal to the second low voltage line; or The first low voltage input terminal and the second low voltage input terminal are both electrically connected to the first low voltage line, the third low voltage input terminal is electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are electrically connected to different pins of the display driver chip, respectively, and the display driver chip is used to provide a first low voltage signal to the first low voltage line and provide a second low voltage signal to the second low voltage line; or The first low voltage input terminal and the third low voltage input terminal are both electrically connected to the first low voltage line, the second low voltage input terminal is electrically connected to the second low voltage line, the first low voltage line and the second low voltage line are respectively electrically connected to different pins of the display driver chip, and the display driver chip is used to provide a first low voltage signal for the first low voltage line and provide a second low voltage signal for the second low voltage line.

23. A display device comprising the driving circuit according to any one of claims 1 to 20.