Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel comprises a substrate, a circuit structure layer, a light-emitting structure layer, and a plurality of transparent conductive layers. The transparent conductive layers are located between the circuit structure layer and the light-emitting structure layer, and comprise a plurality of first-type conductive wires and a plurality of second-type conductive wires. The orthographic projection of the parts of the first-type conductive wires extending in a first direction overlaps with the orthographic projection of shielding electrodes (60) on the substrate, and the orthographic projection of the parts of the second-type conductive wires extending in the first direction does not overlap with the orthographic projection of the shielding electrodes (60) on the substrate. At least one first-type first light-emitting device is connected to at least one first pixel driving circuit (QD1) by means of at least one first-type conductive wire, and at least one second-type first light-emitting device is connected to at least one first pixel driving circuit (QD1) by means of at least one second-type conductive wire. The first-type first light-emitting device is configured to emit first color light, the second-type first light-emitting device is configured to emit second color light, and the second color light is different from the first color light.

Description

Display panel and display device Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. Under-display camera technology is a new technology proposed to increase the screen-to-body ratio of display devices.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, an embodiment of the present disclosure provides a display panel, comprising: a substrate, a circuit structure layer and a light-emitting structure layer stacked on the substrate, and a plurality of conductive layers disposed between the circuit structure layer and the light-emitting structure layer; wherein,

[0006] The substrate comprises: a first display area and a second display area, wherein the second display area is located on at least one side of the first display area, and the light transmittance of the first display area is greater than the light transmittance of the second display area;

[0007] The circuit structure layer includes: a first gate signal line located in the second display area, a constant voltage line, a plurality of shielding electrodes, and a plurality of pixel circuits, wherein the pixel circuit includes a driving transistor, the driving transistor includes a gate, and the plurality of pixel circuits include a plurality of first pixel driving circuits; the first gate signal line is connected to the gate of the driving transistor; the constant voltage line is configured to provide a first constant voltage to the plurality of pixel circuits; the shielding electrode is connected to the constant voltage line, and an orthographic projection of the first gate signal line on the substrate falls within an orthographic projection of the shielding electrode on the substrate;

[0008] The plurality of conductive layers include: a plurality of conductive lines, the plurality of conductive lines including: a plurality of first-type conductive lines and a plurality of second-type conductive lines, wherein the orthographic projections of portions of the first-type conductive lines extending along the first direction overlap with the orthographic projections of at least one of the plurality of shielding electrodes on the substrate, and the orthographic projections of portions of the second-type conductive lines extending along the first direction do not overlap with the orthographic projections of the plurality of shielding electrodes on the substrate;

[0009] The light-emitting structure layer includes: a plurality of first light-emitting devices located in the first display area, the plurality of first light-emitting devices including: a plurality of first-type first light-emitting devices and a plurality of second-type first light-emitting devices, at least one first-type first light-emitting device among the plurality of first-type first light-emitting devices is connected to at least one first pixel driving circuit among the plurality of first pixel driving circuits through at least one first-type conductive line among the plurality of first-type conductive lines, and at least one second-type first light-emitting device among the plurality of second-type first light-emitting devices is connected to at least one first pixel driving circuit among the plurality of first pixel driving circuits through at least one second-type conductive line among the plurality of second-type conductive lines, the first pixel driving circuit is configured to drive the first light-emitting device to emit light, the first-type first light-emitting device is configured to emit a first color light, and the second-type first light-emitting device is configured to emit a second color light, which is different from the first color light.

[0010] On the other hand, an embodiment of the present disclosure further provides a display device, including: a display panel as described in the above embodiment.

[0011] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. Other advantages of the present disclosure can be realized and obtained through the solutions described in the description and the drawings.

[0012] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are intended to facilitate understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not limit the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0014] FIG1 is a schematic structural diagram of a display panel in an embodiment of the present disclosure;

[0015] FIG2 is a schematic plan view of a display panel in an embodiment of the present disclosure;

[0016] FIG3 is an equivalent circuit diagram of a pixel driving circuit in an embodiment of the present disclosure;

[0017] FIG4 is a first partial schematic diagram of a display panel in an embodiment of the present disclosure;

[0018] FIG5 is a schematic diagram of a conductive line passing through a shielding electrode in a first display area in some technologies;

[0019] FIG6A is a second partial schematic diagram of a display panel according to an embodiment of the present disclosure;

[0020] FIG6B is a third partial schematic diagram of a display panel according to an embodiment of the present disclosure;

[0021] FIG6C is a fourth partial schematic diagram of a display panel according to an embodiment of the present disclosure;

[0022] FIG7 is a schematic diagram of a first connection between a first light emitting device and a first pixel driving circuit in an exemplary embodiment of the present disclosure;

[0023] FIG8 is a schematic diagram showing the connection of the first transparent conductive line of the first transparent conductive layer in FIG7 ;

[0024] FIG9 is a schematic diagram showing the connection of the second transparent conductive line of the second transparent conductive layer in FIG7 ;

[0025] FIG10 is a schematic diagram showing the connection of the third transparent conductive line of the third transparent conductive layer in FIG7 ;

[0026] FIG11 is a schematic diagram showing the connection of metal conductive wires of the metal conductive layer in FIG7 ;

[0027] FIG12 is a schematic diagram of a second connection between the first light emitting device and the first pixel driving circuit in an exemplary embodiment of the present disclosure;

[0028] FIG13 is a schematic diagram of a third connection between the first light emitting device and the first pixel driving circuit in an exemplary embodiment of the present disclosure;

[0029] FIG14 is a schematic diagram of an embodiment of the present disclosure after forming a semiconductor layer;

[0030] FIG15A is a schematic diagram of an embodiment of the present disclosure after forming a first conductive layer;

[0031] FIG15B is a schematic plan view of the first conductive layer in FIG15A ;

[0032] FIG16A is a schematic diagram of an embodiment of the present disclosure after forming a second conductive layer;

[0033] FIG16B is a schematic plan view of the second conductive layer in FIG16A ;

[0034] FIG17 is a schematic diagram of an embodiment of the present disclosure after forming a fourth insulating layer;

[0035] FIG18A is a schematic diagram of an embodiment of the present disclosure after forming a third conductive layer;

[0036] FIG18B is a schematic plan view of the third conductive layer in FIG18A ;

[0037] FIG19 is a schematic diagram of an embodiment of the present disclosure after forming a fifth insulating layer;

[0038] FIG20A is a schematic diagram of an embodiment of the present disclosure after forming a fourth conductive layer;

[0039] FIG20B is a schematic plan view of the fourth conductive layer in FIG20A ;

[0040] FIG21A is a schematic diagram of an embodiment of the present disclosure after forming a first transparent conductive layer;

[0041] FIG21B is a schematic plan view of the first transparent conductive layer in FIG21A ;

[0042] FIG22A is a schematic diagram of an embodiment of the present disclosure after forming a second transparent conductive layer;

[0043] FIG22B is a schematic plan view of the second transparent conductive layer in FIG22A ;

[0044] FIG23A is a schematic diagram of an embodiment of the present disclosure after forming a third transparent conductive layer;

[0045] FIG23B is a schematic plan view of the third transparent conductive layer in FIG23A ;

[0046] FIG24A is a first schematic diagram of an embodiment of the present disclosure after forming an anode layer;

[0047] FIG24B is a schematic plan view of the anode layer in FIG23A;

[0048] FIG24C is a second schematic diagram of an embodiment of the present disclosure after forming an anode layer;

[0049] FIG25 is a schematic diagram of an embodiment of the present disclosure after forming a pixel definition layer. DETAILED DESCRIPTION

[0050] A number of embodiments are described herein, but this description is exemplary and not restrictive, and more embodiments and implementations may be possible within the scope of the embodiments described herein. Although many possible feature combinations are shown in the drawings and discussed in the exemplary embodiments, many other combinations of the disclosed features are possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0051] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0052] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0053] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0054] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the circumstances.

[0055] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0056] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode (gate or control electrode), a drain electrode (drain electrode terminal, drain region, or drain), and a source electrode (source electrode terminal, source region, or source). A transistor has a channel region between the drain and source electrodes, and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0057] In this specification, in order to distinguish the two poles of a transistor other than the gate electrode (gate or control electrode), one of the poles is directly described as the first pole and the other pole as the second pole, wherein the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In the case of using transistors with opposite polarity or the case where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged.

[0058] The transistors in the embodiments of the present disclosure may be thin film transistors (TFTs) or field effect transistors (FETs) or other devices with the same characteristics. For example, the thin film transistors used in the embodiments of the present disclosure may include, but are not limited to, oxide TFTs or low temperature polysilicon TFTs (LTPS TFTs). The embodiments of the present disclosure do not limit this.

[0059] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0060] In this disclosure, the terms "approximately", "substantially", and "approximately" are used without strict boundaries and allow for process and measurement errors. For example, in this disclosure, "substantially the same" means that the values ​​differ by less than 10%.

[0061] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0062] In the embodiment of the present disclosure, the first direction X may refer to the extending direction of the gate lines in the display area or the horizontal direction, the second direction Y may refer to the extending direction of the data lines in the display area or the vertical direction, and the third direction Z may refer to the direction perpendicular to the plane of the display panel or the thickness direction of the display panel, etc. The first direction X and the second direction Y may be perpendicular to each other, and the first direction X and the third direction Z may be perpendicular to each other.

[0063] With the development of display technology, full-screen or narrow-bezel products, with their larger screen-to-body ratios and ultra-narrow bezels, have gradually become the development trend of display products. Products such as smart terminals are often equipped with sensors such as camera sensors or fingerprint sensors. To increase the screen-to-body ratio, full-screen or narrow-bezel products often use under-screen camera technology (FDC) or under-screen fingerprint technology. These sensors are placed in the under-display camera (UDC) area of ​​the display panel. The under-display camera area not only has a certain degree of transmittance but also has display functionality, achieving full display in the camera area (FDC).

[0064] Figure 1 is a schematic diagram of the structure of a display panel. As shown in Figure 1, on a plane parallel to the display panel, the display area AA of the display panel may include: a first display area AA1 and a second display area AA2. The second display area AA2 may be located on at least one side of the first display area AA1. For example, the second display area AA2 may at least partially surround the first display area AA1. For example, the second display area AA2 may include: a transition display area AAG, and the transition display area AAG is adjacent to the first display area AA1. For example, the position of the first display area AA1 may correspond to the position of the sensor and be configured to display an image and transmit light. The transmitted light is received by the sensor. The first display area AA1 may also be referred to as a sensor corresponding area, an under-screen camera display area, or a light-transmitting display area. For example, the second display area AA2 is configured to display an image. The second display area AA2 may also be referred to as a normal resolution display area, a normal sub-pixel area, or a low-transmittance display area. For example, the transition display area AAG is configured to display images and configure signal lines, and the signal lines are connected to the signal lines in the light-transmitting display area to lead out these signal lines. The transition display area AAG can also be called a dummy sub-pixel area.

[0065] In an exemplary embodiment, the light transmittance of the first display area AA1 is higher than the light transmittance of the second display area AA2. The light transmittance of the first display area AA1 is higher than the light transmittance of the transition display area AAG. Here, light transmittance refers to the ability of light to pass through a medium, which is the percentage of the luminous flux passing through a transparent or translucent body to its incident luminous flux. In this way, since the position of the first display area AA1 can correspond to the position of the sensor, the orthographic projection of the sensor on the display panel and the first display area AA1 have an overlapping area, which can enable more light to pass through the display panel and be received by the sensor. For example, "the orthographic projection of the sensor on the display panel and the first display area AA1 have an overlapping area" can mean that a part of the orthographic projection of the sensor on the display panel is located within the first display area AA1, or the entire orthographic projection of the sensor on the display panel is located within the first display area AA1, or the orthographic projection of the sensor's light-sensitive window on the display panel is located within the first display area AA1, etc. Here, the embodiments of the present disclosure are not limited to this.

[0066] In an exemplary embodiment, the resolution of the first display area AA1 and the second display area AA2 can be the same, or the resolution of the first display area AA1 can be lower than the resolution of the second display area AA2. Pixels Per Inch (PPI) refers to the number of pixels per unit area, also known as pixel density. A higher PPI value indicates that the display panel can display images at a higher density, resulting in richer image details.

[0067] In an exemplary embodiment, the first display area AA1 may be located at the top, bottom, or edge of the display area of ​​the display panel. For example, the first display area AA1 may be located in the top center of the display area of ​​the display panel, and the second display area AA2 may surround the first display area AA1. Alternatively, the first display area AA1 may be located at other locations such as the upper left corner or upper right corner of the display area of ​​the display panel, and the second display area AA2 may surround at least one side of the first display area AA1 (for example, one side, both sides, left and right, etc.). This is not limited in the embodiments of the present disclosure.

[0068] In an exemplary embodiment, within a plane parallel to the display panel, the shape of the first display area AA1 may be any one or more of the following: square, rectangle, polygon, circle, ellipse, semicircle, or pentagon. For example, the display area of ​​the display panel may be rectangular, such as a rounded rectangle, and the first display area AA1 may be circular. This is not limited in the present disclosure.

[0069] In an exemplary embodiment, in a plane parallel to the display panel, the shape of the outer contour of the transition display area AAG may be any one or more of the following: rectangular, polygonal, circular, and elliptical, etc. This is not limited in the present embodiment.

[0070] In an exemplary embodiment, the sensor may include, but is not limited to, a camera sensor, a fingerprint sensor, a light sensor, an infrared sensor, an ultrasonic sensor, a LIDAR (Light Detection and Ranging) sensor, or a radar sensor, etc. The present disclosure does not limit this.

[0071] In one exemplary embodiment, on a plane perpendicular to the display panel, the first display area AA1 may include: a first circuit structure layer disposed on a substrate and a first light-emitting structure layer disposed on a side of the first circuit structure layer away from the substrate. The second display area AA2 may include a second circuit structure layer disposed on a substrate and a second light-emitting structure layer disposed on a side of the second circuit structure layer away from the substrate.

[0072] In one exemplary embodiment, the first circuit structure layer of the first display area AA1 includes multiple stacked insulating layers, which can be referred to as a composite insulating layer. The first light-emitting structure layer of the first display area AA1 can include multiple functional sub-pixels, each of which can include a first light-emitting device sp1. The first light-emitting device sp1 can include at least a first anode. The first anode of at least one functional sub-pixel is connected to at least one first pixel driving circuit QD1 in the transition display area AAG in the second display area AA2 via a conductive line (e.g., a transparent conductive line). The first pixel driving circuit QD1 is configured to output a corresponding current to the connected first light-emitting device sp1 via the conductive line. The first light-emitting device sp1 is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0073] In one exemplary embodiment, the second circuit structure layer of the second display area AA2 may include: a plurality of first pixel drive circuits QD1 and a plurality of second pixel drive circuits QD2. The second circuit structure layer may be referred to as a drive structure layer. The region of the second display area AA2 where the first pixel drive circuit QD1 is disposed may be referred to as a transition display area AAG. The second light-emitting structure layer of the second display area AA2 may include a plurality of normal sub-pixels. Each normal sub-pixel may include a second light-emitting device sp2. The second light-emitting device sp2 may include at least a second anode. The second anode of at least one normal sub-pixel is connected to at least one second pixel drive circuit QD2. The second pixel drive circuit QD2 is configured to directly output a corresponding current to the connected second light-emitting device sp2. The second light-emitting device sp2 is configured to emit light of corresponding brightness in response to the current output by the connected pixel drive circuit.

[0074] For example, the first light-emitting device sp1 and the first pixel driving circuit QD1 driving the first light-emitting device are located in different display areas. Therefore, the first light-emitting device sp1 can be referred to as a non-in-situ driven light-emitting device, and the first pixel driving circuit QD1 can be referred to as a non-in-situ pixel driving circuit. For example, the second light-emitting device sp2 and the second pixel driving circuit QD2 driving the second light-emitting device are both located in the second display area AA2. Therefore, the second light-emitting device sp2 can be referred to as an in-situ driven light-emitting device, and the second pixel driving circuit QD2 can be referred to as an in-situ pixel driving circuit.

[0075] In an exemplary embodiment, a display area of ​​a display panel may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P may include a plurality of sub-pixels. A sub-pixel may be the smallest portion whose brightness can be controlled. At least one sub-pixel may include a light-emitting device and a pixel driver circuit connected to the light-emitting device, the pixel driver circuit being configured to drive the connected light-emitting device to emit light.

[0076] In an exemplary embodiment, the light-emitting device may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including a mini-LED or a micro-LED), etc. For example, the light-emitting device may be an OLED, which emits red light, green light, blue light, or white light when driven by its corresponding pixel driving circuit.

[0077] In an exemplary embodiment, taking an OLED as an example, the light emitting device may include an anode, a cathode, and an organic light emitting layer located between the anode and the cathode. The anode of the light emitting device may be electrically connected to a corresponding pixel driving circuit.

[0078] In an exemplary embodiment, the color of the light emitted by the light-emitting device can be determined by those skilled in the art based on the actual application scenario. For example, at least one of the multiple pixel units P can include three sub-pixels, and the three sub-pixels can include: a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. For another example, at least one of the multiple pixel units P can include: four sub-pixels, and the four sub-pixels can be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. Here, the embodiments of the present disclosure are not limited to this.

[0079] In an exemplary embodiment, the shape of the light emitting device may be rectangular, rhombus, pentagonal, hexagonal, or the like.

[0080] In an exemplary embodiment, the plurality of sub-pixels in a pixel unit may be arranged in a horizontal parallel, vertical parallel, X-shaped, cross-shaped or herringbone-shaped arrangement. For example, taking a pixel unit including three sub-pixels as an example, the three sub-pixels may be arranged in a horizontal parallel, vertical parallel or herringbone-shaped arrangement. For example, taking a pixel unit including four sub-pixels as an example, the four sub-pixels may be arranged in a horizontal parallel, vertical parallel, square-shaped or diamond-shaped arrangement. For example, as shown in FIG2 , taking four sub-pixels including: a red sub-pixel, a blue sub-pixel and two green sub-pixels as an example, the four sub-pixels may be arranged in a diamond-shaped arrangement to form an RGGB pixel arrangement. Here, the embodiments of the present disclosure do not limit this.

[0081] In an exemplary embodiment, the arrangement of the pixel units in the first display area AA1 may be the same as or different from the arrangement of the pixel units in the second display area AA2. The number of sub-pixels included in the pixel units in the first display area AA1 may be the same as or different from the number of sub-pixels included in the pixel units in the second display area AA2. The arrangement of the sub-pixels included in the pixel units in the first display area AA1 may be the same as or different from the arrangement of the sub-pixels included in the pixel units in the second display area AA2. This is not limited in the embodiments of the present disclosure.

[0082] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure.

[0083] In an exemplary embodiment, the pixel driving circuit of this exemplary embodiment adopts a 7T1C structure as an example for explanation. FIG3 is an equivalent circuit diagram of the pixel driving circuit in the embodiment of the present disclosure. As shown in FIG3, the pixel driving circuit may include: 7 transistors (first transistor T1 to seventh transistor T7) and a storage capacitor Cst. The pixel driving circuit may be connected to 8 signal lines (scan signal line GL, data signal line DL, first power line PL1, second power line PL2, emission control line EML, first initial signal line INIT1, second initial signal line INIT2, first reset control line RST1, and second reset control line RST2). Among them, the third transistor T3 can also be called a driving transistor, the fourth transistor T4 can also be called a data writing transistor, the second transistor T2 can also be called a threshold compensation transistor, the fifth transistor T5 can also be called a first emission control transistor, the sixth transistor T6 can also be called a second emission control transistor, the first transistor T1 can also be called a first reset transistor, and the seventh transistor T7 can also be called a second reset transistor.

[0084] In an exemplary embodiment, transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0085] In one exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0086] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, and oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display panel to form a low-temperature polycrystalline oxide (LTPO) display panel can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0087] In one exemplary embodiment, as shown in FIG3 , a display panel may include scan signal lines GL, data signal lines DL, a first power line PL1, a second power line PL2, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. In one exemplary embodiment, the first power line PL1 may be configured to provide a constant first voltage signal VDD to the pixel driving circuit, and the second power line PL2 may be configured to provide a constant second voltage signal VSS to the pixel driving circuit, with the first voltage signal VDD being greater than the second voltage signal VSS. The scan signal lines GL may be configured to provide a scan signal SCAN to the pixel driving circuit, the data signal lines DL may be configured to provide a data signal DATA to the pixel driving circuit, the emission control line EML may be configured to provide an emission control signal EM to the pixel driving circuit, the first reset control line RST1 may be configured to provide a first reset control signal RESET1 to the pixel driving circuit, and the second reset control line RST2 may be configured to provide a second reset control signal RESET2 to the pixel driving circuit. In an exemplary embodiment, in the n-th row pixel driving circuit, the first reset control line RST1 can be electrically connected to the scan signal line GL of the n-1-th row pixel driving circuit to be input with the scan signal SCAN(n-1), that is, the first reset control signal RESET1(n) is the same as the scan signal SCAN(n-1). The second reset control line RST2 can be electrically connected to the scan signal line GL of the n-th row pixel driving circuit to be input with the scan signal SCAN(n), that is, the second reset control signal RESET2(n) is the same as the scan signal SCAN(n). In an exemplary embodiment, the second reset control line RST2 electrically connected to the n-th row pixel driving circuit and the first reset control line RST1 electrically connected to the n+1-th row pixel driving circuit can be an integrated structure. Wherein, n is an integer greater than 0. In this way, the signal lines of the display panel can be reduced, and a narrow frame design of the display panel can be achieved. However, this embodiment is not limited to this.

[0088] In one exemplary embodiment, the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel driving circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel driving circuit. For example, the first initial signal can be different from the second initial signal. The first initial signal and the second initial signal can be constant voltage signals, whose magnitudes can be, for example, between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto. In other examples, the first initial signal and the second initial signal can be the same, and only the first initial signal line can be provided to provide the first initial signal.

[0089] In one exemplary embodiment, to save wiring, the first power line PL1 can serve as a constant voltage line. For example, in other examples, to save wiring, the first initial signal line INIT1 can also serve as a constant voltage line. Examples of constant voltage lines are not limited to the first power line PL1 and the first initial signal line INIT1; any signal line that provides a constant voltage in the pixel circuit can serve as a constant voltage line.

[0090] In an exemplary embodiment, the scan signal line GL, the emission control line EML, the first initial signal line INIT1, the second initial signal line INIT2, the first reset control line RST1 and the second reset control line RST2 can extend in the horizontal direction, and the first power line PL1, the second power line PL2 and the data signal line DL can extend in the vertical direction.

[0091] In an exemplary embodiment, as shown in FIG3 , the third transistor T3 is electrically connected to the light-emitting device EL and outputs a driving current under the control of signals such as a scan signal SCAN, a data signal DATA, a first voltage signal VDD, and a second voltage signal VSS to drive the light-emitting device EL to emit light. The gate of the fourth transistor T4 is electrically connected to the scan signal line GL, the first electrode of the fourth transistor T4 is electrically connected to the data signal line DL, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the third transistor T3. The gate of the second transistor T2 is electrically connected to the scan signal line GL, the first electrode of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the second electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3. The gate of the fifth transistor T5 is electrically connected to the emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3. The gate of the sixth transistor T6 is electrically connected to the emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is electrically connected to the anode of the light-emitting device EL. The first transistor T1 is electrically connected to the gate of the third transistor T3 and is configured to reset the gate of the third transistor T3. The seventh transistor T7 is electrically connected to the anode of the light-emitting device EL and is configured to reset the anode of the light-emitting device EL. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the gate of the third transistor T3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the anode of the light-emitting device EL. The first capacitor plate of the storage capacitor Cst is electrically connected to the gate of the third transistor T3, and the second capacitor plate of the storage capacitor Cst is electrically connected to the first power line PL1.

[0092] In an exemplary embodiment, as shown in FIG3 , the pixel driving circuit may include: a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is a connection point between the storage capacitor Cst, the first transistor T1, the third transistor T3, and the second transistor T2; the second node N2 is a connection point between the fifth transistor T5, the fourth transistor T4, and the third transistor T3; the third node N3 is a connection point between the third transistor T3, the second transistor T2, and the sixth transistor T6; and the fourth node N4 is a connection point between the sixth transistor T6, the seventh transistor T7, and the light-emitting device EL. The fourth node N4 is an anode connection node.

[0093] In one exemplary embodiment, the light emitting device EL may be an organic electroluminescent diode (OLED) including an anode, a cathode, and an organic light emitting layer disposed between the anode and the cathode.

[0094] The operation process of the pixel driving circuit shown in FIG3 will be described below by taking the case where all the multiple transistors included in the pixel driving circuit shown in FIG3 are P-type transistors as an example.

[0095] In an exemplary embodiment, during a frame display period, the operation process of the pixel driving circuit may include: a first stage S1, a second stage S2 and a third stage S3.

[0096] The first phase S1 is called the reset phase. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first transistor T1. The first initial signal provided by the first initial signal line INIT1 is provided to the first node N1, initializing the first node N1 and clearing the existing data voltage in the storage capacitor Cst. The scan signal SCAN provided by the scan signal line GL is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this phase, the light-emitting device EL does not emit light.

[0097] The second stage S2 is called the data writing stage or the threshold compensation stage. The scan signal SCAN provided by the scan signal line GL is a low-level signal. The first reset control signal RESET1 provided by the first reset control line RST1 and the emission control signal EM provided by the emission control line EML are both high-level signals. The data signal line DL outputs the data signal DATA. During this stage, since the first capacitor plate of the storage capacitor Cst is at a low level, the third transistor T3 is turned on. The scan signal SCAN is a low-level signal, turning on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on, allowing the data voltage Vdata output by the data signal line DL to be provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output by the data signal line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst. The voltage of the first capacitor plate of the storage capacitor Cst (i.e., the first node N1) is Vdata-|Vth|, where Vdata is the data voltage output by the data signal line DL and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, allowing the second initialization signal provided by the second initialization signal line INIT2 to be provided to the anode of the light-emitting device EL, initializing (resetting) the anode of the light-emitting device EL, clearing the pre-stored voltage therein, completing initialization, and ensuring that the light-emitting device EL does not emit light. The first reset control signal RESET1 provided by the first reset control line RST1 is a high signal, turning off the first transistor T1. The light emitting control signal EM provided by the light emitting control signal line EML is a high level signal, which turns off the fifth transistor T5 and the sixth transistor T6.

[0098] The third phase S3 is called the light-emitting phase. The light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, while the scan signal SCAN provided by the scan signal line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals. The light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The first voltage signal VDD output by the first power line PL1 provides a driving voltage to the anode of the light-emitting device EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting device EL to emit light.

[0099] During the pixel circuit driving process, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0100] I=K×(Vgs-Vth)2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2 .

[0101] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting device EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data signal line DL, and VDD is the first voltage signal output by the first power line PL1.

[0102] It can be seen from the above formula that the current flowing through the light emitting device EL has nothing to do with the threshold voltage of the third transistor T3. Therefore, the pixel driving circuit of this embodiment can better compensate for the threshold voltage of the third transistor T3.

[0103] Figure 4 is a first partial schematic diagram of the display panel in the embodiment of the present disclosure, which is an enlarged view of the Q area in Figure 1, illustrating the planar structure of the area adjacent to the transition display area AAG in the first display area AA1, and illustrating the planar structure of the transition display area AAG and its nearby area in the second display area AA2.

[0104] In one exemplary embodiment, as shown in FIG4 , the first display area AA1 may be provided with only the first light-emitting device sp1, without providing the first pixel driving circuit QD1 that drives the first light-emitting device sp1. This allows the first display area AA1 to both display and transmit light. For example, the first light-emitting device sp1 may include at least a first anode, and at least one first pixel driving circuit QD1 in the transition display area AAG of the second display area AA2 may be connected to the first anode of at least one first light-emitting device sp1 via a conductive line L (e.g., a transparent conductive line). The conductive line L may extend from the first display area AA1 to the transition display area AAG of the second display area AA2. In this manner, by providing the first pixel driving circuit QD1 that drives the first light-emitting device sp1 in the transition display area AAG of the second display area AA2, light obstruction by the pixel driving circuit may be reduced, thereby increasing the transmittance of the first display area AA1. For example, taking the first pixel driving circuit QD1 as the 7T1C pixel driving circuit shown in Figure 3 as an example, one end of the conductive line L (for example, a transparent conductive line) can be electrically connected to the fourth node N4 (i.e., the anode connection node) of the first pixel driving circuit QD1, and the other end of the conductive line L can be electrically connected to the first anode of the first light-emitting device sp1.

[0105] In an exemplary embodiment, as shown in FIG4 , the second display area AA2 may include: a plurality of first pixel drive circuits QD1, a plurality of second pixel drive circuits QD2, and a plurality of second light-emitting devices sp2. At least one second pixel drive circuit QD2 among the plurality of second pixel drive circuits QD2 is configured to be connected to at least one second light-emitting device sp2 in the second display area AA2. The second pixel drive circuit QD2 is configured to directly output a corresponding current to the connected second light-emitting device sp2, causing the second light-emitting device sp2 to emit light of a corresponding brightness. That is, the second light-emitting device sp2 electrically connected to the second pixel drive circuit QD2 and the second pixel drive circuit QD2 may both be located within the second display area AA2, and all or part of the second light-emitting device sp2 may be located within the second display area AA2. For example, the orthographic projection of the at least one second pixel drive circuit QD2 on the substrate may at least partially overlap with the orthographic projection of the at least one second light-emitting device sp2 on the substrate.

[0106] In one exemplary embodiment, as shown in FIG4 , the transition display area AAG in the second display area AA2 may include: a plurality of first pixel drive circuits QD1 , at least one of which may be connected to at least one first light-emitting device sp1 in the first display area AA1 via a conductive line L. The at least one first pixel drive circuit QD1 is configured to output a corresponding current to the connected first light-emitting device sp1 via the conductive line L, causing the first light-emitting device sp1 to emit light of a corresponding brightness. That is, the first light-emitting device sp1 electrically connected to the first pixel drive circuit QD1 may be located in a different display area from the first pixel drive circuit QD1. For example, the orthographic projection of the at least one first pixel drive circuit QD1 on the substrate may not overlap with the orthographic projection of the at least one first light-emitting device sp1 on the substrate. In one exemplary embodiment, as shown in FIG4 , the transitional display area AAG may further include: a plurality of second pixel drive circuits QD2 and a plurality of second light-emitting devices sp2 . At least one of the plurality of second pixel drive circuits QD2 may be connected to at least one second light-emitting device sp2 in the transitional display area AAG. The second pixel drive circuit QD2 is configured to directly output a corresponding current to the connected second light-emitting device sp2, causing the second light-emitting device sp2 to emit light of a corresponding brightness. In one exemplary embodiment, one or more second pixel drive circuits QD2 may be provided between adjacent first pixel drive circuits QD1 . For example, two second pixel drive circuits QD2 may be provided between adjacent first pixel drive circuits QD1 . Alternatively, as shown in FIG4 , four second pixel drive circuits QD2 may be provided between adjacent first pixel drive circuits QD1 . This is not limited in the presently disclosed embodiments.

[0107] In one exemplary embodiment, as shown in FIG4 , the transitional display area AAG may further include an inactive pixel drive circuit QD0 . Providing an inactive pixel drive circuit can improve the uniformity of components across multiple film layers during the etching process, thereby ensuring uniformity across the display panel. For example, the inactive pixel drive circuit may have substantially the same structure as the first pixel drive circuit QD1 and the second pixel drive circuit QD2 in its row or column, except that it is not electrically connected to any light-emitting device.

[0108] In an exemplary embodiment, the conductive line L may be made of a transparent conductive material. For example, the transparent conductive material may be a conductive oxide material, such as indium tin oxide (ITO). This is not limited in the present embodiment.

[0109] In the exemplary embodiments of the present disclosure, the pixel driving circuits referred to herein are regions divided according to the base structure layer, and the light-emitting devices referred to herein are regions divided according to the light-emitting structure layer. For example, the positions of the light-emitting devices and the pixel driving circuits driving them may correspond, or they may not correspond. For example, the multiple second light-emitting devices sp2 in the transitional display area AAG may be arranged normally with a regular pitch, while some of the second pixel driving circuits QD2 in the transitional display area AAG may be arranged compactly with a small pitch, leaving space for the first pixel driving circuits QD1 driving the first light-emitting devices sp1. In this case, the positions of the second light-emitting devices sp2 in the transitional display area AAG and the second pixel driving circuits QD2 do not correspond. For another example, the multiple first light-emitting devices sp1 are arranged in the first display area AA1, while the first pixel driving circuit QD1 is arranged in the transitional display area AAG. In this case, the positions of the first light-emitting devices sp1 in the first display area AA1 and the first pixel driving circuit QD1 driving the first light-emitting devices sp1 do not correspond.

[0110] In an exemplary embodiment, in the transitional display area AAG, the size of the second pixel driver circuit QD2 can be reduced to obtain an area for disposing the first pixel driver circuit QD1. For example, the size of the second pixel driver circuit QD2 in the first direction X can be reduced to obtain an area for disposing the first pixel driver circuit QD1; alternatively, the size of the second pixel driver circuit QD2 in the second direction Y can be reduced to obtain an area for disposing the first pixel driver circuit QD1; alternatively, the size of the second pixel driver circuit QD2 in both the first direction X and the second direction Y can be reduced to obtain an area for disposing the first pixel driver circuit QD1. The presently disclosed embodiments are not limited to this.

[0111] For example, taking the example of obtaining an area for arranging the first pixel driving circuit QD1 by reducing the size of the second pixel driving circuit QD2 in the first direction X, as shown in FIG4 , each of the original a columns of pixel driving circuits can be compressed along the first direction X, thereby creating space for arranging an additional column of pixel driving circuits, and the space occupied by the a column of pixel driving circuits before compression and the a+1 column of pixel driving circuits after compression can be the same. Here, a can be an integer greater than 1, for example, a can be equal to 2, 3, or 4. For example, the second pixel driving circuits QD2 and the first pixel driving circuit QD1 can generally be arranged in a manner of 2-to-1, 3-to-1, or 4-to-1 in the first direction X, compressing two, three, or four second pixel driving circuits QD2 in the first direction X to leave one location for arranging the first pixel driving circuit QD1. This is not limited in the present embodiment. In this case, the size of the second pixel driving circuit QD2 in the first direction X can be smaller than the size of the second light-emitting device sp2 in the first direction X.

[0112] For another example, taking the example of obtaining an area for arranging the first pixel driving circuit QD1 by reducing the size of the second pixel driving circuit QD2 in the second direction Y, the original b rows of pixel driving circuits can be compressed along the second direction Y, thereby adding a row of pixel driving circuits, and the space occupied by the b rows of pixel driving circuits before compression and the b+1 rows of pixel driving circuits after compression is the same. Wherein, b can be an integer greater than 1. For example, b can be equal to 2, 3, or 4. In this case, the size of the second pixel driving circuit QD2 in the second direction Y can be smaller than the size of the second light-emitting device sp2 in the second direction Y.

[0113] In an exemplary embodiment, since the transition display area AAG is not only provided with a first pixel driving circuit QD1 electrically connected to the first light-emitting device sp1, but also provided with a second pixel driving circuit QD2 electrically connected to the second light-emitting device sp2, the number of pixel driving circuits in the transition display area AAG can be greater than the number of first light-emitting devices sp1 in the first display area AA1.

[0114] In an exemplary embodiment, to reduce the crosstalk caused by the capacitance between conductive lines (such as ITO traces) on the first node N1, a shielding electrode 60 is provided in the display panel. FIG5 is a schematic diagram of a conductive line passing through a shielding electrode in the first display area AA1 in some technologies. As shown in FIG5 , the shielding electrode 60 below the conductive line is irregularly shaped and reflective, resulting in uneven line widths of the multiple conductive lines L (1 to 7) passing through the shielding electrode 60. The conductive lines passing through the wider portion of the shielding electrode 60 have a thinner line width, while the conductive lines passing through the narrower portion of the shielding electrode 60 have a wider line width. This can result in significant capacitance differences between conductive lines in adjacent pixels in the same row, leading to display mura.

[0115] As shown in FIG5 , taking the conductive line passing through the wider portion of the shielding electrode 60 as conductive line 7 and the conductive line passing through the narrower portion of the shielding electrode 60 as conductive line 3 as an example, the inventors of the present disclosure measured the line widths of the conductive line passing through the wider portion of the shielding electrode 60 and the line widths of the conductive line passing through the narrower portion of the shielding electrode 60 as shown in Table 1. In Table 1, CD(7) refers to the line width of the conductive line 7 passing through the shielding electrode 60 of different display panels, indicating the line width of the conductive line passing through the widest portion of the shielding electrode 60; CD(3) refers to the line width of the conductive line 3 passing through the shielding electrode 60 of different display panels, indicating the line width of the conductive line passing through the narrowest portion of the shielding electrode 60.

[0116] Table 1 Measured line width of the conductive line L passing through the shielding electrode

[0117] Display panel CD(7)CD(3)Panel11.851.90Panel21.762.03Panel31.671.89Panel41.711.94Panel51.821.98Panel61.851.98Panel71.801.98Average line width1.781.96

[0118] Analysis of the data shown in Table 1 reveals that due to the irregular shape of shield electrode 60, i.e., the inconsistent width of shield electrode 60, the line width (critical dimension, CD) of the conductive lines varies by approximately 0.2 μm (micrometers). This results in a capacitance difference of approximately 0.1 fF between conductive lines (e.g., ITO traces) within a pixel unit. Furthermore, taking the 7T1C pixel driver circuit shown in FIG3 as an example, one end of conductive line L can be electrically connected to the fourth node N4 (i.e., the anode connection node) of the first pixel driver circuit QD1, and the other end of conductive line L can be electrically connected to the anode of the first light-emitting device sp1. Because conductive line L extends from the first display area AA1 to the transition display area AAG to electrically connect the first pixel driver circuit QD1 to the first light-emitting device sp1, the conductive line L is relatively long. Consequently, the capacitance between conductive lines (e.g., ITO traces) within a pixel unit can vary by approximately several hundred fF. Thus, at low grayscale, due to the longer turn-on time, the node capacitance of the fourth node N4 (i.e., the anode connection node) is larger, and the capacitance difference between the conductive lines (such as ITO traces) of adjacent pixels in the same row is large, which will cause the turn-on time to be greatly affected, resulting in mura problems.

[0119] In some examples, the capacitance of the conductive wires in the display panel varies significantly. The different lengths of the conductive wires of the multiple light-emitting devices located in the first display area AA1 can result in different capacitance variations among the light-emitting devices of different colors. The capacitance variation of the conductive wires connected to the red-emitting devices is greater than that of the conductive wires connected to the blue-emitting devices. This significant capacitance variation of the conductive wires connected to the green-emitting devices can reduce the emission time of the green-emitting devices, resulting in brightness variations in the display panel and poor display quality. At low grayscales, the degree of poor display quality of the green-emitting devices is greater than that of the red-emitting devices, and the degree of poor display quality of the red-emitting devices is greater than that of the blue-emitting devices. For example, at the same grayscale, the driving current for driving the blue-emitting devices can be greater than that for driving the red-emitting devices, and the driving current for driving the red-emitting devices can be greater than that for driving the green-emitting devices. The driving current for green-emitting devices is the smallest among the three primary-color devices. Therefore, if the capacitance of the fourth node N4 (i.e., the anode connection node) of the devices emitting different light beams is the same, the green-emitting devices will light up later than the red and blue-emitting devices. At low grayscales, the near-to-far connection method may cause some green-emitting devices to not light up, affecting the display quality.

[0120] An embodiment of the present disclosure provides a display panel, which may include: a substrate, a circuit structure layer and a light-emitting structure layer stacked on the substrate, and a plurality of conductive layers arranged between the circuit structure layer and the light-emitting structure layer; wherein the substrate includes: a first display area and a second display area, the second display area is located on at least one side of the first display area, and the transmittance of the first display area is greater than the transmittance of the second display area; the circuit structure layer includes: a first gate signal line located in the second display area, a constant voltage line, a plurality of shielding electrodes and a plurality of pixel circuits, the pixel circuit includes a driving transistor, the driving transistor includes a gate, and the plurality of pixel circuits include a plurality of first pixel driving circuits; the first gate signal line is connected to the gate of the driving transistor; the constant voltage line is configured to provide a first constant voltage to the plurality of pixel circuits; the shielding electrode is connected to the constant voltage line, and the orthographic projection of the first gate signal line on the substrate falls within the orthographic projection of the shielding electrode on the substrate; the plurality of conductive layers include: a plurality of conductive lines, the plurality of conductive lines include: a plurality of first-type conductive lines and a plurality of second-type conductive lines, and the portion of the first-type conductive line extending along the first direction is between the orthographic projection of the substrate and the plurality of At least one of the shielding electrodes has an overlapping orthographic projection on the substrate, and the orthographic projection of the portion of the second-type conductive line extending along the first direction on the substrate does not overlap with the orthographic projection of the multiple shielding electrodes on the substrate; the light-emitting structure layer includes: a plurality of first light-emitting devices located in the first display area, the plurality of first light-emitting devices include: a plurality of first-type first light-emitting devices and a plurality of second-type first light-emitting devices, at least one first-type first light-emitting device among the plurality of first-type first light-emitting devices is connected to at least one first pixel driving circuit among the plurality of first pixel driving circuits through at least one first-type conductive line among the plurality of first-type conductive lines, at least one second-type first light-emitting device among the plurality of second-type first light-emitting devices is connected to at least one first pixel driving circuit among the plurality of first pixel driving circuits through at least one second-type conductive line among the plurality of second-type conductive lines, the first pixel driving circuit is configured to drive the first light-emitting device to emit light, the first-type first light-emitting device is configured to emit a first color light, the second-type first light-emitting device is configured to emit a second color light, and the second color light is different from the first color light.

[0121] Thus, in the display panel provided by the exemplary embodiments of the present disclosure, by arranging for the first type of conductive lines connected to the first type of first light-emitting devices to overlap with the orthographic projection of the shielding electrode on the substrate, the uniformity of the line width of the first type of conductive lines can be maintained, thereby minimizing capacitance variations among the first type of conductive lines. Furthermore, by arranging for the second type of conductive lines connected to the second type of first light-emitting devices to not overlap with the orthographic projection of the shielding electrode on the substrate, the uniformity of the line width of the second type of conductive lines can be maintained, thereby minimizing capacitance variations among the second type of conductive lines. Thus, by optimizing the wiring arrangement, brightness variations can be improved, thereby enhancing display quality.

[0122] In an exemplary embodiment, the shielding electrode may be in a regular shape, for example, a rectangular shape. Thus, by setting the shielding electrode to a rectangular shape, a consistent routing environment for the first-class conductive lines can be ensured, the line width uniformity of the first-class conductive lines can be improved, and capacitance variation among the first-class conductive lines can be minimized.

[0123] In an exemplary embodiment, the plurality of first light-emitting devices in the first display area may include: a plurality of groups of first light-emitting devices. The first light-emitting devices in each of the plurality of groups of first light-emitting devices may be arranged along a first direction X, and the plurality of groups of first light-emitting devices may be arranged along a second direction Y. The second direction Y intersects with the first direction X, for example, the second direction and the first direction are perpendicular to each other. In at least one group of first light-emitting devices sp1, the plurality of first pixel driving circuits QD1 electrically connected to the plurality of first-type first light-emitting devices are closer to the first display area than each of the plurality of first pixel driving circuits QD1 electrically connected to the plurality of second-type first light-emitting devices. In this way, the difference in length of the conductive lines connecting the first-type first light-emitting devices can be reduced, thereby alleviating or avoiding display defects.

[0124] In an exemplary embodiment, taking the conductive layer as a transparent conductive layer as an example, the display panel may include three transparent conductive layers, and the three transparent conductive layers may include: a first transparent conductive layer, a second transparent conductive layer, and a third transparent conductive layer arranged in sequence along a side away from the substrate. The first transparent conductive layer may include a plurality of first transparent conductive lines, the second transparent conductive layer may include a plurality of second transparent conductive lines, and the third transparent conductive layer may include a plurality of third transparent conductive lines. For example, the orthographic projections of the portion of the first transparent conductive line extending along the first direction, the portion of the second transparent conductive line extending along the first direction, and the portion of the third transparent conductive line extending along the first direction on the substrate may not overlap, that is, there are no overlapping lines. For example, the orthographic projections of the portion of the third transparent conductive line extending along the first direction and the portion of the second transparent conductive line extending along the first direction on the substrate may not overlap, that is, there are no overlapping lines. For example, the size of the portion of the first transparent conductive line extending along the first direction X in the second direction Y, the size of the portion of the second transparent conductive line extending along the first direction X in the second direction Y, and the size of the portion of the third transparent conductive line extending along the first direction X in the second direction Y may be substantially the same.

[0125] In an exemplary embodiment, in at least one group of first light-emitting devices in the first display area, a plurality of first-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits through a first transparent conductive line, and a plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits through a third transparent conductive line.

[0126] In an exemplary embodiment, in at least one group of first light-emitting devices in the first display area, a plurality of first-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits through a first transparent conductive line, and a plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits through a second transparent conductive line.

[0127] In an exemplary embodiment, in at least one group of first light-emitting devices in the first display area, a plurality of first-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits through a second transparent conductive line, and a plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits in the second display area through a first transparent conductive line.

[0128] In an exemplary embodiment, in at least one group of first light-emitting devices in the first display area, a plurality of first-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits through a third transparent conductive line, and a plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits in the second display area through a first transparent conductive line.

[0129] In an exemplary embodiment, in at least one group of first light-emitting devices in the first display area, a plurality of second-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits through a first transparent conductive line, and a plurality of second-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits through a third transparent conductive line.

[0130] In an exemplary embodiment, in at least one group of first light-emitting devices in the first display area, the type of transparent conductive wires electrically connected to the multiple second-type first light-emitting devices near the center of the first display area is the same as the type of transparent conductive wires electrically connected to the multiple first-type first light-emitting devices near the center of the first display area, or, the type of transparent conductive wires electrically connected to the multiple second-type first light-emitting devices near the edge of the first display area is the same as the type of transparent conductive wires electrically connected to the multiple first-type first light-emitting devices near the edge of the first display area.

[0131] In an exemplary embodiment, in at least one group of first light-emitting devices in the first display area, the type of transparent conductive wires electrically connected to the multiple second-type first light-emitting devices near the center of the first display area is different from the type of transparent conductive wires electrically connected to the multiple first-type first light-emitting devices near the center of the first display area, or, the type of transparent conductive wires electrically connected to the multiple second-type first light-emitting devices near the edge of the first display area is different from the type of transparent conductive wires electrically connected to the multiple first-type first light-emitting devices near the edge of the first display area.

[0132] In an exemplary embodiment, in at least one group of first light-emitting devices in the first display area, a plurality of second-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits through a first transparent conductive line, and a plurality of second-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits through a third transparent conductive line.

[0133] In an exemplary embodiment, in at least one group of first light-emitting devices in the first display area, a plurality of first-category first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits through a first transparent conductive line, a plurality of first-category first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits through a third transparent conductive line, and a plurality of first-category first light-emitting devices located between the plurality of first-category first light-emitting devices near the center of the first display area and the plurality of first-category first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits through a second transparent conductive line; in at least one group of first light-emitting devices in the first display area, a plurality of second-category first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits through a first transparent conductive line, a plurality of second-category first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits through a third transparent conductive line, and a plurality of second-category first light-emitting devices located between the plurality of second-category first light-emitting devices near the center of the first display area and the plurality of second-category first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits through a second transparent conductive line.

[0134] In an exemplary embodiment, in at least one group of first light-emitting devices in the first display area, a transparent conductive line electrically connecting a plurality of first-type first light-emitting devices is located on one side of a switching electrode of the group of first light-emitting devices in the second direction.

[0135] In an exemplary embodiment, in at least one group of first light-emitting devices in the first display area, the transparent conductive wire electrically connecting the plurality of second-type first light-emitting devices is located on the other side of the switching electrode of the group of first light-emitting devices in the second direction.

[0136] In an exemplary embodiment, the first display area includes: a first sub-area and a second sub-area, the second sub-area is located on at least one side of the first sub-area and is adjacent to the second display area; at least one first light-emitting device located in the first sub-area among the multiple first light-emitting devices is connected to at least one first pixel driving circuit among the multiple first pixel driving circuits through conductive lines of multiple conductive layers; at least one first light-emitting device located in the second sub-area among the multiple first light-emitting devices is connected to at least one first pixel driving circuit among the multiple first pixel driving circuits through conductive lines of the metal conductive layer in the circuit structure layer.

[0137] In an exemplary embodiment, the metal conductive layer and the shielding electrode are located in the same film layer.

[0138] In an exemplary embodiment, the shielding electrode may be rectangular in shape.

[0139] In an exemplary embodiment, the light-emitting structure layer may further include: a plurality of second light-emitting devices located in the second display area; the plurality of pixel circuits further include: a plurality of second pixel driving circuits, at least one second pixel driving circuit among the plurality of second pixel driving circuits is electrically connected to at least one second light-emitting device among the plurality of second light-emitting devices, and the at least one second pixel driving circuit is configured to drive at least one second light-emitting device to emit light.

[0140] In an exemplary embodiment, the second display area may include: a transition display area and a normal display area, the transition display area is located on at least one side of the normal display area and is adjacent to the first display area; the transition display area may include: a plurality of first pixel driving circuits; the normal display area includes: at least part of a plurality of second light-emitting devices and at least part of a plurality of second pixel driving circuits, at least part of the plurality of second light-emitting devices is connected to at least part of the plurality of second pixel driving circuits.

[0141] In an exemplary embodiment, the transition display area may include: multiple sub-transition areas; the light-emitting structure layer may also include: multiple second light-emitting devices located in at least one sub-transition area close to the first display area among the multiple sub-transition areas; the circuit structure layer may also include: multiple second pixel driving circuits located in at least one sub-transition area close to the first display area among the multiple sub-transition areas; at least one second pixel driving circuit among the multiple second pixel driving circuits is electrically connected to at least one second light-emitting device among the multiple second light-emitting devices, and the at least one second pixel driving circuit is configured to drive the at least one second light-emitting device to emit light.

[0142] In an exemplary embodiment, the light-emitting structure layer may further include: a plurality of second light-emitting devices located in the second display area; the circuit structure layer may further include: a plurality of second pixel driving circuits located in the second display area, at least one second pixel driving circuit among the plurality of second pixel driving circuits is electrically connected to at least one second light-emitting device among the plurality of second light-emitting devices, and the at least one second pixel driving circuit is configured to drive at least one second light-emitting device to emit light.

[0143] In an exemplary embodiment, the first color light may be green light, and the second color light may include at least one of red light and blue light. For example, the first type of first light-emitting device may include a green first light-emitting device sp1_g, which is configured to emit green light; the second type of first light-emitting device may include a blue first light-emitting device sp1_b and a red first light-emitting device sp1_r, which is configured to emit blue light and red first light-emitting device sp1_r.

[0144] The display panel in the embodiment of the present disclosure is described below with reference to the drawings, taking as an example a display panel including three transparent conductive layers, a first type of first light-emitting device including a green first light-emitting device sp1_g, and a second type of first light-emitting device including a blue first light-emitting device sp1_b and a red first light-emitting device sp1_r.

[0145] In an exemplary embodiment, the capacitance of the anode connection node can be reduced by reducing the length of the conductive wire connected to the anode connection node of the green first light-emitting device sp1_g, thereby ensuring that the green first light-emitting device sp1_g can be properly turned on. In the following example, the first pixel driving circuit QD1 electrically connected to the green first light-emitting device sp1_g is closest to the first display area AA1. That is, the first pixel driving circuit QD1 electrically connected to the green first light-emitting device sp1_g is preferentially arranged close to the first display area AA1. In the exemplary embodiments of the present disclosure, "element A close to element B" may mean that there are no other elements A and other elements B between element A and element B, but there may be other elements besides element A and element B. For example, the "first pixel driving circuit QD1 electrically connected to the green first light-emitting device sp1_g is close to the first display area AA1" described in the exemplary embodiment of the present disclosure may refer to the first pixel driving circuit QD1 electrically connected to the green first light-emitting device sp1_g and the first display area AA1, which does not have the first pixel driving circuit QD1 electrically connected to the red first light-emitting device sp1_r and the first pixel driving circuit QD1 connected to the blue first light-emitting device sp1_b, but may have other pixel driving circuits such as the second pixel driving circuit QD2 or the invalid pixel driving circuit QD0.

[0146] In one exemplary embodiment, the plurality of first light-emitting devices sp1 in the first display area AA1 may include a plurality of green first light-emitting devices sp1_g, a plurality of blue first light-emitting devices sp1_b, and a plurality of red first light-emitting devices sp1_r. The green first light-emitting devices sp1_g are configured to emit green light, the blue first light-emitting devices sp1_b are configured to emit blue light, and the red first light-emitting devices sp1_r are configured to emit red light. In at least one group of first light-emitting devices sp1, the plurality of second pixel drive circuits QD2 electrically connected to the green first light-emitting devices sp1_g are located closer to the first display area AA1 than each of the plurality of second pixel drive circuits QD2 electrically connected to the blue first light-emitting devices sp1_b and the red first light-emitting devices sp1_r. This reduces the difference in length of the conductive lines electrically connected to the green first light-emitting devices sp1_g, thereby alleviating or preventing display defects.

[0147] Figure 6A is a second partial schematic diagram of a display panel according to an embodiment of the present disclosure, Figure 6B is a third partial schematic diagram of a display panel according to an embodiment of the present disclosure, and Figure 6C is a fourth partial schematic diagram of a display panel according to an embodiment of the present disclosure, illustrating portions of the display area. As shown in Figures 6A through 6C, the first display area AA1 may have a centerline CL extending along the second direction Y. The first display area AA1 may be divided into a left half and a right half along the centerline CL. The conductive lines connecting the first light-emitting devices in the left and right halves may be substantially symmetrical about the centerline CL. In addition to illustrating portions of the light-emitting devices in the first display area AA1, Figures 6A through 6C also illustrate portions of the light-emitting devices in a sub-transition region of the transitional display area AAG adjacent to the first display area AA1.

[0148] In one exemplary embodiment, as shown in Figures 6A and 6B, the first display area AA1 may include a first sub-area AA1a and a second sub-area AA1b. The second sub-area AA1b may surround the first sub-area AA1a and be adjacent to the transitional display area AAG. That is, the second sub-area AA1b may be located between the first sub-area AA1a and the transitional display area AAG. The second sub-area AA1b may be an edge region of the first display area AA1, while the first sub-area AA1a may be the center region of the first display area AA1.

[0149] In one exemplary embodiment, as shown in FIG6A , the first display area AA1 may be approximately circular in shape, the first sub-area AA1a may be circular in shape with a smaller diameter than the first display area AA1, and the first sub-area AA1a may be a ring surrounding the first sub-area AA1a. As shown in FIG6B , the first display area AA1 may be approximately circular in shape, the first sub-area AA1a may be approximately circular in shape with a smaller diameter than the first display area AA1, and the first sub-area AA1a may be a ring surrounding the first sub-area AA1a. This is not limited in the presently disclosed embodiments.

[0150] In an exemplary embodiment, as shown in Figures 6A and 6B, the film layer where the conductive lines connected to at least one first light-emitting device located in the first sub-area AA1a among the multiple first light-emitting devices are located is different from the film layer where the conductive lines connected to at least one first light-emitting device located in the first sub-area AA1a among the multiple first light-emitting devices are located. For example, at least one first light-emitting device located in the first sub-area AA1a among the multiple first light-emitting devices is electrically connected to at least one first light-emitting device among the multiple first light-emitting devices via the conductive lines of the transparent conductive layer; and at least one first light-emitting device located in the first sub-area AA1a among the multiple first light-emitting devices is connected to at least one first pixel driving circuit among the multiple first pixel driving circuits via the conductive lines of the metal conductive layer in the circuit structure layer. For example, the conductive lines of the metal conductive layer can be the conductive lines of the first source-drain metal layer (SD1) or the conductive lines of the second source-drain metal layer (SD2). Here, the embodiments of the present disclosure are not limited to this.

[0151] In an exemplary embodiment, the conductive line of the metal conductive layer and the shielding electrode are located in the same film layer. For example, the shielding electrode and the conductive line of the metal conductive layer can both be located in the second source / drain metal layer.

[0152] In an exemplary embodiment, as shown in FIG6A and FIG6B , in a group of first light emitting devices, the number of green first light emitting devices sp1_g in the first sub-area AA1a may be greater than or equal to the number of green first light emitting devices sp1_g in the second sub-area AA1b.

[0153] In an exemplary embodiment, the transition display area AAG in the second display area AA2 may include: multiple sub-transition areas; the light-emitting structure layer may also include: multiple second light-emitting devices located in at least one sub-transition area close to the first display area among the multiple sub-transition areas; the circuit structure layer may also include: multiple second pixel driving circuits located in at least one sub-transition area close to the first display area among the multiple sub-transition areas; at least one second pixel driving circuit among the multiple second pixel driving circuits is electrically connected to at least one second light-emitting device among the multiple second light-emitting devices, and the at least one second pixel driving circuit is configured to drive the at least one second light-emitting device to emit light.

[0154] For example, FIG6A and FIG6B illustrate 48 columns of light-emitting devices on both sides of a center line CL. On the left side of the center line CL, the light-emitting devices in columns 1 to 39 may be located in the first sub-area AA1a, and the light-emitting devices in columns 40 to 44 may be located in the second sub-area AA1b. The light-emitting devices in columns 1 to 39 and the light-emitting devices in columns 40 to 44 are first light-emitting devices sp1, which may be laterally arranged and extend from the first display area AA1 to the transitional display area AAG in the second display area AA2 via conductive lines L, and connected to the first pixel driving circuit QD1 in the transitional display area AAG. For example, the conductive lines used in columns 1 to 39 may be located in a different film layer than the conductive lines used in columns 40 to 44. For example, with respect to the light-emitting devices in the first display area AA1, as shown in Figures 6A to 13, the light-emitting devices in the first to 39th columns within the first sub-area AA1a can be driven using a horizontal arrangement of conductive lines in the transparent conductive layer. After the arrangement space of the transparent conductive layer is fully utilized, the light-emitting devices in the 40th to 44th columns within the second sub-area AA1b can be driven using a horizontal arrangement of conductive lines in the metal conductive layer (e.g., the second source / drain metal layer SD2). For example, with respect to the light-emitting devices in the transitional display area AAG close to the first display area AA1, the light-emitting devices in the 45th to 48th columns can be located in the sub-transitional area AAGn closest to the first display area AA1 within the transitional display area AAG. The light-emitting devices in the 45th to 48th columns can be the second light-emitting devices sp2 and driven in situ, i.e., the light-emitting devices in the 45th to 48th columns are directly connected to the second pixel driving circuit QD2 located in the transitional display area AAG. This ensures a smooth transition from the transitional display area AAG to the first display area AA1 while not affecting transmittance.

[0155] In an exemplary embodiment, as shown in FIG6C , the first display area AA1 may include: a first pull-wire area AA1-1, a second pull-wire area AA1-2, a third pull-wire area AA1-3, and a fourth pull-wire area AA1-4, which are sequentially arranged away from the center of the first display area AA1. The first pull-wire area AA1-1 may be an area in the first display area AA1 that is relatively close to the geometric center of the first display area AA1, and the fourth pull-wire area AA1-4 may be an area in the first display area AA1 that is relatively close to the edge of the first display area AA1. For example, taking the shape of the first display area AA1 as an approximate circle as an example, the shapes of the first pull-wire area AA1-1, the second pull-wire area AA1-2, the third pull-wire area AA1-3, and the fourth pull-wire area AA1-4 may be parts of an approximate semicircle. The size of the first wire drawing area AA1-1 in the second direction Y may be larger than the size of the second wire drawing area AA1-2 in the second direction Y, the size of the second wire drawing area AA1-2 in the second direction Y may be larger than the size of the third wire drawing area AA1-3 in the second direction Y, and the size of the second wire drawing area AA1-2 in the second direction Y may be larger than the size of the fourth wire drawing area AA1-4 in the second direction Y. Here, the embodiments of the present disclosure are not limited to this.

[0156] In an exemplary embodiment, as shown in Figure 6C, the first light-emitting device sp1 in the first pulling area AA1-1 can be electrically connected using the first conductive line L1 of the first transparent conductive layer, the second pulling area AA1-2 can be electrically connected using the second conductive line L2 of the second transparent conductive layer, the third pulling area AA1-3 can be electrically connected using the third conductive line L3 of the third transparent conductive layer, and the fourth pulling area AA1-4 can be electrically connected using the conductive line of the metal conductive layer (such as the second source and drain metal layer).

[0157] For example, Figure 6C illustrates 48 columns of light-emitting devices on both sides of the center line CL, wherein, on the left side of the center line CL, the 1st to 13th columns of light-emitting devices can be located in the first pulling area AA1-1, the 14th to 26th columns of light-emitting devices can be located in the second pulling area AA1-2, the 27th to 39th columns of light-emitting devices can be located in the third pulling area AA1-3, and the 40th to 44th columns of light-emitting devices can be located in the fourth pulling area AA1-4. The 1st to 39th columns of light-emitting devices and the 40th to 44th columns of light-emitting devices are first light-emitting devices sp1, which can be horizontally arranged through conductive lines L to extend from the first display area AA1 to the transition display area AAG in the second display area AA2, and connected to the first pixel driving circuit QD1 in the transition display area AAG. For example, for the light-emitting devices in the first display area AA1, as shown in Figure 6C, the 1st to 13th columns of light-emitting devices located in the first pulling area AA1-1 can adopt the first transparent conductive line horizontal arrangement driving mode in the first transparent conductive layer, and after the arrangement space of the first transparent conductive layer is fully utilized, the 14th to 26th columns of light-emitting devices located in the second pulling area AA1-2 can adopt the second transparent conductive line horizontal arrangement driving mode in the second transparent conductive layer, and after the arrangement space of the second transparent conductive layer is fully utilized, the 27th to 39th columns of light-emitting devices located in the third pulling area AA1-3 can adopt the third transparent conductive line horizontal arrangement driving mode in the third transparent conductive layer, and after the arrangement space of the transparent conductive layer is fully utilized, the 40th to 44th columns of light-emitting devices located in the fourth pulling area AA1-4 can adopt the conductive line horizontal arrangement driving mode of the metal conductive layer (such as the second source and drain metal layer SD2). For example, for the light-emitting devices close to the first display area AA1 in the transition display area AAG, the 45th to 48th columns of light-emitting devices can be located in the sub-transition area AAGn closest to the first display area AA1 in the transition display area AAG, and the 45th to 48th columns of light-emitting devices can be the second light-emitting devices sp2, and adopt an in-situ driving method, that is, the 45th to 48th columns of light-emitting devices are directly connected to the second pixel driving circuit QD2 located in the transition display area AAG. In this way, the transmittance will not be affected, and a good transition from the transition display area AAG to the first display area AA1 is guaranteed.

[0158] In this example, the first light-emitting device sp1 near the center of the first display area AA1 can be electrically connected using the conductive wires of the transparent conductive layer. After the wiring arrangement space of the transparent conductive layer is fully utilized, the first light-emitting device sp1 near the edge of the first display area AA1 can be electrically connected using the conductive wires of the metal conductive layer (such as the second source and drain metal layer). In this way, the aperture can be kept constant, the wiring environment is uniform, and the mask (mask) is not increased. Moreover, since the load of the metal conductive layer (such as the second source and drain metal layer) is small, the impact on the surrounding wiring environment is small. In addition, since the light-emitting devices at the boundary position are electrically connected using the conductive wires of the metal conductive layer (such as the second source and drain metal layer), the transmittance of the first display area AA1 is less affected.

[0159] The following describes the connection method for the light-emitting devices in the first display area AA1, with reference to the layout shown in Figures 6A to 6C . The following example illustrates the connection between the left half of a group of first light-emitting devices in the first display area AA1 and a row of first pixel driver circuits QD1 in the transitional display area AAG of the second display area AA2, omitting other structures. Different line types are used to represent different layers of transparent conductive lines: the first transparent conductive line L1 is represented by a solid line, the second transparent conductive line L2 by a dashed line, and the third transparent conductive line L3 by a dotted line.

[0160] Figure 7 is a schematic diagram of a first connection method between the first light-emitting device and the first pixel driving circuit QD1 in an exemplary embodiment of the present disclosure. Figure 8 is a schematic diagram of a connection method between the first transparent conductive line L1 of the first transparent conductive layer in Figure 7. Figure 9 is a schematic diagram of a connection method between the second transparent conductive line L2 of the second transparent conductive layer in Figure 7. Figure 10 is a schematic diagram of a connection method between the third transparent conductive line L3 of the third transparent conductive layer in Figure 7. Figure 11 is a schematic diagram of a connection method between the metal conductive line L4 of the metal conductive layer in Figure 7. Figure 12 is a schematic diagram of a second connection method between the first light-emitting device and the first pixel driving circuit QD1 in an exemplary embodiment of the present disclosure. Figure 13 is a schematic diagram of a third connection method between the first light-emitting device and the first pixel driving circuit QD1 in an exemplary embodiment of the present disclosure. The following describes the connection method of the light-emitting device in conjunction with Figures 6A to 13.

[0161] In one exemplary embodiment, as shown in Figures 7 and 8 , the green first light-emitting device sp1_g within the first sub-area AA1a of the first display area AA1 can be electrically connected to the first pixel driving circuit QD1 in the transitional display area AAG of the second display area AA2 via a first transparent conductive line L1 located in the first transparent conductive layer. As shown in Figures 7 and 9 , the green first light-emitting device sp1_g within the first sub-area AA1a can be electrically connected to the first pixel driving circuit QD1 in the transitional display area AAG via a second transparent conductive line L2 located in the second transparent conductive layer. As shown in Figures 7 and 10 , the green first light-emitting device sp1_g within the first sub-area AA1a can be electrically connected to the first pixel driving circuit QD1 in the transitional display area AAG via a third transparent conductive line L3 located in the third transparent conductive layer. As shown in FIG7 , multiple green first light-emitting devices sp1_g near the center of the first display area AA1 are electrically connected to the first pixel driver circuit QD1 in the transitional display area AAG via the first transparent conductive line L1. Multiple green first light-emitting devices sp1_g near the edge of the second display area AA1 are electrically connected to the first pixel driver circuit QD1 in the transitional display area AAG via the third transparent conductive line L3. That is, multiple green first light-emitting devices sp1_g away from the transitional display area AAG along the first direction X are electrically connected to the first pixel driver circuit QD1 in the transitional display area AAG via the first transparent conductive line L1, while multiple green first light-emitting devices sp1_g near the transitional display area AAG are electrically connected to the first pixel driver circuit QD1 in the transitional display area AAG via the third transparent conductive line L3. As shown in FIG7 , the first transparent conductive line L1, the second transparent conductive line L2, and the third transparent conductive line L3 electrically connected to the green first light-emitting devices sp1_g are located on the same side of the anode connection electrode of the group of first light-emitting devices in the second direction Y, for example, on the upper side. As shown in FIG7 , the orthographic projections of the first transparent conductive line L1, the second transparent conductive line L2, and the third transparent conductive line L3 electrically connected to the green first light-emitting device sp1_g on the display panel plane may overlap with the orthographic projection of the shielding electrode 60 on the display panel plane. The shielding electrode 60 is configured to shield the crosstalk caused by the capacitance between the conductive lines to the first node N1.

[0162] In one exemplary embodiment, as shown in Figures 7 and 8 , the red first light-emitting device sp1_r and the blue first light-emitting device sp1_b within the first sub-area AA1a can be electrically connected to the first pixel driving circuit QD1 of the transitional display area AAG via a first transparent conductive line L1 located in the first transparent conductive layer. As shown in Figures 7 and 9 , the red first light-emitting device sp1_r and the blue first light-emitting device sp1_b within the first sub-area AA1a can be electrically connected to the first pixel driving circuit QD1 of the transitional display area AAG via a second transparent conductive line L2 located in the second transparent conductive layer. As shown in Figures 7 and 10 , the red first light-emitting device sp1_r and the blue first light-emitting device sp1_b within the first sub-area AA1a can be electrically connected to the first pixel driving circuit QD1 of the transitional display area AAG via a third transparent conductive line L3 located in the third transparent conductive layer. As shown in Figures 7 to 10, multiple red first light-emitting devices sp1_r and blue first light-emitting devices sp1_b within the first sub-area AA1a, located near the transitional display area AAG, can be electrically connected to the first pixel driving circuit QD1 of the transitional display area AAG via the third transparent conductive line L3 located in the third transparent conductive layer. Multiple red first light-emitting devices sp1_r and blue first light-emitting devices sp1_b within the first sub-area AA1a, located away from the transitional display area AAG, can be electrically connected to the first pixel driving circuit QD1 of the transitional display area AAG via the first transparent conductive line L1 located in the first transparent conductive layer. As shown in Figure 7, the first transparent conductive line L1, the second transparent conductive line L2, and the third transparent conductive line L3 electrically connected to the red first light-emitting device sp1_r are located on the same side of the transfer electrode of the group of first light-emitting devices in the second direction Y, for example, on the lower side. As shown in Figure 7, the first transparent conductive line L1, the second transparent conductive line L2, and the third transparent conductive line L3 electrically connected to the blue first light-emitting device sp1_b are located on the same side of the group of first light-emitting devices in the second direction Y, for example, on the lower side. As shown in FIG7 , the first transparent conductive line L1, the second transparent conductive line L2, and the third transparent conductive line L32 electrically connected to the red first light-emitting device sp1_r, and the first transparent conductive line L1, the second transparent conductive line L2, and the third transparent conductive line L3 electrically connected to the blue first light-emitting device sp1_b are located on the same side, for example, the lower side, of the transfer electrode of the group of first light-emitting devices in the second direction Y. As shown in FIG7 , the orthographic projection of the first transparent conductive line L1, the second transparent conductive line L2, and the third transparent conductive line L3 electrically connected to the red first light-emitting device sp1_r and the blue first light-emitting device sp1_b on the display panel plane may not overlap with the orthographic projection of the shielding electrode 60 on the display panel plane.

[0163] In an exemplary embodiment, as shown in FIG7 , the second transparent conductive line L2 electrically connected to the green first light-emitting device sp1_g and the second transparent conductive line L2 electrically connected to the blue first light-emitting device sp1_b are located on both sides of the switching electrode of the group of first light-emitting devices in the second direction Y. The second transparent conductive line L2 electrically connected to the green first light-emitting device sp1_g and the second transparent conductive line L2 electrically connected to the red first light-emitting device sp1_r are located on both sides of the switching electrode of the group of first light-emitting devices in the second direction Y.

[0164] In one exemplary embodiment, as shown in Figures 7 and 11, the green first light-emitting device sp1_g within the second sub-area AA1b can be electrically connected to the first pixel driving circuit QD1 of the transitional display area AAG via a metal conductive line L4 located in the metal conductive layer. As shown in Figures 7 and 11, the red first light-emitting device sp1_r and the blue first light-emitting device sp1_b within the second sub-area AA1b can be electrically connected to the first pixel driving circuit QD1 of the transitional display area AAG via a metal conductive line L4 located in the metal conductive layer. As shown in Figures 7 and 11, the metal conductive line L4 electrically connecting the green first light-emitting device sp1_g, the red first light-emitting device sp1_r, and the blue first light-emitting device sp1_b is located on the same side of the transfer electrode of the group of first light-emitting devices in the second direction Y, for example, on the lower side. As shown in Figures 7 and 11, the orthographic projection of the metal conductive line L4 electrically connecting the first light-emitting device sp1 on the display panel plane may not overlap with the orthographic projection of the shielding electrode 60 on the display panel plane. As shown in Figures 7 and 11, the orthographic projection of the metal conductive line L4 electrically connected to the first light-emitting device sp1 on the display panel plane may overlap with the orthographic projection of the first transparent conductive line L1, the second transparent conductive line L2, and the third transparent conductive line L3 electrically connected to the red first light-emitting device sp1_r and the blue first light-emitting device sp1_b on the display panel plane. As shown in Figures 7 and 11, the orthographic projection of the metal conductive line L4 electrically connected to the first light-emitting device sp1 on the display panel plane may not overlap with the orthographic projection of the first transparent conductive line L1, the second transparent conductive line L2, and the third transparent conductive line L3 electrically connected to the green first light-emitting device sp1_g on the display panel plane.

[0165] In an exemplary embodiment, the wiring arrangement space of the first transparent conductive layer can be arranged with approximately 10 to 15 first transparent conductive lines L1. For example, as shown in Figures 7 and 8, the wiring arrangement space of the first transparent conductive layer can be arranged with 13 first transparent conductive lines L1. The wiring arrangement space of the second transparent conductive layer can be arranged with approximately 10 to 15 second transparent conductive lines L2. For example, as shown in Figures 7 and 9, the wiring arrangement space of the second transparent conductive layer can be arranged with 13 second transparent conductive lines L2. The wiring arrangement space of the third transparent conductive layer can be arranged with approximately 10 to 15 third transparent conductive lines L3. For example, as shown in Figures 7 and 10, the wiring arrangement space of the third transparent conductive layer can be arranged with 13 third transparent conductive lines L3. For example, as shown in Figures 7 and 11, the wiring arrangement space of the metal conductive layer can be arranged with approximately 5 metal conductive lines L4. Here, the embodiments of the present disclosure are not limited to this.

[0166] For example, the metal conductive layer may be a first source-drain metal layer (SD1) or a second source-drain metal layer (SD2). For example, the first source-drain metal layer (SD1) may include: first and second electrodes of multiple transistors in the pixel driving circuit, data signal lines, and first power lines. For example, the second source-drain metal layer (SD2) may include: a shielding electrode 60.

[0167] In one exemplary embodiment, as shown in Figures 7, 12, and 13, the second light-emitting device sp2 in the second display area AA2, which is relatively close to the first display area AA1, is driven in situ. That is, the second light-emitting device sp2 in the transitional display area, which is relatively close to the first display area AA1, and the second pixel driving circuit QD2 driving the second light-emitting device sp2 are both located in the transitional display area AAG. For example, as shown in Figure 7, the light-emitting devices in columns 45 through 48 are driven in situ.

[0168] In one exemplary embodiment, as shown in FIG12 , multiple green first light-emitting devices sp1_g near the center of the first display area AA1 are electrically connected to the first pixel driving circuit QD1 in the transitional display area AAG via a first transparent conductive line L1. Multiple green first light-emitting devices sp1_g near the edge of the first display area AA1 (i.e., the portion of the first display area AA1 that is relatively close to the second display area AA2) are electrically connected to the first pixel driving circuit QD1 in the transitional display area AAG via a second transparent conductive line L2 of the second transparent conductive layer. Multiple red first light-emitting devices sp1_r and blue first light-emitting devices sp1_b near the center of the first display area AA1 are electrically connected to the first pixel driving circuit QD1 in the transitional display area AAG via the first transparent conductive line L1. Multiple red first light-emitting devices sp1_r and blue first light-emitting devices sp1_b near the edge of the first display area AA1 (i.e., the portion of the first display area AA1 that is relatively close to the second display area AA2) are electrically connected to the first pixel driving circuit QD1 in the transitional display area AAG via a second transparent conductive line L2 of the second transparent conductive layer.

[0169] In an exemplary embodiment, as shown in FIG13 , multiple green first light-emitting devices sp1_g near the center of the first display area AA1 are electrically connected to the first pixel driving circuit QD1 in the transitional display area AAG via the second transparent conductive line L2 of the second transparent conductive layer. Multiple green first light-emitting devices sp1_g near the edge of the first display area AA1 (i.e., the portion of the first display area AA1 that is relatively close to the second display area AA2) are electrically connected to the first pixel driving circuit QD1 in the transitional display area AAG via the first transparent conductive line L1 of the first transparent conductive layer. Multiple red first light-emitting devices sp1_r and blue first light-emitting devices sp1_b near the center of the first display area AA1 are electrically connected to the first pixel driving circuit QD1 in the transitional display area AAG via the first transparent conductive line L1. Multiple red first light-emitting devices sp1_r and blue first light-emitting devices sp1_b near the edge of the first display area AA1 (i.e., the portion of the first display area AA1 that is relatively close to the second display area AA2) are electrically connected to the first pixel driving circuit QD1 in the transitional display area AAG via the third transparent conductive line L3 located in the third transparent conductive layer.

[0170] In this example, for the first light-emitting device sp1 in the first display area AA1, the first light-emitting device sp1 near the center in the first sub-area AA1a can be electrically connected using the first transparent conductive line L1 of the first transparent conductive layer. After the wiring arrangement space of the first transparent conductive layer is fully utilized, the second transparent conductive line L2 of the second transparent conductive layer can be electrically connected. After the wiring arrangement space of the second transparent conductive layer is fully utilized, the first light-emitting device sp1 in the first sub-area AA1a relatively close to the transition display area AAG can be electrically connected using the third transparent conductive line L3 of the third transparent conductive layer. After the wiring arrangement space of the third transparent conductive layer is fully utilized, the first light-emitting device sp1 in the second sub-area AA1b can be electrically connected using the metal conductive line L4 of the metal conductive layer. Of course, other arrangements can also be used. For example, the first light-emitting device sp1 near the transition display area AAG can be electrically connected using the second transparent conductive line L2 of the second transparent conductive layer. Here, the embodiments of the present disclosure are not limited to this.

[0171] The structure of the display panel is explained below by taking the example of the preparation process of the display panel as an example. The “patterning process” mentioned in the embodiment of the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in the present disclosure. “Thin film” refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the “thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the “thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one “pattern”.

[0172] In one exemplary embodiment, the display panels of the second display area AA2 and the first display area AA1, in a direction perpendicular to the display panel, may include: a substrate, a circuit structure layer disposed on the substrate, a first transparent conductive layer, a second transparent conductive layer, a third transparent conductive layer, and a light-emitting structure layer. The circuit structure layer of the first display area AA1 may include multiple insulating layers. The circuit structure layer of the second display area AA2 may include multiple first pixel driving circuits and multiple second pixel driving circuits. A first planarization layer may be disposed between the first and second transparent conductive layers, and a second planarization layer may be disposed between the second and third transparent conductive layers. A third planarization layer may be disposed between the third transparent conductive layer and the light-emitting structure layer. For example, the first through third planarization layers may be organic material layers. The light-emitting structure layer may include an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode layer. The anode layer may include an anode of a first light-emitting device located in the first display area AA1 and an anode of a second light-emitting device located in the second display area AA2. For example, the anode area of ​​the first light-emitting device may be smaller than the anode area of ​​a second light-emitting device emitting light of the same color to improve light transmittance in the first display area AA1. In some other examples, the display panel may include two or more transparent conductive layers, which is not limited in the present disclosure.

[0173] In an exemplary embodiment, the preparation process of the display panel may include the following operations. The following is an explanation using a first pixel driving circuit QD1 and a second pixel driving circuit QD2 of the second display area AA2 as an example. Among them, the first pixel driving circuit QD1 of the transition display area AAG can adopt the pixel driving circuit shown in Figure 3. In addition, the structure of the second pixel driving circuit QD2 can be basically the same as that of the first pixel driving circuit QD1, and the structure of the invalid pixel driving circuit can be basically similar to that of the first pixel driving circuit QD1, but the invalid pixel driving circuit has no via connection and does not receive signals. Those skilled in the art can refer to the relevant description for understanding, and the embodiments of the present disclosure will not be elaborated on here.

[0174] (1) Provide a substrate.

[0175] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. For example, the rigid substrate may include, but is not limited to, one or more of glass and quartz. For example, the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. For example, the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., which are configured to improve the water and oxygen resistance of the substrate. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0176] (2) A semiconductor layer pattern is formed on a substrate.

[0177] In an exemplary embodiment, forming a semiconductor layer pattern on a substrate may include: sequentially depositing a first insulating film and a semiconductor film on the substrate, patterning the semiconductor film through a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, as shown in FIG. 14 .

[0178] In an exemplary embodiment, the first insulating layer may be referred to as a buffer layer, configured to improve the substrate's resistance to water and oxygen, and the semiconductor layer may be referred to as an active (ACT) layer.

[0179] In an exemplary embodiment, as shown in FIG14 , the semiconductor layer of the second display area AA2 may include at least: active layers of multiple transistors of the pixel driving circuit, for example, a first active layer 11 of the first transistor T1, a second active layer 12 of the second transistor T2, a third active layer 13 of the third transistor T3, a fourth active layer 14 of the fourth transistor T4, a fifth active layer 15 of the fifth transistor T5, a sixth active layer 16 of the sixth transistor T6, and a seventh active layer 17 of the seventh transistor T7.

[0180] In an exemplary embodiment, as shown in FIG. 14 , active layers (eg, the first active layer 11 to the seventh active layer 17 ) of multiple transistors of one pixel driving circuit may be interconnected in an integrated structure.

[0181] In an exemplary embodiment, as shown in FIG14 , the second active layer 12 and the sixth active layer 16 may be located on one side of the third active layer 13 in the first direction X, and the fourth active layer 14 and the fifth active layer 15 may be located on a side of the third active layer 13 in the opposite direction to the first direction X. The fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 are located on one side of the third active layer 13 in the second direction Y, and the first active layer 11, the second active layer 12, and the fourth active layer 14 may be located on a side of the third active layer 13 in the opposite direction to the second direction Y.

[0182] In an exemplary embodiment, as shown in FIG14 , the first active layer 11 may be shaped like an “n”. The second active layer 12 may be shaped like an inverted “L”. The third active layer 13 may be shaped like an “Ω”. The fourth active layer 14, the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 may all be shaped like an “I”.

[0183] In an exemplary embodiment, the active layer of each transistor may include: at least one channel region, and a first region and a second region located on both sides of the channel region. For example, the channel region may not be doped with impurities and have semiconductor properties. The first region and the second region may be on both sides of the channel region and are doped with impurities and thus have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as a wiring doped with impurities and may be configured to electrically connect the transistors.

[0184] In an exemplary embodiment, as shown in FIG14 , the first region 11-1 of the first active layer 11, the first region 14-1 of the fourth active layer 14, the first region 15-1 of the fifth active layer 15, and the first region 17-1 of the seventh active layer 17 can be provided separately. The second region 11-2 of the first active layer 11 can simultaneously serve as the first region 12-1 of the second active layer 12 and the second gate signal portion SL2. The first region 13-1 of the third active layer 13 can simultaneously serve as the second region 14-2 of the fourth active layer 14 and the second region 15-2 of the fifth active layer 15. The second region 13-2 of the third active layer 13 can simultaneously serve as the second region 12-2 of the second active layer 12 and the first region 16-1 of the sixth active layer 16. The second region 16-2 of the sixth active layer 16 can simultaneously serve as the second region 17-2 of the seventh active layer 17.

[0185] In an exemplary embodiment, the semiconductor layer can be made of a metal oxide material. For example, the metal oxide material can include, but is not limited to: an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, an oxide containing indium, gallium and zinc, etc. For example, the semiconductor layer can be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology. For example, the semiconductor layer can be a single layer, a double layer or a multilayer, etc. Here, the embodiments of the present disclosure are not limited to this.

[0186] In an exemplary embodiment, the first insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer.

[0187] (3) Forming a first conductive layer pattern.

[0188] In an exemplary embodiment, forming a first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on a substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern arranged on the second insulating layer, as shown in Figures 15A and 15B, where Figure 15B is a planar schematic diagram of the first conductive layer in Figure 15A.

[0189] In an exemplary embodiment, the second insulating layer may be referred to as a gate insulating (GI) layer, and the first conductive layer may be referred to as a first gate metal (Gate1) layer.

[0190] In an exemplary embodiment, as shown in Figures 15A and 15B, the first conductive layer of the second display area AA2 may include at least: a scanning signal line 21, a first reset control line 22, a light emitting control line 23, a first electrode 24 of the storage capacitor Cst and a second reset control line 25.

[0191] In an exemplary embodiment, the shape of the first electrode plate 24 of the storage capacitor can be rectangular, and the corners of the rectangle can be chamfered, and the orthographic projection of the first electrode plate 24 on the substrate at least partially overlaps with the orthographic projection of the third active layer 13 on the substrate. In an exemplary embodiment, the first electrode plate 24 can simultaneously serve as a first electrode plate of the storage capacitor and a gate electrode of the third transistor T3. For example, the transistors used in the embodiments of the present disclosure can include a variety of structures, such as a top-gate type, a bottom-gate type, or a dual-gate structure. In an exemplary embodiment, the second transistor T2 and the first transistor T1 connected to the gate electrode of the third transistor T3 can be dual-gate thin-film transistors, which can help reduce the leakage current of the gate electrode of the third transistor T3.

[0192] In one exemplary embodiment, the scan signal line 21, the first reset control line 22, the second reset control line 25, and the light emission control line 23 may be in the shape of a line with a main portion extending along the first direction X. The scan signal line 21 and the light emission control line 23 may be located on both sides of the first electrode plate 24 in the second direction Y. The first reset control line 22 may be located on a side of the scan signal line 21 away from the first electrode plate 24. The second reset control line 25 may be located on a side of the scan signal line 21 away from the first electrode plate 24.

[0193] In an exemplary embodiment, the region where the scan signal line 21 overlaps with the second active layer 12 can serve as a gate electrode of the second transistor T2, and the orthographic projection of the scan signal line 21 on the substrate and the orthographic projection of the second active layer 12 on the substrate have a first overlapping region. For example, the scan signal line 21 is provided with a gate block 21-1 that protrudes toward the side of the first reset control line 22, and the region where the gate block 21-1 overlaps with the second active layer 12 can serve as another gate electrode of the second transistor T2. The orthographic projection of the gate block 21-1 on the substrate and the orthographic projection of the second active layer 12 on the substrate have a second overlapping region. In this way, a second transistor T2 with a dual-gate structure can be formed. For example, the scan signal line 21 and the gate electrode of the second transistor T2 of the pixel driving circuit in the same row can be an interconnected integral structure.

[0194] In an exemplary embodiment, the region where the scan signal line 21 overlaps with the fourth active layer 14 can serve as the gate electrode of the fourth transistor T4, and the orthographic projection of the scan signal line 21 on the substrate overlaps with the orthographic projection of the fourth active layer 14 on the substrate. For example, the scan signal line 21 and the gate electrodes of the fourth transistors T4 of the pixel driving circuits in the same row can be interconnected and integrated.

[0195] In an exemplary embodiment, the region where the first reset control line 22 overlaps the first active layer 11 can serve as the gate electrode of the first transistor T1 of the dual-gate structure, and the orthographic projection of the first reset control line 22 on the substrate overlaps with the orthographic projection of the first active layer 11 on the substrate. For example, the first reset control line 22 and the gate electrodes of the first transistors T1 of the pixel driving circuit in the same row can be interconnected and integrated.

[0196] In an exemplary embodiment, the region where the second reset control line 25 overlaps with the seventh active layer 17 serves as the gate electrode of the seventh transistor T7, and the orthographic projection of the second reset control line 25 on the substrate overlaps with the orthographic projection of the second active layer 12 on the substrate. For example, the second reset control line 25 and the gate electrodes of the seventh transistors T7 of the pixel driving circuits in the same row may be interconnected and integrally formed.

[0197] In one exemplary embodiment, the region where the light-emitting control line 23 overlaps with the fifth active layer 15 serves as the gate electrode of the fifth transistor T5, and the region where the light-emitting control line 23 overlaps with the sixth active layer 16 serves as the gate electrode of the sixth transistor T6. The orthographic projection of the light-emitting control line 23 on the substrate overlaps with the orthographic projection of the fifth active layer 15 on the substrate, and the orthographic projection of the light-emitting control line 23 on the substrate overlaps with the orthographic projection of the sixth active layer 16 on the substrate. For example, in this manner, the light-emitting control line 23 and the gate electrodes of the fifth transistor T5 and the gate electrodes of the sixth transistor T6 of the pixel driving circuit in the same row may be interconnected and integrated.

[0198] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first and second areas of the first to seventh active layers are both conductorized.

[0199] In one exemplary embodiment, the second conductive layer can be formed of a metal material. For example, the metal material can include, but is not limited to, any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the aforementioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). For example, the second conductive layer can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo.

[0200] In an exemplary embodiment, the second insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer.

[0201] (4) Forming a second conductive layer pattern.

[0202] In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on a substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern arranged on the third insulating layer, as shown in Figures 16A and 16B, where Figure 16B is a planar schematic diagram of the second conductive layer in Figure 16A.

[0203] In an exemplary embodiment, the third insulating layer may be referred to as a gate insulating (GI) layer, and the second conductive layer may be referred to as a second gate metal (Gate2) layer.

[0204] In an exemplary embodiment, as shown in Figures 16A and 16B, the second conductive layer of the second display area AA2 may at least include: a first initial signal line 31, a second initial signal line 32, a second plate 33 of the storage capacitor Cst, a block 34 and a plate connecting line 35.

[0205] In an exemplary embodiment, the second plate 33 of the storage capacitor can be located between the scanning signal line 21 and the light-emitting control line 23 of the pixel driving circuit. The second plates 33 of adjacent pixel driving circuits in the first direction X or the opposite direction of the first direction X can be connected through a plate connecting line 35. The first end of the plate connecting line 35 is connected to the second plate 33 of the pixel driving circuit. The second end of the plate connecting line 35 extends along the first direction X or the opposite direction of the first direction X and is connected to the second plate 33 of the adjacent pixel driving circuit. That is, the plate connecting line 35 is configured to connect the second plates 33 of adjacent pixel driving circuits on a unit row to each other.

[0206] In an exemplary embodiment, the second plates of multiple pixel driving circuits in a unit row can be connected to each other through the plate connecting line to form an integrated structure. The second plates of the integrated structure can be reused as power connection lines to ensure that the multiple second plates in a unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display panel, and ensuring the display effect of the display panel.

[0207] In an exemplary embodiment, the outline of the second electrode plate 33 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 33 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 24 on the substrate. The first electrode plate 24 and the second electrode plate 33 constitute a storage capacitor of the pixel driving circuit.

[0208] In an exemplary embodiment, an opening 36 is provided on the second electrode plate 33. The opening 36 can be located in the middle of the second electrode plate 33. For example, the opening 36 can be rectangular, so that the second electrode plate 33 forms a ring structure. For example, the opening 36 exposes the third insulating layer covering the first electrode plate 24, and the orthographic projection of the first electrode plate 24 on the substrate includes the orthographic projection of the opening 36 on the substrate. For example, the opening 36 can be configured to accommodate a first via hole formed later. The first via hole is located within the opening 36 and exposes the first electrode plate 24, so that the second electrode of the first transistor T1 formed later is connected to the first electrode plate 24 through the first via hole.

[0209] In an exemplary embodiment, the first preliminary signal line 31 and the second preliminary signal line 32 may have a line shape in which a main portion extends along the first direction X.

[0210] In an exemplary embodiment, the block 34 can be located between the scan signal line 21 and the first initial signal line 31. For example, the block 34 can be shaped like a broken line. For example, the block 34 can include a first electrode segment extending along the first direction X and a second electrode segment extending along the second direction Y. For example, the orthographic projection of the block 34 on the substrate at least partially overlaps with the orthographic projection of the subsequently formed data signal line 45 on the substrate. Thus, the block 34 can shield the impact of data voltage jumps on key nodes, preventing the data voltage jumps from affecting the potential of key nodes of the pixel driving circuit, thereby improving the display effect. For example, the orthographic projection of the block 34 on the substrate at least partially overlaps with the orthographic projection of the second region 11-2 of the first active layer 11 (also the first region 12-1 of the second active layer 12 and the second gate signal portion SL2) on the substrate. Thus, the block 34 can block the second gate signal portion SL2, thereby providing a shielding effect. This can shield the impact of voltage jumps on key nodes, preventing the voltage jumps from affecting the potential of key nodes of the pixel driving circuit, thereby improving the display effect. For example, the second electrode segment of the left block 34 can extend to the pixel driving circuit on the left (not shown in the figure) to block the conductive connection portion of the second transistor T2, and the first electrode segment of the right block 34 can extend to the pixel driving circuit on the left in the figure to block the conductive connection portion of the second transistor T2. Of course, in other embodiments, the block 34 may not be provided, or the orthographic projection of the block 34 on the substrate does not overlap with the orthographic projection of the second gate signal line SL2 on the substrate.

[0211] (5) Form a fourth insulating layer pattern.

[0212] In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, and providing a plurality of vias on the fourth insulating layer, as shown in FIG. 17 .

[0213] In one exemplary embodiment, the fourth insulating layer may be referred to as an interlayer dielectric (ILD) layer.

[0214] In an exemplary embodiment, as shown in FIG17 , the plurality of vias may include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, and an eleventh via V11.

[0215] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the opening 36 of the second electrode plate 33 on the substrate, the fourth insulating layer and the third insulating layer in the first via hole V1 are etched away to expose the surface of the first electrode plate 24, and the first via hole V1 is configured to connect the second electrode of the subsequently formed first transistor T1 to the first electrode plate 24 through the via hole.

[0216] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the second electrode plate 33 on the substrate, the fourth insulating layer in the second via V2 is etched away to expose the surface of the second electrode plate 33, and the second via V2 is configured to connect the first electrode of the subsequently formed fifth transistor T5 to the second electrode plate 33 through the via.

[0217] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer 55 on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the third via hole V3 are etched away to expose the surface of the first region of the fifth active layer 55, and the third via hole V3 is configured to connect the first electrode of the subsequently formed fifth transistor T5 to the first region of the fifth active layer 55 through the via hole.

[0218] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the second region of the sixth active layer 66 on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via V4 are etched away to expose the surface of the second region of the sixth active layer 16 (also the second region of the seventh active layer), and the fourth via V4 is configured to connect the second electrode of the subsequently formed sixth transistor T6 (also the second electrode of the seventh transistor T7) to the second region of the sixth active layer 16 through the via.

[0219] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer 14 on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via V5 are etched away to expose the surface of the first area of ​​the fourth active layer 14, and the fifth via V5 is configured to connect the first electrode of the subsequently formed fourth transistor T4 to the first area of ​​the fourth active layer 14 through the via.

[0220] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second region of the first active layer 11 on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via V6 are etched away to expose the surface of the second region of the first active layer 11 (also the first region of the second active layer 12), and the sixth via V6 is configured to connect the second electrode of the subsequently formed first transistor T1 (the first electrode of the second transistor T2) to the second region of the first active layer 11 through the via.

[0221] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer 17 on the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the seventh via V7 are etched away, exposing the surface of the first region of the seventh active layer 17. The seventh via V7 is configured to connect the first electrode of a subsequently formed seventh transistor T7 to the first region of the seventh active layer through the via.

[0222] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first region of the first active layer 11 on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the eighth via V8 are etched away to expose the surface of the first region of the first active layer 11, and the eighth via V8 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first region of the first active layer 11 through the via.

[0223] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first initial signal line 31 on the substrate, the fourth insulating layer in the ninth via V9 is etched away to expose the surface of the first initial signal line 31, and the ninth via V9 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first initial signal line 31 through the via.

[0224] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is located within the range of the orthographic projection of the second initial signal line 32 on the substrate, the fourth insulating layer in the tenth via V10 is etched away, exposing the surface of the second initial signal line 32, and the tenth via V10 is configured to connect the first electrode of the subsequently formed seventh transistor T7 to the second initial signal line 32 through the via.

[0225] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the block 34 on the substrate, the fourth insulating layer in the eleventh via hole V11 is etched away to expose the surface of the block 34, and the eleventh via hole V11 is configured to connect a subsequently formed first power line to the block 34 through the via hole.

[0226] In an exemplary embodiment, the via pattern of the second pixel driving circuit QD2 or the invalid pixel driving circuit may be substantially the same as the via pattern of the first pixel driving circuit QD1 .

[0227] (6) Forming a third conductive layer pattern.

[0228] In an exemplary embodiment, forming a third conductive layer may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on a fourth insulating layer, as shown in Figures 18A and 18B, where Figure 18B is a planar schematic diagram of the third conductive layer in Figure 18A.

[0229] In one exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0230] In an exemplary embodiment, the third conductive layer of the second display area AA2 may include a first connection electrode 41 , a second connection electrode 42 , a third connection electrode 43 , a fourth connection electrode 44 , a data signal line 45 and a first power line 46 .

[0231] In one exemplary embodiment, the first connection electrode 41 may be in the shape of a strip with a main portion extending along the second direction Y. In one exemplary embodiment, the first connection electrode 41 may serve as the first gate signal line SL1, which is connected to the gate electrode of the third transistor T3. In one exemplary embodiment, the first connection electrode 41 may simultaneously serve as the first gate signal line SL1, the second electrode of the first transistor T1, and the first electrode of the second transistor T2. The first end of the first connection electrode 41 is connected to the first electrode plate 24 (which is also the gate electrode of the third transistor T3) through the first via V1 and the opening 36, thereby connecting the first gate signal line SL1 to the gate electrode of the third transistor T3. The second end of the first connecting electrode 41 is connected to the second area of ​​the first active layer (also the first area of ​​the second active layer) through the sixth via V6, so that the second electrode of the first transistor T1 and the first electrode of the second transistor T2 on the first electrode plate 24 (also the gate electrode of the third transistor T3) have the same potential. In this way, the second electrode of the first transistor T1, the first electrode of the second transistor T2 and the gate electrode of the third transistor T3 are connected, and the second gate signal line SL2 is connected to the first gate signal line SL1.

[0232] For example, the first gate signal line SL1 and the second gate signal line SL2 may be made of different materials, such as metal, and the second gate signal line SL2 may be made of a conductive material formed by converting a semiconductor material into a conductor.

[0233] For example, the first gate signal line SL1, the second gate signal line SL2, and the gate electrode of the third transistor T3 are connected to form a first node N1 (also referred to as a gate signal portion). The potential at the first node N1 is the same. Of course, in other embodiments, the second gate signal line SL2 may not be provided. In this case, the gate electrode of the third transistor T3 and the first gate signal line SL1 form the first node N1. For example, the second gate signal line SL2 may be the second electrode of the first transistor T1, or it may be the first electrode of the second transistor T2.

[0234] In one exemplary embodiment, the second connection electrode 42 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the second connection electrode 42 is connected to the first region of the first active layer 11 via an eighth via V8, and a second end of the second connection electrode 42 is connected to the first initial signal line 31 via a ninth via V9. In one exemplary embodiment, the second connection electrode 42 may serve as the first electrode of the first transistor T1, enabling the first initial signal line 31 to write the first initial signal into the first transistor T1.

[0235] In one exemplary embodiment, the third connection electrode 43 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the third connection electrode 43 is connected to the first region of the seventh active layer 17 via a seventh via V7, and a second end of the third connection electrode 43 is connected to the second initial signal line 32 via a tenth via V10. In one exemplary embodiment, the third connection electrode 43 may serve as the first electrode of the seventh transistor T7, enabling the second initial signal line 32 to write the second initial signal into the seventh transistor T7.

[0236] In an exemplary embodiment, the fourth connection electrode 44 may be rectangular in shape and connected to the second region of the sixth active layer 16 (also the second region of the seventh active layer 17) through a fourth via V4, so that the second region of the sixth active layer 16 and the second region of the seventh active layer 17 have the same potential. For example, the fourth connection electrode 44 may serve as the second electrode of the sixth transistor T6 (or the second electrode of the seventh transistor T7) and is configured to be connected to a subsequently formed anode electrode.

[0237] In an exemplary embodiment, the data signal line 45 may be in the shape of a line with a main portion extending along the second direction Y. The data signal line 45 is connected to the first region of the fourth active layer 14 through a fifth via V5. Therefore, the data signal line 45 may serve as the first electrode of the fourth transistor T4, enabling the data signal line 45 to write a data signal to the first electrode of the fourth transistor T4. For example, the orthographic projection of the data signal line 45 on the substrate overlaps with the orthographic projection of the block 34 on the substrate.

[0238] In one exemplary embodiment, the first power line 46 can be shaped like a line with a main portion extending along the second direction Y. The first power line 46 is connected to the first region of the fifth active layer 15 via a third via V3 and to the second electrode plate 33 via a second via V2. Because the first power line 46 is connected to both the second electrode plate 33 and the first region of the fifth active layer 15, the first power line 46 writes the first power signal to the first electrode of the fifth transistor T5, ensuring that the second electrode plate 33 and the first region of the fifth active layer have the same potential. For example, the first power line 46 can serve as the first electrode of the fifth transistor T5. The orthographic projection of the first power line 46 on the substrate overlaps with the orthographic projection of the block 34 on the substrate. The first power line 46 is connected to the block 34 via an eleventh via V11. Because the first power line 46 is configured to provide a constant voltage to the pixel driving circuit, it stabilizes the voltage on the block 34, providing a shielding effect.

[0239] In an exemplary embodiment, the first power lines 46 may be designed with unequal widths. The unequal width design of the first power lines 46 not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance generated by the first power lines.

[0240] In one exemplary embodiment, the third conductive layer can be formed of a metal material. For example, the metal material may include, but is not limited to, any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the aforementioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The third conductive layer can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo.

[0241] (7) Forming a fourth conductive layer pattern.

[0242] In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fifth insulating film and a fourth conductive film on a substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process to form a fifth insulating layer covering the third conductive layer, as shown in FIG19 , and forming a fourth conductive layer arranged on the fifth insulating layer, as shown in FIG20A and FIG20B , where FIG20B is a planar schematic diagram of the fourth conductive layer in FIG20A .

[0243] In an exemplary embodiment, the fifth insulating layer may include a plurality of vias, which may include a second-first via V21 and a second-second via V22. For example, the orthographic projection of the second-first via V21 on the substrate overlaps with the orthographic projection of the first power line 46 on the substrate, and is configured to expose the surface of the first power line 46. For example, the orthographic projection of the second-second via V22 on the substrate overlaps with the orthographic projection of the fourth connection electrode 44 on the substrate, and is configured to expose the surface of the fourth connection electrode 44.

[0244] In one exemplary embodiment, the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0245] In an exemplary embodiment, the fourth conductive layer of the second display area AA2 may include at least a shielding electrode 60 and a fifth connecting electrode 50 .

[0246] In one exemplary embodiment, the orthographic projection of the shielding electrode 60 on the substrate overlaps with the orthographic projection of the first gate signal line SL1 on the substrate. A shielding block 60-1 is provided on one side of the shielding electrode 60 in the first direction X. The orthographic projection of the shielding block 60-1 on the substrate at least partially overlaps with the orthographic projection of the first power line 46 on the substrate. The shielding block 60-1 is connected to the first power line 46 via the second first via V21. The shielding block 60-1 is configured to connect the shielding electrode 60 to the first power line 46 via the second first via V21. The first power line 46 is configured to provide a constant voltage to the pixel driving circuit. In this way, the voltage on the shielding electrode 60 is stable, thereby providing a shielding effect. Since the anode light emitting signal is extracted in the first display area AA1 via the conductive line L, the provision of the shielding electrode 60 can prevent the conductive line L from affecting key nodes (such as the first node N1), thereby improving the display effect. For example, the orthographic projection of the first gate signal line SL1 on the substrate completely falls within the boundary of the orthographic projection of the shielding electrode 60 on the substrate, thereby enabling the shielding electrode 60 to provide a better shielding effect. For example, to reduce display mura and improve display quality, the distance between the orthographic projection of the first gate signal line SL1 on the substrate and the boundary of the orthographic projection of the shielding electrode 60 on the substrate is greater than or equal to 1.75 μm (micrometers). Because the area occupied by the pixel unit is limited, the distance that the shielding electrode 60 extends beyond the first gate signal line SL1 can be limited. For example, in some embodiments, to achieve a better shielding effect, the distance between the orthographic projection of the first gate signal line SL1 on the substrate and the boundary of the orthographic projection of the shielding electrode SE on the substrate is greater than or equal to 2.33 μm.

[0247] In an exemplary embodiment, when the display panel includes a second gate signal line SL2, the second gate signal line SL2 is connected to the first gate signal line SL1 to form a first node N1. Therefore, the orthographic projection of the shielding electrode 60 on the substrate overlaps with the orthographic projection of the second gate signal line SL2 on the substrate.

[0248] In an exemplary embodiment, the orthographic projection of the shielding electrode 60 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 24 (also the gate electrode of the third transistor T3) on the substrate, the orthographic projection of the first gate signal line SL1 (also the second electrode of the first transistor T1 and the first electrode of the second transistor T2) on the substrate, and the orthographic projection of the second gate signal line SL2 (also the second region of the first active layer 11 and the first region of the second active layer 12) on the substrate.

[0249] In one exemplary embodiment, the orthographic projection of the shielding electrode 60 on the substrate partially overlaps with the orthographic projection of the second gate signal line SL2 on the substrate, and the orthographic projection of the block 34 on the substrate partially overlaps with the orthographic projection of the second gate signal line SL2 on the substrate. Thus, in the display panel shown in FIG20A , the shielding electrode 60 and the block 34 form a double shield for the second gate signal line SL2.

[0250] In an exemplary embodiment, the orthographic projection of the shielding electrode 60 on the substrate partially overlaps with the orthographic projection of the stopper 34 on the substrate.

[0251] In an exemplary embodiment, the orthographic projection of the shielding electrode 60 on the substrate partially overlaps with the orthographic projection of the first gate signal line SL1 on the substrate, and the orthographic projection of the block 34 on the substrate partially overlaps with the orthographic projection of the second gate signal line SL2 on the substrate, so that the shielding electrode 60, the shielding electrode SE and the block 34 jointly play a shielding role for the first node N1.

[0252] Of course, in other embodiments, the block 34 may not be provided, or the orthographic projection of the block 34 on the substrate may not overlap with the orthographic projection of the second gate signal line SL2 on the substrate.

[0253] In one exemplary embodiment, the shielding electrode 60 can be in a regular shape, for example, a rectangular shape. By providing the shielding electrode 60 with a regular shape, the width of the shielding electrode 60 can be made uniform at different locations. This can also ensure that the width of the transparent conductive lines passing over the shielding electrode 60 is consistent, reducing the impact on the width of the transparent conductive lines. This, in turn, helps improve uneven brightness.

[0254] In one exemplary embodiment, the fifth connection electrode 50 can be rectangular in shape. The orthographic projection of the fifth connection electrode on the substrate at least partially overlaps the orthographic projection of the fourth connection electrode 44 on the substrate. The fifth connection electrode 50 can serve as an anode connection electrode. The fifth connection electrode 50 is connected to the fourth connection electrode 44 through the second via V22 and is configured to be connected to a subsequently formed anode electrode.

[0255] In one exemplary embodiment, within a plane perpendicular to the display panel, the circuit structure layers of the second display area AA2 may include: a substrate, and a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, and a fourth conductive layer stacked sequentially on the substrate. The semiconductor layer may include: the active layers of multiple transistors in the first pixel driving circuit QD1 and the second pixel driving circuit QD2; the first conductive layer may include: the gate electrodes of the multiple transistors, the first plates of the storage capacitors, the scan signal lines, the first reset control lines, the light emission control lines, and the second reset control lines; the second conductive layer may include: the second plates of the storage capacitors, the plate connection lines, the blockers, the first initial signal lines and the second initial signal lines; the third conductive layer may include: the first and second electrodes of the multiple transistors, the data signal lines, and the first power lines; and the fourth conductive layer may include: the anode connection electrode and the shielding electrode. In other words, the circuit structure layers of the second display area AA2 may include: the first pixel driving circuit QD1 and the second pixel driving circuit QD2.

[0256] In one exemplary embodiment, within a plane perpendicular to the display panel, the light-transmitting region of the first display area AA1 may include: a substrate, and a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer stacked sequentially on the substrate. The non-light-transmitting region of the first display area AA1 may include: a substrate, and a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer stacked sequentially on the substrate. In other words, the circuit structure layer of the first display area AA1 does not include a pixel driving circuit.

[0257] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo.

[0258] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer.

[0259] At this point, the circuit structure layer is prepared on the substrate.

[0260] (8) Forming a first transparent conductive layer.

[0261] In an exemplary embodiment, a sixth insulating film and a first transparent conductive film are deposited on the substrate on which the aforementioned pattern is formed, and the first transparent conductive film is patterned through a patterning process to form a sixth insulating layer covering the fourth conductive layer, and a first transparent conductive layer arranged on the sixth insulating layer, as shown in Figures 21A and 21B.

[0262] In an exemplary embodiment, the first transparent conductive layer may include a sixth connection electrode 61 .

[0263] In one exemplary embodiment, the sixth connection electrode 61 can be rectangular. The orthographic projection of the sixth connection electrode 61 on the substrate at least partially overlaps with the orthographic projection of the fifth connection electrode 50 on the substrate. When the first light-emitting device is electrically connected to the first pixel driving circuit QD1 of the transitional display area AAG via the first transparent conductive line L1 located in the first transparent conductive layer, the sixth connection electrode 61 can serve as a switching electrode for the first light-emitting device. The sixth connection electrode 61 is connected to the fifth connection electrode 50 through a via in the sixth insulating layer and is configured to be connected to a subsequently formed anode electrode.

[0264] In an exemplary embodiment, the first transparent conductive layer may further include a first transparent conductive line L1. For example, one end of the first transparent conductive line L1 may be connected to a sixth connection electrode 61 located in the first display area AA1, and the other end of the first transparent conductive line L1 may be connected to a sixth connection electrode 61 located in the first pixel driving circuit QD1 in the transition display area AAG in the second display area AA2. In this way, a subsequently formed anode electrode may be connected to the first pixel driving circuit QD1 in the transition display area AAG.

[0265] (9) Forming a second transparent conductive layer.

[0266] In one exemplary embodiment, a first planar film is applied to the substrate on which the aforementioned pattern is formed, and a patterning process is performed to form a first planar layer. Subsequently, a second transparent conductive film is deposited and patterned through a patterning process to form a second transparent conductive layer disposed on the first planar layer, as shown in Figures 22A and 22B.

[0267] In an exemplary embodiment, the second transparent conductive layer may include a seventh connection electrode 71 .

[0268] In one exemplary embodiment, the seventh connection electrode 71 can be rectangular. The orthographic projection of the seventh connection electrode 71 on the substrate at least partially overlaps with the orthographic projection of the sixth connection electrode 61 on the substrate. When the first light-emitting device is electrically connected to the first pixel driving circuit QD1 of the transitional display area AAG via the second transparent conductive line L2 located in the second transparent conductive layer, the seventh connection electrode 71 can serve as a switching electrode for the first light-emitting device. The seventh connection electrode 71 is connected to the sixth connection electrode 61 through a via in the first planar layer and is configured to be connected to a subsequently formed anode electrode.

[0269] In an exemplary embodiment, the second transparent conductive layer may further include a second transparent conductive line L2. For example, one end of the second transparent conductive line L2 may be connected to a seventh connection electrode 71 located in the first display area AA1, and the other end of the second transparent conductive line L2 may be connected to a seventh connection electrode 71 located in the first pixel driving circuit QD1 in the transition display area AAG within the second display area AA2. In this way, a subsequently formed anode electrode may be connected to the first pixel driving circuit QD1 in the transition display area AAG.

[0270] (10) A third transparent conductive layer is formed.

[0271] In one exemplary embodiment, a second planar film is applied to the substrate on which the aforementioned pattern is formed, and a patterning process is performed to form a second planar layer. Subsequently, a third transparent conductive film is deposited and patterned through a patterning process to form a third transparent conductive layer disposed on the second planar layer, as shown in Figures 23A and 23B.

[0272] In an exemplary embodiment, the third transparent conductive layer may include an eighth connecting electrode 81 .

[0273] In one exemplary embodiment, the eighth connection electrode 81 may be rectangular. The orthographic projection of the eighth connection electrode 81 on the substrate at least partially overlaps with the orthographic projection of the seventh connection electrode 71 on the substrate. When the first light-emitting device is electrically connected to the first pixel driving circuit QD1 located in the transition display area AAG within the second display area AA2 via the third transparent conductive line L3 located in the third transparent conductive layer, the eighth connection electrode 81 may serve as a switching electrode for the first light-emitting device. The eighth connection electrode 81 is connected to the seventh connection electrode 71 through a via in the second planar layer and is configured to be connected to a subsequently formed anode electrode.

[0274] In an exemplary embodiment, the third transparent conductive layer may further include a third transparent conductive line L3. For example, one end of the third transparent conductive line L3 may be connected to an eighth connection electrode 81 located in the first display area AA1, and the other end of the second transparent conductive line L2 may be connected to an eighth connection electrode 81 located in the first pixel driving circuit QD1 in the transition display area AAG in the second display area AA2. In this way, a subsequently formed anode electrode may be connected to the first pixel driving circuit QD1 in the transition display area AAG.

[0275] In one exemplary embodiment, the conductive line L may include one or more of a first transparent conductive line L1, a second transparent conductive line L2, and a third transparent conductive line L3. For example, the orthographic projection of the conductive line L1 on the substrate partially overlaps with the orthographic projection of the first pixel drive circuit QD1 on the substrate. For example, the orthographic projection of the conductive line L1 on the substrate partially overlaps with the orthographic projection of the first gate signal line SL1 in the first pixel drive circuit QD1 on the substrate. The shielding electrode 60 is located between the conductive line L1 and the first gate signal line SL1. In an embodiment of the present disclosure, after forming the pixel drive circuit, the shielding electrode 60 is formed, and then the conductive line L1 (such as the first transparent conductive line L1, the second transparent conductive line L2, and the third transparent conductive line L3) is formed, and then the light-emitting device is formed. As a result, the film layer where the shielding electrode 60 is located is located between the film layer where the conductive line L1 is located and the film layer where the first gate signal line SL1 is located, and the film layer where the shielding electrode 60 is located is located between the film layer where the conductive line L1 is located and the film layer where the gate electrode of the third transistor T3 is located.

[0276] (11) Forming a light-emitting structure layer.

[0277] In an exemplary embodiment, a third flat film is coated on a substrate on which the aforementioned pattern is formed, and a third flat layer is formed by a patterning process. Subsequently, an anode conductive film is deposited, and the anode conductive film is patterned by a patterning process to form an anode layer arranged on the third flat layer, as shown in Figures 24A and 24B. Subsequently, a pixel definition film is coated on the substrate on which the aforementioned pattern is formed, and a pixel definition layer (PDL, Pixel Define Layer) is formed by a mask, exposure and development process. The pixel definition layer is formed with a plurality of pixel openings exposing the anode layer, and the pixel openings are configured to define the light-emitting area of ​​the pixel unit, as shown in Figure 25. An organic light-emitting layer is formed in the pixel opening formed above, and the organic light-emitting layer is connected to the anode. Subsequently, a cathode film is deposited, and the cathode film is patterned by a patterning process to form a cathode pattern, and the cathode is electrically connected to the organic light-emitting layer and the second power line, respectively. Subsequently, an encapsulation layer is formed on the cathode, and the encapsulation layer may include a laminated structure of inorganic material / organic material / inorganic material. 24A, 24B, and 25 illustrate eight light-emitting devices in the second display area AA2, omitting the second pixel driver circuit QD2. FIG. 24C illustrates the connection between the second anode of a second light-emitting device in the second display area AA2 and the second pixel driver circuit QD2. The structure of the light-emitting devices in the first display area AA1 can be substantially similar, and those skilled in the art will appreciate the relevant description. The disclosed embodiments will not be further elaborated upon herein.

[0278] In an exemplary embodiment, the anode layer may include a first anode electrode 91 , a second anode electrode 92 , and a third anode electrode 93 .

[0279] In an exemplary embodiment, the first anode electrode 91 can serve as the anode of a green light emitting device. The orthographic projection of the first anode electrode 91 on the substrate can partially overlap with the orthographic projections of the eighth connection electrode 81, the seventh connection electrode 71, the sixth connection electrode 61, and the fifth connection electrode 50 on the substrate.

[0280] In an exemplary embodiment, the second anode electrode 92 can serve as the anode of the red light emitting device. The orthographic projection of the second anode electrode 92 on the substrate can partially overlap with the orthographic projections of the eighth connection electrode 81, the seventh connection electrode 71, the sixth connection electrode 61, and the fifth connection electrode 50 on the substrate.

[0281] In an exemplary embodiment, the third anode electrode 93 may serve as an anode of a blue light emitting device. The orthographic projection of the third anode electrode 93 on the substrate may partially overlap with the orthographic projections of the eighth connection electrode 81, the seventh connection electrode 71, the sixth connection electrode 61, and the fifth connection electrode 50 on the substrate.

[0282] In an exemplary embodiment, the plurality of pixel openings may include a first pixel opening 94 , a second pixel opening 95 , and a third pixel opening 96 .

[0283] In an exemplary embodiment, the shape of the first pixel opening 94 may be a pentagon, and the orthographic projection of the first pixel opening 94 on the substrate falls within the boundary of the orthographic projection of the first anode electrode 91 on the substrate.

[0284] In an exemplary embodiment, the second pixel opening 95 may be hexagonal in shape, and the orthographic projection of the second pixel opening 95 on the substrate falls within the boundary of the orthographic projection of the second anode electrode 92 on the substrate.

[0285] In an exemplary embodiment, the third pixel opening 96 may be hexagonal in shape, and the orthographic projection of the third pixel opening 96 on the substrate falls within the boundary of the orthographic projection of the third anode electrode 93 on the substrate.

[0286] In an exemplary embodiment, the first to third transparent conductive layers may be made of a transparent conductive material, such as indium tin oxide (ITO). The sixth insulating layer and the first to third planar layers may be made of an organic material, such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer may be made of an organic material, such as polyimide, acrylic, or polyethylene terephthalate. The anode layer may be made of a reflective material, such as a metal, and the cathode may be made of a transparent conductive material. This is not limited in the present embodiment.

[0287] The structure of the display panel and its manufacturing process in the disclosed embodiment are merely exemplary. In an exemplary embodiment, the corresponding structure can be modified and the patterning process can be added or removed based on the actual application scenario. The manufacturing process of this exemplary embodiment can be implemented using currently available manufacturing equipment and is well compatible with manufacturing processes in other technologies. The process is simple to implement, easy to implement, and has high production efficiency, low production cost, and high yield rate.

[0288] In one exemplary embodiment, the display panel may include four or more transparent conductive layers. The transparent conductive lines electrically connected to the first type of first light-emitting devices and the second type of first light-emitting devices within the first sub-region of the first display area may be located in two different transparent conductive layers, and at least one transparent conductive layer may be spaced between the two different transparent conductive layers.

[0289] In the display panel provided by the embodiment of the present disclosure, by adjusting the wiring method of the transparent conductive lines electrically connected to the first type of first light-emitting devices and the second type of first light-emitting devices in the first display area, the uniformity of the conductive lines can be ensured, thereby improving the display uniformity of the first display area and enhancing the display effect of the first display area.

[0290] The present disclosure also provides a display device, which may include: the display panel according to one or more of the above exemplary embodiments.

[0291] In an exemplary embodiment, the display device may further include: a sensor, the sensor being located on a non-display side of the display panel, and an orthographic projection of the sensor on the display panel overlapping with the first display area of ​​the display panel.

[0292] Here, the display device may be a product having an image (including a static image or a dynamic image, wherein the dynamic image may be a video) display function.

[0293] In an exemplary embodiment, the display device may include, but is not limited to, any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a billboard, a laser printer with a display function, a picture screen, a personal digital assistant (PDA), a digital camera, a camcorder, a viewfinder, a navigation system, a vehicle, a large-area wall, an information query device (such as a business query device for e-government, a bank, a hospital, a power department, etc.), or a monitor. The embodiments of the present disclosure are not limited to this.

[0294] In an exemplary embodiment, the sensor may include, but is not limited to, a camera sensor, a fingerprint sensor, a light sensor, an infrared sensor, or an ultrasonic sensor, etc. This is not limited in the embodiments of the present disclosure.

[0295] The description of the display device embodiment above is similar to the description of the display panel embodiment above, and has similar beneficial effects as the display panel embodiment. For technical details not disclosed in the display device embodiment of the present disclosure, those skilled in the art should refer to the description of the display panel embodiment of the present disclosure for understanding, and will not be repeated here.

[0296] Although the embodiments disclosed in this disclosure are as described above, the above contents are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the appended claims.

Claims

1. A display panel, comprising: A substrate, a circuit structure layer and a light emitting structure layer stacked on the substrate, and a plurality of conductive layers arranged between the circuit structure layer and the light emitting structure layer; wherein, The substrate comprises: a first display area and a second display area, wherein the second display area is located on at least one side of the first display area, and the light transmittance of the first display area is greater than the light transmittance of the second display area; The circuit structure layer includes: a first gate signal line located in the second display area, a constant voltage line, a plurality of shielding electrodes, and a plurality of pixel circuits, wherein the pixel circuit includes a driving transistor, the driving transistor includes a gate, and the plurality of pixel circuits include a plurality of first pixel driving circuits; the first gate signal line is connected to the gate of the driving transistor; the constant voltage line is configured to provide a first constant voltage to the plurality of pixel circuits; the shielding electrode is connected to the constant voltage line, and an orthographic projection of the first gate signal line on the substrate falls within an orthographic projection of the shielding electrode on the substrate; The plurality of conductive layers include: a plurality of conductive lines, the plurality of conductive lines including: a plurality of first-type conductive lines and a plurality of second-type conductive lines, wherein the orthographic projections of portions of the first-type conductive lines extending along the first direction overlap with the orthographic projections of at least one of the plurality of shielding electrodes on the substrate, and the orthographic projections of portions of the second-type conductive lines extending along the first direction do not overlap with the orthographic projections of the plurality of shielding electrodes on the substrate; The light-emitting structure layer includes: a plurality of first light-emitting devices located in the first display area, the plurality of first light-emitting devices including: a plurality of first-type first light-emitting devices and a plurality of second-type first light-emitting devices, at least one first-type first light-emitting device among the plurality of first-type first light-emitting devices is connected to at least one first pixel driving circuit among the plurality of first pixel driving circuits through at least one first-type conductive line among the plurality of first-type conductive lines, and at least one second-type first light-emitting device among the plurality of second-type first light-emitting devices is connected to at least one first pixel driving circuit among the plurality of first pixel driving circuits through at least one second-type conductive line among the plurality of second-type conductive lines, the first pixel driving circuit is configured to drive the first light-emitting device to emit light, the first-type first light-emitting device is configured to emit a first color light, and the second-type first light-emitting device is configured to emit a second color light, which is different from the first color light.

2. The display panel according to claim 1, wherein The plurality of first light-emitting devices in the first display area include: a plurality of groups of first light-emitting devices, wherein the first light-emitting devices in each group of the plurality of groups of first light-emitting devices are arranged along the first direction, and the plurality of groups of first light-emitting devices are arranged along a second direction, wherein the second direction intersects the first direction; In the at least one group of first light-emitting devices, the multiple first pixel driving circuits electrically connected to the multiple first-type first light-emitting devices are closer to the first display area than each of the multiple first pixel driving circuits electrically connected to the multiple second-type first light-emitting devices.

3. The display panel according to claim 2, wherein: The multiple conductive layers include: a first transparent conductive layer, a second transparent conductive layer and a third transparent conductive layer arranged in sequence along a side away from the substrate; the first transparent conductive layer includes a plurality of first transparent conductive lines, the second transparent conductive layer includes a plurality of second transparent conductive lines, and the third transparent conductive layer includes a plurality of third transparent conductive lines.

4. The display panel according to claim 3, wherein: In at least one group of first light-emitting devices in the first display area, a plurality of first-category first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits through the first transparent conductive line, and a plurality of first-category first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits through the third transparent conductive line.

5. The display panel according to claim 3, wherein: In at least one group of first light-emitting devices in the first display area, a plurality of first-category first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits through the first transparent conductive line, and a plurality of first-category first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits through the second transparent conductive line. The display panel according to claim 3 , wherein: In at least one group of first light-emitting devices in the first display area, a plurality of first-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits through the second transparent conductive line, and a plurality of first-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits in the second display area through the first transparent conductive line.

7. The display panel according to claim 3, wherein: In at least one group of first light-emitting devices in the first display area, a plurality of first-category first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits through the third transparent conductive line, and a plurality of first-category first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits in the second display area through the first transparent conductive line.

8. The display panel according to any one of claims 4 to 7, wherein: In at least one group of first light-emitting devices in the first display area, a plurality of second-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits through the first transparent conductive line, and a plurality of second-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits through the third transparent conductive line.

9. The display panel according to any one of claims 4 to 7, wherein: In at least one group of first light-emitting devices in the first display area, the type of transparent conductive wires electrically connected to the multiple second-type first light-emitting devices near the center of the first display area is the same as the type of transparent conductive wires electrically connected to the multiple first-type first light-emitting devices near the center of the first display area, or the type of transparent conductive wires electrically connected to the multiple second-type first light-emitting devices near the edge of the first display area is the same as the type of transparent conductive wires electrically connected to the multiple first-type first light-emitting devices near the edge of the first display area.

10. The display panel according to any one of claims 4 to 7, wherein: In at least one group of first light-emitting devices in the first display area, the type of transparent conductive wires electrically connected to the multiple second-type first light-emitting devices near the center of the first display area is different from the type of transparent conductive wires electrically connected to the multiple first-type first light-emitting devices near the center of the first display area, or the type of transparent conductive wires electrically connected to the multiple second-type first light-emitting devices near the edge of the first display area is different from the type of transparent conductive wires electrically connected to the multiple first-type first light-emitting devices near the edge of the first display area.

11. The display panel according to any one of claims 4 to 7, wherein: In at least one group of first light-emitting devices in the first display area, a plurality of second-type first light-emitting devices near the center of the first display area are electrically connected to a plurality of first pixel driving circuits through the first transparent conductive line, and a plurality of second-type first light-emitting devices near the edge of the first display area are electrically connected to a plurality of first pixel driving circuits through the third transparent conductive line.

12. The display panel according to any one of claims 4 to 7, wherein: In at least one group of first light-emitting devices in the first display area, the conductive wire electrically connecting the plurality of first-type first light-emitting devices is located on one side of the switching electrode of the group of first light-emitting devices in the second direction.

13. The display panel according to claim 12, wherein: In at least one group of first light-emitting devices in the first display area, the conductive wire electrically connecting the plurality of second-type first light-emitting devices is located on the other side of the switching electrode of the group of first light-emitting devices in the second direction.

14. The display panel according to claim 3, wherein: In at least one group of first light-emitting devices in the first display area, a plurality of first-category first light-emitting devices near the center of the first display area are electrically connected to the plurality of first pixel driving circuits through the first transparent conductive lines, a plurality of first-category first light-emitting devices near the edge of the first display area are electrically connected to the plurality of first pixel driving circuits through the third transparent conductive lines, and a plurality of first-category first light-emitting devices located between the plurality of first-category first light-emitting devices near the center of the first display area and the plurality of first-category first light-emitting devices near the edge of the first display area are electrically connected to the plurality of first pixel driving circuits through the second transparent conductive lines; In at least one group of first light-emitting devices in the first display area, a plurality of second-class first light-emitting devices near the center of the first display area are electrically connected to the plurality of first pixel driving circuits through the first transparent conductive line, a plurality of second-class first light-emitting devices near the edge of the first display area are electrically connected to the plurality of first pixel driving circuits through the third transparent conductive line, and a plurality of second-class first light-emitting devices located between the plurality of second-class first light-emitting devices near the center of the first display area and the plurality of second-class first light-emitting devices near the edge of the first display area are electrically connected to the plurality of first pixel driving circuits through the second transparent conductive line.

15. The display panel according to any one of claims 1 to 7, wherein: The first display area includes: a first sub-area and a second sub-area, and the second sub-area is located between the first sub-area and the second display area; At least one first light-emitting device located in the first sub-region among the plurality of first light-emitting devices is connected to at least one first pixel driving circuit among the plurality of first pixel driving circuits through the conductive lines of the plurality of conductive layers; At least one first light-emitting device located in the second sub-region among the plurality of first light-emitting devices is connected to at least one first pixel driving circuit among the plurality of first pixel driving circuits through a conductive line of the metal conductive layer in the circuit structure layer.

16. The display panel according to claim 15, wherein: The metal conductive layer and the shielding electrode are located in the same film layer.

17. The display panel according to any one of claims 1 to 7, wherein: The light emitting structure layer further includes: a plurality of second light emitting devices located in the second display area; The multiple pixel circuits also include: multiple second pixel driving circuits, at least one second pixel driving circuit among the multiple second pixel driving circuits is electrically connected to at least one second light-emitting device among the multiple second light-emitting devices, and the at least one second pixel driving circuit is configured to drive the at least one second light-emitting device to emit light.

18. The display panel according to claim 17, wherein: The second display area includes: a transition display area and a normal display area, and the transition display area is located between the first display area and the normal display area; The transition display area includes: the plurality of first pixel driving circuits; The normal display area includes: at least part of the plurality of second light emitting devices and at least part of the plurality of second pixel driving circuits, and at least part of the plurality of second light emitting devices is connected to at least part of the plurality of second pixel driving circuits.

19. The display panel according to any one of claims 1 to 7, wherein: The first color light is green light, and the second color light includes at least one of blue light and red light.

20. A display device comprising: The display panel according to any one of claims 1 to 19.

21. The display device according to claim 20, further comprising: A sensor is located on a non-display side of the display panel, and an orthographic projection of the sensor on the display panel overlaps with a first display area of ​​the display panel.