Using neural networks to perform object detection, instance segmentation, and semantic correspondence from bounding box supervision

Abstract

A processor comprises circuits used to run one or more neural networks 106 to segment images 102, 104 using at least partially, bounding boxes. The neural networks may be supervised or unsupervised an

Description

TECHNICAL FIELD [()001 ] At least one embodiment pertains to processing resources used to train neural networks. For example, at least one embodiment, pertains to processors or computing systems used to train neural networks to perform object detection, instance segmentation, and semantic correspondence according to various novel techniques described herein. BACKGROUND

[0002] Training neural networks to perform segmentation tasks can present issues in various contexts. For example, training data for segmentation tasks can be difficult to obtain, and generating such training data can require large amounts of resources. This can result in significant memory, time, or computing resources being used to train neural networks to perform segmentation tasks. However, in some examples, training data for object detection tasks, such as bounding box annotations, can be more easily obtained, and generation of such training data can require less resources. Amounts of memory, time, or computing resources used to train neural networks to perform segmentation tasks can be improved. SUMMARY OF THE INVENTION [()003] According to various aspects described herein, there may be provided apparatuses, systems, and techniques to train one or more neural networks. In at least one embodiment, one or more neural networks may be trained to perform segmentation tasks based at least in part on training data comprising bounding box annotations.

[0004] Further features of the disclosure are characterized by the independent and dependent claims. 16 05 23 [ 0005] Any feature in one aspect of the disclosure may be applied to other aspects of the disclosure, in any appropriate combination. In particular, method aspects may be applied to apparatus or system aspects, and vice versa.

[0006] Furthermore, features implemented in hardware may be implemented in software, and vice versa. Any reference to software and hardware features herein should be construed accordingly.

[0007] Any system or apparatus feature as described herein may also be provided as a method feature, and vice versa. System and / or apparatus aspects described functionally (including means plus function features) may be expressed alternatively in terms of their corresponding structure, such as a suitably programmed processor and associated memory.

[0008] It should also be appreciated that particular combinations of the various features described and defined in any aspects of the disclosure can be implemented and / or supplied and / or used independently. [0009 ] The disclosure also provides computer programs and computer program products comprising software code adapted, when executed on a data processing apparatus, to perform any of the methods and / or for embodying any of the apparatus and system features described herein, including any or all of the component steps of any method.

[0010] The disclosure also provides a computer or computing system (including networked or distributed systems) having an operating system which supports a computer program for carrying out any of the methods described herein and / or for embodying any of the apparatus or system features described herein.

[0011] The disclosure also provides a computer readable media having stored thereon any one or more of the computer programs aforesaid.

[0012] The disclosure also provides a signal carrying any one or more of the computer programs aforesaid.

[0013] The disclosure extends to methods and / or apparatus and / or systems as herein described with reference to the accompanying drawings. 16 05 23

[0014] Aspects and embodiments of the disclosure will now be described purely by way of example, with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0015] FIG. 1 illustrates an example of a framework for object detection, instance segmentation, and semantic correspondence, according to at least one embodiment; [0016 ] FIG. 2 illustrates an example of a detailed overview of a framework for object detection, instance segmentation, and semantic correspondence, according to at least one embodiment;

[0017] FIG. 3 illustrates an example of multiple instance learning where stripes of pixels are used for calculating loss, according to at least one embodiment;

[0018] FIG. 4 illustrates an example of optimal transport used to improve accuracy of semantic correspondence and instance segmentation, according to at least one embodiment;

[0019] FIG. 5 illustrates an example of results using a framework for object detection, instance segmentation, and semantic correspondence, according to at least one embodiment;

[0020] FIG. 6 illustrates an example of visualizations of results using a framework for object detection, instance segmentation, and semantic correspondence, according to at least one embodiment;

[0021] FIG. 7 illustrates an example of a process for a framework for object detection, instance segmentation, and semantic correspondence, according to at least one embodiment;

[0022] FIG. 8A illustrates inference and / or training logic, according to at least one embodiment;

[0023] FIG. 8B illustrates inference and / or training logic, according to at least one embodiment;

[0024] FIG. 9 illustrates training and deployment of a neural network, according to at least one embodiment;

[0025] FIG. 10 illustrates an example data center system, according to at least one embodiment;

[0026] FIG. 11A illustrates an example of an autonomous vehicle, according to at least one embodiment;

[0027] FIG. 1 IB illustrates an example of camera locations and fields of view for the autonomous vehicle of FIG. 11A, according to at least one embodiment;

[0028] FIG. 1 IC is a block diagram illustrating an example system architecture for the autonomous vehicle of FIG. 11 A, according to at least one embodiment;

[0029] FIG. 1 ID is a diagram illustrating a system for communication between cloud-based server(s) and the autonomous vehicle of FIG. 11 A, according to at least one embodiment;

[0030] FIG. 12 is a block diagram illustrating a computer system, according to at least one embodiment; 16 05 23 [0031 ] FIG. 13 is a block diagram illustrating a computer system, according to at least one embodiment;

[0032] FIG. 14 illustrates a computer system, according to at least one embodiment;

[0033] FIG. 15 illustrates a computer system, according to at least one embodiment;

[0034] FIG. 16A illustrates a computer system, according to at least one embodiment;

[0035] FIG. 16B illustrates a computer system, according to at least one embodiment;

[0036] FIG. 16C illustrates a computer system, according to at least one embodiment;

[0037] FIG. 16D illustrates a computer system, according to at least one embodiment;

[0038] FIGS. 16E and 16F illustrate a shared programming model, according to at least one embodiment;

[0039] FIG. 17 illustrates exemplary integrated circuits and associated graphics processors, according to at least one embodiment;

[0040] FIGS. 18A and 18B illustrate exemplary integrated circuits and associated graphics processors, according to at least one embodiment; 16 05 23 [0041 ] FIGS. 19A and 19B illustrate additional exemplary graphics processor logic according to at least one embodiment;

[0042] FIG. 20 illustrates a computer system, according to at least one embodiment; [0043 ] FIG. 21A illustrates a parallel processor, according to at least one embodiment; [()044] FIG. 2IB illustrates a partition unit, according to at least one embodiment;

[0045] FIG. 21C illustrates a processing cluster, according to at least one embodiment;

[0046] FIG. 2ID illustrates a graphics multiprocessor, according to at least one embodiment;

[0047] FIG. 22 illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment;

[0048] FIG. 23 illustrates a graphics processor, according to at least one embodiment;

[0049] FIG. 24 is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment;

[0050] FIG. 25 illustrates a deep learning application processor, according to at least one embodiment;

[0051] FIG. 26 is a block diagram illustrating an example neuromorphic processor, according to at least one embodiment;

[0052] FIG. 27 illustrates at least portions of a graphics processor, according to one or more embodiments;

[0053] FIG. 28 illustrates at least portions of a graphics processor, according to one or more embodiments;

[0054] FIG. 29 illustrates at least portions of a graphics processor, according to one or more embodiments;

[0055] FIG. 30 is a block diagram of a graphics processing engine of a graphics processor in accordance with at least one embodiment; 16 05 23

[0056] FIG. 31 is a block diagram of at least portions of a graphics processor core, according to at least one embodiment;

[0057] FIGS. 32A and 32B illustrate thread execution logic including an array of processing elements of a graphics processor core according to at least one embodiment;

[0058] FIG. 33 illustrates a parallel processing unit (“PPU”), according to at least one embodiment;

[0059] FIG. 34 illustrates a general processing cluster (“GPC”), according to at least one embodiment;

[0060] FIG. 35 illustrates a memory partition unit of a parallel processing unit (“PPU”), according to at least one embodiment; [0061 ] FIG. 36 illustrates a streaming multi-processor, according to at least one embodiment.

[0062] FIG. 37 is an example data flow diagram for an advanced computing pipeline, in accordance with at least one embodiment;

[0063] FIG. 38 is a system diagram for an example system for training, adapting, instantiating and deploying machine learning models in an advanced computing pipeline, in accordance with at least one embodiment;

[0064] FIG. 39 includes an example illustration of an advanced computing pipeline 3810A for processing imaging data, in accordance with at least one embodiment;

[0065] FIG. 40A includes an example data flow diagram of a virtual instrument supporting an ultrasound device, in accordance with at least one embodiment;

[0066] FIG. 40B includes an example data flow diagram of a virtual instrument supporting an CT scanner, in accordance with at least one embodiment;

[0067] FIG. 41A illustrates a data flow diagram for a process to train a machine learning model, in accordance with at least one embodiment; and

[0068] FIG. 4IB is an example illustration of a client-server architecture to enhance annotation tools with pre-trained annotation models, in accordance with at least one embodiment. 16 05 23 DETAILED DESCRIPTION [0069 ] In at least one embodiment, training neural networks to perform segmentation related tasks, such as instance segmentation and semantic segmentation, often requires complex training data comprising images in which every pixel is labeled, both according to which object type it belongs and according to which portion of an object it belongs. In at least one embodiment, training data for object detection tasks often comprises images with associated bounding box annotations that indicate locations of objects in images and classifications of objects. In at least one embodiment, a framework for object detection, instance segmentation, and semantic correspondence comprises one or more neural networks that are trained to perform object detection, instance segmentation, and semantic correspondence with training data comprising bounding box annotations.

[0070] In at least one embodiment, a framework jointly learns to perform object detection, instance segmentation, and semantic correspondence with bounding-boxes and self-supervision. In at least one embodiment, a framework for object detection, instance segmentation, and semantic correspondence is weakly supervised since it does not require object masks and semantic correspondence labels during training. In at least one embodiment, a framework for object detection, instance segmentation, and semantic correspondence comprises at least three task learning heads supervised by detection and several self-supervisions. In at least one embodiment, a framework for object detection, instance segmentation, and semantic correspondence utilizes box-supervised detection and supervises instance segmentation with a teacher-student self-distillation guided by multiple instance learning and conditional random fields (CRFs).

[0071] In at least one embodiment, a framework for object detection, instance segmentation, and semantic correspondence leverages multi-view self-supervision by coupling instance segmentation with semantic correspondence, and formulates it as contrastive learning under optimal transport and solves it with a differentiable Hungarian algorithm. In at least one embodiment, this enables two tasks (e.g., instance segmentation and semantic correspondence) to mutually improve each other, which then enables semantic correspondence in cases with multi-object scenarios. In at least one embodiment, a framework for object detection, instance 16 05 23 segmentation, and semantic correspondence is real-time and achieves efficient weakly supervised instance segmentation performance on various datasets.

[0072] In at least one embodiment, techniques described herein achieve various technical advantages, including but not limited to: an ability to train one or more neural networks to simultaneously predict bounding boxes, instance segmentation masks and cross-instance semantic correspondences while only requiring box supervision during training; an ability to couple instance segmentation and semantic correspondence learning in a weakly supervised and multitasking manner; an ability to efficiently and accurately perform instance segmentation and semantic correspondence based on bounding box annotations; an ability to leverage multi-view self-supervision by modeling inter-image feature correlations using a differentiable Hungarian algorithm; and various other technical advantages. [0073 ] FIG. 1 illustrates an example 100 of a framework for object detection, instance segmentation, and semantic correspondence, according to at least one embodiment. In at least one embodiment, example 100 includes at least a first image 102 and a second image 104 that are input to a framework 106 for object detection, instance segmentation, and semantic correspondence (e.g., also referred to herein as a Disco-Box framework), which performs object detection 108, instance segmentation 110, and semantic correspondence 112 for input images 102, 104. In at least one embodiment, a second image 104 includes one or more instances of a same object that is also present in a first image 102. In at least one embodiment, a processor comprises one or more circuits to use one or more neural networks to segment one or more objects of one or more images 102, 104 based, at least in part, on one or more bounding boxes identified by said one or more neural networks. In at least one embodiment, said processor performs such operations as described in FIG. 2, which shows one or more training processes for a framework 106 for object detection 108, instance segmentation 110, and semantic correspondence 112.

[0074] In at least one embodiment, a first image 102 and / or a second image 104 are images captured from one or more images and / or video capturing devices, such as one or more systems of a vehicle (e.g., autonomous vehicle, semi-autonomous vehicle) or other imaging system (e.g., robotic device, grasping device, medical imaging device, satellite imaging system). In at least one embodiment, a first image 102 and / or a second image 104 are computer image files of any 16 05 23 suitable format, such as a bitmap image file format. In at least one embodiment, a first image 102 and / or a second image 104 are in compressed or uncompressed form. In at least one embodiment, a first image 102 and / or a second image 104 are red-green-blue (RGB) images. In at least one embodiment, a first image 102 and / or a second image 104 are black-and-white (BW) images. In at least one embodiment, a first image 102 and / or a second image 104 are grayscale images.

[0075] In at least one embodiment, a first image 102 and / or a second image 104 are images depicting one or more objects. In at least one embodiment, a first image 102 depicts a car object. In at least one embodiment, a second image 104 depicts two car objects where a first car object overlaps a second car object. In at least one embodiment, a first image 102 and / or a second image 104 are obtained or otherwise received by a framework 106. In at least one embodiment, a first image 102 and / or a second image 104 are provided to a framework 106 from one or more systems through one or more communication networks, data transfer operations, and / or variations thereof. [007€>] In at least one embodiment, a framework 106 is a unified neural network framework for object detection 108, instance segmentation 110, and semantic correspondence 112. In at least one embodiment, a framework 106 is a collection of one or more hardware and / or software computing resources with instructions that, when executed, performs one or more processes of one or more neural networks. In at least one embodiment, a framework 106 is a software program executing on computer hardware, application executing on computer hardware, and / or variations thereof. In at least one embodiment, a framework 106 comprises various neural network models such as a perceptron model, a radial basis network (RBN), an auto encoder (AE), Boltzmann Machine (BM), Restricted Boltzmann Machine (RBM), deep belief network (DBN), deep convolutional network (DCN), extreme learning machine (ELM), deep residual network (DRN), support vector machines (SVM), and / or variations thereof. In at least one embodiment, a framework 106 performs at least processes such as object detection 108, instance segmentation 110, and semantic correspondence 112. In at least one embodiment, a framework 106 is trained using bounding box annotations, also referred to as ground truth bounding boxes, and one or more loss functions. In at least one embodiment, a framework 106 comprises three branches: a detection head (e g., object detection 108), a segmentation head 16 05 23 (e.g., instance segmentation 110), and a correspondence head (e.g., semantic correspondence 112). Further information regarding performing object detection 108, instance segmentation 110, and semantic correspondence 112 using a framework 106 can be found in connection with FIG. 2.

[0077] In at least one embodiment, a framework 106 for object detection 108, instance segmentation 110, and semantic correspondence 112 comprises a student neural network and a teacher neural network (not depicted in FIG. 1, but is described in more detail in FIG. 2), and is trained using training data comprising images 102, 104 and associated bounding box annotations. In at least one embodiment, a student network is referred to as a first neural network from a plurality of neural networks and a teacher neural network is referred to as a second neural network from a plurality of neural networks. In at least one embodiment, a teacher network obtains and processes training images 102, 104 by determining features of said training images 102, 104. In at least one embodiment, a teacher network processes determined features to perform instance segmentation 110, in which said teacher network generates masks, also referred to as instance proposals, indicating pixels of objects of training images 102, 104 to determine instances of said objects (e.g., car objects) in training images 102, 104. In at least one embodiment, a teacher network applies one or more smoothing operations to generated masks.

[0078] In at least one embodiment, a student network obtains and processes training images 102, 104 by determining features of said training images 102, 104. In at least one embodiment, a student network processes determined features to perform object detection 108, in which said student network generates box proposals indicating potential locations of objects of training images 102, 104 and classifications of said objects. In at least one embodiment, a student network processes determined features to perform instance segmentation 110, in which said student network generates masks indicating pixels of objects of training images 102, 104 to determine instances of said objects in training images. In at least one embodiment, a student network processes determined features to perform semantic segmentation, in which said student network generates one or more segmentation maps indicating pixels of objects of training images 102, 104.

[0079] In at least one embodiment, one or more systems of a framework 106 for object detection 108, instance segmentation 110, and semantic correspondence 112 perform semantic 16 05 23 correspondence 112 based on features and instance proposals output from a teacher network and / or a student network, and box proposals output from said student network to determine correspondence between objects of images 102, 104. In at least one embodiment, one or more systems of a framework 106 calculate loss by comparing outputs of a student network with outputs of a teacher network. In at least one embodiment, one or more systems of a framework 106 calculate loss by comparing outputs of a student network with training data 102, 104. In at least one embodiment, one or more systems of a framework 106 update one or more parameters of a student network such that loss is minimized.

[0080] In at least one embodiment, a framework 106 for object detection 108, instance segmentation 110, and semantic correspondence 112 formulates instance segmentation learning as a teacher-student self-distillation problem where a teacher is guided by multiple instance learning and CRF smoothing. In at least one embodiment, boxes contain rich information about object masks as they tightly enclose objects. In at least one embodiment, for a framework 106 for object detection 108, instance segmentation 110, and semantic correspondence 112, foreground / background localization naturally emerges as network attention under box supervision. In at least one embodiment, CRF can promote inductive bias on contrast-sensitive smoothness. In at least one embodiment, for a framework 106 for object detection 108, instance segmentation 110, and semantic correspondence 112, self-training / distillation with pseudo-labels can considerably benefit weakly and semi-supervised learning tasks.

[0081] In at least one embodiment, a framework 106 for object detection 108, instance segmentation 110, and semantic correspondence 112 considers multi-view self-supervision across different images 102, 104. In at least one embodiment, a framework 106 utilizes a contrastive learning framework in which pair-wise foreground features are matched from two images 102, 104 if they correspond to a same object part, and not matched otherwise. In at least one embodiment, a framework 106 formulates semantic correspondence 112 as an optimal transport problem where pairs are found by jointly minimizing a matching cost via a differentiable Hungarian algorithm. In at least one embodiment, framework 106 improves a quality of instance segmentation and can handle highly multi-object scenarios.

[0082] In at least one embodiment, object detection 108 refers to one or more processes that detect and / or classify objects in images. In at least one embodiment, object detection 108 refers 16 05 23 to one or more processes that generate bounding boxes that indicate potential locations of objects depicted in an image and classifications of said objects. In at least one embodiment, for object detection 108, a framework 106 obtains and processes an image (e.g., a first image 102 and / or a second image 104) to generate bounding box proposals that indicate potential locations and classifications of objects depicted in said image. In at least one embodiment, a framework 106 extracts features of an image 102, 104, and analyzes extracted features through one or more convolution processes, activation function processes, pooling processes, and / or other neural network processes to determine a potential location and classification of an object of said image 102, 104. In at least one embodiment, referring to FIG. 1, object detection 108 comprises one or more processes that generate a bounding box indicating a location of a car object depicted in a first image 102.

[0083] In at least one embodiment, instance segmentation 110 refers to one or more processes that detect objects and identify instances of said objects in images. In at least one embodiment, instance segmentation 110 refers to one or more processes that generate one or more masks that indicate pixels that belong to one or more objects of an image, and determine instances of said one or more objects in said image (e.g., by determining which pixels of said image correspond to instances of said one or more objects). In at least one embodiment, for instance segmentation 110, a framework 106 obtains and processes an image (e.g., a first image 102 and / or a second image 104) to generate masks that indicate pixels corresponding to a class of object depicted in said image, and determine instances of said object in said image. In at least one embodiment, a framework 106 extracts features of an image 102, 104, processes said features to determine objects of said image 102, 104, and generates masks corresponding to said objects. In at least one embodiment, referring to FIG. 1, instance segmentation 110 comprises one or more processes that generate a mask indicating pixels corresponding to a car object depicted in a first image 102, and determine instances of a car object depicted in first image 102.

[0084] In at least one embodiment, semantic correspondence 112 refers to one or more processes that determine regions of images 102, 104 that are semantically related. In at least one embodiment, regions of images 102, 104 that are semantically related refer to regions of images that belong to a same class of object, such as car, person, plant, and / or variations thereof. In at least one embodiment, semantic correspondence 112 refers to one or more processes that 16 05 23 determine correspondence between pixels or sets of pixels of images 102, 104 (e.g., pixels or sets of pixels that are semantically related) by extracting and comparing features of said images 102, 104. In at least one embodiment, for semantic correspondence 112, a framework 106 obtains and processes one or more images (e.g., image 102 and / or image 104) to determine correspondence between objects of said one or more images 102, 104 (e.g., determining if one or more objects of a first image are depicted in a second image). In at least one embodiment, a framework 106 extracts features of an image, identifies objects of said image by analyzing said features, and compares identified objects from said image with other identified objects of other images to determine correspondence between objects of said image and said other images. In at least one embodiment, referring to FIG. 1, semantic correspondence 112 comprises one or more processes that determine correspondence between a car object depicted in a first image 102 and a first car object and a second car object depicted in a second image 104. In at least one embodiment, referring to FIG. 1, semantic correspondence 112 comprises one or more processes that determine correspondence between a first car object and / or a second car object depicted in a second image 104 and a car object depicted in a first image 102.

[0085] FIG. 2 illustrates an example 200 of a detailed overview of a framework for object detection, instance segmentation, and semantic correspondence, according to at least one embodiment. In at least one embodiment, example 200 illustrates one or more training processes for a framework for object detection, instance segmentation, and semantic correspondence. In at least one embodiment, a framework for object detection, instance segmentation, and semantic correspondence comprises a teacher network 204 and a student network 206, and one or more systems not depicted in FIG. 2 that include executable code that, when executed, performs various processes in connection with teacher network 204 and / or student network 206 such as calculating loss, updating parameters, optimization, and / or other neural network processes. In at least one embodiment, teacher network 204 is a supervised neural network, an unsupervised neural network, a partially supervised neural network, or semi-supervised neural network. In at least one embodiment, student network 206 is a supervised neural network, an unsupervised neural network, a partially supervised neural network, or semi-supervised neural network.

[0086] In at least one embodiment, for a framework for object detection, instance segmentation, and semantic correspondence, an input image is denoted by I (e.g., input 16 05 23 images 202), deep features are denoted by F (e.g., features determined by a feature pyramid 206B and / or a feature pyramid 204B), bounding box proposals are denoted by O (e.g., box proposals 206D), and instance segmentation proposals are denoted by M (e.g., masks 208 and / or masks 210). In at least one embodiment, input images 202 are images in accordance with those described in connection with FIG. 1. In at least one embodiment, input images 202 are images of a set of training data. In at least one embodiment, input images 202 are associated with bounding box annotations that indicate locations of objects of input images 202 and classifications of said objects of input images 202. In at least one embodiment, a bounding box annotation comprises one or more indications of a location (e.g., coordinates, borders) of an object of an image and a classification (e.g., category) of said object of said image. [0087 ] In at least one embodiment, input images 202 and associated bounding box annotations are obtained or otherwise received by a teacher network 204 and a student network 206. In at least one embodiment, a teacher network 204 is one or more neural networks that perform object detection, instance segmentation, and semantic correspondence processes. In at least one embodiment, a student network 206 is one or more neural networks that perform object detection, instance segmentation, and semantic correspondence processes. In at least one embodiment, a neural network (e.g., a teacher network 204 and / or a student network 206) is implemented through one or more data structures, such as one or more arrays, lists, and / or trees, that encode weights, biases, and structural connections (e.g., architecture(s) and / or configuration(s) of one or more neurons) of said neural network.

[0088] In at least one embodiment, input images 202 are input to a feature backbone 206A. In at least one embodiment, a feature backbone 206A is one or more neural networks that extract features from input data (e.g., images). In at least one embodiment, a feature backbone 206A is a feature extracting neural network. In at least one embodiment, a feature backbone 206A is a convolutional neural network that extracts features from images through one or more convolution operations. In at least one embodiment, one or more features determined by a feature backbone 206A are input to a feature pyramid 206B. In at least one embodiment, a feature pyramid 206B is part of one or more neural networks that determine feature maps. In at least one embodiment, one or more systems, in connection with a feature pyramid 206B, combine 16 05 23 low-resolution, semantically strong features with high resolution, semantically weak features through one or more pathways and lateral connections to determine one or more feature maps.

[0089] In at least one embodiment, a feature pyramid 206B comprises one or more feature maps that indicate one or more features of input images 202. In at least one embodiment, a feature pyramid 206B augments a convolutional network (e.g., a feature backbone 206A) with a top-down pathway and lateral connections to construct one or more multi-scale feature maps from input images 202. In at least one embodiment, feature maps comprise indications of one or more features of input images 202, such as particular features (e.g., edges, corners), particular colors (e.g., red, blue, green), and / or variations thereof. In at least one embodiment, a feature pyramid 206B comprises one or more feature maps indicating features of objects of input images 202. 10090 ] In at least one embodiment, features of a feature pyramid 206B are input to a prediction head 206C. In at least one embodiment, a prediction head 206C comprises one or more neural networks that determine bounding box proposals indicating potential locations of objects in one or more images (e.g., input images 202). In at least one embodiment, a prediction head 206C obtains features (e.g., feature maps) from a feature pyramid 206B and generates box proposals 206D, which comprise bounding box proposals indicating potential locations of objects of input images 202 and predicted classifications of said objects of said bounding box proposals. In at least one embodiment, a prediction head 206C comprises one or more regression processes and one or more classification processes, in which said one or more regression processes predict relative offsets between pre-defined bounding boxes (e.g., anchor bounding boxes) and predicted boxes, and said one or more classification processes estimate classifications of objects of said predicted boxes. In at least one embodiment, a prediction head 206C is implemented with one or more classes or categories of objects (e.g., person, vehicle, plant, road, and / or any suitable objects), in which prediction head 206C classifies objects as belonging to said one or more classes or categories. In at least one embodiment, box proposals 206D are utilized by one or more systems to calculate a loss function such as a detection loss, denoted by £det> by determining differences between bounding box annotations associated with input images 202 and box proposals 206D. 16 05 23 [0091 ] In at least one embodiment, a prediction head 206C comprises a coefficient network, which is one or more neural networks that generate mask coefficients 206E. In at least one embodiment, mask coefficients 206E comprise linear combination weights that are utilized to determine how to combine mask prototypes 206G to form a final mask. In at least one embodiment, a mask coefficient is determined for each mask prototype. In at least one embodiment, features from a feature pyramid 206B are input to a prototype network 206F, which is one or more neural networks that generate mask prototypes for one or more objects of one or more images. In at least one embodiment, a mask prototype refers to a potential mask for an object in an image. In at least one embodiment, a mask for a particular object in an image indicates which pixels of said image belong to said particular object.

[0092] In at least one embodiment, a prototype network 206F generates mask prototypes, also referred to as foreground prototypes, denoted by P G j^dxhxiv for pjxe] where D, H, W represent a number of prototypes, a height and a width of segmentation, respectively. In at least one embodiment, a coefficient net produces query feature Q G BWxD for each box candidate (e.g., proposal), where N, D represent a number of box candidates and weights for prototypes, respectively. In at least one embodiment, an inner product is applied (e.g., depicted in FIG. 2 as a circle comprising an icon “X”) between a first dimension of foreground prototypes P and a second dimension of query feature Q to determine final masks, denoted by M G (0, for object candidates. In at least one embodiment, final masks are cropped based at least in part on determined box proposals 206D and / or bounding box annotations to determine masks 208. In at least one embodiment, masks of objects are cropped with corresponding bounding boxes (e.g., bounding box proposals and / or bounding box annotations) of said objects. In at least one embodiment, for a particular mask and corresponding bounding box, said particular mask is cropped such that it comprises an area or region indicated by said corresponding bounding box. In at last one embodiment, cropping is performed on feature maps from feature pyramid 206B so that features maps are used for every corresponding bounding box to result in masks 208.

[0093] In at least one embodiment, masks 208, also referred to as instance proposals, instance segmentation proposals, and / or variations thereof, indicate masks of objects of input images 202. In at least one embodiment, masks 208 comprise indications of which pixels of input images 202 belong to which objects of input images 202. In at least one embodiment, masks 208 indicate 16 05 23 which pixels of input images 202 correspond to instances of objects of particular classes. In at least one embodiment, for an input image depicting two instances of a car object, denoted by a first car object and a second car object, masks 208 indicate a first set of pixels corresponding to said first car object and a second set of pixels corresponding to said second car object. In at least one embodiment, a multiple instance learning loss is utilized to train a student network 206 for segmentation.

[0094] In at least one embodiment, one or more systems determine positive and negative stripes (e.g., bags) for boxes indicated by box proposals 206D. In at least one embodiment, a bag is defined as a narrow stripe of pixels with a horizontal shape of [1, w] and / or a vertical shape of [h, 1], In at least one embodiment, a bag is determined as positive or negative by whether it overlaps foreground pixels, in which a positive bag overlaps with foreground pixels and a negative bag does not overlap with foreground pixels. In at least one embodiment, foreground pixels refer to one or more pixels of one or more objects of an image. In at least one embodiment, one or more systems enumerate all negative stripes starting at a left and ending at a right of an image as well as stripes starting at a top and ending at a bottom to learn different kinds of background segmentation for one or more networks (e.g., a student network 206).

[0095] In at least one embodiment, bags used for calculating loss is described in more detail with respect to FIG. 3, which illustrates an example 300 of multiple instance learning where stripes of pixels are used for calculating loss, according to at least one embodiment. In at least one embodiment, an image 302 and a box proposal 304 are in accordance with those described in connection with FIG. 2. In at least one embodiment, an image 302 depicts a first object and a bounding box proposal indicating a location of said first object in image 302. In at least one embodiment, an image 302 is processed by a student network 206 and / or a teacher network 204 to determine bounding box proposals for objects of image 302. In at least one embodiment, a box proposal 304 is a bounding box proposal for an object of an image 302. In at least one embodiment, an image 302 depicts a car object, in which a bounding box proposal is determined for image 302 that indicates a location of said car object and box proposal 304 corresponds to said bounding box proposal. [()096] In at least one embodiment, example 300 depicts positive bags with a first dashed line pattern and negative bags with a second dashed line pattern. In at least one embodiment, an 16 05 23 image 302 comprises a first negative bag indicating a first region of image 302 that does not comprise a detected object of image 302, and a second negative bag indicating a second region of image 302 that does not comprise a detected object of image 302. In at least one embodiment, a box proposal 304 comprises a first positive bag indicating a first region of box proposal 304 that comprises an object of box proposal 304, a second positive bag indicating a second region of box proposal 304 that comprises an object of box proposal 304, a third positive bag indicating a third region of box proposal 304 that comprises an object of box proposal 304, and a fourth negative bag indicating a fourth region of box proposal 304 that does not comprise an object of box proposal 304.

[0097] In at least one embodiment, positive bags and negative bags are utilized to determine multiple instance learning loss. In at least one embodiment, a loss function such as multiple instance learning loss is used to train one or more neural networks based on positive and negative bags (e.g., stripes of pixels) and one or more masks. In at least one embodiment, one or more systems utilize max pooling to summarize activations in each bag and a sigmoid cross-entropy loss. In at least one embodiment, multiple instance learning loss, denoted by Lmu, is defined by a following equation, although any variation thereof can be utilized: = -^^1 log(Pi) + (1- y;)log (1 - Pi) i m which pj = maxjebag. (cr(M7)), a is a sigmoid function, M denotes instance segmentation proposals, yt = 0 if bagt is negative and = 1 if bagt is positive.

[0098] In at least one embodiment, features from a feature pyramid 206B are input to a semantic segmentation head 206H. In at least one embodiment, a semantic segmentation head 206H is one or more neural networks that perform semantic segmentation. In at least one embodiment, semantic segmentation refers to one or more processes that classify pixels of an image as belonging to one or more classes. In at least one embodiment, semantic segmentation head 206H determines semantic segmentation 2061, which comprises indications of classifications of pixels of input images 202. In at least one embodiment, semantic segmentation 2061 comprises one or more segmentation maps indicating segmentation values of pixels of input images 202. In at least one embodiment, a segmentation value of a pixel indicates 16 05 23 a prediction of a class or classification that an object corresponding to said pixel belongs to. In at least one embodiment, semantic segmentation 2061 is utilized in connection with bounding box annotations corresponding to input images 202 to calculate loss.

[0099] In at least one embodiment, an auxiliary softmax cross-entropy loss is calculated by one or more systems for a student network 206 to learn a rough semantic segmentation determined by regions indicated by boxes of bounding box annotations. In at least one embodiment, auxiliary softmax cross-entropy loss refers to loss that is based at least in part on one or more softmax functions and one or more cross-entropy loss functions. In at least one embodiment, a softmax function is a function that transforms a vector of real numbers of any suitable ranges of values into a different vector of real numbers of a range of (0, 1) that add up to a value of 1. In at least one embodiment, a cross-entropy loss function is a function that indicates a distance or difference between a predicted output distribution and a ground truth output distribution.

[0100] In at least one embodiment, an auxiliary softmax cross-entropy loss is used to learn more information of box annotations and is discarded during inference. In at least on embodiment, a loss function such as an auxiliary softmax cross-entropy loss is used to train one or more neural networks is based on one or more segmentation maps and information of bounding box annotations. In at least one embodiment, an auxiliary softmax cross-entropy loss, denoted by £ss, is defined by a following equation, although any variation thereof can be utilized: h w c =-»v it x r y y y nog +iog(i -n X W X C Z-u Z-u Z-u t = l j=i c=l in which H, IV, C represent height, width of segmentation map, and a number of categories, respectively, i / ms a softmax function, and if location (i,j) is covered by a bounding box of c-th category, Scij is assigned as 1, otherwise it is equals to 0.

[0101] In at least one embodiment, a teacher network 204 shares a same architecture as a student network 206, with an addition of a conditional random fields (CRF) module. In at least one embodiment, a teacher network 204 is initialized using same parameters as a student network 206. In at least one embodiment, a feature backbone 204A, a feature pyramid 204B, a 16 05 23 prediction head 204C, a mask coefficients 204E, a prototype network 204F, mask prototypes 204G, and one or more masks 210 of a teacher network 204 are same or similar as a feature backbone 206A, a feature pyramid 206B, a prediction head 206C, a mask coefficients 206E, a prototype network 206F, mask prototypes 206G, and masks 208, respectively, of a student network 206. In at least one embodiment, cropping is performed on feature maps from feature pyramid 204B so that features maps are used for every corresponding bounding box to result in one or more masks 210. In at least one embodiment, a CRF module refers to a collection of hardware and / or software computing resources with instructions that, when executed, performs one or more CRF operations. In at least one embodiment, a CRF module refers to a discriminative model / classifier for prediction that utilizes contextual information from previous labels to determine predictions. In at least one embodiment, CRF operations comprise defining a conditional probability distribution over label sequences for a particular observation sequence to determine predictions.

[0102] In at least one embodiment, a teacher network 204 and a student network 206 form a self-distillation framework to further improve segmentation quality. In at least one embodiment, a student network 206 is a learnable network that performs instance segmentation. In at least one embodiment, a teacher network 204 is a temporally-consistent network guided by one or more CRF modules to generate pseudo-labels from images to generate less noisy and sharper instance segmentation. In at least one embodiment, one or more systems apply one or more CRF operations to one or more masks output from a teacher network 204 to determine masks 212. In at least one embodiment, a student network 206 is caused by one or more systems to generate a same output as a teacher network 204. In at least one embodiment, one or more neural networks is trained using a loss function such as a distillation loss. In at least one embodiment, distillation loss is based on a first set of masks and a set of bounding boxes corresponding to one or more objects generated by student network 206 and a second sets of masks corresponding to one or more objects generated by teacher network 204. In at least one embodiment, teacher-student loss, also referred to as distillation loss, is defined through a following equation, although any variation thereof can be utilized: 16 05 23 i=l jEboxt in which N denotes a number of box proposals generated by a student network 206, / £ and fs denote a teacher network 204 and student network 206, respectively, ft (Mjj |l) denotes instance segmentation proposals output from teacher network 204 (e.g., masks 212), / ■’(Mj 7|l) denotes instance segmentation proposals output from student network 206 (e.g., masks 208), and box-, is a set of pixels regarding / -th object proposals. In at least one embodiment, an object proposal refers to an object of a bounding box indicated by bounding box proposal. In at least one embodiment, segmentation scores of a student network 206 are aligned with those of a teacher network 204 for all box proposals (e.g., box proposals 206D).

[0103] In at least one embodiment, parameters of a teacher network 204 are updated by one or more systems using an exponential moving average, which is defined by a following equation, although any variation thereof can be utilized: 3t e- mdt + (1- m)6s where 0t, 0s,m denote parameters of a teacher network 204, a student network 206, and momentum, respectively. In at least one embodiment, updating parameters through an exponential moving average improves a stability of a teacher network 204 and enforces an output more consistent between iterations.

[0104] In at least one embodiment, contrast sensitive smoothness is utilized as a prior in one or more segmentation processes. In at least one embodiment, a CRF is constructed and is defined by pixel affinity and local smoothness, in which initialization confidence is obtained from one or more neural networks. In at least one embodiment, one or more systems apply an efficient approximating solver algorithm, such as a mean-field algorithm, on a CRF, in which label agreement between similar pixels is maximized and local smoothness constraints are applied in a final segmentation. 16 05 23

[0105] In at least one embodiment, for a teacher network 204, a mean-field algorithm is applied by one or more systems to minimize energy of a CRF, and is defined by a following algorithm (referred to herein as Algorithm 1), although any variation thereof can be utilized: Algorithm X Mean field algorithm for fully connected CRFs of i-th segmentation proposals Mf. 1: procedure MeanField(M, i) 2: Xj «- ><pm is a threshold function. ~ iz (1} I Pi,;-Pi,k | , 3: K Jk w exp--L-— + \ / 4- w(2)PYnf IPm-P^I2 Ikj-FfcH 4. Wv J eXD I------;---I 1 V J 5: >Initialize Gaussian kernels 6: while not converge do >iterate until convergence 7: for j «- 1 to |XJ do 8: X; ,■ <- 0 9: forp( / < e MP.j) do >Convolution 10: Xu + Kijk*Xik I,J I,J I,J,A. I,A. 11: end for 12: end for 13: Xi <pm(Xd 14: end while 15: return Xt 16: end procedure

[0106] In at least one embodiment, referring to Algorithm 1, pjj denotes a j-th position of an i-th segmentation proposal, Ijj denotes normalized color values (e.g., red, green, blue) of a j-th position of an i-th segmentation proposal. In at least one embodiment, referring to Algorithm 1, one or more systems define N(Pij) as neighbors of a j-th position of an i-th segmentation proposal. In at least one embodiment, referring to Algorithm 1, one or more systems define neighbors of a 3x 3 square space and implement an iteration by a convolution with a 3x 3 kernel. In at least one embodiment, referring to Algorithm 1, (pm denotes a threshold function and is defined as (pm(x) = 11(% >0.5) * 0.1 + 0.45, or any variation thereof. In at least one 16 05 23 embodiment, referring to Algorithm 1, one or more systems define nA1), qa, as 0.2, 1.0, 0.5, 30, 30, 0.5, respectively, in which values can be any suitable values.

[0107] In at least one embodiment, for a teacher network 204 and / or a student network 206, one or more systems build a random field on an image (e.g., input images 202), denoted by I, and a random field on instance segmentation, denoted by M, where Q = (V, S) is a graph on M and each clique in a set of cliques in Q includes a potentials <PC. In at least one embodiment, a maximum a posteriori (MAP) labeling of a random field is denoted by M* = arg maxMG,01 'iv P(M|I). In at least one embodiment, t(M) is utilized by one or more systems to denote 0(M11). In at least one embodiment, unary and pair-wise cliques are considered in a fully connected CRF model and Gibbs energy is defined through a following equation, although any variation thereof can be utilized: E(M) = in which t, represents unary confidence produced by one or more neural networks and fc) denotes pairwise potentials.

[0108] In at least one embodiment, for a teacher network 204 and / or a student network 206, smoothness and appearance constraints are utilized in pairwise energy, denoted by following equations, although any variation thereof can be utilized: = w'^exp + w® exp(JP‘-> ~P2<^ zSy2 in which pt denotes a position of an z-th pixel. In at least one embodiment, pairwise energy is minimized through one or more mean-field algorithms.

[0109] In at least one embodiment, for semantic correspondence via a teacher network 204 and / or a student network 206, deep features, denoted by F (e.g., features determined by a feature pyramid 206B and / or a feature pyramid 204B), bounding box proposals, denoted by O (e.g., box proposals 206D), and associated instance proposals, denoted by M (e.g., masks 208 and / or masks 210) are utilized. In at least one embodiment, a first-in-first-out (FIFO) object queue is maintained to store deep feature maps of each object (e.g., objects of input images 202). In at 16 05 23 least one embodiment, one or more systems determine most similar objects in a FIFO object queue for each object proposal of a current image. In at least one embodiment, for pushing an object into a queue, a teacher network 204 / student network 206 architecture as described herein is utilized. In at least one embodiment, a teacher network 204 generates consistent features of objects for one or more semantic correspondence processes. In at least one embodiment, after pushing objects, out-of-date objects are removed when a size of a queue exceeds an upper limit. In at least one embodiment, one or more systems perform dense correspondence between a retrieved object and object proposals. In at least one embodiment, a system performs dense correspondence for an object (e.g., an object indicated by an object proposal) to identify instances of said object in one or more images (e.g., input images 202) through one or more algorithms such as Algorithm 2 and Algorithm 3 as described in connection with FIG. 4.

[0110] In at least one embodiment, semantic correspondence is formulated as an optimal transport problem. In at least one embodiment, optimal transport loss establishes correspondence between two intra-class objects and aligns features between corresponding keypoints. FIG. 4 illustrates an example 400 of optimal transport used to improve accuracy of semantic correspondence and instance segmentation, according to at least one embodiment. In at least one embodiment, optimal transport is utilized to improve accuracy of semantic correspondence, and improve instance segmentation by enhancing deep features (e.g., features 406 and / or features 408). In at least one embodiment, In at least one embodiment, optimal transport energy is defined through a following equation, although any variation thereof can be utilized: sup Eot “ g [Q l]LaxLb ^CT|Oa, ®b> ^a> s- t- Tlta — ^a> — Pb in which 0 denotes parameters of network (e.g., a teacher network 204 and / or a student network 206), Oa and Ob denote an object in a first image (e.g., an image 402) and another corresponding object in a second image (e.g., an image 404), respectively, T denotes a one-to-one soft assignment, I)j denotes a matching score between an i-th location in Oa and j-th location in Oy, La, Lb denote a number of locations in a first image and a second image, respectively, and [ia, p.b denote importance of all locations in a first image and a second image, respectively. In at least one embodiment, P(T) is denoted by a following equation, although any variation thereof can be utilized: P(T) = P(T|Oa, Ob, Ia, Ib; 0). 16 05 23

[0111] In at least one embodiment, for optimal transport loss, a pairwise smoothness regularization term is incorporated in an optimal transportation problem in addition to feature similarity. In at least one embodiment, one or more systems minimize P by considering appearance cost Cu and geometric consistency cost Cg through a following equation, although any variation thereof can be utilized: P(T)«^TU(CUO + C^ ij in which Tig denotes a soft assignment scores of correspondence between an i-th location in Oa and a j-th location in Ob In at least one embodiment, appearance cost is defined through a following equation, although any variation thereof can be utilized: F.a • IF; HF,-| in which F“ and Fy’ denote a feature of i-th location in Oa and j-th location in Ofe, respectively. In at least one embodiment, geometric consistency cost is defined through a following equation, although any variation thereof can be utilized: keoa,ieob in which off;j represents a relative spatial offset between i-location in On and j-location in Ob

[0112] In at least one embodiment, smoothness constraints are applied to pairwise offsets such that correspondence can be made smooth. In at least one embodiment, an iterated conditional mode where T is optimized iteratively is approximated by a system such as an optimal transport solver 412 through following equations, although any variations thereof can be utilized: Fa-F6 1. Initialize: Cu <---—,-, C° <-Cu(i,n U |Fa| |Fb| UV 2. Assign: <- exp( , Tf «- HfT) * ,J T.keob^{-Ct{i,k^ V J 3. Update: £„.,exp = C„(l.j) + C^i.^ in which Jf denotes a differentiable Hungarian algorithm, such as a Sinkhom’s algorithm. In at least one embodiment, optimal transport loss is defined through a following equation, although any variation thereof can be utilized: 16 05 23 in which tfc = arg maxj Tkj. In at least one embodiment, hinge loss is utilized to prevent over-confidence correspondence from dominating loss.

[0113] In at least one embodiment, referring to FIG. 4, images 402 and 404 are images (e.g., input images 202) with corresponding masks (e.g., masks 208 and / or masks 210) that indicate instance segmentation of objects of images 402 and 404. In at least one embodiment, referring to FIG. 4, features 406 and 408 are features determined based on images 402 and 404, respectively, through one or more feature extraction processes (e.g., processes of a feature pyramid 206B and / or a feature pyramid 204B). In at least one embodiment, referring to FIG. 4, image 402 is associated with features 406 and image 404 is associated with features 408. In at least one embodiment, referring to FIG. 4, a cost volume 410A is initialized through one or more cosine distances between features 406 and features 408. In at least one embodiment, referring to FIG. 4, an optimal transport solver 412 is a collection of one or more software and / or hardware computing resources with instructions that, when executed, applies one or more algorithms to perform dense correspondence between objects. In at least one embodiment, referring to FIG. 4, an optimal transport solver 412 applies a differential Hungarian algorithm and pair-wise smoothness on a cost volume 410A to determine a cost volume 410B. In at least one embodiment, referring to FIG. 4, an optimal transport solver 412 iteratively applies a differential Hungarian algorithm and pairwise smoothness on a cost volume 410B. [0114 ] In at least one embodiment, an optimal transport solver 412 considers constraints such as a one-to-one constraint and a smoothness constraint. In at least one embodiment, an optimal 16 05 23 transport solver 412 performs one or more processes of a following algorithm (referred to herein as Algorithm 2), although any variation thereof can be utilized: Algorithm 2 Optimal Transport Solver. procedure MEANFlELD(Fa, Fd, Ma, Mb) «- Vb <- Cu , F«-Fb |Fa||F»| C° «- CM o Initialization t 0 while not converge and t <tmax do for i <- 1 to |Fa | do for j «- 1 to |F& | do *. exp C; 1 • ■ — -----------7— l,J Zkeob exp (-qfc) o Normalization end for end for Tf = (T, pa, p.b~) >Diff. Hungarian Alg t> (Sinkhorn’s Algorithm) for i«- to |Fa| do forj Ito |Fb| do > Smoothness Ch1 = CH- + Cf.. '■’J C,J 1 / ] > Update scores end for end for end while return Cf end procedure 16 05 23

[0115] In at least one embodiment, referring to Algorithm 2, for two objects of images (e.g., image 402 and / or image 404) denoted by an object a and an object b, respectively, Fa, F6, Ma, and denote a feature map of object a, a feature map of object b, a segmentation of object a, and a segmentation of object b, respectively, and <p° denotes a threshold function. In at least one embodiment, referring to Algorithm 2, cp° is defined as ^°(%) = l(x >0.5) * 0.4 + 0.6, although any variation thereof can be utilized. In at least one embodiment, referring to Algorithm 2, a Sinkhorn’s Algorithm is utilized to approximate one-to-one assignment (e.g., Tf) between objects of images. In at least one embodiment, one or more processes of Algorithm 2 are performed for object proposals corresponding to objects of image 402 and / or image 404 to determine instances of said objects depicted in one or more images (e.g., image 402 and / or image 404). In at least one embodiment, a Sinkhorn’s Algorithm is defined by a following algorithm (referred to herein as Algorithm 3), although any variation thereof can be utilized: Algorithm 3 Sinkhorn’s Algorithm procedure H (T, ^ft) K = exp (— |) 6^1 t <- 0 while t <tmax and not converge do Ma a = — Kb b _ Mh KTa end while R = diag^a^KdiagOj) return R end procedure

[0116] In at least one embodiment, joint training loss is defined through a following equation, although any variation thereof can be utilized: £ ^det "f + ^ss^ss 4" ^ts^ts + ^ot^ot 16 05 23 in which £det denotes detection loss, amtt denotes multiple instance learning loss weight, £mii denotes multiple instance learning loss, ass denotes auxiliary softmax cross-entropy loss weight, £ss denotes auxiliary softmax cross-entropy loss, ats denotes teacher-student loss weight, £ts denotes teacher-student loss, aot denotes optimal transport loss weight, and £ot denotes optimal transport loss.

[0117] In at least one embodiment, one or more systems, in connection with a teacher network 204 and / or a student network 206, utilize stochastic gradient descent (SGD) for optimization and an initial learning rate of 1X 10~3, although any suitable optimization algorithms and / or learning rates can be utilized. In at least one embodiment, loss weights are set to amii = 10, ass = 1, ats = 2, aot = 10, although values can be any suitable values. In at least one embodiment, for correspondence learning, a size of an FIFO object queue is 40, although can be any suitable value. In at least one embodiment, joint training loss is utilized to update one or more configurations of a student network 206, a teacher network 204, and / or associated systems.

[0118] In at least one embodiment, one or more systems update weights, biases, components, structural configurations, and / or variations thereof of a student network 206 and / or a teacher network 204 based on calculated joint training loss such that joint training loss is minimized. In at least one embodiment, one or more systems update weights, biases, components, structural configurations, and / or variations thereof of a student network 206 and / or a teacher network 204 using one or more SGD operations, although any suitable optimization algorithm such as gradient descent, batch gradient descent, and / or variations thereof can be utilized. In at least one embodiment, SGD refers to one or more optimization algorithms that determine / update parameters of one or more models (e.g., a student network 206) to minimize loss. In at least one embodiment, SGD refers to a stochastic approximation of gradient descent optimization, in which a probabilistic approximation is utilized for gradients of a loss function with respect to input variables to determine / update parameters. In at least one embodiment, a student network 206 is updated by one or more systems until calculated loss is below a defined threshold, which can be any suitable value. [0119 ] FIG. 5 illustrates an example 500 of results using a framework for object detection, instance segmentation, and semantic correspondence, according to at least one embodiment. In at 16 05 23 least one embodiment, example 500 includes tables 502, 504, and 506, which indicate results for a framework for object detection, instance segmentation, and semantic correspondence. [0.120] In at least one embodiment, table 502 depicts results from a dataset such as a MS COCO validation 2017 dataset and a PASCAL VOC 2012 dataset. In at least one embodiment, referring to table 502, MNC denotes a multi-task network cascades method, FCIS denotes a fully convolutional instance-aware semantic segmentation method, Mask R-CNN denotes a mask regional convolutional neural network method, YOLACT denotes a You Only Look At the CoefficienTs method, YOLACT++ denotes a better You Only Look At the CoefficienTs method, WSIS-BBTP denotes a weakly supervised instance segmentation using a bounding box tightness prior method, WSIS-LACI denotes a weakly supervised instance segmentation by learning annotation consistent instances method, and Disco-Box denotes a framework for object detection, instance segmentation, and semantic correspondence method such as described in connection with FIGS. 1-4. In at least one embodiment, referring to table 502, AP2p5, APp0, APp0, and AP7p5 denote average precision values using intersection-over-union (loU) thresholds of 25%, 50%, 70%, and 75% on a dataset such as a PASCAL VOC 2012 dataset, respectively, and AP^ and AP^ denote overall average precision values, and APf0, and AP75 denote average precision values using loU thresholds of 50% and 75% on a dataset such as a MS COCO 2017 validation dataset, respectively. [01211 In at least one embodiment, table 504 depicts results of an ablation study on datasets such as a PASCAL VOC 2012 dataset and a MS COCO validation 2016 dataset. In at least one embodiment, referring to table 504, MIL, SS, TS, and OT denote multiple instance learning loss, semantic segmentation loss, teacher-student distillation loss, and optimal transport loss, respectively. In at least one embodiment, referring to table 504, APp denotes overall average precision, and APp0 and AP7p denote average precision values using loU thresholds of 50% and 70%, on a dataset such as a PASCAL VOC 2012 dataset, respectively, and AP^ denotes overall average precision, and AP5c0 and AP75 denote average precision values using loU thresholds of 50% and 75%, on a dataset such as a MS COCO 2017 validation dataset, respectively. 16 05 23

[0122] In at least one embodiment, table 506 depicts results from multi-object correspondence on a dataset such as PASCAL 3D dataset. In at least one embodiment, referring to table 506, Identity denotes an identity mapping baseline method, SCOT denotes a semantic correspondence as an optimal transport problem method, Disco-Box w / o ot denotes a framework for object detection, instance segmentation, and semantic correspondence without optimal transport loss method such as described in connection with FIGS. 1-4, and Disco-Box w / ot denotes a framework for object detection, instance segmentation, and semantic correspondence with optimal transport loss method such as described in connection with FIGS. 1-4. In at least one embodiment, referring to table 506, AP0 75, AP,. AP^, AP2, and AP3 denote average precision with thresholds of .75%, 1%, 1.5%, 2%, 3%, respectively, of object size. In at least one embodiment, mAP denotes a mean value of AP0 75, AP15 APX 5, AP2, and AP3.

[0123] FIG. 6 illustrates an example 600 of visualizations of results using a framework for object detection, instance segmentation, and semantic correspondence, according to at least one embodiment. In at least one embodiment, example 600 includes an instance segmentation visualization 602 and a multi-object correspondence visualization 604, which are results from one or more processes of a framework for object detection, instance segmentation, and semantic correspondence, also referred to as Disco-Box.

[0124] In at least one embodiment, an instance segmentation visualization 602 comprises a visualization of results of one or more instance segmentation processes such as those described in connection with FIG. 1-4. In at least one embodiment, instance segmentation refers to one or more processes that detect objects and identify instances of said objects in images. In at least one embodiment, referring to FIG. 6, an instance segmentation visualization 602 comprises visualizations of identified instances of objects within images (e.g., depicted by shaded regions and corresponding bounding boxes within images).

[0125] In at least one embodiment, a multi-object correspondence visualization 604 comprises a visualization of results of one or more multi-object correspondence processes. In at least one embodiment, a multi-object correspondence process refers to one or more semantic correspondence processes, such as those described in connection with FIGS. 1-4, that determine objects of images that correspond to each other (e.g., belong to a same class of object). In at least one embodiment, referring to FIG. 6, a multi-object correspondence visualization 604 comprises 16 05 23 visualizations of correspondence of objects (e.g., depicted by shaded regions and lines indicating correspondence between objects) between images (e.g., a top image and an associated bottom image).

[0126] FIG. 7 illustrates an example of a process 700 for a framework for object detection, instance segmentation, and semantic correspondence, according to at least one embodiment. In at least one embodiment, some or all of process 700 (or any other processes described herein, or variations and / or combinations thereof) is performed under control of one or more computer systems configured with computer-executable instructions and is implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) executing collectively on one or more processors, by hardware, software, or combinations thereof. In at least one embodiment, code is stored on a computer-readable storage medium in form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, a computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some computer-readable instructions usable to perform process 700 are not stored solely using transitory signals (e.g., a propagating transient electric or electromagnetic transmission). In at least one embodiment, a non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within transceivers of transitory signals. In at least one embodiment, process 700 is performed at least in part on a computer system such as those described elsewhere in this disclosure.

[0127] In at least one embodiment, process 700 comprises using supervised learning to train a student network to perform object detection (e.g., identification of bounding boxes around objects in images), then using bounding boxes to guide self-supervision for segmentation tasks. In at least one embodiment, bounding boxes are used to focus evaluation of a student network’s segmentation / correspondence performance on specific areas of an image (e.g., within a bounding box). In at least one embodiment, segmentation / correspondence performance is evaluated relative to a teacher network, where a teacher network is an average of previous versions of a student network. In at least one embodiment, as multiple rounds of training are performed, both bounding boxes and a teacher network improve, further focusing training until a student network is fully trained. 16 05 23

[0128] In at least one embodiment, a system performing at least a part of process 700 includes executable code to obtain 702 training data comprising two or more images. In at least one embodiment, training data comprises images depicting one or more objects and associated bounding box annotations. In at least one embodiment, a bounding box annotation comprises one or more indications of a location (e.g., coordinates, borders) of an object of an image and a classification (e.g., category) of said object of said image. In at least one embodiment, training data comprises images such as those captured from a view of an autonomous vehicle, such as an autonomous car, unmanned aerial vehicle (UAV), and / or variations thereof.

[0129] In at least one embodiment, a system performing at least a part of process 700 includes executable code to use 704 a student network to determine a bounding box for an object in two or more images, perform object detection on object, and determine whether additional instances of object are present in two or more images. In at least one embodiment, a student network comprises one or more processes that determine features for two or more images. In at least one embodiment, a student network processes determined features to generate a bounding box proposal indicating a potential location of an object in two or more images, and a classification indicating a potential classification of said object. In at least one embodiment, a student network generates one or more masks indicating pixels belonging to an object in two or more images. In at least one embodiment, a student network generates one or more segmentation maps indicating pixels belonging to one or more objects in two or more images In at least one embodiment, a student network processes a determined bounding box and mask for an object to determine whether additional instances of said object are present in two or more images. Further information regarding processes of a student network can be found in description of FIG. 2.

[0130] In at least one embodiment, a system performing at least a part of process 700 includes executable code to determine 706 detection loss and auxiliary loss based at least in part on a student network. In at least one embodiment, a system determines detection loss by determining differences between bounding box proposals generated by a student network and bounding box annotations of training data. In at least one embodiment, a system determines auxiliary loss, also referred to as auxiliary softmax cross-entropy loss, by analyzing segmentation maps generated by a student network and bounding box annotations of training data. 16 05 23 [0131 ] In at least one embodiment, a system performing at least a part of process 700 includes executable code to use 708 a teacher network to perform instance segmentation on objects in two or more images in connection with a conditional random field (CRF) smoothing technique. In at least one embodiment, a teacher network performs instance segmentation by generating one or more masks corresponding to objects in two or more images, and applying one or more CRF operations to said one or more masks. Further information regarding processes of a teacher network can be found in description of FIG. 2. [0132 ] In at least one embodiment, a system performing at least a part of process 700 includes executable code to determine 710 whether parts of object exist in two or more images based on outputs from a student network and a teacher network. In at least one embodiment, a system performs one or more semantic correspondence processes based at features, box proposals, and instance proposals output from a student network and / or a teacher network. In at least one embodiment, a first-in-first-out (FIFO) object queue is maintained to store deep feature maps of each object. In at least one embodiment, one or more systems determine most similar objects in a FIFO object queue for each object proposal (e.g., box proposal) of an image. [0133 ] In at least one embodiment, a system performing at least a part of process 700 includes executable code to update 712 a student network using output of a teacher network and one or more loss functions. In at least one embodiment, a system calculates loss based at least in part on a detection loss, multiple instance learning loss, auxiliary softmax cross-entropy loss, teacher-student loss, and optimal transport loss such as in accordance with those discussed in connection with FIG. 2. In at least one embodiment, a system minimizes calculated loss by updating one or more parameters of a student network through one or more SGD operations. In at least one embodiment, a system performs one or more processes of process 700 until calculated loss is below a defined threshold, which can indicate that a student network is trained. In at least one embodiment, one or more processes of process 700 are performed in any suitable order and in any suitable fashion, including sequential, parallel, and / or variations thereof. INFERENCE AND TRAINING LOGIC

[0134] FIG. 8A illustrates inference and / or training logic 815 used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are provided below in conjunction with FIGS. 8A and / or 8B. 16 05 23

[0135] In at least one embodiment, inference and / or training logic 815 may include, without limitation, code and / or data storage 801 to store forward and / or output weight and / or input / output data, and / or other parameters to configure neurons or layers of a neural network trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, training logic 815 may include, or be coupled to code and / or data storage 801 to store graph code or other software to control timing and / or order, in which weight and / or other parameter information is to be loaded to configure, logic, including integer and / or floating point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code, such as graph code, loads weight or other parameter information into processor ALUs based on an architecture of a neural network to which such code corresponds. In at least one embodiment, code and / or data storage 801 stores weight parameters and / or input / output data of each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inferencing using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 801 may be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory.

[0136] In at least one embodiment, any portion of code and / or data storage 801 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data storage 801 may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, a choice of whether code and / or code and / or data storage 801 is internal or external to a processor, for example, or comprising DRAM, SRAM, flash or some other storage type may depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors. [0137 ] In at least one embodiment, inference and / or training logic 815 may include, without limitation, a code and / or data storage 805 to store backward and / or output weight and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, code and / or data 16 05 23 storage 805 stores weight parameters and / or input / output data of each layer of a neural network trained or used in conjunction with one or more embodiments during backward propagation of input / output data and / or weight parameters during training and / or inferencing using aspects of one or more embodiments. In at least one embodiment, training logic 815 may include, or be coupled to code and / or data storage 805 to store graph code or other software to control timing and / or order, in which weight and / or other parameter information is to be loaded to configure, logic, including integer and / or floating point units (collectively, arithmetic logic units (ALUs)).

[0138] In at least one embodiment, code, such as graph code, causes the loading of weight or other parameter information into processor ALUs based on an architecture of a neural network to which such code corresponds. In at least one embodiment, any portion of code and / or data storage 805 may be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 805 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 805 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, a choice of whether code and / or data storage 805 is internal or external to a processor, for example, or comprising DRAM, SRAM, flash memory or some other storage type may depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors.

[0139] In at least one embodiment, code and / or data storage 801 and code and / or data storage 805 may be separate storage structures. In at least one embodiment, code and / or data storage 801 and code and / or data storage 805 may be a combined storage structure. In at least one embodiment, code and / or data storage 801 and code and / or data storage 805 may be partially combined and partially separate. In at least one embodiment, any portion of code and / or data storage 801 and code and / or data storage 805 may be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory.

[0140] In at least one embodiment, inference and / or training logic 815 may include, without limitation, one or more arithmetic logic unit(s) (“ALU(s)”) 810, including integer and / or floating point units, to perform logical and / or mathematical operations based, at least in part on, or 16 05 23 indicated by, training and / or inference code (e.g., graph code), a result of which may produce activations (e.g., output values from layers or neurons within a neural network) stored in an activation storage 820 that are functions of input / output and / or weight parameter data stored in code and / or data storage 801 and / or code and / or data storage 805. In at least one embodiment, activations stored in activation storage 820 are generated according to linear algebraic and or matrix-based mathematics performed by ALU(s) 810 in response to performing instructions or other code, wherein weight values stored in code and / or data storage 805 and / or data storage 801 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 805 or code and / or data storage 801 or another storage on or off-chip. [0141 ] In at least one embodiment, ALU(s) 810 are included within one or more processors or other hardware logic devices or circuits, whereas in another embodiment, ALU(s) 810 may be external to a processor or other hardware logic device or circuit that uses them (e.g., a co-processor). In at least one embodiment, ALUs 810 may be included within a processor’s execution units or otherwise within a bank of ALUs accessible by a processor’s execution units either within same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 801, code and / or data storage 805, and activation storage 820 may share a processor or other hardware logic device or circuit, whereas in another embodiment, they may be in different processors or other hardware logic devices or circuits, or some combination of same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 820 may be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory. Furthermore, inferencing and / or training code may be stored with other code accessible to a processor or other hardware logic or circuit and fetched and / or processed using a processor’s fetch, decode, scheduling, execution, retirement and / or other logical circuits.

[0142] In at least one embodiment, activation storage 820 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 820 may be completely or partially within or external to one or more processors or other logical circuits. In at least one embodiment, a choice of whether activation 16 05 23 storage 820 is internal or external to a processor, for example, or comprising DRAM, SRAM, flash memory or some other storage type may depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training of a neural network, or some combination of these factors. [0143 ] In at least one embodiment, inference and / or training logic 815 illustrated in FIG. 8A may be used in conjunction with an application-specific integrated circuit (“ASIC”), such as a TensorFlow® Processing Unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp. In at least one embodiment, inference and / or training logic 815 illustrated in FIG. 8A may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware or other hardware, such as field programmable gate arrays (“FPGAs”).

[0144] FIG. 8B illustrates inference and / or training logic 815, according to at least one embodiment. In at least one embodiment, inference and / or training logic 815 may include, without limitation, hardware logic in which computational resources are dedicated or otherwise exclusively used in conjunction with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, inference and / or training logic 815 illustrated in FIG. 8B may be used in conjunction with an application-specific integrated circuit (ASIC), such as TensorFlow® Processing Unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp. In at least one embodiment, inference and / or training logic 815 illustrated in FIG. 8B may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware or other hardware, such as field programmable gate arrays (FPGAs). In at least one embodiment, inference and / or training logic 815 includes, without limitation, code and / or data storage 801 and code and / or data storage 805, which may be used to store code (e.g., graph code), weight values and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In at least one embodiment illustrated in FIG. 8B, each of code and / or data storage 801 and code and / or data storage 805 is associated with a dedicated computational resource, such as computational hardware 802 and computational hardware 806, respectively. In at least one embodiment, each of 16 05 23 computational hardware 802 and computational hardware 806 comprises one or more ALUs that perform mathematical functions, such as linear algebraic functions, only on information stored in code and / or data storage 801 and code and / or data storage 805, respectively, result of which is stored in activation storage 820.

[0145] In at least one embodiment, each of code and / or data storage 801 and 805 and corresponding computational hardware 802 and 806, respectively, correspond to different layers of a neural network, such that resulting activation from one storage / computational pair 801 / 802 of code and / or data storage 801 and computational hardware 802 is provided as an input to a next storage / computational pair 805 / 806 of code and / or data storage 805 and computational hardware 806, in order to mirror a conceptual organization of a neural network. In at least one embodiment, each of storage / computational pairs 801 / 802 and 805 / 806 may correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) subsequent to or in parallel with storage / computation pairs 801 / 802 and 805 / 806 may be included in inference and / or training logic 815.

[0146] In at least one embodiment, one or more systems depicted in FIGS. 8A-8B are utilized to train a neural network to perform object detection, instance segmentation, and semantic correspondence with bounding box annotations. In at least one embodiment, one or more systems depicted in FIGS. 8A-8B are utilized to implement a framework for object detection, instance segmentation, and semantic correspondence. In at least one embodiment, one or more systems depicted in FIGS. 8A-8B are utilized to implement one or more networks and processes such as those described in connection with FIGS. 1-7. NEURAL NETWORK TRAINING AND DEPLOYMENT

[0147] FIG. 9 illustrates training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, untrained neural network 906 is trained using a training dataset 902. In at least one embodiment, training framework 904 is a PyTorch framework, whereas in other embodiments, training framework 904 is a TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, training framework 904 trains an untrained neural network 906 and enables it to be trained using processing resources described herein to generate a trained neural network 908. In at least one embodiment, weights may be chosen 16 05 23 randomly or by pre-training using a deep belief network. In at least one embodiment, training may be performed in either a supervised, partially supervised, or unsupervised manner. [0.148] In at least one embodiment, untrained neural network 906 is trained using supervised learning, wherein training dataset 902 includes an input paired with a desired output for an input, or where training dataset 902 includes input having a known output and an output of neural network 906 is manually graded. In at least one embodiment, untrained neural network 906 is trained in a supervised manner and processes inputs from training dataset 902 and compares resulting outputs against a set of expected or desired outputs. In at least one embodiment, errors are then propagated back through untrained neural network 906. In at least one embodiment, training framework 904 adjusts weights that control untrained neural network 906. In at least one embodiment, training framework 904 includes tools to monitor how well untrained neural network 906 is converging towards a model, such as trained neural network 908, suitable to generating correct answers, such as in result 914, based on input data such as a new dataset 912. In at least one embodiment, training framework 904 trains untrained neural network 906 repeatedly while adjust weights to refine an output of untrained neural network 906 using a loss function and adjustment algorithm, such as stochastic gradient descent. In at least one embodiment, training framework 904 trains untrained neural network 906 until untrained neural network 906 achieves a desired accuracy. In at least one embodiment, trained neural network 908 can then be deployed to implement any number of machine learning operations.

[0149] In at least one embodiment, untrained neural network 906 is trained using unsupervised learning, wherein untrained neural network 906 attempts to train itself using unlabeled data. In at least one embodiment, unsupervised learning training dataset 902 will include input data without any associated output data or “ground truth” data. In at least one embodiment, untrained neural network 906 can learn groupings within training dataset 902 and can determine how individual inputs are related to untrained dataset 902. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in trained neural network 908 capable of performing operations useful in reducing dimensionality of new dataset 912. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in new dataset 912 that deviate from normal patterns of new dataset 912.

[0150] In at least one embodiment, semi-supervised learning may be used, which is a technique in which in training dataset 902 includes a mix of labeled and unlabeled data. In at least one embodiment, training framework 904 may be used to perform incremental learning, such as through transferred learning techniques. In at least one embodiment, incremental learning enables trained neural network 908 to adapt to new dataset 912 without forgetting knowledge instilled within trained neural network 908 during initial training.

[0151] In at least one embodiment, one or more systems depicted in FIG. 9 are utilized to train a neural network to perform object detection, instance segmentation, and semantic correspondence with bounding box annotations. In at least one embodiment, one or more systems depicted in FIG. 9 are utilized to implement a framework for object detection, instance segmentation, and semantic correspondence. In at least one embodiment, one or more systems depicted in FIG. 9 are utilized to implement one or more networks and processes such as those described in connection with FIGS. 1-7. 16 05 23 DATA CENTER

[0152] FIG. 10 illustrates an example data center 1000, in which at least one embodiment may be used. In at least one embodiment, data center 1000 includes a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030 and an application layer 1040.

[0153] In at least one embodiment, as shown in FIG. 10, data center infrastructure layer 1010 may include a resource orchestrator 1012, grouped computing resources 1014, and node computing resources (“node C.R.s”) 1016(1)-1016(N), where “N” represents a positive integer (which may be a different integer “N” than used in other figures). In at least one embodiment, node C.R.S 1016(l)-1016(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1018(1 )-1018(N) (e.g., dynamic read-only memory, solid state storage or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more node C.R.s from among node C.R.s 1016(1)-1016(N) may be a server having one or more of above-mentioned computing resources. 16 05 23

[0154] In at least one embodiment, grouped computing resources 1014 may include separate groupings of node C.R.S housed within one or more racks (not shown), or many racks housed in data centers at various geographical locations (also not shown). In at least one embodiment, separate groupings of node C.R.S within grouped computing resources 1014 may include grouped compute, network, memory or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R.S including CPUs or processors may grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, m any combination.

[0155] In at least one embodiment, resource orchestrator 1012 may configure or otherwise control one or more node C.R.S 1016(l)-1016(N) and / or grouped computing resources 1014. In at least one embodiment, resource orchestrator 1012 may include a software design infrastructure (“SDI”) management entity for data center 1000. In at least one embodiment, resource orchestrator 812 may include hardware, software or some combination thereof.

[0156] In at least one embodiment, as shown in FIG. 10, framework layer 1020 includes a job scheduler 1022, a configuration manager 1024, a resource manager 1026 and a distributed file system 1028. In at least one embodiment, framework layer 1020 may include a framework to support software 1032 of software layer 1030 and / or one or more application(s) 1042 of application layer 1040. In at least one embodiment, software 1032 or application(s) 1042 may respectively include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud and Microsoft Azure. In at least one embodiment, framework layer 1020 may be, but is not limited to, a type of free and open-source software web application framework such as Apache Spark™ (hereinafter “Spark”) that may utilize distributed file system 1028 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 1022 may include a Spark driver to facilitate scheduling of workloads supported by various layers of data center 1000. In at least one embodiment, configuration manager 1024 may be capable of configuring different layers such as software layer 1030 and framework layer 1020 including Spark and distributed file system 1028 for supporting large-scale data processing. In at least one embodiment, resource manager 1026 may be capable of managing clustered or grouped computing resources mapped to or allocated for support of distributed file system 1028 and job 16 05 23 scheduler 1022. In at least one embodiment, clustered or grouped computing resources may include grouped computing resources 1014 at data center infrastructure layer 1010. In at least one embodiment, resource manager 1026 may coordinate with resource orchestrator 1012 to manage these mapped or allocated computing resources.

[0157] In at least one embodiment, software 1032 included in software layer 1030 may include software used by at least portions of node C.R.s 1016(l)-1016(N), grouped computing resources 1014, and / or distributed file system 1028 of framework layer 1020. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, e-mail virus scan software, database software, and streaming video content software.

[0158] In at least one embodiment, application(s) 1042 included in application layer 1040 may include one or more types of applications used by at least portions of node C.R.s 1016(l)-1016(N), grouped computing resources 1014, and / or distributed file system 1028 of framework layer 1020. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of a genomics application, a cognitive compute, application and a machine learning application, including training or inferencing software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.) or other machine learning applications used in conjunction with one or more embodiments.

[0159] In at least one embodiment, any of configuration manager 1024, resource manager 1026, and resource orchestrator 1012 may implement any number and type of self-modifying actions based on any amount and type of data acquired in any technically feasible fashion. In at least one embodiment, self-modifying actions may relieve a data center operator of data center 1000 from making possibly bad configuration decisions and possibly avoiding underutilized and / or poor performing portions of a data center.

[0160] In at least one embodiment, data center 1000 may include tools, services, software or other resources to train one or more machine learning models or predict or infer information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using software and computing resources described above with respect to data center 1000. In at least one 16 05 23 embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using resources described above with respect to data center 1000 by using weight parameters calculated through one or more training techniques described herein. [0161 ] In at least one embodiment, data center may use CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and / or inferencing using above-described resources. Moreover, one or more software and / or hardware resources described above may be configured as a service to allow users to train or performing inferencing of information, such as image recognition, speech recognition, or other artificial intelligence services.

[0162] Inference and / or training logic 815 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are provided herein in conjunction with FIGS. 8A and / or 8B. In at least one embodiment, inference and / or training logic 815 may be used in system FIG. 10 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0163] In at least one embodiment, one or more systems depicted in FIG. 10 are utilized to train a neural network to perform object detection, instance segmentation, and semantic correspondence with bounding box annotations. In at least one embodiment, one or more systems depicted in FIG. 10 are utilized to implement a framework for object detection, instance segmentation, and semantic correspondence. In at least one embodiment, one or more systems depicted in FIG. 10 are utilized to implement one or more networks and processes such as those described in connection with FIGS. 1-7. AUTONOMOUS VEHICLE

[0164] FIG. 11A illustrates an example of an autonomous vehicle 1100, according to at least one embodiment. In at least one embodiment, autonomous vehicle 1100 (alternatively referred to herein as “vehicle 1100”) may be, without limitation, a passenger vehicle, such as a car, a truck, a bus, and / or another type of vehicle that accommodates one or more passengers. In at least one 16 05 23 embodiment, vehicle 1100 may be a semi-tractor-trailer truck used for hauling cargo. In at least one embodiment, vehicle 1100 may be an airplane, robotic vehicle, or other kind of vehicle.

[0165] Autonomous vehicles may be described in terms of automation levels, defined by National Highway Traffic Safety Administration (“NHTSA”), a division of US Department of Transportation, and Society of Automotive Engineers (“SAE”) “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e g., Standard No. J3016-201806, published on June 15, 2018, Standard No. J3016-201609, published on September 30, 2016, and previous and future versions of this standard). In at least one embodiment, vehicle 1100 may be capable of functionality in accordance with one or more of Level 1 through Level 5 of autonomous driving levels. For example, in at least one embodiment, vehicle 1100 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on embodiment.

[0166] In at least one embodiment, vehicle 1100 may include, without limitation, components such as a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of a vehicle. In at least one embodiment, vehicle 1100 may include, without limitation, a propulsion system 1150, such as an internal combustion engine, hybrid electric power plant, an all-electric engine, and / or another propulsion system type. In at least one embodiment, propulsion system 1150 may be connected to a drive train of vehicle 1100, which may include, without limitation, a transmission, to enable propulsion of vehicle 1100. In at least one embodiment, propulsion system 1150 may be controlled in response to receiving signals from a throttle / accelerator(s) 1152.

[0167] In at least one embodiment, a steering system 1154, which may include, without limitation, a steering wheel, is used to steer vehicle 1100 (e.g., along a desired path or route) when propulsion system 1150 is operating (e.g., when vehicle 1100 is in motion). In at least one embodiment, steering system 1154 may receive signals from steering actuator(s) 1156. In at least one embodiment, a steering wheel may be optional for full automation (Level 5) functionality. In at least one embodiment, a brake sensor system 1146 may be used to operate vehicle brakes in response to receiving signals from brake actuator(s) 1148 and / or brake sensors.

[0168] In at least one embodiment, controller(s) 1136, which may include, without limitation, one or more system on chips (“SoCs”) (not shown in FIG. 11 A) and / or graphics processing 16 05 23 unit(s) (“GPU(s)”), provide signals (e.g., representative of commands) to one or more components and / or systems of vehicle 1100. For instance, in at least one embodiment, controller(s) 1136 may send signals to operate vehicle brakes via brake actuator(s) 1148, to operate steering system 1154 via steering actuator(s) 1156, to operate propulsion system 1150 via throttle / accelerator(s) 1152. In at least one embodiment, controller(s) 1136 may include one or more onboard (e.g., integrated) computing devices that process sensor signals, and output operation commands (e.g., signals representing commands) to enable autonomous driving and / or to assist a human driver in driving vehicle 1100. In at least one embodiment, controller(s) 1136 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functionality (e.g., computer vision), a fourth controller for infotainment functionality, a fifth controller for redundancy in emergency conditions, and / or other controllers. In at least one embodiment, a single controller may handle two or more of above functionalities, two or more controllers may handle a single functionality, and / or any combination thereof.

[0169] In at least one embodiment, controller(s) 1136 provide signals for controlling one or more components and / or systems of vehicle 1100 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be received from, for example and without limitation, global navigation satellite systems (“GNSS”) sensor(s) 1158 (e.g., Global Positioning System sensor(s)), RADAR sensor(s) 1160, ultrasonic sensor(s) 1162, LIDAR sensor(s) 1164, inertial measurement unit (“IMU”) sensor(s) 1166 (e.g., accelerometer(s), gyroscope(s), a magnetic compass or magnetic compasses, magnetometer(s), etc.), microphone(s) 1196, stereo camera(s) 1168, wide-view camera(s) 1170 (e.g., fisheye cameras), infrared camera(s) 1172, surround camera(s) 1174 (e.g., 360 degree cameras), long-range cameras (not shown in FIG. 11 A), mid-range camera(s) (not shown in FIG. 11 A), speed sensor(s) 1144 (e.g., for measuring speed of vehicle 1100), vibration sensor(s) 1142, steering sensor(s) 1140, brake sensor(s) (e.g., as part of brake sensor system 1146), and / or other sensor types.

[0170] In at least one embodiment, one or more of controller(s) 1136 may receive inputs (e.g., represented by input data) from an instrument cluster 1132 of vehicle 1100 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) 16 05 23 display 1134, an audible annunciator, a loudspeaker, and / or via other components of vehicle 1100. In at least one embodiment, outputs may include information such as vehicle velocity, speed, time, map data (e.g., a High Definition map (not shown in FIG. HA)), location data (e.g., vehicle’s 1100 location, such as on a map), direction, location of other vehicles (e.g., an occupancy grid), information about objects and status of objects as perceived by controller(s) 1136, etc. For example, in at least one embodiment, HMI display 1134 may display information about presence of one or more objects (e.g., a street sign, caution sign, traffic light changing, etc.), and / or information about driving maneuvers vehicle has made, is making, or will make (e.g., changing lanes now, taking exit 34B in two miles, etc.).

[0171] In at least one embodiment, vehicle 1100 further includes a network interface 1124 which may use wireless antenna(s) 1126 and / or modem(s) to communicate over one or more networks. For example, in at least one embodiment, network interface 1124 may be capable of communication over Long-Term Evolution (“LTE”) (RTM), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile communication (“GSM”) (RTM), IMT-CDMA Multi-Carrier (“CDMA2000”) networks, etc. In at least one embodiment, wireless antenna(s) 1126 may also enable communication between objects in environment (e.g., vehicles, mobile devices, etc.), using local area network(s), such as Bluetooth (RTM), Bluetooth (RTM) Low Energy (“LE”), Z-Wave (RTM), ZigBee (RTM), etc., and / or low power wide-area network(s) (“LPWANs”), such as LoRaWAN (RTM), SigFox, etc. protocols.

[0172] Inference and / or training logic 815 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are provided herein in conjunction with FIGS. 8A and / or 8B. In at least one embodiment, inference and / or training logic 815 may be used in system FIG. 11A for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0173] FIG. 1 IB illustrates an example of camera locations and fields of view for autonomous vehicle 1100 of FIG. 11 A, according to at least one embodiment. In at least one embodiment, cameras and respective fields of view are one example embodiment and are not intended to be 16 05 23 limiting. For instance, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be located at different locations on vehicle 1100.

[0174] In at least one embodiment, camera types for cameras may include, but are not limited to, digital cameras that may be adapted for use with components and / or systems of vehicle 1100. In at least one embodiment, camera(s) may operate at automotive safety integrity level (“ASIL”) B and / or at another ASIL. In at least one embodiment, camera types may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on embodiment. In at least one embodiment, cameras may be capable of using rolling shutters, global shutters, another type of shutter, or a combination thereof. In at least one embodiment, color filter array may include a red clear clear clear (“RCCC”) color filter array, a red clear clear blue (“RCCB”) color filter array, a red blue green clear (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensors (“RGGB”) color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, clear pixel cameras, such as cameras with an RCCC, an RCCB, and / or an RBGC color filter array, may be used in an effort to increase light sensitivity. [0175 ] In at least one embodiment, one or more of camera(s) may be used to perform advanced driver assistance systems (“ADAS”) functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a Multi-Function Mono Camera may be installed to provide functions including lane departure warning, traffic sign assist and intelligent headlamp control. In at least one embodiment, one or more of camera(s) (e.g., all cameras) may record and provide image data (e.g., video) simultaneously.

[0176] In at least one embodiment, one or more camera may be mounted in a mounting assembly, such as a custom designed (three-dimensional (“3D”) printed) assembly, in order to cut out stray light and reflections from within vehicle 1100 (e.g., reflections from dashboard reflected in windshield mirrors) which may interfere with camera image data capture abilities. With reference to wing-mirror mounting assemblies, in at least one embodiment, wing-mirror assemblies may be custom 3D printed so that a camera mounting plate matches a shape of a wing-mirror. In at least one embodiment, camera(s) may be integrated into wing-mirrors. In at least one embodiment, for side-view cameras, camera(s) may also be integrated within four pillars at each corner of a cabin. 16 05 23

[0177] In at least one embodiment, cameras with a field of view that include portions of an environment in front of vehicle 1100 (e.g., front-facing cameras) may be used for surround view, to help identify forward facing paths and obstacles, as well as aid in, with help of one or more of controller(s) 1136 and / or control SoCs, providing information critical to generating an occupancy grid and / or determining preferred vehicle paths. In at least one embodiment, front-facing cameras may be used to perform many similar ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, front-facing cameras may also be used for ADAS functions and systems including, without limitation, Lane Departure Warnings (“LDW”), Autonomous Cruise Control (“ACC”), and / or other functions such as traffic sign recognition.

[0178] In at least one embodiment, a variety of cameras may be used in a front-facing configuration, including, for example, a monocular camera platform that includes a CMOS (“complementary metal oxide semiconductor”) color imager. In at least one embodiment, a wide-view camera 1170 may be used to perceive objects coming into view from a periphery (e.g., pedestrians, crossing traffic or bicycles). Although only one wide-view camera 1170 is illustrated in FIG. 1 IB, in other embodiments, there may be any number (including zero) wide-view cameras on vehicle 1100. In at least one embodiment, any number of long-range camera(s) 1198 (e.g., a long-view stereo camera pair) may be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, long-range camera(s) 1198 may also be used for object detection and classification, as well as basic object tracking.

[0179] In at least one embodiment, any number of stereo camera(s) 1168 may also be included in a front-facing configuration. In at least one embodiment, one or more of stereo camera(s) 1168 may include an integrated control unit comprising a scalable processing unit, which may provide a programmable logic (“FPGA”) and a multi-core micro-processor with an integrated Controller Area Network (“CAN”) or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of an environment of vehicle 1100, including a distance estimate for all points in an image. In at least one embodiment, one or more of stereo camera(s) 1168 may include, without limitation, compact stereo vision sensor(s) that may include, without limitation, two camera lenses (one each on left and right) and an image 16 05 23 processing chip that may measure distance from vehicle 1100 to target object and use generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo camera(s) 1168 may be used in addition to, or alternatively from, those described herein.

[0180] In at least one embodiment, cameras with a field of view that include portions of environment to sides of vehicle 1100 (e.g., side-view cameras) may be used for surround view, providing information used to create and update an occupancy grid, as well as to generate side impact collision warnings. For example, in at least one embodiment, surround camera(s) 1174 (e.g., four surround cameras as illustrated in FIG. 1 IB) could be positioned on vehicle 1100. In at least one embodiment, surround camera(s) 1174 may include, without limitation, any number and combination of wide-view cameras, fisheye camera(s), 360 degree camera(s), and / or similar cameras. For instance, in at least one embodiment, four fisheye cameras may be positioned on a front, a rear, and sides of vehicle 1100. In at least one embodiment, vehicle 1100 may use three surround camera(s) 1174 (e.g., left, right, and rear), and may leverage one or more other camera(s) (e.g., a forward-facing camera) as a fourth surround-view camera. [0181 ] In at least one embodiment, cameras with a field of view that include portions of an environment behind vehicle 1100 (e.g., rear-view cameras) may be used for parking assistance, surround view, rear collision warnings, and creating and updating an occupancy grid. In at least one embodiment, a wide variety of cameras may be used including, but not limited to, cameras that are also suitable as a front-facing camera(s) (e.g., long-range cameras 1198 and / or mid-range camera(s) 1176, stereo camera(s) 1168), infrared camera(s) 1172, etc., as described herein.

[0182] Inference and / or training logic 815 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are provided herein in conjunction with FIGS. 8A and / or 8B. In at least one embodiment, inference and / or training logic 815 may be used in system FIG. 1 IB for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. [01.83] FIG. 1 IC is a block diagram illustrating an example system architecture for autonomous vehicle 1100 of FIG. 11A, according to at least one embodiment. In at least one 16 05 23 embodiment, each of components, features, and systems of vehicle 1100 in FIG. 1 IC is illustrated as being connected via a bus 1102. In at least one embodiment, bus 1102 may include, without limitation, a CAN data interface (alternatively referred to herein as a “CAN bus”). In at least one embodiment, a CAN may be a network inside vehicle 1100 used to aid in control of various features and functionality of vehicle 1100, such as actuation of brakes, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 1102 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1102 may be read to find steering wheel angle, ground speed, engine revolutions per minute (“RPMs”), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1102 may be a CAN bus that is ASIL B compliant.

[0184] In at least one embodiment, in addition to, or alternatively from CAN, FlexRay and / or Ethernet protocols may be used. In at least one embodiment, there may be any number of busses forming bus 1102, which may include, without limitation, zero or more CAN busses, zero or more FlexRay busses, zero or more Ethernet busses, and / or zero or more other types of busses using different protocols. In at least one embodiment, two or more busses may be used to perform different functions, and / or may be used for redundancy. For example, a first bus may be used for collision avoidance functionality and a second bus may be used for actuation control. In at least one embodiment, each bus of bus 1102 may communicate with any of components of vehicle 1100, and two or more busses of bus 1102 may communicate with corresponding components. In at least one embodiment, each of any number of system(s) on chip(s) (“SoC(s)”) 1104 (such as SoC 1104(A) and SoC 1104(B)), each of controller(s) 1136, and / or each computer within vehicle may have access to same input data (e.g., inputs from sensors of vehicle 1100), and may be connected to a common bus, such CAN bus. [01.85] In at least one embodiment, vehicle 1100 may include one or more controller(s) 1136, such as those described herein with respect to FIG. 11 A. In at least one embodiment, controller(s) 1136 may be used for a variety of functions. In at least one embodiment, controller(s) 1136 may be coupled to any of various other components and systems of vehicle 1100, and may be used for control of vehicle 1100, artificial intelligence of vehicle 1100, infotainment for vehicle 1100, and / or other functions. 16 05 23

[0186] In at least one embodiment, vehicle 1100 may include any number of SoCs 1104. In at least one embodiment, each of SoCs 1104 may include, without limitation, central processing units (“CPU(s)”) 1106, graphics processing units (“GPU(s)”) 1108, processor(s) 1110, cache(s) 1112, accelerator(s) 1114, data store(s) 1116, and / or other components and features not illustrated. In at least one embodiment, SoC(s) 1104 may be used to control vehicle 1100 in a variety of platforms and systems. For example, in at least one embodiment, SoC(s) 1104 may be combined in a system (e.g., system of vehicle 1100) with a High Definition (“HD”) map 1122 which may obtain map refreshes and / or updates via network interface 1124 from one or more servers (not shown m FIG. 1 IC).

[0187] In at least one embodiment, CPU(s) 1106 may include a CPU cluster or CPU complex (alternatively referred to herein as a “CCPLEX”). In at least one embodiment, CPU(s) 1106 may include multiple cores and / or level two (“L2”) caches. For instance, in at least one embodiment, CPU(s) 1106 may include eight cores in a coherent multi-processor configuration. In at least one embodiment, CPU(s) 1106 may include four dual-core clusters where each cluster has a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, CPU(s) 1106 (e.g., CCPLEX) may be configured to support simultaneous cluster operations enabling any combination of clusters of CPU(s) 1106 to be active at any given time.

[0188] In at least one embodiment, one or more of CPU(s) 1106 may implement power management capabilities that include, without limitation, one or more of following features: individual hardware blocks may be clock-gated automatically when idle to save dynamic power; each core clock may be gated when such core is not actively executing instructions due to execution of Wait for Interrupt (“WFI”) / Wait for Event (“WFE”) instructions; each core may be independently power-gated; each core cluster may be independently clock-gated when all cores are clock-gated or power-gated; and / or each core cluster may be independently power-gated when all cores are power-gated. In at least one embodiment, CPU(s) 1106 may further implement an enhanced algorithm for managing power states, where allowed power states and expected wakeup times are specified, and hardware / microcode determines which best power state to enter for core, cluster, and CCPLEX. In at least one embodiment, processing cores may support simplified power state entry sequences in software with work offloaded to microcode. 16 05 23

[0189] In at least one embodiment, GPU(s) 1108 may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, GPU(s) 1108 may be programmable and may be efficient for parallel workloads. In at least one embodiment, GPU(s) 1108 may use an enhanced tensor instruction set. In at least one embodiment, GPU(s) 1108 may include one or more streaming microprocessors, where each streaming microprocessor may include a level one (“LI”) cache (e.g., an LI cache with at least 96 KB storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with a 512 KB storage capacity). In at least one embodiment, GPU(s) 1108 may include at least eight streaming microprocessors. In at least one embodiment, GPU(s) 1108 may use compute application programming interface(s) (API(s)). In at least one embodiment, GPU(s) 1108 may use one or more parallel computing platforms and / or programming models (e g., NVIDIA’s (RTM) CUDA model).

[0190] In at least one embodiment, one or more of GPU(s) 1108 may be power-optimized for best performance in automotive and embedded use cases. For example, in at least one embodiment, GPU(s) 1108 could be fabricated on Fin field-effect transistor (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may incorporate a number of mixed-precision processing cores partitioned into multiple blocks. For example, and without limitation, 64 PF32 cores and 32 PF64 cores could be partitioned into four processing blocks. In at least one embodiment, each processing block could be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA (RTM) Tensor cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a warp scheduler, a dispatch unit, and / or a 64 KB register file. In at least one embodiment, streaming microprocessors may include independent parallel integer and floating-point data paths to provide for efficient execution of workloads with a mix of computation and addressing calculations. In at least one embodiment, streaming microprocessors may include independent thread scheduling capability to enable finer-grain synchronization and cooperation between parallel threads. In at least one embodiment, streaming microprocessors may include a combined LI data cache and shared memory unit in order to improve performance while simplifying programming. [0191 ] In at least one embodiment, one or more of GPU(s) 1108 may include a high bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem to provide, in some examples, 16 05 23 about 900 GB / second peak memory bandwidth. In at least one embodiment, in addition to, or alternatively from, HBM memory, a synchronous graphics random-access memory (“SGRAM”) may be used, such as a graphics double data rate type five synchronous random-access memory (“GDDR5”). [0192 [ In at least one embodiment, GPU(s) 1108 may include unified memory technology. In at least one embodiment, address translation services (“ATS”) support may be used to allow GPU(s) 1108 to access CPU(s) 1106 page tables directly. In at least one embodiment, embodiment, when a GPU of GPU(s) 1108 memory management unit (“MMU”) experiences a miss, an address translation request may be transmitted to CPU(s) 1106. In response, 2 CPU of CPU(s) 1106 may look in its page tables for a virtual-to-physical mapping for an address and transmit translation back to GPU(s) 1108, in at least one embodiment. In at least one embodiment, unified memory technology may allow a single unified virtual address space for memory of both CPU(s) 1106 and GPU(s) 1108, thereby simplifying GPU(s) 1108 programming and porting of applications to GPU(s) 1108.

[0193] In at least one embodiment, GPU(s) 1108 may include any number of access counters that may keep track of frequency of access of GPU(s) 1108 to memory of other processors. In at least one embodiment, access counter(s) may help ensure that memory pages are moved to physical memory of a processor that is accessing pages most frequently, thereby improving efficiency for memory ranges shared between processors.

[0194] In at least one embodiment, one or more of SoC(s) 1104 may include any number of cache(s) 1112, including those described herein. For example, in at least one embodiment, cache(s) 1112 could include a level three (“L3”) cache that is available to both CPU(s) 1106 and GPU(s) 1108 (e.g., that is connected to CPU(s) 1106 and GPU(s) 1108). In at least one embodiment, cache(s) 1112 may include a write-back cache that may keep track of states of lines, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, a L3 cache may include 4 MB of memory or more, depending on embodiment, although smaller cache sizes may be used.

[0195] In at least one embodiment, one or more of SoC(s) 1104 may include one or more accelerator(s) 1114 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, SoC(s) 1104 may include a hardware acceleration cluster that may 16 05 23 include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4 MB of SRAM), may enable a hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, a hardware acceleration cluster may be used to complement GPU(s) 1108 and to off-load some of tasks of GPU(s) 1108 (e.g., to free up more cycles of GPU(s) 1108 for performing other tasks). In at least one embodiment, accelerator(s) 1114 could be used for targeted workloads (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.) that are stable enough to be amenable to acceleration. In at least one embodiment, a CNN may include a region-based or regional convolutional neural networks (“RCNNs”) and Fast RCNNs (e.g., as used for object detection) or other type of CNN.

[0196] In at least one embodiment, accelerator(s) 1114 (e.g., hardware acceleration cluster) may include one or more deep learning accelerator (“DLA”). In at least one embodiment, DLA(s) may include, without limitation, one or more Tensor processing units (“TPUs”) that may be configured to provide an additional ten trillion operations per second for deep learning applications and inferencing. In at least one embodiment, TPUs may be accelerators configured to, and optimized for, performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, DLA(s) may further be optimized for a specific set of neural network types and floating point operations, as well as inferencing. In at least one embodiment, design of DLA(s) may provide more performance per millimeter than a typical general-purpose GPU, and typically vastly exceeds performance of a CPU. In at least one embodiment, TPU(s) may perform several functions, including a single-instance convolution function, supporting, for example, INT8, INTI 6, and FP16 data types for both features and weights, as well as post-processor functions. In at least one embodiment, DLA(s) may quickly and efficiently execute neural networks, especially CNNs, on processed or unprocessed data for any of a variety of functions, including, for example and without limitation: a CNN for object identification and detection using data from camera sensors; a CNN for distance estimation using data from camera sensors; a CNN for emergency vehicle detection and identification and detection using data from microphones; a CNN for facial recognition and vehicle owner identification using data from camera sensors; and / or a CNN for security and / or safety related events. 16 05 23

[0197] In at least one embodiment, DLA(s) may perform any function of GPU(s) 1108, and by using an inference accelerator, for example, a designer may target either DLA(s) or GPU(s) 1108 for any function. For example, in at least one embodiment, a designer may focus processing of CNNs and floating point operations on DLA(s) and leave other functions to GPU(s) 1108 and / or accelerator(s) 1114. [0198 ] In at least one embodiment, accelerator(s) 1114 may include programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance system (“ADAS”) 1138, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example and without limitation, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0199] In at least one embodiment, RISC cores may interact with image sensors (e.g., image sensors of any cameras described herein), image signal processor(s), etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, RISC cores may use any of a number of protocols, depending on embodiment. In at least one embodiment, RISC cores may execute a real-time operating system (“RTOS”). In at least one embodiment, RISC cores may be implemented using one or more integrated circuit devices, application specific integrated circuits (“ASICs”), and / or memory devices. For example, in at least one embodiment, RISC cores could include an instruction cache and / or a tightly coupled RAM.

[0200] In at least one embodiment, DMA may enable components of PVA to access system memory independently of CPU(s) 1106. In at least one embodiment, DMA may support any number of features used to provide optimization to a PVA including, but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, DMA may support up to six or more dimensions of addressing, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping. 16 05 23 [0201 ] In at least one embodiment, vector processors may be programmable processors that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, a PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, a PVA core may include a processor subsystem, DMA engine(s) (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, a vector processing subsystem may operate as a primary processing engine of a PVA, and may include a vector processing unit (“VPU”), an instruction cache, and / or vector memory (e.g., “VMEM’). In at least one embodiment, VPU core may include a digital signal processor such as, for example, a single instruction, multiple data (“SIMD”), very long instruction word (“VLIW”) digital signal processor. In at least one embodiment, a combination of SIMD and VLIW may enhance throughput and speed.

[0202] In at least one embodiment, each of vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each of vector processors may be configured to execute independently of other vector processors. In at least one embodiment, vector processors that are included in a particular PVA may be configured to employ data parallelism. For instance, in at least one embodiment, plurality of vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may simultaneously execute different computer vision algorithms, on one image, or even execute different algorithms on sequential images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in hardware acceleration cluster and any number of vector processors may be included in each PVA. In at least one embodiment, PVA may include additional error correcting code (“ECC”) memory, to enhance overall system safety.

[0203] In at least one embodiment, accelerator(s) 1114 may include a computer vision network on-chip and static random-access memory (“SRAM”), for providing a high-bandwidth, low latency SRAM for accelerator(s) 1114. In at least one embodiment, on-chip memory may include at least 4 MB SRAM, comprising, for example and without limitation, eight field-configurable memory blocks, that may be accessible by both a PVA and a DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, 16 05 23 configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, a PVA and a DLA may access memory via a backbone that provides a PVA and a DLA with high-speed access to memory. In at least one embodiment, a backbone may include a computer vision network on-chip that interconnects a PVA and a DLA to memory (e g., using APB). [0204 ] In at least one embodiment, a computer vision network on-chip may include an interface that determines, before transmission of any control signal / address / data, that both a PVA and a DLA provide ready and valid signals. In at least one embodiment, an interface may provide for separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-type communications for continuous data transfer. In at least one embodiment, an interface may comply with International Organization for Standardization (“ISO”) 26262 or International Electrotechnical Commission (“IEC”) 61508 standards, although other standards and protocols may be used.

[0205] In at least one embodiment, one or more of SoC(s) 1104 may include a real-time ray-tracing hardware accelerator. In at least one embodiment, real-time ray-tracing hardware accelerator may be used to quickly and efficiently determine positions and extents of objects (e.g., within a world model), to generate real-time visualization simulations, for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulation, for comparison to LIDAR data for purposes of localization and / or other functions, and / or for other uses.

[0206] In at least one embodiment, accelerator(s) 1114 can have a wide array of uses for autonomous driving. In at least one embodiment, a PVA may be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, a PVA’s capabilities are a good match for algorithmic domains needing predictable processing, at low power and low latency. In other words, a PVA performs well on semi-dense or dense regular computation, even on small data sets, which might require predictable run-times with low latency and low power. In at least one embodiment, such as in vehicle 1100, PVAs might be designed to run classic computer vision algorithms, as they can be efficient at object detection and operating on integer math.

[0207] For example, according to at least one embodiment of technology, a PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based 16 05 23 algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching on-the-fly (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, a PVA may perform computer stereo vision functions on inputs from two monocular cameras.

[0208] In at least one embodiment, a PVA may be used to perform dense optical flow. For example, in at least one embodiment, a PVA could process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, a PVA is used for time of flight depth processing, by processing raw time of flight data to provide processed time of flight data, for example. [ 0209] In at least one embodiment, a DLA may be used to run any type of network to enhance control and driving safety, including for example and without limitation, a neural network that outputs a measure of confidence for each object detection. In at least one embodiment, confidence may be represented or interpreted as a probability, or as providing a relative “weight” of each detection compared to other detections. In at least one embodiment, a confidence measure enables a system to make further decisions regarding which detections should be considered as true positive detections rather than false positive detections. In at least one embodiment, a system may set a threshold value for confidence and consider only detections exceeding threshold value as true positive detections. In an embodiment in which an automatic emergency braking (“AEB”) system is used, false positive detections would cause vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, highly confident detections may be considered as triggers for AEB. In at least one embodiment, a DLA may run a neural network for regressing confidence value. In at least one embodiment, neural network may take as its input at least some subset of parameters, such as bounding box dimensions, ground plane estimate obtained (e.g., from another subsystem), output from IMU sensor(s) 1166 that correlates with vehicle 1100 orientation, distance, 3D location estimates of object obtained from neural network and / or other sensors (e.g., LIDAR sensor(s) 1164 or RADAR sensor(s) 1160), among others.

[0210] In at least one embodiment, one or more of SoC(s) 1104 may include data store(s) 1116 (e.g., memory). In at least one embodiment, data store(s) 1116 may be on-chip memory of 16 05 23 SoC(s) 1104, which may store neural networks to be executed on GPU(s) 1108 and / or a DLA. In at least one embodiment, data store(s) 1116 may be large enough in capacity to store multiple instances of neural networks for redundancy and safety. In at least one embodiment, data store(s) 1116 may comprise L2 or L3 cache(s). [0211 ] In at least one embodiment, one or more of SoC(s) 1104 may include any number of processor(s) 1110 (e.g., embedded processors). In at least one embodiment, processor(s) 1110 may include a boot and power management processor that may be a dedicated processor and subsystem to handle boot power and management functions and related security enforcement. In at least one embodiment, a boot and power management processor may be a part of a boot sequence of SoC(s) 1104 and may provide runtime power management services. In at least one embodiment, a boot power and management processor may provide clock and voltage programming, assistance in system low power state transitions, management of SoC(s) 1104 thermals and temperature sensors, and / or management of SoC(s) 1104 power states. In at least one embodiment, each temperature sensor may be implemented as a ring-oscillator whose output frequency is proportional to temperature, and SoC(s) 1104 may use nng-oscillators to detect temperatures of CPU(s) 1106, GPU(s) 1108, and / or accelerator(s) 1114. In at least one embodiment, if temperatures are determined to exceed a threshold, then a boot and power management processor may enter a temperature fault routine and put SoC(s) 1104 into a lower power state and / or put vehicle 1100 into a chauffeur to safe stop mode (e.g., bring vehicle 1100 to a safe stop).

[0212] In at least one embodiment, processor(s) 1110 may further include a set of embedded processors that may serve as an audio processing engine which may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces, and a broad and flexible range of audio I / O interfaces. In at least one embodiment, an audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[0213] In at least one embodiment, processor(s) 1110 may further include an always-on processor engine that may provide necessary hardware features to support low power sensor management and wake use cases. In at least one embodiment, an always-on processor engine may include, without limitation, a processor core, a tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic. 16 05 23

[0214] In at least one embodiment, processor(s) 1110 may further include a safety cluster engine that includes, without limitation, a dedicated processor subsystem to handle safety management for automotive applications. In at least one embodiment, a safety cluster engine may include, without limitation, two or more processor cores, a tightly coupled RAM, support peripherals (e.g., timers, an interrupt controller, etc.), and / or routing logic. In a safety mode, two or more cores may operate, in at least one embodiment, in a lockstep mode and function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, processor(s) 1110 may further include a real-time camera engine that may include, without limitation, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, processor(s) 1110 may further include a high-dynamic range signal processor that may include, without limitation, an image signal processor that is a hardware engine that is part of a camera processing pipeline. [02! 5] In at least one embodiment, processor(s) 1110 may include a video image compositor that may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions needed by a video playback application to produce a final image for a player window. In at least one embodiment, a video image compositor may perform lens distortion correction on wide-view camera(s) 1170, surround camera(s) 1174, and / or on in-cabin monitoring camera sensor(s). In at least one embodiment, in-cabin monitoring camera sensor(s) are preferably monitored by a neural network running on another instance of SoC 1104, configured to identify in cabin events and respond accordingly. In at least one embodiment, an in-cabin system may perform, without limitation, lip reading to activate cellular service and place a phone call, dictate emails, change a vehicle’s destination, activate or change a vehicle’s infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to a driver when a vehicle is operating in an autonomous mode and are disabled otherwise.

[0216] In at least one embodiment, a video image compositor may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in a video, noise reduction weights spatial information appropriately, decreasing weights of information provided by adjacent frames. In at least one embodiment, where an image or portion of an image does not include motion, temporal noise 16 05 23 reduction performed by video image compositor may use information from a previous image to reduce noise in a current image.

[0217] In at least one embodiment, a video image compositor may also be configured to perform stereo rectification on input stereo lens frames. In at least one embodiment, a video image compositor may further be used for user interface composition when an operating system desktop is in use, and GPU(s) 1108 are not required to continuously render new surfaces. In at least one embodiment, when GPU(s) 1108 are powered on and active doing 3D rendering, a video image compositor may be used to offload GPU(s) 1108 to improve performance and responsiveness.

[0218] In at least one embodiment, one or more SoC of SoC(s) 1104 may further include a mobile industry processor interface (“MIPI”) camera serial interface for receiving video and input from cameras, a high-speed interface, and / or a video input block that may be used for a camera and related pixel input functions. In at least one embodiment, one or more of SoC(s) 1104 may further include an input / output controller(s) that may be controlled by software and may be used for receiving I / O signals that are uncommitted to a specific role.

[0219] In at least one embodiment, one or more Soc of SoC(s) 1104 may further include a broad range of peripheral interfaces to enable communication with peripherals, audio encoders / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, SoC(s) 1104 may be used to process data from cameras (e.g., connected over Gigabit Multimedia Serial Link and Ethernet channels), sensors (e.g., LIDAR sensor(s) 1164, RADAR sensor(s) 1160, etc. that may be connected over Ethernet channels), data from bus 1102 (e.g., speed of vehicle 1100, steering wheel position, etc.), data from GNSS sensor(s) 1158 (e.g., connected over a Ethernet bus or a CAN bus), etc. In at least one embodiment, one or more SoC of SoC(s) 1104 may further include dedicated high-performance mass storage controllers that may include their own DMA engines, and that may be used to free CPU(s) 1106 from routine data management tasks.

[0220] In at least one embodiment, SoC(s) 1104 may be an end-to-end platform with a flexible architecture that spans automation Levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and makes efficient use of computer vision and ADAS techniques for diversity and redundancy, and provides a platform for a flexible, reliable driving 16 05 23 software stack, along with deep learning tools. In at least one embodiment, SoC(s) 1104 may be faster, more reliable, and even more energy-efficient and space-efficient than conventional systems. For example, in at least one embodiment, accelerator(s) 1114, when combined with CPU(s) 1106, GPU(s) 1108, and data store(s) 1116, may provide for a fast, efficient platform for Level 3-5 autonomous vehicles.

[0221] In at least one embodiment, computer vision algorithms may be executed on CPUs, which may be configured using a high-level programming language, such as C, to execute a wide variety of processing algorithms across a wide variety of visual data. However, in at least one embodiment, CPUs are oftentimes unable to meet performance requirements of many computer vision applications, such as those related to execution time and power consumption, for example. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real-time, which is used in in-vehicle ADAS applications and in practical Level 3-5 autonomous vehicles.

[0222] Embodiments described herein allow for multiple neural networks to be performed simultaneously and / or sequentially, and for results to be combined together to enable Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executing on a DLA or a discrete GPU (e.g., GPU(s) 1120) may include text and word recognition, allowing reading and understanding of traffic signs, including signs for which a neural network has not been specifically trained. In at least one embodiment, a DLA may further include a neural network that is able to identify, interpret, and provide semantic understanding of a sign, and to pass that semantic understanding to path planning modules running on a CPU Complex.

[0223] In at least one embodiment, multiple neural networks may be run simultaneously, as for Level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign stating “Caution: flashing lights indicate icy conditions,” along with an electric light, may be independently or collectively interpreted by several neural networks. In at least one embodiment, such warning sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), text “flashing lights indicate icy conditions” may be interpreted by a second deployed neural network, which informs a vehicle’s path planning software (preferably executing on a CPU Complex) that when flashing lights are detected, icy conditions exist. In at least one embodiment, a flashing light may be identified by operating a 16 05 23 third deployed neural network over multiple frames, informing a vehicle’s path-planning software of a presence (or an absence) of flashing lights. In at least one embodiment, all three neural networks may run simultaneously, such as within a DLA and / or on GPU(s) 1108.

[0224] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from camera sensors to identify presence of an authorized driver and / or owner of vehicle 1100. In at least one embodiment, an always-on sensor processing engine may be used to unlock a vehicle when an owner approaches a driver door and turns on lights, and, in a security mode, to disable such vehicle when an owner leaves such vehicle. In this way, SoC(s) 1104 provide for security against theft and / or carjacking.

[0225] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphones 1196 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC(s) 1104 use a CNN for classifying environmental and urban sounds, as well as classifying visual data. In at least one embodiment, a CNN running on a DLA is trained to identify a relative closing speed of an emergency vehicle (e.g., by using a Doppler effect). In at least one embodiment, a CNN may also be trained to identify emergency vehicles specific to a local area in which a vehicle is operating, as identified by GNSS sensor(s) 1158. In at least one embodiment, when operating in Europe, a CNN will seek to detect European sirens, and when in North America, a CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program may be used to execute an emergency vehicle safety routine, slowing a vehicle, pulling over to a side of a road, parking a vehicle, and / or idling a vehicle, with assistance of ultrasonic sensor(s) 1162, until emergency vehicles pass.

[0226] In at least one embodiment, vehicle 1100 may include CPU(s) 1118 (e.g., discrete CPU(s), or dCPU(s)), that may be coupled to SoC(s) 1104 via a high-speed interconnect (e g., PCIe). In at least one embodiment, CPU(s) 1118 may include an X86 processor, for example. CPU(s) 1118 may be used to perform any of a variety of functions, including arbitrating potentially inconsistent results between ADAS sensors and SoC(s) 1104, and / or monitoring status and health of controller(s) 1136 and / or an infotainment system on a chip (“infotainment SoC”) 1130, for example. 16 05 23

[0227] In at least one embodiment, vehicle 1100 may include GPU(s) 1120 (e.g., discrete GPU(s), or dGPU(s)), that may be coupled to SoC(s) 1104 via a high-speed interconnect (e.g., NVIDIA’s (RTM) NVLINK channel). In at least one embodiment, GPU(s) 1120 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on input (e.g., sensor data) from sensors of a vehicle 1100.

[0228] In at least one embodiment, vehicle 1100 may further include network interface 1124 which may include, without limitation, wireless antenna(s) 1126 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth (RTM) antenna, etc.). In at least one embodiment, network interface 1124 may be used to enable wireless connectivity to Internet cloud services (e.g., with server(s) and / or other network devices), with other vehicles, and / or with computing devices (e.g., client devices of passengers). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 110 and another vehicle and / or an indirect link may be established (e.g., across networks and over the Internet). In at least one embodiment, direct links may be provided using a vehicle-to-vehicle communication link. In at least one embodiment, a vehicle-to-vehicle communication link may provide vehicle 1100 information about vehicles in proximity to vehicle 1100 (e.g., vehicles in front of, on a side of, and / or behind vehicle 1100). In at least one embodiment, such aforementioned functionality may be part of a cooperative adaptive cruise control functionality of vehicle 1100.

[0229] In at least one embodiment, network interface 1124 may include an SoC that provides modulation and demodulation functionality and enables controller(s) 1136 to communicate over wireless networks. In at least one embodiment, network interface 1124 may include a radio frequency front-end for up-conversion from baseband to radio frequency, and down conversion from radio frequency to baseband. In at least one embodiment, frequency conversions may be performed in any technically feasible fashion. For example, frequency conversions could be performed through well-known processes, and / or using super-heterodyne processes. In at least one embodiment, radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, network interfaces may include wireless functionality for communicating over LTE (RTM), WCDMA, UMTS, GSM (RTM), CDMA2000, Bluetooth 16 05 23 (RTM), Bluetooth (RTM) LE, Wi-Fi (RTM), Z-Wave (RTM), ZigBee (RTM), LoRaWAN (RTM), and / or other wireless protocols.

[0230] In at least one embodiment, vehicle 1100 may further include data store(s) 1128 which may include, without limitation, off-chip (e.g., off SoC(s) 1104) storage. In at least one embodiment, data store(s) 1128 may include, without limitation, one or more storage elements including RAM, SRAM, dynamic random-access memory (“DRAM”), video random-access memory (“VRAM”), flash memory, hard disks, and / or other components and / or devices that may store at least one bit of data. [0231 ] In at least one embodiment, vehicle 1100 may further include GNSS sensor(s) 1158 (e.g., GPS and / or assisted GPS sensors), to assist in mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensor(s) 1158 may be used, including, for example and without limitation, a GPS using a USB connector with an Ethernet-to-Serial (e.g., RS-232) bridge. [02321 In at least one embodiment, vehicle 1100 may further include RADAR sensor(s) 1160. In at least one embodiment, RADAR sensor(s) 1160 may be used by vehicle 1100 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, RADAR functional safety levels may be ASIL B. In at least one embodiment, RADAR sensor(s) 1160 may use a CAN bus and / or bus 1102 (e.g., to transmit data generated by RADAR sensor(s) 1160) for control and to access object tracking data, with access to Ethernet channels to access raw data in some examples. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, and without limitation, RADAR sensor(s) 1160 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more sensor of RADAR sensors(s) 1160 is a Pulse Doppler RADAR sensor.

[0233] In at least one embodiment, RADAR sensor(s) 1160 may include different configurations, such as long-range with narrow field of view, short-range with wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR may be used for adaptive cruise control functionality. In at least one embodiment, long-range RADAR systems may provide a broad field of view realized by two or more independent scans, such as within a 250 m (meter) range. In at least one embodiment, RADAR sensor(s) 1160 may help in distinguishing between static and moving objects, and may be used by ADAS system 1138 for 16 05 23 emergency brake assist and forward collision warning. In at least one embodiment, sensors 1160(s) included in a long-range RADAR system may include, without limitation, monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennae and a high-speed CAN and FlexRay interface. In at least one embodiment, with six antennae, a central four antennae may create a focused beam pattern, designed to record vehicle’s 1100 surroundings at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, another two antennae may expand field of view, making it possible to quickly detect vehicles entering or leaving a lane of vehicle 1100.

[0234] In at least one embodiment, mid-range RADAR systems may include, as an example, a range of up to 160 m (front) or 80 m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, short-range RADAR systems may include, without limitation, any number of RADAR sensor(s) 1160 designed to be installed at both ends of a rear bumper. When installed at both ends of a rear bumper, in at least one embodiment, a RADAR sensor system may create two beams that constantly monitor blind spots in a rear direction and next to a vehicle. In at least one embodiment, short-range RADAR systems may be used m ADAS system 1138 for blind spot detection and / or lane change assist.

[0235] In at least one embodiment, vehicle 1100 may further include ultrasonic sensor(s) 1162. In at least one embodiment, ultrasonic sensor(s) 1162, which may be positioned at a front, a back, and / or side location of vehicle 1100, may be used for parking assist and / or to create and update an occupancy grid. In at least one embodiment, a wide variety of ultrasonic sensor(s) 1162 may be used, and different ultrasonic sensor(s) 1162 may be used for different ranges of detection (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensor(s) 1162 may operate at functional safety levels of ASIL B.

[0236] In at least one embodiment, vehicle 1100 may include LIDAR sensor(s) 1164. In at least one embodiment, LIDAR sensor(s) 1164 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, LIDAR sensor(s) 1164 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 1100 may include multiple LIDAR sensors 1164 (e.g., two, four, six, etc.) that may use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch). 16 05 23

[0237] In at least one embodiment, LIDAR sensor(s) 1164 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available LIDAR sensor(s) 1164 may have an advertised range of approximately 100 m, with an accuracy of 2 cm to 3 cm, and with support for a 100 Mbps Ethernet connection, for example. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, LIDAR sensor(s) 1164 may include a small device that may be embedded into a front, a rear, a side, and / or a corner location of vehicle 1100. In at least one embodiment, LIDAR sensor(s) 1164, in such an embodiment, may provide up to a 120-degree horizontal and 35-degree vertical field-of-view, with a 200 m range even for low-reflectivity objects. In at least one embodiment, front-mounted LIDAR sensor(s) 1164 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0238] In at least one embodiment, LIDAR technologies, such as 3D flash LIDAR, may also be used. In at least one embodiment, 3D flash LIDAR uses a flash of a laser as a transmission source, to illuminate surroundings of vehicle 1100 up to approximately 200 m. In at least one embodiment, a flash LIDAR unit includes, without limitation, a receptor, which records laser pulse transit time and reflected light on each pixel, which in turn corresponds to a range from vehicle 1100 to objects. In at least one embodiment, flash LIDAR may allow for highly accurate and distortion-free images of surroundings to be generated with every laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one at each side of vehicle 1100. In at least one embodiment, 3D flash LIDAR systems include, without limitation, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, flash LIDAR device may use a 5 nanosecond class I (eye-safe) laser pulse per frame and may capture reflected laser light as a 3D range point cloud and co-registered intensity data.

[0239] In at least one embodiment, vehicle 1100 may further include IMU sensor(s) 1166. In at least one embodiment, IMU sensor(s) 1166 may be located at a center of a rear axle of vehicle 1100. In at least one embodiment, IMU sensor(s) 1166 may include, for example and without limitation, accelerometer(s), magnetometer(s), gyroscope(s), a magnetic compass, magnetic compasses, and / or other sensor types. In at least one embodiment, such as in six-axis 16 05 23 applications, IMU sensor(s) 1166 may include, without limitation, accelerometers and gyroscopes. In at least one embodiment, such as in nine-axis applications, IMU sensor(s) 1166 may include, without limitation, accelerometers, gyroscopes, and magnetometers.

[0240] In at least one embodiment, IMU sensor(s) 1166 may be implemented as a miniature, high performance GPS-Aided Inertial Navigation System (“GPS / INS”) that combines micro-electro-mechanical systems (“MEMS”) inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, IMU sensor(s) 1166 may enable vehicle 1100 to estimate its heading without requiring input from a magnetic sensor by directly observing and correlating changes in velocity from a GPS to IMU sensor(s) 1166. In at least one embodiment, IMU sensor(s) 1166 and GNSS sensor(s) 1158 may be combined in a single integrated unit. [0241 ] In at least one embodiment, vehicle 1100 may include microphone(s) 1196 placed in and / or around vehicle 1100. In at least one embodiment, microphone(s) 1196 may be used for emergency vehicle detection and identification, among other things.

[0242] In at least one embodiment, vehicle 1100 may further include any number of camera types, including stereo camera(s) 1168, wide-view camera(s) 1170, infrared camera(s) 1172, surround camera(s) 1174, long-range camera(s) 1198, mid-range camera(s) 1176, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around an entire periphery of vehicle 1100. In at least one embodiment, which types of cameras used depends on vehicle 1100. In at least one embodiment, any combination of camera types may be used to provide necessary coverage around vehicle 1100. In at least one embodiment, a number of cameras deployed may differ depending on embodiment. For example, in at least one embodiment, vehicle 1100 could include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, cameras may support, as an example and without limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet communications. In at least one embodiment, each camera might be as described with more detail previously herein with respect to FIG. 11A and FIG. 1 IB.

[0243] In at least one embodiment, vehicle 1100 may further include vibration sensor(s) 1142. In at least one embodiment, vibration sensor(s) 1142 may measure vibrations of components of vehicle 1100, such as axle(s). For example, in at least one embodiment, changes in vibrations 16 05 23 may indicate a change in road surfaces. In at least one embodiment, when two or more vibration sensors 1142 are used, differences between vibrations may be used to determine friction or slippage of road surface (e.g., when a difference in vibration is between a power-driven axle and a freely rotating axle).

[0244] In at least one embodiment, vehicle 1100 may include ADAS system 1138. In at least one embodiment, ADAS system 1138 may include, without limitation, an SoC, in some examples. In at least one embodiment, ADAS system 1138 may include, without limitation, any number and combination of an autonomous / adaptive / automatic cruise control (“ACC”) system, a cooperative adaptive cruise control (“CACC”) system, a forward crash warning (“FCW”) system, an automatic emergency braking (“AEB”) system, a lane departure warning (“LDW)” system, a lane keep assist (“LKA”) system, a blind spot warning (“BSW”) system, a rear cross-traffic warning (“RCTW”) system, a collision warning (“CW”) system, a lane centering (“LC”) system, and / or other systems, features, and / or functionality.

[0245] In at least one embodiment, ACC system may use RADAR sensor(s) 1160, LIDAR sensor(s) 1164, and / or any number of camera(s). In at least one embodiment, ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, a longitudinal ACC system monitors and controls distance to another vehicle immediately ahead of vehicle 1100 and automatically adjusts speed of vehicle 1100 to maintain a safe distance from vehicles ahead. In at least one embodiment, a lateral ACC system performs distance keeping, and advises vehicle 1100 to change lanes when necessary. In at least one embodiment, a lateral ACC is related to other ADAS applications, such as LC and CW.

[0246] In at least one embodiment, a CACC system uses information from other vehicles that may be received via network interface 1124 and / or wireless antenna(s) 1126 from other vehicles via a wireless link, or indirectly, over a network connection (e.g., over the Internet). In at least one embodiment, direct links may be provided by a vehicle-to-vehicle (“V2V”) communication link, while indirect links may be provided by an infrastructure-to-vehicle (“I2V”) communication link. In general, V2V communication provides information about immediately preceding vehicles (e.g., vehicles immediately ahead of and in same lane as vehicle 1100), while I2V communication provides information about traffic further ahead. In at least one embodiment, a CACC system may include either or both I2V and V2V information sources. In at least one 16 05 23 embodiment, given information of vehicles ahead of vehicle 1100, a CACC system may be more reliable and it has potential to improve traffic flow smoothness and reduce congestion on road.

[0247] In at least one embodiment, an FCW system is designed to alert a driver to a hazard, so that such driver may take corrective action. In at least one embodiment, an FCW system uses a front-facing camera and / or RADAR sensor(s) 1160, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibrating component. In at least one embodiment, an FCW system may provide a warning, such as in form of a sound, visual warning, vibration and / or a quick brake pulse.

[0248] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object, and may automatically apply brakes if a driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, AEB system may use front-facing camera(s) and / or RADAR sensor(s) 1160, coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when an AEB system detects a hazard, it will typically first alert a driver to take corrective action to avoid collision and, if that driver does not take corrective action, that AEB system may automatically apply brakes in an effort to prevent, or at least mitigate, an impact of a predicted collision. In at least one embodiment, an AEB system may include techniques such as dynamic brake support and / or crash imminent braking.

[0249] In at least one embodiment, an LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert driver when vehicle 1100 crosses lane markings. In at least one embodiment, an LDW system does not activate when a driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, an LDW system may use front-side facing cameras, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibrating component. In at least one embodiment, an LKA system is a variation of an LDW system. In at least one embodiment, an LKA system provides steering input or braking to correct vehicle 1100 if vehicle 1100 starts to exit its lane.

[0250] In at least one embodiment, a BSW system detects and warns a driver of vehicles in an automobile’s blind spot. In at least one embodiment, a BSW system may provide a visual, audible, and / or tactile alert to indicate that merging or changing lanes is unsafe. In at least one 16 05 23 embodiment, a BSW system may provide an additional warning when a driver uses a turn signal. In at least one embodiment, a BSW system may use rear-side facing camera(s) and / or RADAR sensor(s) 1160, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to driver feedback, such as a display, speaker, and / or vibrating component. [0251 ] In at least one embodiment, an RCTW system may provide visual, audible, and / or tactile notification when an object is detected outside a rear-camera range when vehicle 1100 is backing up. In at least one embodiment, an RCTW system includes an AEB system to ensure that vehicle brakes are applied to avoid a crash. In at least one embodiment, an RCTW system may use one or more rear-facing RADAR sensor(s) 1160, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, that is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibrating component. [0252 ] In at least one embodiment, conventional ADAS systems may be prone to false positive results which may be annoying and distracting to a driver, but typically are not catastrophic, because conventional ADAS systems alert a driver and allow that driver to decide whether a safety condition truly exists and act accordingly. In at least one embodiment, vehicle 1100 itself decides, in case of conflicting results, whether to heed result from a primary computer or a secondary computer (e.g., a first controller or a second controller of controllers 1136). For example, in at least one embodiment, ADAS system 1138 may be a backup and / or secondary computer for providing perception information to a backup computer rationality module. In at least one embodiment, a backup computer rationality monitor may run redundant diverse software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, outputs from ADAS system 1138 may be provided to a supervisory MCU. In at least one embodiment, if outputs from a primary computer and outputs from a secondary computer conflict, a supervisory MCU determines how to reconcile conflict to ensure safe operation.

[0253] In at least one embodiment, a primary computer may be configured to provide a supervisory MCU with a confidence score, indicating that primary computer’s confidence in a chosen result. In at least one embodiment, if that confidence score exceeds a threshold, that supervisory MCU may follow that primary computer’s direction, regardless of whether that secondary computer provides a conflicting or inconsistent result. In at least one embodiment, 16 05 23 where a confidence score does not meet a threshold, and where primary and secondary computers indicate different results (e.g., a conflict), a supervisory MCU may arbitrate between computers to determine an appropriate outcome.

[0254] In at least one embodiment, a supervisory MCU may be configured to run a neural network(s) that is trained and configured to determine, based at least in part on outputs from a primary computer and outputs from a secondary computer, conditions under which that secondary computer provides false alarms. In at least one embodiment, neural network(s) in a supervisory MCU may learn when a secondary computer’s output may be trusted, and when it cannot. For example, in at least one embodiment, when that secondary computer is a RADAR-based FCW system, a neural network(s) in that supervisory MCU may learn when an FCW system is identifying metallic objects that are not, in fact, hazards, such as a drainage grate or manhole cover that triggers an alarm. In at least one embodiment, when a secondary computer is a camera-based LDW system, a neural network in a supervisory MCU may learn to override LDW when bicyclists or pedestrians are present and a lane departure is, in fact, a safest maneuver. In at least one embodiment, a supervisory MCU may include at least one of a DLA or a GPU suitable for running neural network(s) with associated memory. In at least one embodiment, a supervisory MCU may comprise and / or be included as a component of SoC(s) 1104.

[0255] In at least one embodiment, ADAS system 1138 may include a secondary computer that performs ADAS functionality using traditional rules of computer vision. In at least one embodiment, that secondary computer may use classic computer vision rules (if-then), and presence of a neural network(s) in a supervisory MCU may improve reliability, safety and performance. For example, in at least one embodiment, diverse implementation and intentional non-identity makes an overall system more fault-tolerant, especially to faults caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a software bug or error in software running on a primary computer, and non-identical software code running on a secondary computer provides a consistent overall result, then a supervisory MCU may have greater confidence that an overall result is correct, and a bug in software or hardware on that primary computer is not causing a material error. 16 05 23

[0256] In at least one embodiment, an output of ADAS system 1138 may be fed into a primary computer’s perception block and / or a primary computer’s dynamic driving task block. For example, in at least one embodiment, if ADAS system 1138 indicates a forward crash warning due to an object immediately ahead, a perception block may use this information when identifying objects. In at least one embodiment, a secondary computer may have its own neural network that is trained and thus reduces a risk of false positives, as described herein.

[0257] In at least one embodiment, vehicle 1100 may further include infotainment SoC 1130 (e.g., an in-vehicle infotainment system (IVI)). Although illustrated and described as an SoC, infotainment system SoC 1130, in at least one embodiment, may not be an SoC, and may include, without limitation, two or more discrete components. In at least one embodiment, infotainment SoC 1130 may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, a personal digital assistant, navigational instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE (RTM), WiFi (RTM), etc.), and / or information services (e.g., navigation systems, rear-parking assistance, a radio data system, vehicle related information such as fuel level, total distance covered, brake fuel level, oil level, door open / close, air filter information, etc.) to vehicle 1100. For example, infotainment SoC 1130 could include radios, disk players, navigation systems, video players, USB and Bluetooth (RTM) connectivity, carputers, in-car entertainment, WiFi (RTM), steering wheel audio controls, hands free voice control, a heads-up display (“HUD”), HMI display 1134, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 1130 may further be used to provide information (e.g., visual and / or audible) to user(s) of vehicle 1100, such as information from ADAS system 1138, autonomous driving information such as planned vehicle maneuvers, trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information. [0258 ] In at least one embodiment, infotainment SoC 1130 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 1130 may communicate over bus 1102 with other devices, systems, and / or components of vehicle 1100. In at least one embodiment, infotainment SoC 1130 may be coupled to a supervisory MCU such that a GPU of 16 05 23 an infotainment system may perform some self-driving functions in event that primary controller(s) 1136 (e.g., primary and / or backup computers of vehicle 1100) fail. In at least one embodiment, infotainment SoC 1130 may put vehicle 1100 into a chauffeur to safe stop mode, as described herein.

[0259] In at least one embodiment, vehicle 1100 may further include instrument cluster 1132 (e.g., a digital dash, an electronic instrument cluster, a digital instrument panel, etc.). In at least one embodiment, instrument cluster 1132 may include, without limitation, a controller and / or supercomputer (e g., a discrete controller or supercomputer). In at least one embodiment, instrument cluster 1132 may include, without limitation, any number and combination of a set of instrumentation such as a speedometer, fuel level, oil pressure, tachometer, odometer, turn indicators, gearshift position indicator, seat belt warning light(s), parking-brake warning light(s), engine-malfunction light(s), supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared among infotainment SoC 1130 and instrument cluster 1132. In at least one embodiment, instrument cluster 1132 may be included as part of infotainment SoC 1130, or vice versa.

[0260] Inference and / or training logic 815 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are provided herein in conjunction with FIGS. 8A and / or 8B. In at least one embodiment, inference and / or training logic 815 may be used in system FIG. 1 IC for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0261] FIG. 1 ID is a diagram of a system for communication between cloud-based server(s) and autonomous vehicle 1100 of FIG. 11A, according to at least one embodiment. In at least one embodiment, system may include, without limitation, server(s) 1178, network(s) 1190, and any number and type of vehicles, including vehicle 1100. In at least one embodiment, server(s) 1178 may include, without limitation, a plurality of GPUs 1184(A)-1184(H) (collectively referred to herein as GPUs 1184), PCIe switches 1182(A)-1182(D) (collectively referred to herein as PCIe switches 1182), and / or CPUs 1180(A)-! 180(B) (collectively referred to herein as CPUs 1180). In 16 05 23 at least one embodiment, GPUs 1184, CPUs 1180, and PCIe switches 1182 may be interconnected with high-speed interconnects such as, for example and without limitation, NVLink interfaces 1188 developed by NVIDIA (RTM) and / or PCIe connections 1186. In at least one embodiment, GPUs 1184 are connected via an NVLink and / or NVSwitch SoC and GPUs 1184 and PCIe switches 1182 are connected via PCIe interconnects. Although eight GPUs 1184, two CPUs 1180, and four PCIe switches 1182 are illustrated, this is not intended to be limiting. In at least one embodiment, each of server(s) 1178 may include, without limitation, any number of GPUs 1184, CPUs 1180, and / or PCIe switches 1182, in any combination. For example, in at least one embodiment, server(s) 1178 could each include eight, sixteen, thirty-two, and / or more GPUs 1184.

[0262] In at least one embodiment, server(s) 1178 may receive, over network(s) 1190 and from vehicles, image data representative of images showing unexpected or changed road conditions, such as recently commenced road-work. In at least one embodiment, server(s) 1178 may transmit, over network(s) 1190 and to vehicles, neural networks 1192, updated or otherwise, and / or map information 1194, including, without limitation, information regarding traffic and road conditions. In at least one embodiment, updates to map information 1194 may include, without limitation, updates for HD map 1122, such as information regarding construction sites, potholes, detours, flooding, and / or other obstructions. In at least one embodiment, neural networks 1192, and / or map information 1194 may have resulted from new training and / or experiences represented in data received from any number of vehicles in an environment, and / or based at least in part on training performed at a data center (e.g., using server(s) 1178 and / or other servers).

[0263] In at least one embodiment, server(s) 1178 may be used to train machine learning models (e.g., neural networks) based at least in part on training data. In at least one embodiment, training data may be generated by vehicles, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is tagged (e.g., where associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, any amount of training data is not tagged and / or pre-processed (e.g., where associated neural network does not require supervised learning). In at least one embodiment, once machine learning models are trained, machine learning models may 16 05 23 be used by vehicles (e.g., transmitted to vehicles over network(s) 1190), and / or machine learning models may be used by server(s) 1178 to remotely monitor vehicles.

[0264] In at least one embodiment, server(s) 1178 may receive data from vehicles and apply data to up-to-date real-time neural networks for real-time intelligent inferencing. In at least one embodiment, server(s) 1178 may include deep-learning supercomputers and / or dedicated AI computers powered by GPU(s) 1184, such as a DGX and DGX Station machines developed by NVIDIA (RTM). However, in at least one embodiment, server(s) 1178 may include deep learning infrastructure that uses CPU-powered data centers.

[0265] In at least one embodiment, deep-learning infrastructure of server(s) 1178 may be capable of fast, real-time inferencing, and may use that capability to evaluate and verify health of processors, software, and / or associated hardware in vehicle 1100. For example, in at least one embodiment, deep-learning infrastructure may receive periodic updates from vehicle 1100, such as a sequence of images and / or objects that vehicle 1100 has located in that sequence of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, deep-learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 1100 and, if results do not match and deep-learning infrastructure concludes that AI in vehicle 1100 is malfunctioning, then server(s) 1178 may transmit a signal to vehicle 1100 instructing a fail-safe computer of vehicle 1100 to assume control, notify passengers, and complete a safe parking maneuver.

[0266] In at least one embodiment, server(s) 1178 may include GPU(s) 1184 and one or more programmable inference accelerators (e.g., NVIDIA’s (RTM) TensorRT 3 devices). In at least one embodiment, a combination of GPU-powered servers and inference acceleration may make real-time responsiveness possible. In at least one embodiment, such as where performance is less critical, servers powered by CPUs, FPGAs, and other processors may be used for inferencing. In at least one embodiment, hardware structure(s) 815 are used to perform one or more embodiments. Details regarding hardware structure(x) 815 are provided herein in conjunction with FIGS. 8A and / or 8B.

[0267] In at least one embodiment, one or more systems depicted in FIGS. 11 A-l ID are utilized to train a neural network to perform object detection, instance segmentation, and semantic correspondence with bounding box annotations. In at least one embodiment, one or 16 05 23 more systems depicted in FIGS. 11 A-l ID are utilized to implement a framework for object detection, instance segmentation, and semantic correspondence. In at least one embodiment, one or more systems depicted in FIGS. 11 A-l ID are utilized to implement one or more networks and processes such as those described in connection with FIGS. 1-7. COMPUTER SYSTEMS [0268 ] FIG. 12 is a block diagram illustrating an exemplary computer system, which may be a system with interconnected devices and components, a system-on-a-chip (SOC) or some combination thereof formed with a processor that may include execution units to execute an instruction, according to at least one embodiment. In at least one embodiment, a computer system 1200 may include, without limitation, a component, such as a processor 1202 to employ execution units including logic to perform algorithms for process data, in accordance with present disclosure, such as in embodiment described herein. In at least one embodiment, computer system 1200 may include processors, such as PENTIUM® Processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™. Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes and like) may also be used. In at least one embodiment, computer system 1200 may execute a version of WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux, for example), embedded software, and / or graphical user interfaces, may also be used.

[0269] Embodiments may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor (“DSP”), system on a chip, network computers (“NetPCs”), set-top boxes, network hubs, wide area network (“WAN”) switches, or any other system that may perform one or more instructions in accordance with at least one embodiment.

[0270] In at least one embodiment, computer system 1200 may include, without limitation, processor 1202 that may include, without limitation, one or more execution units 1208 to perform machine learning model training and / or inferencing according to techniques described 16 05 23 herein. In at least one embodiment, computer system 1200 is a single processor desktop or server system, but in another embodiment, computer system 1200 may be a multiprocessor system. In at least one embodiment, processor 1202 may include, without limitation, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, for example. In at least one embodiment, processor 1202 may be coupled to a processor bus 1210 that may transmit data signals between processor 1202 and other components in computer system 1200.

[0271] In at least one embodiment, processor 1202 may include, without limitation, a Level 1 (“LI”) internal cache memory (“cache”) 1204. In at least one embodiment, processor 1202 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 1202. Other embodiments may also include a combination of both internal and external caches depending on particular implementation and needs. In at least one embodiment, a register file 1206 may store different types of data in various registers including, without limitation, integer registers, floating point registers, status registers, and an instruction pointer register.

[0272] In at least one embodiment, execution unit 1208, including, without limitation, logic to perform integer and floating point operations, also resides in processor 1202. In at least one embodiment, processor 1202 may also include a microcode (“ucode”) read only memory (“ROM”) that stores microcode for certain macro instructions. In at least one embodiment, execution unit 1208 may include logic to handle a packed instruction set 1209. In at least one embodiment, by including packed instruction set 1209 in an instruction set of a general-purpose processor, along with associated circuitry to execute instructions, operations used by many multimedia applications may be performed using packed data in processor 1202. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using a full width of a processor’s data bus for performing operations on packed data, which may eliminate a need to transfer smaller units of data across that processor’s data bus to perform one or more operations one data element at a time. 16 05 23

[0273] In at least one embodiment, execution unit 1208 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1200 may include, without limitation, a memory 1220. In at least one embodiment, memory 1220 may be a Dynamic Random Access Memory (“DRAM”) device, a Static Random Access Memory (“SRAM”) device, a flash memory device, or another memory device. In at least one embodiment, memory 1220 may store instruction(s) 1219 and / or data 1221 represented by data signals that may be executed by processor 1202.

[0274] In at least one embodiment, a system logic chip may be coupled to processor bus 1210 and memory 1220. In at least one embodiment, a system logic chip may include, without limitation, a memory controller hub (“MCH”) 1216, and processor 1202 may communicate with MCH 1216 via processor bus 1210. In at least one embodiment, MCH 1216 may provide a high bandwidth memory path 1218 to memory 1220 for instruction and data storage and for storage of graphics commands, data and textures. In at least one embodiment, MCH 1216 may direct data signals between processor 1202, memory 1220, and other components in computer system 1200 and to bridge data signals between processor bus 1210, memory 1220, and a system I / O interface 1222. In at least one embodiment, a system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1216 may be coupled to memory 1220 through high bandwidth memory path 1218 and a graphics / video card 1212 may be coupled to MCH 1216 through an Accelerated Graphics Port (“AGP”) interconnect 1214.

[0275] In at least one embodiment, computer system 1200 may use system I / O interface 1222 as a proprietary hub interface bus to couple MCH 1216 to an I / O controller hub (“ICH”) 1230. In at least one embodiment, ICH 1230 may provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, a local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 1220, a chipset, and processor 1202. Examples may include, without limitation, an audio controller 1229, a firmware hub (“flash BIOS”) 1228, a wireless transceiver 1226, a data storage 1224, a legacy I / O controller 1223 containing user input and keyboard interfaces 1225, a serial expansion port 1227, such as a Universal Serial Bus (“USB”) port, and a network controller 1234. In at least one embodiment, data storage 1224 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device. 16 05 23

[0276] In at least one embodiment, FIG. 12 illustrates a system, which includes interconnected hardware devices or “chips”, whereas in other embodiments, FIG. 12 may illustrate an exemplary SoC. In at least one embodiment, devices illustrated in FIG. 12 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components of computer system 1200 are interconnected using compute express link (CXL) interconnects.

[0277] Inference and / or training logic 815 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are provided herein in conjunction with FIGS. 8A and / or 8B. In at least one embodiment, inference and / or training logic 815 may be used in system FIG. 12 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0278] In at least one embodiment, one or more systems depicted m FIG. 12 are utilized to train a neural network to perform object detection, instance segmentation, and semantic correspondence with bounding box annotations. In at least one embodiment, one or more systems depicted in FIG. 12 are utilized to implement a framework for object detection, instance segmentation, and semantic correspondence. In at least one embodiment, one or more systems depicted in FIG. 12 are utilized to implement one or more networks and processes such as those described in connection with FIGS. 1-7.

[0279] FIG. 13 is a block diagram illustrating an electronic device 1300 for utilizing a processor 1310, according to at least one embodiment. In at least one embodiment, electronic device 1300 may be, for example and without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0280] In at least one embodiment, electronic device 1300 may include, without limitation, processor 1310 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 1310 is coupled using a bus or interface, such as a I2C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial 16 05 23 Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 13 illustrates a system, which includes interconnected hardware devices or “chips”, whereas in other embodiments, FIG. 13 may illustrate an exemplary SoC. In at least one embodiment, devices illustrated in FIG. 13 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components of FIG. 13 are interconnected using compute express link (CXL) interconnects. [0281 ] In at least one embodiment, FIG. 13 may include a display 1324, a touch screen 1325, a touch pad 1330, a Near Field Communications unit (“NFC”) 1345, a sensor hub 1340, a thermal sensor 1346, an Express Chipset (“EC”) 1335, a Trusted Platform Module (“TPM”) 1338, BlOS / firmware / flash memory (“BIOS, FW Flash”) 1322, a DSP 1360, a drive 1320 such as a Solid State Disk (“SSD”) or a Hard Disk Drive (“HDD”), a wireless local area network unit (“WLAN”) 1350, a Bluetooth (RTM) unit 1352, a Wireless Wide Area Network unit (“WWAN”) 1356, a Global Positioning System (GPS) unit 1355, a camera (“USB 3.0 camera”) 1354 such as a USB 3.0 camera, and / or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1315 implemented in, for example, an LPDDR3 standard. These components may each be implemented in any suitable manner.

[0282] In at least one embodiment, other components may be communicatively coupled to processor 1310 through components described herein. In at least one embodiment, an accelerometer 1341, an ambient light sensor (“ALS”) 1342, a compass 1343, and a gyroscope 1344 may be communicatively coupled to sensor hub 1340. In at least one embodiment, a thermal sensor 1339, a fan 1337, a keyboard 1336, and touch pad 1330 may be communicatively coupled to EC 1335. In at least one embodiment, speakers 1363, headphones 1364, and a microphone (“mic”) 1365 may be communicatively coupled to an audio unit (“audio codec and class D amp”) 1362, which may in turn be communicatively coupled to DSP 1360. In at least one embodiment, audio unit 1362 may include, for example and without limitation, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”) 1357 may be communicatively coupled to WWAN unit 1356. In at least one 16 05 23 embodiment, components such as WLAN unit 1350 and Bluetooth (RTM) unit 1352, as well as WWAN unit 1356 may be implemented in a Next Generation Form Factor (“NGFF”).

[0283] Inference and / or training logic 815 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are provided herein in conjunction with FIGS. 8A and / or 8B. In at least one embodiment, inference and / or training logic 815 may be used in system FIG. 13 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0284] In at least one embodiment, one or more systems depicted in FIG. 13 are utilized to train a neural network to perform object detection, instance segmentation, and semantic correspondence with bounding box annotations. In at least one embodiment, one or more systems depicted in FIG. 13 are utilized to implement a framework for object detection, instance segmentation, and semantic correspondence. In at least one embodiment, one or more systems depicted in FIG. 13 are utilized to implement one or more networks and processes such as those described in connection with FIGS. 1-7.

[0285] FIG. 14 illustrates a computer system 1400, according to at least one embodiment. In at least one embodiment, computer system 1400 is configured to implement various processes and methods described throughout this disclosure.

[0286] In at least one embodiment, computer system 1400 comprises, without limitation, at least one central processing unit (“CPU”) 1402 that is connected to a communication bus 1410 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), peripheral component interconnect express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol(s). In at least one embodiment, computer system 1400 includes, without limitation, a main memory 1404 and control logic (e.g., implemented as hardware, software, or a combination thereof) and data are stored in main memory 1404, which may take form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1422 provides an interface to other computing devices and networks for receiving data from and transmitting data to other systems with computer system 1400. 16 05 23

[0287] In at least one embodiment, computer system 1400, in at least one embodiment, includes, without limitation, input devices 1408, a parallel processing system 1412, and display devices 1406 that can be implemented using a conventional cathode ray tube (“CRT”), a liquid crystal display (“LCD”), a light emitting diode (“LED”) display, a plasma display, or other suitable display technologies. In at least one embodiment, user input is received from input devices 1408 such as keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, each module described herein can be situated on a single semiconductor platform to form a processing system.

[0288] Inference and / or training logic 815 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are provided herein in conjunction with FIGS. 8A and / or 8B. In at least one embodiment, inference and / or training logic 815 may be used in system FIG. 14 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0289] In at least one embodiment, one or more systems depicted in FIG. 14 are utilized to train a neural network to perform object detection, instance segmentation, and semantic correspondence with bounding box annotations. In at least one embodiment, one or more systems depicted in FIG. 14 are utilized to implement a framework for object detection, instance segmentation, and semantic correspondence. In at least one embodiment, one or more systems depicted in FIG. 14 are utilized to implement one or more networks and processes such as those described in connection with FIGS. 1-7.

[0290] FIG. 15 illustrates a computer system 1500, according to at least one embodiment. In at least one embodiment, computer system 1500 includes, without limitation, a computer 1510 and a USB stick 1520. In at least one embodiment, computer 1510 may include, without limitation, any number and type of processor(s) (not shown) and a memory (not shown). In at least one embodiment, computer 1510 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[0291] In at least one embodiment, USB stick 1520 includes, without limitation, a processing unit 1530, a USB interface 1540, and USB interface logic 1550. In at least one embodiment, 16 05 23 processing unit 1530 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1530 may include, without limitation, any number and type of processing cores (not shown). In at least one embodiment, processing unit 1530 comprises an application specific integrated circuit (“ASIC”) that is optimized to perform any amount and type of operations associated with machine learning. For instance, in at least one embodiment, processing unit 1530 is a tensor processing unit (“TPC”) that is optimized to perform machine learning inference operations. In at least one embodiment, processing unit 1530 is a vision processing unit (“VPU”) that is optimized to perform machine vision and machine learning inference operations.

[0292] In at least one embodiment, USB interface 1540 may be any type of USB connector or USB socket. For instance, in at least one embodiment, USB interface 1540 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1540 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1550 may include any amount and type of logic that enables processing unit 1530 to interface with devices (e.g., computer 1510) via USB connector 1540.

[0293] Inference and / or training logic 815 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are provided herein in conjunction with FIGS. 8A and / or 8B. In at least one embodiment, inference and / or training logic 815 may be used in system FIG. 15 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0294] In at least one embodiment, one or more systems depicted in FIG. 15 are utilized to train a neural network to perform object detection, instance segmentation, and semantic correspondence with bounding box annotations. In at least one embodiment, one or more systems depicted in FIG. 15 are utilized to implement a framework for object detection, instance segmentation, and semantic correspondence. In at least one embodiment, one or more systems depicted in FIG. 15 are utilized to implement one or more networks and processes such as those described in connection with FIGS. 1-7. 16 05 23

[0295] FIG. 16A illustrates an exemplary architecture in which a plurality of GPUs 1610(l)-1610(N) is communicatively coupled to a plurality of multi-core processors 1605(1)-1605(M) over high-speed links 1640(1 )-1640(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, high-speed links 1640(1)-1640(N) support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s or higher. In at least one embodiment, various interconnect protocols may be used including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In various figures, “N” and “M” represent positive integers, values of which may be different from figure to figure.

[0296] In addition, and in at least one embodiment, two or more of GPUs 1610 are interconnected over high-speed links 1629(1)-1629(2), which may be implemented using similar or different protocols / links than those used for high-speed links 1640(1 )-1640(N). Similarly, two or more of multi-core processors 1605 may be connected over a high-speed link 1628 which may be symmetric multi-processor (SMP) buses operating at 20 GB / s, 30 GB / s, 120 GB / s or higher. Alternatively, all communication between various system components shown in FIG. 16A may be accomplished using similar protocols / links (e.g., over a common interconnection fabric).

[0297] In at least one embodiment, each multi-core processor 1605 is communicatively coupled to a processor memory 1601(l)-1601(M), via memory interconnects 1626(1)-1626(M), respectively, and each GPU 1610(l)-1610(N) is communicatively coupled to GPU memory 1620(1 )-1620(N) over GPU memory interconnects 1650(1 )-1650(N), respectively. In at least one embodiment, memory interconnects 1626 and 1650 may utilize similar or different memory access technologies. By way of example, and not limitation, processor memories 1601 (1)-1601(M) and GPU memories 1620 may be volatile memories such as dynamic random access memories (DRAMs) (including stacked DRAMs), Graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or High Bandwidth Memory (HBM) and / or may be non-volatile memories such as 3D XPoint or Nano-Ram. In at least one embodiment, some portion of processor memories 1601 may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0298] As described herein, although various multi-core processors 1605 and GPUs 1610 may be physically coupled to a particular memory 1601, 1620, respectively, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as 16 05 23 “effective address” space) is distributed among various physical memories. For example, processor memories 1601 (1)-1601 (M) may each comprise 64 GB of system memory address space and GPU memories 1620(1)-1620(N) may each comprise 32 GB of system memory address space resulting in a total of 256 GB addressable memory when M=2 and N=4. Other values for N and M are possible. [0299 ] FIG. 16B illustrates additional details for an interconnection between a multi-core processor 1607 and a graphics acceleration module 1646 in accordance with one exemplary embodiment. In at least one embodiment, graphics acceleration module 1646 may include one or more GPU chips integrated on a line card which is coupled to processor 1607 via high-speed link 1640 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, graphics acceleration module 1646 may alternatively be integrated on a package or chip with processor 1607. [03()0 ] In at least one embodiment, processor 1607 includes a plurality of cores 1660A-1660D, each with a translation lookaside buffer (“TLB”) 1661 A-166ID and one or more caches 1662A-1662D. In at least one embodiment, cores 1660A-1660D may include various other components for executing instructions and processing data that are not illustrated. In at least one embodiment, caches 1662A-1662D may comprise Level 1 (LI) and Level 2 (L2) caches. In addition, one or more shared caches 1656 may be included in caches 1662A-1662D and shared by sets of cores 1660A-1660D. For example, one embodiment of processor 1607 includes 24 cores, each with its own LI cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. In at least one embodiment, processor 1607 and graphics acceleration module 1646 connect with system memory 1614, which may include processor memories 1601(l)-1601(M) of FIG. 16A.

[0301] In at least one embodiment, coherency is maintained for data and instructions stored in various caches 1662A-1662D, 1656 and system memory 1614 via inter-core communication over a coherence bus 1664. In at least one embodiment, for example, each cache may have cache coherency logic / circuitry associated therewith to communicate to over coherence bus 1664 in response to detected reads or writes to particular cache lines. In at least one embodiment, a cache snooping protocol is implemented over coherence bus 1664 to snoop cache accesses. [0302 ] In at least one embodiment, a proxy circuit 1625 communicatively couples graphics acceleration module 1646 to coherence bus 1664, allowing graphics acceleration module 1646 to 16 05 23 participate in a cache coherence protocol as a peer of cores 1660A-1660D. In particular, in at least one embodiment, an interface 1635 provides connectivity to proxy circuit 1625 over high-speed link 1640 and an interface 1637 connects graphics acceleration module 1646 to high-speed link 1640.

[0303] In at least one embodiment, an accelerator integration circuit 1636 provides cache management, memory access, context management, and interrupt management services on behalf of a plurality of graphics processing engines 1631(1)-1631(N) of graphics acceleration module 1646. In at least one embodiment, graphics processing engines 1631 (1)-1631 (N) may each comprise a separate graphics processing unit (GPU). In at least one embodiment, graphics processing engines 1631 (1)-1631 (N) alternatively may comprise different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, graphics acceleration module 1646 may be a GPU with a plurality of graphics processing engines 1631 (1)-1631 (N) or graphics processing engines 1631 (1)-1631 (N) may be individual GPUs integrated on a common package, line card, or chip.

[0304] In at least one embodiment, accelerator integration circuit 1636 includes a memory management unit (MMU) 1639 for performing various memory management functions such as virtual-to-physical memory translations (also referred to as effective-to-real memory translations) and memory access protocols for accessing system memory 1614. In at least one embodiment, MMU 1639 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In at least one embodiment, a cache 1638 can store commands and data for efficient access by graphics processing engines 1631(1)-1631(N). In at least one embodiment, data stored in cache 1638 and graphics memories 1633(1)-1633(M) is kept coherent with core caches 1662A-1662D, 1656 and system memory 1614, possibly using a fetch unit 1644. As mentioned, this may be accomplished via proxy circuit 1625 on behalf of cache 1638 and memories 1633(1)- 1633(M) (e.g., sending updates to cache 1638 related to modifications / accesses of cache lines on processor caches 1662A-1662D, 1656 and receiving updates from cache 1638).

[0305] In at least one embodiment, a set of registers 1645 store context data for threads executed by graphics processing engines 1631 (1 )-1631 (N) and a context management 16 05 23 circuit 1648 manages thread contexts. For example, context management circuit 1648 may perform save and restore operations to save and restore contexts of various threads during contexts switches (e.g., where a first thread is saved and a second thread is stored so that a second thread can be execute by a graphics processing engine). For example, on a context switch, context management circuit 1648 may store current register values to a designated region in memory (e.g., identified by a context pointer). It may then restore register values when returning to a context. In at least one embodiment, an interrupt management circuit 1647 receives and processes interrupts received from system devices.

[0306] In at least one embodiment, virtual / effective addresses from a graphics processing engine 1631 are translated to real / physical addresses in system memory 1614 by MMU 1639. In at least one embodiment, accelerator integration circuit 1636 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1646 and / or other accelerator devices. In at least one embodiment, graphics accelerator module 1646 may be dedicated to a single application executed on processor 1607 or may be shared between multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which resources of graphics processing engines 1631(1)-1631(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” which are allocated to different VMs and / or applications based on processing requirements and priorities associated with VMs and / or applications.

[0307] In at least one embodiment, accelerator integration circuit 1636 performs as a bridge to a system for graphics acceleration module 1646 and provides address translation and system memory cache services. In addition, in at least one embodiment, accelerator integration circuit 1636 may provide virtualization facilities for a host processor to manage virtualization of graphics processing engines 1631(1)-1631(N), interrupts, and memory management.

[0308] In at least one embodiment, because hardware resources of graphics processing engines 1631(1)-1631(N) are mapped explicitly to a real address space seen by host processor 1607, any host processor can address these resources directly using an effective address value. In at least one embodiment, one function of accelerator integration circuit 1636 is physical separation of graphics processing engines 1631(1)-1631(N) so that they appear to a system as independent units. 16 05 23

[0309] In at least one embodiment, one or more graphics memories 1633(1)-1633(M) are coupled to each of graphics processing engines 1631(1)-1631(N), respectively and N=M. In at least one embodiment, graphics memories 1633( 1)-1633(M) store instructions and data being processed by each of graphics processing engines 1631(1)-1631(N). In at least one embodiment, graphics memories 1633( 1)-163 3(M) may be volatile memories such as DRAMs (including stacked DRAMs), GDDR memory (e g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories such as 3D XPoint or Nano-Ram.

[0310] In at least one embodiment, to reduce data traffic over high-speed link 1640, biasing techniques can be used to ensure that data stored in graphics memories 1633(1 )-1633(M) is data that will be used most frequently by graphics processing engines 1631(1 )-1631(N) and preferably not used by cores 1660A-1660D (at least not frequently). Similarly, in at least one embodiment, a biasing mechanism attempts to keep data needed by cores (and preferably not graphics processing engines 1631(1)-1631(N)) within caches 1662A-1662D, 1656 and system memory 1614. [0311 ] FIG. 16C illustrates another exemplary embodiment in which accelerator integration circuit 1636 is integrated within processor 1607. In this embodiment, graphics processing engines 1631(1)-1631(N) communicate directly over high-speed link 1640 to accelerator integration circuit 1636 via interface 1637 and interface 1635 (which, again, may be any form of bus or interface protocol). In at least one embodiment, accelerator integration circuit 1636 may perform similar operations as those described with respect to FIG. 16B, but potentially at a higher throughput given its close proximity to coherence bus 1664 and caches 1662A-1662D, 1656. In at least one embodiment, an accelerator integration circuit supports different programming models including a dedicated-process programming model (no graphics acceleration module virtualization) and shared programming models (with virtualization), which may include programming models which are controlled by accelerator integration circuit 1636 and programming models which are controlled by graphics acceleration module 1646.

[0312] In at least one embodiment, graphics processing engines 1631(1)-1631 (N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a 16 05 23 single application can funnel other application requests to graphics processing engines 1631(1)-1631(N), providing virtualization within a VM / partition.

[0313] In at least one embodiment, graphics processing engines 1631(1)-1631( N), may be shared by multiple VM / application partitions. In at least one embodiment, shared models may use a system hypervisor to virtualize graphics processing engines 1631(1)-1631(N) to allow access by each operating system. In at least one embodiment, for single-partition systems without a hypervisor, graphics processing engines 1631(1)-1631(N) are owned by an operating system. In at least one embodiment, an operating system can virtualize graphics processing engines 1631 (1)-1631 (N) to provide access to each process or application.

[0314] In at least one embodiment, graphics acceleration module 1646 or an individual graphics processing engine 1631(1)-1631(N) selects a process element using a process handle. In at least one embodiment, process elements are stored in system memory 1614 and are addressable using an effective address to real address translation technique described herein. In at least one embodiment, a process handle may be an implementation-specific value provided to a host process when registering its context with graphics processing engine 1631(1 )-1631(N) (that is, calling system software to add a process element to a process element linked list). In at least one embodiment, a lower 16-bits of a process handle may be an offset of a process element within a process element linked list.

[0315] FIG. 16D illustrates an exemplary accelerator integration slice 1690. In at least one embodiment, a “slice” comprises a specified portion of processing resources of accelerator integration circuit 1636. In at least one embodiment, an application is effective address space 1682 within system memory 1614 stores process elements 1683. In at least one embodiment, process elements 1683 are stored in response to GPU invocations 1681 from applications 1680 executed on processor 1607. In at least one embodiment, a process element 1683 contains process state for corresponding application 1680. In at least one embodiment, a work descriptor (WD) 1684 contained in process element 1683 can be a single job requested by an application or may contain a pointer to a queue of jobs. In at least one embodiment, WD 1684 is a pointer to a job request queue in an application’s effective address space 1682. 16 05 23

[0316] In at least one embodiment, graphics acceleration module 1646 and / or individual graphics processing engines 1631(1)-1631(N) can be shared by all or a subset of processes in a system. In at least one embodiment, an infrastructure for setting up process states and sending a WD 1684 to a graphics acceleration module 1646 to start a job in a virtualized environment may be included. [0317 ] In at least one embodiment, a dedicated-process programming model is implementation-specific. In at least one embodiment, in this model, a single process owns graphics acceleration module 1646 or an individual graphics processing engine 1631. In at least one embodiment, when graphics acceleration module 1646 is owned by a single process, a hypervisor initializes accelerator integration circuit 1636 for an owning partition and an operating system initializes accelerator integration circuit 1636 for an owning process when graphics acceleration module 1646 is assigned.

[0318] In at least one embodiment, in operation, a WD fetch unit 1691 in accelerator integration slice 1690 fetches next WD 1684, which includes an indication of work to be done by one or more graphics processing engines of graphics acceleration module 1646. In at least one embodiment, data from WD 1684 may be stored in registers 1645 and used by MMU 1639, interrupt management circuit 1647 and / or context management circuit 1648 as illustrated. For example, one embodiment of MMU 1639 includes segment / page walk circuitry for accessing segment / page tables 1686 within an OS virtual address space 1685. In at least one embodiment, interrupt management circuit 1647 may process interrupt events 1692 received from graphics acceleration module 1646. In at least one embodiment, when performing graphics operations, an effective address 1693 generated by a graphics processing engine 1631 (1)-1631 (N) is translated to a real address by MMU 1639.

[0319] In at least one embodiment, registers 1645 are duplicated for each graphics processing engine 1631 (1)-1631 (N) and / or graphics acceleration module 1646 and may be initialized by a hypervisor or an operating system. In at least one embodiment, each of these duplicated registers may be included in an accelerator integration slice 1690. Exemplary registers that may be initialized by a hypervisor are shown in Table 1. Table 1 - Hypervisor Initialized Registers 16 05 23 Register # Description 1 Slice Control Register 2 Real Address (RA) Scheduled Processes Area Pointer 3 Authority Mask Override Register 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector Table Entry Limit 6 State Register 7 Logical Partition ID 8 Real address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0320] Exemplary registers that may be initialized by an operating system are shown in Table 2. Table 2 - Operating System Initialized Registers Register # Description 1 Process and Thread Identification 2 Effective Address (EA) Context Save / Restore Pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) Storage Segment Table Pointer 5 Authority Mask 6 Work descriptor [0321 ] In at least one embodiment, each WD 1684 is specific to a particular graphics acceleration module 1646 and / or graphics processing engines 1631(1)-1631(N). In at least one embodiment, it contains all information required by a graphics processing engine 1631(1)-1631(N) to do work, or it can be a pointer to a memory location where an application has set up a command queue of work to be completed.

[0322] FIG. 16E illustrates additional details for one exemplary embodiment of a shared model. This embodiment includes a hypervisor real address space 1698 in which a process element list 1699 is stored. In at least one embodiment, hypervisor real address space 1698 is 16 05 23 accessible via a hypervisor 1696 which virtualizes graphics acceleration module engines for operating system 1695.

[0323] In at least one embodiment, shared programming models allow for all or a subset of processes from all or a subset of partitions in a system to use a graphics acceleration module 1646. In at least one embodiment, there are two programming models where graphics acceleration module 1646 is shared by multiple processes and partitions, namely time-sliced shared and graphics directed shared.

[0324] In at least one embodiment, in this model, system hypervisor 1696 owns graphics acceleration module 1646 and makes its function available to all operating systems 1695. In at least one embodiment, for a graphics acceleration module 1646 to support virtualization by system hypervisor 1696, graphics acceleration module 1646 may adhere to certain requirements, such as (1) an application’s job request must be autonomous (that is, state does not need to be maintained between jobs), or graphics acceleration module 1646 must provide a context save and restore mechanism, (2) an application’s job request is guaranteed by graphics acceleration module 1646 to complete in a specified amount of time, including any translation faults, or graphics acceleration module 1646 provides an ability to preempt processing of a job, and (3) graphics acceleration module 1646 must be guaranteed fairness between processes when operating in a directed shared programming model.

[0325] In at least one embodiment, application 1680 is required to make an operating system 1695 system call with a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, graphics acceleration module type describes a targeted acceleration function for a system call. In at least one embodiment, graphics acceleration module type may be a system-specific value. In at least one embodiment, WD is formatted specifically for graphics acceleration module 1646 and can be in a form of a graphics acceleration module 1646 command, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure to describe work to be done by graphics acceleration module 1646.

[0326] In at least one embodiment, an AMR value is an AMR state to use for a current process. In at least one embodiment, a value passed to an operating system is similar to an application 16 05 23 setting an AMR. In at least one embodiment, if accelerator integration circuit 1636 (not shown) and graphics acceleration module 1646 implementations do not support a User Authority Mask Override Register (UAMOR), an operating system may apply a current UAMOR value to an AMR value before passing an AMR in a hypervisor call. In at least one embodiment, hypervisor 1696 may optionally apply a current Authority Mask Override Register (AMOR) value before placing an AMR into process element 1683. In at least one embodiment, CSRP is one of registers 1645 containing an effective address of an area in an application’s effective address space 1682 for graphics acceleration module 1646 to save and restore context state. In at least one embodiment, this pointer is optional if no state is required to be saved between jobs or when a job is preempted. In at least one embodiment, context save / restore area may be pinned system memory.

[0327] Upon receiving a system call, operating system 1695 may verify that application 1680 has registered and been given authority to use graphics acceleration module 1646. In at least one embodiment, operating system 1695 then calls hypervisor 1696 with information shown in Table 3. Table 3 - OS to Hypervisor Call Parameters Parameter # Description 1 A work descriptor (WD) 2 An Authority Mask Register (AMR) value (potentially masked) 3 An effective address (EA) Context Save Restore Area Pointer (CSRP) 4 A process ID (PID) and optional thread ID (TTD) 5 A virtual address (VA) accelerator utilization record pointer (AURP) 6 Virtual address of storage segment table pointer (SSTP) 7 A logical interrupt service number (LISN)

[0328] In at least one embodiment, upon receiving a hypervisor call, hypervisor 1696 verifies that operating system 1695 has registered and been given authority to use graphics acceleration module 1646. In at least one embodiment, hypervisor 1696 then puts process element 1683 into a process element linked list for a corresponding graphics acceleration module 1646 type. In at least one embodiment, a process element may include information shown in Table 4. Table 4 - Process Element Information 16 05 23 Element # Description 1 A work descriptor (WD) 2 An Authority Mask Register (AMR) value (potentially masked). 3 An effective address (EA) Context Save / Restore Area Pointer (CSRP) 4 A process ID (PID) and optional thread ID (HD) 5 A virtual address (VA) accelerator utilization record pointer (AURP) 6 Virtual address of storage segment table pointer (SSTP) 7 A logical interrupt service number (LISN) 8 Interrupt vector table, derived from hypervisor call parameters 9 A state register (SR) value 10 A logical partition ID (LPID) 11 A real address (RA) hypervisor accelerator utilization record pointer 12 Storage Descriptor Register (SDR)

[0329] In at least one embodiment, hypervisor initializes a plurality of accelerator integration slice 1690 registers 1645.

[0330] As illustrated in FIG. 16F, in at least one embodiment, a unified memory is used, addressable via a common virtual memory address space used to access physical processor memories 1601(1 )-1601(N) and GPU memories 1620(1 )-1620(N). In this implementation, operations executed on GPUs 1610(1)- 1610(N) utilize a same virtual / effective memory address space to access processor memories 1601 (1)-1601 (M) and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of a virtual / effective address space is allocated to processor memory 1601(1), a second portion to second processor memory 1601(N), a third portion to GPU memory 1620(1), and so on. In at least one embodiment, an entire virtual / effective memory space (sometimes referred to as an effective address space) is thereby distributed across each of processor memories 1601 and GPU memories 1620, allowing any processor or GPU to access any physical memory with a virtual address mapped to that memory.

[0331] In at least one embodiment, bias / coherence management circuitry 1694A-1694E within one or more of MMUs 1639A-1639E ensures cache coherence between caches of one or more 16 05 23 host processors (e.g., 1605) and GPUs 1610 and implements biasing techniques indicating physical memories in which certain types of data should be stored. In at least one embodiment, while multiple instances of bias / coherence management circuitry 1694A-1694E are illustrated in FIG. 16F, bias / coherence circuitry may be implemented within an MMU of one or more host processors 1605 and / or within accelerator integration circuit 1636. [0332 ] One embodiment allows GPU memories 1620 to be mapped as part of system memory, and accessed using shared virtual memory (SVM) technology, but without suffering performance drawbacks associated with full system cache coherence. In at least one embodiment, an ability for GPU memories 1620 to be accessed as system memory without onerous cache coherence overhead provides a beneficial operating environment for GPU offload. In at least one embodiment, this arrangement allows software of host processor 1605 to setup operands and access computation results, without overhead of tradition I / O DMA data copies. In at least one embodiment, such traditional copies involve driver calls, interrupts and memory mapped I / O (MMIO) accesses that are all inefficient relative to simple memory accesses. In at least one embodiment, an ability to access GPU memories 1620 without cache coherence overheads can be critical to execution time of an offloaded computation. In at least one embodiment, in cases with substantial streaming write memory traffic, for example, cache coherence overhead can significantly reduce an effective write bandwidth seen by a GPU 1610. In at least one embodiment, efficiency of operand setup, efficiency of results access, and efficiency of GPU computation may play a role in determining effectiveness of a GPU offload.

[0333] In at least one embodiment, selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, a bias table may be used, for example, which may be a page-granular structure (e.g., controlled at a granularity of a memory page) that includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, a bias table may be implemented m a stolen memory range of one or more GPU memories 1620, with or without a bias cache in a GPU 1610 (e.g., to cache frequently / recently used entries of a bias table). Alternatively, in at least one embodiment, an entire bias table may be maintained within a GPU.

[0334] In at least one embodiment, a bias table entry associated with each access to a GPU attached memory 1620 is accessed prior to actual access to a GPU memory, causing following 16 05 23 operations. In at least one embodiment, local requests from a GPU 1610 that find their page in GPU bias are forwarded directly to a corresponding GPU memory 1620. In at least one embodiment, local requests from a GPU that find their page in host bias are forwarded to processor 1605 (e.g., over a high-speed link as described herein). In at least one embodiment, requests from processor 1605 that find a requested page in host processor bias complete a request like a normal memory read. Alternatively, requests directed to a GPU-biased page may be forwarded to a GPU 1610. In at least one embodiment, a GPU may then transition a page to a host processor bias if it is not currently using a page. In at least one embodiment, a bias state of a page can be changed either by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a purely hardware-based mechanism.

[0335] In at least one embodiment, one mechanism for changing bias state employs an API call (e.g., OpenCL), which, in turn, calls a GPU’s device driver which, in turn, sends a message (or enqueues a command descriptor) to a GPU directing it to change a bias state and, for some transitions, perform a cache flushing operation in a host. In at least one embodiment, a cache flushing operation is used for a transition from host processor 1605 bias to GPU bias, but is not for an opposite transition.

[0336] In at least one embodiment, cache coherency is maintained by temporarily rendering GPU-biased pages uncacheable by host processor 1605. In at least one embodiment, to access these pages, processor 1605 may request access from GPU 1610, which may or may not grant access right away. In at least one embodiment, thus, to reduce communication between processor 1605 and GPU 1610 it is beneficial to ensure that GPU-biased pages are those which are required by a GPU but not host processor 1605 and vice versa.

[0337] Hardware structure(s) 815 are used to perform one or more embodiments. Details regarding a hardware structure(s) 815 may be provided herein in conjunction with FIGS. 8A and / or 8B.

[0338] In at least one embodiment, one or more systems depicted in FIGS. 16A-16F are utilized to train a neural network to perform object detection, instance segmentation, and semantic correspondence with bounding box annotations. In at least one embodiment, one or more systems depicted in FIGS. 16A-16F are utilized to implement a framework for object detection, instance segmentation, and semantic correspondence. In at least one embodiment, one 16 05 23 or more systems depicted in FIGS. 16A-16F are utilized to implement one or more networks and processes such as those described in connection with FIGS. 1-7.

[0339] FIG. 17 illustrates exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0340] FIG. 17 is a block diagram illustrating an exemplary system on a chip integrated circuit 1700 that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, integrated circuit 1700 includes one or more application processor(s) 1705 (e.g., CPUs), at least one graphics processor 1710, and may additionally include an image processor 1715 and / or a video processor 1720, any of which may be a modular IP core. In at least one embodiment, integrated circuit 1700 includes peripheral or bus logic including a USB controller 1725, a UART controller 1730, an SPI SDK) controller 1735, and an I22S / I22C controller 1740. In at least one embodiment, integrated circuit 1700 can include a display device 1745 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1750 and a mobile industry processor interface (MIPI) display interface 1755. In at least one embodiment, storage may be provided by a flash memory subsystem 1760 including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1765 for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1770. [034 J ] Inference and / or training logic 815 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are provided herein in conjunction with FIGS. 8A and / or 8B. In at least one embodiment, inference and / or training logic 815 may be used in integrated circuit 1700 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. 16 05 23

[0342] In at least one embodiment, one or more systems depicted in FIG. 17 are utilized to train a neural network to perform object detection, instance segmentation, and semantic correspondence with bounding box annotations. In at least one embodiment, one or more systems depicted m FIG. 17 are utilized to implement a framework for object detection, instance segmentation, and semantic correspondence. In at least one embodiment, one or more systems depicted in FIG. 17 are utilized to implement one or more networks and processes such as those described in connection with FIGS. 1-7. [0343 ] FIGS. 18A-18B illustrate exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0344] FIGS. 18A-18B are block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein. FIG. 18A illustrates an exemplary graphics processor 1810 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. FIG. 18B illustrates an additional exemplary graphics processor 1840 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, graphics processor 1810 of FIG. 18A is a low power graphics processor core. In at least one embodiment, graphics processor 1840 of FIG. 18B is a higher performance graphics processor core. In at least one embodiment, each of graphics processors 1810, 1840 can be variants of graphics processor 1710 of FIG. 17.

[0345] In at least one embodiment, graphics processor 1810 includes a vertex processor 1805 and one or more fragment processor(s) 1815A-1815N (e.g., 1815A, 1815B, 1815C, 1815D, through 1815N-1, and 1815N). In at least one embodiment, graphics processor 1810 can execute different shader programs via separate logic, such that vertex processor 1805 is optimized to execute operations for vertex shader programs, while one or more fragment processor(s) 1815A-1815N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor 1805 performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. In at least 16 05 23 one embodiment, fragment processor(s) 1815A-1815N use primitive and vertex data generated by vertex processor 1805 to produce a framebuffer that is displayed on a display device. In at least one embodiment, fragment processor(s) 1815A-1815N are optimized to execute fragment shader programs as provided for in an OpenGL API, which may be used to perform similar operations as a pixel shader program as provided for in a Direct 3D API.

[0346] In at least one embodiment, graphics processor 1810 additionally includes one or more memory management units (MMUs) 1820A-1820B, cache(s) 1825A-1825B, and circuit interconnect(s) 1830A-1830B. In at least one embodiment, one or more MMU(s) 1820A-1820B provide for virtual to physical address mapping for graphics processor 1810, including for vertex processor 1805 and / or fragment processor(s) 1815A-1815N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more cache(s) 1825A-1825B. In at least one embodiment, one or more MMU(s) 1820A-1820B may be synchronized with other MMUs within a system, including one or more MMUs associated with one or more application processor(s) 1705, image processors 1715, and / or video processors 1720 of FIG. 17, such that each processor 1705-1720 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnect(s) 1830A-1830B enable graphics processor 1810 to interface with other IP cores within SoC, either via an internal bus of SoC or via a direct connection.

[0347] In at least one embodiment, graphics processor 1840 includes one or more shader core(s) 1855A-1855N (e.g., 1855A, 1855B, 1855C, 1855D, 1855E, 1855F, through 1855N-1, and 1855N) as shown in FIG. 18B, which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, a number of shader cores can vary. In at least one embodiment, graphics processor 1840 includes an inter-core task manager 1845, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1855A-1855N and a tiling unit 1858 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches. 16 05 23

[0348] Inference and / or training logic 815 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are provided herein in conjunction with FIGS. 8A and / or 8B. In at least one embodiment, inference and / or training logic 815 may be used in integrated circuit 18A and / or 18B for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0349] In at least one embodiment, one or more systems depicted in FIGS. 18A-18B are utilized to train a neural network to perform object detection, instance segmentation, and semantic correspondence with bounding box annotations. In at least one embodiment, one or more systems depicted in FIGS. 18A-18B are utilized to implement a framework for object detection, instance segmentation, and semantic correspondence. In at least one embodiment, one or more systems depicted in FIGS. 18A-18B are utilized to implement one or more networks and processes such as those described in connection with FIGS. 1-7.

[0350] FIGS. 19A-19B illustrate additional exemplary graphics processor logic according to embodiments described herein. FIG. 19A illustrates a graphics core 1900 that may be included within graphics processor 1710 of FIG. 17, in at least one embodiment, and may be a unified shader core 1855A-1855N as in FIG. 18B in at least one embodiment. FIG. 19B illustrates a highly-parallel general-purpose graphics processing unit (“GPGPU”) 1930 suitable for deployment on a multi-chip module in at least one embodiment.

[0351] In at least one embodiment, graphics core 1900 includes a shared instruction cache 1902, a texture unit 1918, and a cache / shared memory 1920 that are common to execution resources within graphics core 1900. In at least one embodiment, graphics core 1900 can include multiple slices 1901 A-190IN or a partition for each core, and a graphics processor can include multiple instances of graphics core 1900. In at least one embodiment, slices 1901A-1901N can include support logic including a local instruction cache 1904A-1904N, a thread scheduler 1906A-1906N, a thread dispatcher 1908A-1908N, and a set of registers 1910A-1910N. In at least one embodiment, slices 1901 A-190IN can include a set of additional function units (AFUs 1912A-1912N), floating-point units (FPUs 1914A-1914N), integer arithmetic logic units (ALUs 1916A-1916N), address computational units (ACUs 1913A-1913N), double-precision floating-point units (DPFPUs 1915A-1915N), and matrix processing units (MPUs 1917A-1917N). 16 05 23

[0352] In at least one embodiment, FPUs 1914A-1914N can perform single-precision (32-bit) and half-precision (16-bit) floating point operations, while DPFPUs 1915A-1915N perform double precision (64-bit) floating point operations. In at least one embodiment, ALUs 1916A-1916N can perform variable precision integer operations at 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed precision operations. In at least one embodiment, MPUs 1917A-1917N can also be configured for mixed precision matrix operations, including half-precision floating point and 8-bit integer operations. In at least one embodiment, MPUs 1917-1917N can perform a variety of matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix to matrix multiplication (GEMM). In at least one embodiment, AFUs 1912A-1912N can perform additional logic operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0353] Inference and / or training logic 815 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are provided herein in conjunction with FIGS. 8A and / or 8B. In at least one embodiment, inference and / or training logic 815 may be used in graphics core 1900 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0354] FIG. 19B illustrates a general-purpose processing unit (GPGPU) 1930 that can be configured to enable highly-parallel compute operations to be performed by an array of graphics processing units, in at least one embodiment. In at least one embodiment, GPGPU 1930 can be linked directly to other instances of GPGPU 1930 to create a multi-GPU cluster to improve training speed for deep neural networks. In at least one embodiment, GPGPU 1930 includes a host interface 1932 to enable a connection with a host processor. In at least one embodiment, host interface 1932 is a PCI Express interface. In at least one embodiment, host interface 1932 can be a vendor-specific communications interface or communications fabric. In at least one embodiment, GPGPU 1930 receives commands from a host processor and uses a global 16 05 23 scheduler 1934 to distribute execution threads associated with those commands to a set of compute clusters 1936A-1936H. In at least one embodiment, compute clusters 1936A-1936H share a cache memory 1938. In at least one embodiment, cache memory 1938 can serve as a higher-level cache for cache memories within compute clusters 1936A-1936H.

[0355] In at least one embodiment, GPGPU 1930 includes memory 1944A-1944B coupled with compute clusters 1936A-1936H via a set of memory controllers 1942A-1942B. In at least one embodiment, memory 1944A-1944B can include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0356] In at least one embodiment, compute clusters 1936A-1936H each include a set of graphics cores, such as graphics core 1900 of FIG. 19A, which can include multiple types of integer and floating point logic units that can perform computational operations at a range of precisions including suited for machine learning computations. For example, in at least one embodiment, at least a subset of floating point units in each of compute clusters 1936A-1936H can be configured to perform 16-bit or 32-bit floating point operations, while a different subset of floating point units can be configured to perform 64-bit floating point operations.

[0357] In at least one embodiment, multiple instances of GPGPU 1930 can be configured to operate as a compute cluster. In at least one embodiment, communication used by compute clusters 1936A-1936H for synchronization and data exchange varies across embodiments. In at least one embodiment, multiple instances of GPGPU 1930 communicate over host interface 1932. In at least one embodiment, GPGPU 1930 includes an I / O hub 1939 that couples GPGPU 1930 with a GPU link 1940 that enables a direct connection to other instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1930. In at least one embodiment, GPU link 1940 couples with a high-speed interconnect to transmit and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1930 are located in separate data processing systems and communicate via a network device that is accessible via host 16 05 23 interface 1932. In at least one embodiment GPU link 1940 can be configured to enable a connection to a host processor in addition to or as an alternative to host interface 1932.

[0358] In at least one embodiment, GPGPU 1930 can be configured to train neural networks. In at least one embodiment, GPGPU 1930 can be used within an inferencing platform. In at least one embodiment, in which GPGPU 1930 is used for inferencing, GPGPU 1930 may include fewer compute clusters 1936A-1936H relative to when GPGPU 1930 is used for training a neural network. In at least one embodiment, memory technology associated with memory 1944A-1944B may differ between inferencing and training configurations, with higher bandwidth memory technologies devoted to training configurations. In at least one embodiment, an inferencing configuration of GPGPU 1930 can support inferencing specific instructions. For example, in at least one embodiment, an inferencing configuration can provide support for one or more 8-bit integer dot product instructions, which may be used during inferencing operations for deployed neural networks.

[0359] Inference and / or training logic 815 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are provided herein in conjunction with FIGS. 8A and / or 8B. In at least one embodiment, inference and / or training logic 815 may be used in GPGPU 1930 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0360] In at least one embodiment, one or more systems depicted in FIGS. 19A-19B are utilized to train a neural network to perform object detection, instance segmentation, and semantic correspondence with bounding box annotations. In at least one embodiment, one or more systems depicted in FIGS. 19A-19B are utilized to implement a framework for object detection, instance segmentation, and semantic correspondence. In at least one embodiment, one or more systems depicted in FIGS. 19A-19B are utilized to implement one or more networks and processes such as those described in connection with FIGS. 1-7.

[0361] FIG. 20 is a block diagram illustrating a computing system 2000 according to at least one embodiment. In at least one embodiment, computing system 2000 includes a processing subsystem 2001 having one or more processor(s) 2002 and a system memory 2004 16 05 23 communicating via an interconnection path that may include a memory hub 2005. In at least one embodiment, memory hub 2005 may be a separate component within a chipset component or may be integrated within one or more processor(s) 2002. In at least one embodiment, memory hub 2005 couples with an I / O subsystem 2011 via a communication link 2006. In at least one embodiment, I / O subsystem 2011 includes an I / O hub 2007 that can enable computing system 2000 to receive input from one or more input device(s) 2008. In at least one embodiment, I / O hub 2007 can enable a display controller, which may be included in one or more processor(s) 2002, to provide outputs to one or more display device(s) 2010A. In at least one embodiment, one or more display device(s) 2010A coupled with I / O hub 2007 can include a local, internal, or embedded display device.

[0362] In at least one embodiment, processing subsystem 2001 includes one or more parallel processor(s) 2012 coupled to memory hub 2005 via a bus or other communication link 2013. In at least one embodiment, communication link 2013 may use one of any number of standards based communication link technologies or protocols, such as, but not limited to PCI Express, or may be a vendor-specific communications interface or communications fabric. In at least one embodiment, one or more parallel processor(s) 2012 form a computationally focused parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as a many-integrated core (MIC) processor. In at least one embodiment, some or all of parallel processor(s) 2012 form a graphics processing subsystem that can output pixels to one of one or more display device(s) 2010A coupled via I / O Hub 2007. In at least one embodiment, parallel processor(s) 2012 can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s) 2010B.

[0363] In at least one embodiment, a system storage unit 2014 can connect to I / O hub 2007 to provide a storage mechanism for computing system 2000. In at least one embodiment, an I / O switch 2016 can be used to provide an interface mechanism to enable connections between I / O hub 2007 and other components, such as a network adapter 2018 and / or a wireless network adapter 2019 that may be integrated into platform, and various other devices that can be added via one or more add-in device(s) 2020. In at least one embodiment, network adapter 2018 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless 16 05 23 network adapter 2019 can include one or more of a Wi-Fi (RTM), Bluetooth (RTM), near field communication (NFC), or other network device that includes one or more wireless radios.

[0364] In at least one embodiment, computing system 2000 can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and like, may also be connected to I / O hub 2007. In at least one embodiment, communication paths interconnecting various components in FIG. 20 may be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI-Express), or other bus or point-to-point communication interfaces and / or protocol(s), such as NV-Link high-speed interconnect, or interconnect protocols.

[0365] In at least one embodiment, parallel processor(s) 2012 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU). In at least one embodiment, parallel processor(s) 2012 incorporate circuitry optimized for general purpose processing. In at least embodiment, components of computing system 2000 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, parallel processor(s) 2012, memory hub 2005, processor(s) 2002, and I / O hub 2007 can be integrated into a system on chip (SoC) integrated circuit. In at least one embodiment, components of computing system 2000 can be integrated into a single package to form a system in package (SIP) configuration. In at least one embodiment, at least a portion of components of computing system 2000 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.

[0366] Inference and / or training logic 815 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are provided herein in conjunction with FIGS. 8A and / or 8B. In at least one embodiment, inference and / or training logic 815 may be used in system FIG. 2000 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0367] In at least one embodiment, one or more systems depicted in FIG. 20 are utilized to train a neural network to perform object detection, instance segmentation, and semantic 16 05 23 correspondence with bounding box annotations. In at least one embodiment, one or more systems depicted in FIG. 20 are utilized to implement a framework for object detection, instance segmentation, and semantic correspondence. In at least one embodiment, one or more systems depicted in FIG. 20 are utilized to implement one or more networks and processes such as those described in connection with FIGS. 1-7. PROCESSORS

[0368] FIG. 21A illustrates a parallel processor 2100 according to at least one embodiment. In at least one embodiment, various components of parallel processor 2100 may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGA). In at least one embodiment, illustrated parallel processor 2100 is a variant of one or more parallel processor(s) 2012 shown in FIG. 20 according to an exemplary embodiment.

[0369] In at least one embodiment, parallel processor 2100 includes a parallel processing unit 2102. In at least one embodiment, parallel processing unit 2102 includes an I / O unit 2104 that enables communication with other devices, including other instances of parallel processing unit 2102. In at least one embodiment, I / O unit 2104 may be directly connected to other devices. In at least one embodiment, I / O unit 2104 connects with other devices via use of a hub or switch interface, such as a memory hub 2105. In at least one embodiment, connections between memory hub 2105 and I / O unit 2104 form a communication link 2113. In at least one embodiment, I / O unit 2104 connects with a host interface 2106 and a memory crossbar 2116, where host interface 2106 receives commands directed to performing processing operations and memory crossbar 2116 receives commands directed to performing memory operations.

[0370] In at least one embodiment, when host interface 2106 receives a command buffer via I / O unit 2104, host interface 2106 can direct work operations to perform those commands to a front end 2108. In at least one embodiment, front end 2108 couples with a scheduler 2110, which is configured to distribute commands or other work items to a processing cluster array 2112. In at least one embodiment, scheduler 2110 ensures that processing cluster array 2112 is properly configured and in a valid state before tasks are distributed to a cluster of processing cluster array 2112. In at least one embodiment, scheduler 2110 is implemented via firmware logic executing on a microcontroller. In at least one embodiment, microcontroller implemented 16 05 23 scheduler 2110 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid preemption and context switching of threads executing on processing array 2112. In at least one embodiment, host software can prove workloads for scheduling on processing cluster array 2112 via one of multiple graphics processing paths. In at least one embodiment, workloads can then be automatically distributed across processing array cluster 2112 by scheduler 2110 logic within a microcontroller including scheduler 2110.

[0371] In at least one embodiment, processing cluster array 2112 can include up to “N” processing clusters (e.g., cluster 2114A, cluster 2114B, through cluster 2114N), where “N” represents a positive integer (which may be a different integer “N” than used in other figures). In at least one embodiment, each cluster 2114A-2114N of processing cluster array 2112 can execute a large number of concurrent threads. In at least one embodiment, scheduler 2110 can allocate work to clusters 2114A-2114N of processing cluster array 2112 using various scheduling and / or work distribution algorithms, which may vary depending on workload arising for each type of program or computation. In at least one embodiment, scheduling can be handled dynamically by scheduler 2110, or can be assisted in part by compiler logic during compilation of program logic configured for execution by processing cluster array 2112. In at least one embodiment, different clusters 2114A-2114N of processing cluster array 2112 can be allocated for processing different types of programs or for performing different types of computations.

[0372] In at least one embodiment, processing cluster array 2112 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2112 is configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing cluster array 2112 can include logic to execute processing tasks including filtering of video and / or audio data, performing modeling operations, including physics operations, and performing data transformations.

[0373] In at least one embodiment, processing cluster array 2112 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 2112 can include additional logic to support execution of such graphics processing operations, including but not limited to, texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, 16 05 23 processing cluster array 2112 can be configured to execute graphics processing related shader programs such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 2102 can transfer data from system memory via I / O unit 2104 for processing. In at least one embodiment, during processing, transferred data can be stored to on-chip memory (e.g., parallel processor memory 2122) during processing, then written back to system memory.

[0374] In at least one embodiment, when parallel processing unit 2102 is used to perform graphics processing, scheduler 2110 can be configured to divide a processing workload into approximately equal sized tasks, to better enable distribution of graphics processing operations to multiple clusters 2114A-2114N of processing cluster array 2112. In at least one embodiment, portions of processing cluster array 2112 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. In at least one embodiment, intermediate data produced by one or more of clusters 2114A-2114N may be stored in buffers to allow intermediate data to be transmitted between clusters 2114A-2114N for further processing.

[0375] In at least one embodiment, processing cluster array 2112 can receive processing tasks to be executed via scheduler 2110, which receives commands defining processing tasks from front end 2108. In at least one embodiment, processing tasks can include indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how data is to be processed (e.g., what program is to be executed). In at least one embodiment, scheduler 2110 may be configured to fetch indices corresponding to tasks or may receive indices from front end 2108. In at least one embodiment, front end 2108 can be configured to ensure processing cluster array 2112 is configured to a valid state before a workload specified by incoming command buffers (e.g., batch-buffers, push buffers, etc.) is initiated.

[0376] In at least one embodiment, each of one or more instances of parallel processing unit 2102 can couple with a parallel processor memory 2122. In at least one embodiment, 16 05 23 parallel processor memory 2122 can be accessed via memory crossbar 2116, which can receive memory requests from processing cluster array 2112 as well as I / O unit 2104. In at least one embodiment, memory crossbar 2116 can access parallel processor memory 2122 via a memory interface 2118. In at least one embodiment, memory interface 2118 can include multiple partition units (e.g., partition unit 2120A, partition unit 2120B, through partition unit 2120N) that can each couple to a portion (e.g., memory unit) of parallel processor memory 2122. In at least one embodiment, a number of partition units 2120A-2120N is configured to be equal to a number of memory units, such that a first partition unit 2120A has a corresponding first memory unit 2124A, a second partition unit 2120B has a corresponding memory unit 2124B, and an N-th partition unit 2120N has a corresponding N-th memory unit 2124N. In at least one embodiment, a number of partition units 2120A-2120N may not be equal to a number of memory units.

[0377] In at least one embodiment, memory units 2124A-2124N can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2124A-2124N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets, such as frame buffers or texture maps may be stored across memory units 2124A-2124N, allowing partition units 2120A-2120N to write portions of each render target in parallel to efficiently use available bandwidth of parallel processor memory 2122. In at least one embodiment, a local instance of parallel processor memory 2122 may be excluded in favor of a unified memory design that utilizes system memory in conjunction with local cache memory.

[0378] In at least one embodiment, any one of clusters 2114A-2114N of processing cluster array 2112 can process data that will be written to any of memory units 2124A-2124N within parallel processor memory 2122. In at least one embodiment, memory crossbar 2116 can be configured to transfer an output of each cluster 2114A-2114N to any partition unit 2120A-2120N or to another cluster 2114A-2114N, which can perform additional processing operations on an output. In at least one embodiment, each cluster 2114A-2114N can communicate with memory interface 2118 through memory crossbar 2116 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 2116 has a connection to memory 16 05 23 interface 2118 to communicate with I / O unit 2104, as well as a connection to a local instance of parallel processor memory 2122, enabling processing units within different processing clusters 2114A-2114N to communicate with system memory or other memory that is not local to parallel processing unit 2102. In at least one embodiment, memory crossbar 2116 can use virtual channels to separate traffic streams between clusters 2114A-2114N and partition units 2120A-2120N.

[0379] In at least one embodiment, multiple instances of parallel processing unit 2102 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 2102 can be configured to interoperate even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2102 can include higher precision floating point units relative to other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 2102 or parallel processor 2100 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0380] FIG. 21B is a block diagram of a partition unit 2120 according to at least one embodiment. In at least one embodiment, partition unit 2120 is an instance of one of partition units 2120A-2120N of FIG. 21 A. In at least one embodiment, partition unit 2120 includes an L2 cache 2121, a frame buffer interface 2125, and a ROP 2126 (raster operations unit). In at least one embodiment, L2 cache 2121 is a read / write cache that is configured to perform load and store operations received from memory crossbar 2116 and ROP 2126. In at least one embodiment, read misses and urgent write-back requests are output by L2 cache 2121 to frame buffer interface 2125 for processing. In at least one embodiment, updates can also be sent to a frame buffer via frame buffer interface 2125 for processing. In at least one embodiment, frame buffer interface 2125 interfaces with one of memory units in parallel processor memory, such as memory units 2124A-2124N of FIG. 21 (e.g., within parallel processor memory 2122).

[0381] In at least one embodiment, ROP 2126 is a processing unit that performs raster operations such as stencil, z test, blending, etc. In at least one embodiment, ROP 2126 then 16 05 23 outputs processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 2126 includes compression logic to compress depth or color data that is written to memory and decompress depth or color data that is read from memory. In at least one embodiment, compression logic can be lossless compression logic that makes use of one or more of multiple compression algorithms. In at least one embodiment, a type of compression that is performed by ROP 2126 can vary based on statistical characteristics of data to be compressed. For example, in at least one embodiment, delta color compression is performed on depth and color data on a per-tile basis.

[0382] In at least one embodiment, ROP 2126 is included within each processing cluster (e.g., cluster 2114A-2114N of FIG. 21 A) instead of within partition unit 2120. In at least one embodiment, read and write requests for pixel data are transmitted over memory crossbar 2116 instead of pixel fragment data. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display device(s) 2010 of FIG. 20, routed for further processing by processor(s) 2002, or routed for further processing by one of processing entities within parallel processor 2100 of FIG. 21 A.

[0383] FIG. 21C is a block diagram of a processing cluster 2114 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is an instance of one of processing clusters 2114A-2114N of FIG. 21 A. In at least one embodiment, processing cluster 2114 can be configured to execute many threads in parallel, where “thread” refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction, multiple-data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of a large number of generally synchronized threads, using a common instruction unit configured to issue instructions to a set of processing engines within each one of processing clusters.

[0384] In at least one embodiment, operation of processing cluster 2114 can be controlled via a pipeline manager 2132 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, pipeline manager 2132 receives instructions from scheduler 2110 of FIG. 21A and manages execution of those instructions via a graphics multiprocessor 2134 and / or a texture 16 05 23 unit 2136. In at least one embodiment, graphics multiprocessor 2134 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of differing architectures may be included within processing cluster 2114. In at least one embodiment, one or more instances of graphics multiprocessor 2134 can be included within a processing cluster 2114. In at least one embodiment, graphics multiprocessor 2134 can process data and a data crossbar 2140 can be used to distribute processed data to one of multiple possible destinations, including other shader units. In at least one embodiment, pipeline manager 2132 can facilitate distribution of processed data by specifying destinations for processed data to be distributed via data crossbar 2140.

[0385] In at least one embodiment, each graphics multiprocessor 2134 within processing cluster 2114 can include an identical set of functional execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, functional execution logic can be configured in a pipelined manner in which new instructions can be issued before previous instructions are complete. In at least one embodiment, functional execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, bit-shifting, and computation of various algebraic functions. In at least one embodiment, same functional-unit hardware can be leveraged to perform different operations and any combination of functional units may be present.

[0386] In at least one embodiment, instructions transmitted to processing cluster 2114 constitute a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a common program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within a graphics multiprocessor 2134. In at least one embodiment, a thread group may include fewer threads than a number of processing engines within graphics multiprocessor 2134. In at least one embodiment, when a thread group includes fewer threads than a number of processing engines, one or more of processing engines may be idle during cycles in which that thread group is being processed. In at least one embodiment, a thread group may also include more threads than a number of processing engines within graphics multiprocessor 2134. In at least one embodiment, when a thread group includes more threads than number of processing engines within graphics multiprocessor 2134, 16 05 23 processing can be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on a graphics multiprocessor 2134.

[0387] In at least one embodiment, graphics multiprocessor 2134 includes an internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor 2134 can forego an internal cache and use a cache memory (e.g., LI cache 2148) within processing cluster 2114. In at least one embodiment, each graphics multiprocessor 2134 also has access to L2 caches within partition units (e.g., partition units 2120A-2120N of FIG. 21 A) that are shared among all processing clusters 2114 and may be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2134 may also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2102 may be used as global memory. In at least one embodiment, processing cluster 2114 includes multiple instances of graphics multiprocessor 2134 and can share common instructions and data, which may be stored in LI cache 2148.

[0388] In at least one embodiment, each processing cluster 2114 may include an MMU 2145 (memory management unit) that is configured to map virtual addresses into physical addresses. In at least one embodiment, one or more instances of MMU 2145 may reside within memory interface 2118 of FIG. 21 A. In at least one embodiment, MMU 2145 includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile and optionally a cache line index. In at least one embodiment, MMU 2145 may include address translation lookaside buffers (TLB) or caches that may reside within graphics multiprocessor 2134 or LI 2148 cache or processing cluster 2114. In at least one embodiment, a physical address is processed to distribute surface data access locally to allow for efficient request interleaving among partition units. In at least one embodiment, a cache line index may be used to determine whether a request for a cache line is a hit or miss.

[0389] In at least one embodiment, a processing cluster 2114 may be configured such that each graphics multiprocessor 2134 is coupled to a texture unit 2136 for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture LI cache (not shown) or from an LI cache within graphics multiprocessor 2134 and is fetched from an L2 16 05 23 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 2134 outputs processed tasks to data crossbar 2140 to provide processed task to another processing cluster 2114 for further processing or to store processed task in an L2 cache, local parallel processor memory, or system memory via memory crossbar 2116. In at least one embodiment, a preROP 2142 (pre-raster operations unit) is configured to receive data from graphics multiprocessor 2134, and direct data to ROP units, which may be located with partition units as described herein (e.g., partition units 2120A-2120N of FIG. 21A). In at least one embodiment, preROP 2142 unit can perform optimizations for color blending, organizing pixel color data, and performing address translations.

[0390] Inference and / or training logic 815 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are provided herein in conjunction with FIGS. 8A and / or 8B. In at least one embodiment, inference and / or training logic 815 may be used in graphics processing cluster 2114 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0391] FIG. 21D shows a graphics multiprocessor 2134 according to at least one embodiment. In at least one embodiment, graphics multiprocessor 2134 couples with pipeline manager 2132 of processing cluster 2114. In at least one embodiment, graphics multiprocessor 2134 has an execution pipeline including but not limited to an instruction cache 2152, an instruction unit 2154, an address mapping unit 2156, a register file 2158, one or more general purpose graphics processing unit (GPGPU) cores 2162, and one or more load / store units 2166. In at least one embodiment, GPGPU cores 2162 and load / store units 2166 are coupled with cache memory 2172 and shared memory 2170 via a memory and cache interconnect 2168.

[0392] In at least one embodiment, instruction cache 2152 receives a stream of instructions to execute from pipeline manager 2132. In at least one embodiment, instructions are cached in instruction cache 2152 and dispatched for execution by an instruction unit 2154. In at least one embodiment, instruction unit 2154 can dispatch instructions as thread groups (e.g., warps), with each thread of thread group assigned to a different execution unit within GPGPU cores 2162. In at least one embodiment, an instruction can access any of a local, shared, or global address space 16 05 23 by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2156 can be used to translate addresses in a unified address space into a distinct memory address that can be accessed by load / store units 2166.

[0393] In at least one embodiment, register file 2158 provides a set of registers for functional units of graphics multiprocessor 2134. In at least one embodiment, register file 2158 provides temporary storage for operands connected to data paths of functional units (e.g., GPGPU cores 2162, load / store units 2166) of graphics multiprocessor 2134. In at least one embodiment, register file 2158 is divided between each of functional units such that each functional unit is allocated a dedicated portion of register file 2158. In at least one embodiment, register file 2158 is divided between different warps being executed by graphics multiprocessor 2134.

[0394] In at least one embodiment, GPGPU cores 2162 can each include floating point units (FPUs) and / or integer arithmetic logic units (ALUs) that are used to execute instructions of graphics multiprocessor 2134. In at least one embodiment, GPGPU cores 2162 can be similar in architecture or can differ in architecture. In at least one embodiment, a first portion of GPGPU cores 2162 include a single precision FPU and an integer ALU while a second portion of GPGPU cores include a double precision FPU. In at least one embodiment, FPUs can implement IEEE 754-2008 standard floating point arithmetic or enable variable precision floating point arithmetic. In at least one embodiment, graphics multiprocessor 2134 can additionally include one or more fixed function or special function units to perform specific functions such as copy rectangle or pixel blending operations. In at least one embodiment, one or more of GPGPU cores 2162 can also include fixed or special function logic.

[0395] In at least one embodiment, GPGPU cores 2162 include SIMD logic capable of performing a single instruction on multiple sets of data. In at least one embodiment, GPGPU cores 2162 can physically execute SIMD4, SIMD8, and SIMD 16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU cores can be generated at compile time by a shader compiler or automatically generated when executing programs written and compiled for single program multiple data (SPMD) or SIMT architectures. In at least one embodiment, multiple threads of a program configured for an SIMT execution model can executed via a single SIMD instruction. 16 05 23 For example, in at least one embodiment, eight SIMT threads that perform same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0396] In at least one embodiment, memory and cache interconnect 2168 is an interconnect network that connects each functional unit of graphics multiprocessor 2134 to register file 2158 and to shared memory 2170. In at least one embodiment, memory and cache interconnect 2168 is a crossbar interconnect that allows load / store unit 2166 to implement load and store operations between shared memory 2170 and register file 2158. In at least one embodiment, register file 2158 can operate at a same frequency as GPGPU cores 2162, thus data transfer between GPGPU cores 2162 and register file 2158 can have very low latency. In at least one embodiment, shared memory 2170 can be used to enable communication between threads that execute on functional units within graphics multiprocessor 2134. In at least one embodiment, cache memory 2172 can be used as a data cache for example, to cache texture data communicated between functional units and texture unit 2136. In at least one embodiment, shared memory 2170 can also be used as a program managed cache. In at least one embodiment, threads executing on GPGPU cores 2162 can programmatically store data within shared memory in addition to automatically cached data that is stored within cache memory 2172.

[0397] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to host / processor cores to accelerate graphics operations, machine-learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, a GPU may be communicatively coupled to host processor / cores over a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, a GPU may be integrated on a package or chip as cores and communicatively coupled to cores over an internal processor bus / interconnect internal to a package or chip. In at least one embodiment, regardless a manner in which a GPU is connected, processor cores may allocate work to such GPU in a form of sequences of commands / instructions contained in a work descriptor. In at least one embodiment, that GPU then uses dedicated circuitry / logic for efficiently processing these commands / instructions.

[0398] Inference and / or training logic 815 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are provided herein in conjunction with FIGS. 8A and / or 8B. In at least one 16 05 23 embodiment, inference and / or training logic 815 may be used in graphics multiprocessor 2134 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0399] In at least one embodiment, one or more systems depicted in FIGS. 21A-21D are utilized to train a neural network to perform object detection, instance segmentation, and semantic correspondence with bounding box annotations. In at least one embodiment, one or more systems depicted in FIGS. 21A-21D are utilized to implement a framework for object detection, instance segmentation, and semantic correspondence. In at least one embodiment, one or more systems depicted in FIGS. 21A-21D are utilized to implement one or more networks and processes such as those described in connection with FIGS. 1-7. |{)400] FIG. 22 illustrates a multi-GPU computing system 2200, according to at least one embodiment. In at least one embodiment, multi-GPU computing system 2200 can include a processor 2202 coupled to multiple general purpose graphics processing units (GPGPUs) 2206A-D via a host interface switch 2204. In at least one embodiment, host interface switch 2204 is a PCI express switch device that couples processor 2202 to a PCI express bus over which processor 2202 can communicate with GPGPUs 2206A-D. In at least one embodiment, GPGPUs 2206A-D can interconnect via a set of high-speed point-to-point GPU-to-GPU links 2216. In at least one embodiment, GPU-to-GPU links 2216 connect to each of GPGPUs 2206A-D via a dedicated GPU link. In at least one embodiment, P2P GPU links 2216 enable direct communication between each of GPGPUs 2206A-D without requiring communication over host interface bus 2204 to which processor 2202 is connected. In at least one embodiment, with GPU-to-GPU traffic directed to P2P GPU links 2216, host interface bus 2204 remains available for system memory access or to communicate with other instances of multi-GPU computing system 2200, for example, via one or more network devices. While in at least one embodiment GPGPUs 2206A-D connect to processor 2202 via host interface switch 2204, in at least one embodiment processor 2202 includes direct support for P2P GPU links 2216 and can connect directly to GPGPUs 2206A-D.

[0401] Inference and / or training logic 815 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training 16 05 23 logic 815 are provided herein in conjunction with FIGS. 8A and / or 8B. In at least one embodiment, inference and / or training logic 815 may be used in multi-GPU computing system 2200 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. [0402 ] In at least one embodiment, one or more systems depicted in FIG. 22 are utilized to train a neural network to perform object detection, instance segmentation, and semantic correspondence with bounding box annotations. In at least one embodiment, one or more systems depicted m FIG. 22 are utilized to implement a framework for object detection, instance segmentation, and semantic correspondence. In at least one embodiment, one or more systems depicted in FIG. 22 are utilized to implement one or more networks and processes such as those described in connection with FIGS. 1-7.

[0403] FIG. 23 is a block diagram of a graphics processor 2300, according to at least one embodiment. In at least one embodiment, graphics processor 2300 includes a ring interconnect 2302, a pipeline front-end 2304, a media engine 2337, and graphics cores 2380A-2380N. In at least one embodiment, ring interconnect 2302 couples graphics processor 2300 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2300 is one of many processors integrated within a multi-core processing system.

[0404] In at least one embodiment, graphics processor 2300 receives batches of commands via ring interconnect 2302. In at least one embodiment, incoming commands are interpreted by a command streamer 2303 in pipeline front-end 2304. In at least one embodiment, graphics processor 2300 includes scalable execution logic to perform 3D geometry processing and media processing via graphics core(s) 2380A-2380N. In at least one embodiment, for 3D geometry processing commands, command streamer 2303 supplies commands to geometry pipeline 2336. In at least one embodiment, for at least some media processing commands, command streamer 2303 supplies commands to a video front end 2334, which couples with media engine 2337. In at least one embodiment, media engine 2337 includes a Video Quality Engine (VQE) 2330 for video and image post-processing and a multi-format encode / decode (MFX) 2333 engine to provide hardware-accelerated media data encoding and decoding. In at 16 05 23 least one embodiment, geometry pipeline 2336 and media engine 2337 each generate execution threads for thread execution resources provided by at least one graphics core 2380.

[0405] In at least one embodiment, graphics processor 2300 includes scalable thread execution resources featuring graphics cores 2380A-2380N (which can be modular and are sometimes referred to as core slices), each having multiple sub-cores 2350A-50N, 2360A-2360N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2300 can have any number of graphics cores 2380A. In at least one embodiment, graphics processor 2300 includes a graphics core 2380A having at least a first sub-core 2350A and a second sub-core 2360A. In at least one embodiment, graphics processor 2300 is a low power processor with a single sub-core (e.g., 2350A). In at least one embodiment, graphics processor 2300 includes multiple graphics cores 2380A-2380N, each including a set of first sub-cores 2350A-2350N and a set of second sub-cores 2360A-2360N. In at least one embodiment, each sub-core in first sub-cores 2350A-2350N includes at least a first set of execution units 2352A-2352N and media / texture samplers 2354A-2354N. In at least one embodiment, each sub-core in second sub-cores 2360A-2360N includes at least a second set of execution units 2362A-2362N and samplers 2364A-2364N. In at least one embodiment, each sub-core 2350A-2350N, 2360A-2360N shares a set of shared resources 2370A-2370N. In at least one embodiment, shared resources include shared cache memory and pixel operation logic.

[0406] Inference and / or training logic 815 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 815 are provided herein in conjunction with FIGS. 8A and / or 8B. In at least one embodiment, inference and / or training logic 815 may be used in graphi...

Claims

01 04 251. A processor comprising:one or more circuits to use one or more neural networks to:generate one or more bounding boxes in one or more first images; and segment one or more first objects of the one or more first imagesbased, at least in part, on the one or more bounding boxes;wherein the one or more neural networks include a teacher neural network having a first version of the one or more neural networks and a student neural network having a different version from the first version of the one or more neural networks.

2. The processor of claim 1, wherein the one or more neural networks are further to determine correspondence between the segmented one or more objects in the one or more first images and one or more objects in one or more second images.

3. The processor of claim 1 or claim 2, wherein the one or more neural networks comprise at least two neural networks and the at least two neural networks include a supervised neural network and an unsupervised neural network.

4. The processor of any preceding claim, wherein the one or more circuits are to use the one or more neural networks to determine one or more classifications of the one or more first objects.

5. The processor of any preceding claim, wherein the one or more circuits are to use the one or more neural networks to determine instances of the one or more first objects in the one or more first images.

6. Hie processor of any preceding claim, wherein the one or more circuits are to use the one or more neural networks to determine semantic correspondence between the one or more first objects in the one or more first images.

7. The processor of any preceding claim, wherein the one or more circuitsare to use the one or more neural networks to segment the one or more first objects during training of the one or more neural networks.01 04 258. The processor of any preceding claim, wherein the one or more circuits are to use the one or more neural networks simultaneously to segment the one or more first objects of the one or more first images and to generate the one or more bounding boxes.

9. A system comprising: one or more computers having one or more processors to use one or more neural networks to: generate one or more bounding boxes in one or more first images; and segment one or more first objects of one or more first images based, at least in part, on the one or more bounding boxes; wherein the one or more neural networks include a teacher neural network having a first version of tire one or more neural networks and a student neural network having a different version from the first version of the one or more neural networks.

10. The system of claim 9, wherein the one or more neural networks are further to determine correspondence between the segmented one or more objects in the one or more first images and one or more objects in one or more second images.

11. The system of claim 9 or claim 10, wherein the one or more neural networks comprise at least two neural networks and the at least two neural networks include a supervised neural network and an unsupervised neural network.

12. The system of any of claims 9 to 11, wherein the one or more circuits are to use the one or more neural networks to determine one or more classifications of the one or more first objects.

13. The system of any of claims 9 to 12, wherein the one or more circuits are to use the one or more neural networks to determine instances of the one or more first objects in the one or more first images.

14. The system of any of claims 9 to 13, wherein the one or more circuits are to use the one or more neural networks to determine semantic correspondence between the one or more first objects in the one or more first images.

15. The system of any of claims 9 to 14, wherein the one or more circuits are to use the one or more neural networks to segment the one or more first objects during training of the one or more neural networks.01 04 2516. The system of any of claims 9 to 15, wherein the one or more circuits are to use the one or more neural networks simultaneously to segment the one or more first objects of the one or more first images and to generate the one or more bounding boxes.

17. A machine-readable medium having stored thereon a set ofinstructions, which if performed by one or more processors, cause the one or more processors to use one or more neural networks to: generate one or more bounding boxes in one or more first images; and segment one or more first objects of one or more first images based, at least in part, on one or more bounding boxes; wherein the one or more neural networks include a teacher neural network having a first version of the one or more neural networks and a student neural network having a different version from the first version of the one or more neural networks.

18. The machine-readable medium of claim 17, wherein the one or more neural networks are further to determine correspondence between the segmented one or more objects in the one or more first images and one or more objects in one or more second images.

19. Hie machine-readable medium of claim 17 or claim 18, wherein the one or more neural networks comprise at least two neural networks and the at least two neural networks include a supervised neural network and an unsupervised neural network.

20. The machine-readable medium of any of claims 17 to 19, wherein the one or more circuits are to use the one or more neural networks to determine one or more classifications of the one or more first objects.

21. The machine-readable medium of any of claims 17 to 20, wherein the one or more circuits are to use the one or more neural networks to determine instances of the one or more first objects in the one or more first images.

22. The machine-readable medium of any of claims 17 to 21, w herein the one or more circuits are to use the one or more neural networks to determine semantic correspondence between the one or more first objects in the one or more first images.

23. The machine-readable medium of any of claims 17 to 22, wherein the one or more circuits are to use the one or more neural networks to segment the one or more first objects during training of the one or more neural networks.

24. The machine-readable medium of any of claims 17 to 23, wherein the one or more circuits are to use the one or more neural networks simultaneously to segment the one or more first objects of the one or more first images and to generate the one or more bounding boxes.01 04 25

Images