A system and method for detecting a pattern in a data stream

Abstract

A system 200 for detecting a pattern in a data stream comprises an optical multiplication circuit 210 adapted to multiply a plurality of optical input vectors with a pattern matrix, the input vectors comprising a set of input signals encoding data values, and wherein the pattern matrix comprises target values of the pattern to be detected. Upon multiplying each optical input vector with the pattern matrix, the multiplication circuit provides a set of multiplication values (optical output signals). The system further comprises a comparator 230 configured to compare the values with at least one threshold to identify the pattern or a similar pattern in the vectors, wherein the comparator may identify the highest value. The vectors may be multiplied sequentially or in parallel on different wavelength channels. Vector generator 220 may convert the data stream from the electronic to the optical domain, and may comprise a format converter 222 and an electrical to optical domain converter 224. The multiplication circuit may comprise a plurality of input, output and coupling waveguides, and a plurality of amplitude adjusters whose transmission factors are set to encode the pattern to be detected.

Description

Figure 1 is a flow chart of a method for detecting a pattern in a data stream. The method includes the steps 110-140. Figure 2 is a diagram of a system for detecting a pattern in a data stream. The system 200 includes an optical multiplication circuit 210 coupled to an identifier 230, also referred to as comparator circuit or threshold detection circuit. Optionally, the system 200 may also include a controller 205 for controlling a set of amplitude adjusters or modulators present in the optical multiplication circuit 210. Depending on the nature and format of the data stream, a vector generator 220 may be provided to generate optical input vectors suitable for use by the multiplication circuit. The vector generator 220 may include a format converter 222 and an electronic to optical domain converter 224. The optical multiplication circuit 210 is adapted to multiply a plurality of optical input vectors with a pattern vector or pattern matrix. The optical input vectors include a set of logic values (0 or 1) and the pattern vector includes logic values of the pattern to be detected. The optical multiplication circuit 210 is used to receive the optical input vectors and multiply each input vector with the pattern vector to provide a set of multiplication values. The identifier 230 is configured to identify the highest multiplication value among the set of multiplication values. The highest multiplication value corresponds to the input vector comprising the pattern. A data converter not shown may be provided to identify logic low values (0) in the input vectors and the pattern vector, and to convert each logic low value (0) to an inverted logic high value (-1) prior to the multiplication step. The data converter may be provided as part of the vector generator 220 or as a separate data processor circuit. In a mathematical example the pattern / 1\ to find may be written as pattern vector: 0 \1 / / 1\ / 1\ / 0\ / 0\ The input data in vector form may be the input vectors: 0,1,0,0 \1 / \1 / W \1 / The data converter converts all the 0 of the pattern and input vector entries into -1. This can be achieved by setting the input reference adjustors / modulators used to generate the optical input vectors and the matrix reference adjustors / modulators to a middle state (half opened state / ). The matrix reference modulators enable negative matrix entries (can be used to convert the Os in the pattern also to -1). Each reference amplitude adjuster is operable in a plurality of states that include a first state for minimum transmission (closed state), a second state for maximum transmission (open state), and a middle state between the first state and the second state. Each input reference amplitude adjuster and each matrix reference amplitude adjuster is set to the middle state. The minimum and maximum transmissions depend of the implementation of the adjustors. If the first state corresponds to 50% transmission and the second states corresponds to 100% transmission, then the middle state corresponds to 75% transmission. / i \ The pattern to find becomes the new pattern vector: —1 , and \ 1 / / 1 \ Zl\ / -1\ / -1 The input vectors become the new input vectors: -1,1,-1, -1 \ 1 / \1 / \-l / \ 1 The multiplication circuit is then used to calculate dot products between the (new) input vectors and the (new) pattern vector as follows: / 1 \ / 1 \         / 1\ / 1 \          / -1\ / 1 \        / -1\ / 1 \ -1 • -1 =3;      1 • -1 1=1;      -1 • -1 =-l;    -1 • -1 =1 \ 1 / \ 1 /        \1 / \ 1 /         \-l / \ 1 /        \ 1 / \ 1 / The output of the dot product is the highest if the pattern vector and the input vector match. The output value also provides a measure of similarity between pattern vector and input vector. The more bits match, the higher the output. Exact matches or degrees of similarity may be identified by setting a threshold value for the identifier. In the above example one can detect exact matches by setting the threshold to be equal or greater than 3 to detect the exact pattern match. A plurality of threshold values may be used to identify a degree of similarity with the pattern. In this case each threshold value may be set to a predetermined level to identify a match or a degree of similarity between an input vector and the pattern. The input data stream can be either electronic or optical in nature. The input data may also have different format, for instance a serial data format or a parallel data format. If the input data stream is received from an electronic domain, the vector generator 220 converts the data stream from the electronic domain to the optical domain. The multiplication circuit, also referred to as photonic matrix, receives parallel inputs, so in case of parallel optical input, the vectors can be directly sent to the multiplication circuit. When the input data stream is provided in a serial data format, the data need to be parallelized, hence converted to the parallel data format. Figure 3 shows a format converter circuit for converting serial data to parallel data. The format converter 300 includes a splitter for splitting the input data stream into N sub data streams. In this example the format converter 300 is designed for a data pattern length of 3 bits and N = 3, however it will be appreciated that N may take different values depending on the data pattern length. The splitter 310 is coupled to 3 waveguides 312, 314 and 316. The waveguide 312 has no optical delay line. The waveguide 314 has one optical delay line 324, and the waveguide 316 has two optical delay lines 326a and 326b. This principle can be extended to N waveguides in which the first waveguide has no delay line, the second waveguide 1 delay line and the Nth waveguide has N-l optical delay lines. In this example each optical delay line has a same fixed delay (same length) to delay the data stream by 1 bit. In another example the multiple delay lines on a single waveguide are combined. For instance waveguide 316 may have a single delay line having a length equal to twice the length of the delay line 324. So for N waveguides, the length of the delay line on the Nth waveguide would have a length of (N-1) times the length of the delay on the second waveguide. The optical delay lines can be implemented in different ways. For instance they may be optical fibres, on-chip waveguides (Si, SiN, ..), free-space sections. As explained above, the optical delay lines may be fixed or variable. In operation, the splitter 310 receives the data stream and split it into 3 sub data streams such that the second sub data stream is delayed by 1 bit with respect to the first data stream, and the third sub data stream is delayed by 2 bits with respect to the first sub data stream. For each sub data stream, the first 2 bits and the last 2 bits are discarded. For a N splitter this would N-l bits. The bit discarding functions may be performed in different ways. For instance, a timer may be used to identify when, that is at which time step, the system should start performing the matching. A clock may be recovered from the input data stream. As explained above, the first two columns are discarded, then the third column (which corresponds to the input to the matrix multiplier at a certain time step) of the sub data streams corresponds to the first three bits (bits 1 to 3) of the input data stream, and the fourth column corresponds to bits 2 to 4 of the input data stream, etc... In this way the input data stream is converted from serial format into a parallel or vector format. Figure 4 is a diagram of another format converter circuit for converting serial data to parallel data. The format converter 400 has two splitters 410 and 420, each splitter being adapted to split an input signal input into two sub signals. The first splitter 410 is coupled to waveguides 412 and 414. The waveguide 414 is coupled to the input of the second splitter 420. The second splitter 420 is coupled to two waveguides 422 and 424. The waveguides 412 and 422 have no optical delay lines, while the waveguides 414 and 424 have each one optical delay line. The splitting ratio of the splitters 410 and 420 is chosen to obtain an equal amount of power at the three outputs of the format converter. In this example 1 / 3 of the input signal goes to waveguide 412, and 2 / 3 to the waveguide 414. Then the splitter 420 splits the incoming sub signal 50 / 50. As a result, the channels 412, 422 and 424 each provide 33% (1 / 3) of the input signal. The format converter 400 has three outputs for providing three sub data streams. The format converter 400 performs the same function as the format converter 300 but can be implemented with a smaller footprint. The format converter 400 also reduces optical losses. Figure 5 is a diagram of a device for performing a multiplication operation in the optical domain. The optical system or device 500 includes a matrix multiplication unit 510 coupled to an input unit 520 and an output unit 530. The input unit 520 and the output unit 530 may be referred to as input and output circuits, respectively. A controller 505 is provided to control the operation of the various amplitude adjusters provided in the circuit 500. An amplitude adjuster may be an optical modulator or an optical amplifier or a combination of both. For instance the controller may adjust the transmission factor or transmission coefficients of the adjusters. When the adjuster is an amplifier the transmission factor may be greater than 1. The matrix multiplication unit 510 also referred to as multiplication circuit, has a plurality of cells comprising at least one primary cell also referred to as data cell, and at least one reference cell. The primary cell has a primary adjuster (M) having a primary transmission factor (A). The primary adjuster may be referred to as data adjuster and the primary transmission factor as data transmission factor. Each reference cell has a reference adjuster (Mref) having a reference transmission factor (Aref). The matrix multiplication unit 510 has two input waveguides 512a and 512b (rows) coupled to the light source unit 520 and three output waveguides 513a, 513b, 513c (columns) coupled to the output unit 530. It will be appreciated that the number of input and output waveguides may vary and can be generalised to Nin input waveguides and Mout output waveguides. The input and output waveguides 512, 513 are arranged to form a grid of multiplication unit cells 511. For each unit cell, the input and output waveguides 512, 513 cross one another at a crossing point C. A coupler or coupling channel / waveguide 514 is interposed between the input waveguide 512 and the associated output waveguide 513. The coupler 514 is provided with an amplitude adjuster M. The amplitude adjusters may be implemented in different fashion and can be made of any material that is switchable between different states corresponding to different optical properties of the adjuster. An optical amplifier may be implemented as a semiconductor optical amplifier SOA. An optical attenuator may be Mach Zehnder modulators (MZMs) also referred to as Mach Zehnder interferometers (MZIs), or electroabsorption modulators (EAMs), electro optic modulator (EOM), or microring resonators (MRR), or a phase-change material (PCM) modulators. An attenuator can be used to cancel or extinct an optical signal that should not be transferred to an output port. In this scenario the amplifier is turned off and the attenuator is turned on. The amplifier / attenuator combination may be implemented using a same component or as two separate components. An adjuster component, such as for instance an SOA, may be designed to perform signal amplification when a positive voltage is applied to it, and to perform signal attenuation when a negative voltage is applied to it. The input waveguide 512 and the coupler 514 act as two directional couplers in the unit cell, with fixed transmission. The input waveguide 512 splits light from the input row so that part of the light is transmitted along 512 to the next cell and part of the light is sent to the adjuster M to adjust the amplitude of the light hence increase or attenuate the light intensity. The coupler 514 then adds the modulated light to the output waveguide 513 so that each unit cell contributes equally to the output. In figure 5, six unit cells are shown. Four primary cells labelled 511aa, 511ab, 511ba, 511bb are provided with adjusters Maa, Mab, Mba, Mbb. Two reference cells labelled 511ca, 511cb are provided with adjusters Mca, Mcb, respectively. Each adjuster has a corresponding transmission factor or transmission coefficient labelled A. For instance adjuster / modulator Maa has transmission factor An. The input unit 520 is configured to generate one or more input signals. Each input signal includes two signals: an input optical signal at a data wavelength (Ad) and an input reference optical signal at a reference wavelength (Aref). The input unit 520 has a light source 521 coupled to a plurality of combiners or wavelength multiplexers 522a and 522b. The light source 521 is configured to provide optical signals with different wavelengths. In this example two wavelengths are used: Adi, and Aref. The output of multiplexer 532a is coupled to the input waveguide 512a, and the output of multiplexer 532b is coupled to the input waveguide 512b. The light source 521 is coupled to each multiplexer via two waveguides; a first waveguide fitted with a first modulator / adjuster Ml or M2 for providing a first input optical signal, and a second waveguide fitted with a reference modulator / adjuster Mlref or M2ref for providing an input reference optical signal. In figure 5, the multiplexer 522a receives the input optical signal VI, and the input reference optical signal Vref,l. Similarly, the multiplexer 522b receives the input optical signal V2, and the input reference optical signal Vref,2. In some applications the optical input signals VI, V2 are provided by another optical system and therefore do not need to be generated by the circuit 520. In such cases the controller 505 would not receive the input data stream, and the input unit 520 may be modified to only provide the reference signals Vrefl, Vref2. Optionally, optical amplifiers (not shown) may be provided at the output of the output channels 513a, 513b and 513c. The output unit 530 includes three splitters or wavelength demultiplexers labelled 532a, 532b and 532c, coupled to the output of the output waveguides 513a, 513b and 513c respectively. Each splitter / wavelength demultiplexer is adapted to split the output signal in a plurality of wavelength dependent sub signals. In this example the wavelength demultiplexers split the output signals in two sub signals at the data wavelength and the reference wavelength respectively. A pair of photodetectors is coupled to each demultiplexer via waveguides. The demultiplexer 532a is coupled to photodetectors DI and D2 for measuring photo current intensities from optical powers Oi,i and Oi,2, respectively. The demultiplexer 532b is coupled to photodetectors D3 and D4 for measuring photo current intensities from ¢)2,1 and ¢)2,2. The demultiplexer 532c is coupled to photodetectors D5 and D6, for measuring photo current intensities from Or,i and Or,2. The output of each photodetector is coupled to a subtraction circuit 535 for generating the result signals RI and R2. An input vector may have a plurality Nin of input signals. In figure 5 Nin=2, but the matrix multiplication unit 510 may be extended to receive any number Nin of inputs. It will also be appreciated that the input unit 520 may be extended to generate multiple input vectors. For example for two input vectors the light source 521 would be coupled to each multiplexer via three waveguides, and would provide signals at Adi for the first vector, Ad2 for the second vector, and Aref. In this case each demultiplexer would be connected to a third detector for detecting the second data wavelength Ad2. More generally for a number N of input vectors N different data wavelengths are provided: Adi- AdN, and the same reference wavelength Aref is used for all the input reference optical signals. Then each demultiplexer is coupled to N+l detectors. In operation the input optical signal at a first data wavelength (Adi) and the input reference optical signal at the reference wavelength (Aref) travel together but independently in the matrix 510. For each input signal two pairs of output modulated signals are obtained: a first pair of output modulated signals modulated by a primary modulator / adjuster, and a second pair of output modulated signals modulated by a reference modulator / adjuster. The output adjusted / modulated signals obtained at the output of waveguides 513a, 513b and 513c are then separated (demultiplexed based on their wavelength) before being detected by the photodetectors D1-D6. The one or more input signals form an input vector, and the transmission factors of the modulators / adjusters present in the multiplication circuit from a coefficient matrix. The subtraction circuit 235 is then used to process the first and second pairs of output modulated signals to obtain a result R (RI, R2) of a multiplication operation of the input vector with the coefficient matrix. The values of can be obtained from the detected values as follows: _ ol,l~°l,2~°r,l+ °r,2                                  r _ °2,l~°2,2~°r,l+ °r,2 Onorm                                            Onorm By multiplying the input vector with reference matrix states (extra column 521ca, 521cb) and multiplying the matrix states with a reference vector, one can obtain the input-dependent offset values to be subtracted to find the correct mathematical result of the matrix vector multiplication (MVM). In this way the reference values are obtained in parallel at the same time together with the data outputs. Using a balanced detection scheme between the input and reference vector outputs and a subsequent analogue electronic subtraction to remove the offset using the reference column, reveals the mathematical result in real time. The optical system 500 is used to perform the multiplication A-V = R with A = ^21' and In which Aii’ is the mathematical value encoded in the adjuster / modulator of the corresponding primary cell; V / is the value encoded in the input power Pinl of the first input optical signal; V2' is the value encoded in the input power Pin_2 of the second input optical signal; R^is the value encoded in the out power Pout l of the first output optical signal; and R2 is the value encoded in the out power Pout_2 of the second output optical signal. The values R^ and R2' of vector R can be expressed as: Ri = A1±'■    + A12'■ V2' and ^2 = ^21 '     "I” ^22 ’    • The photodetectors D1-D6 detect the optical powers 0^, O12, O22, Or l, Or2 in parallel simultaneously. The detected optical power is converted to a current that is proportional to the optical power. The photodetector DI detects O11= Alt ■ Pin_l + / 1^ ■ Pin_2 at Adi. The photodetector D2 detects 2= ^11 ‘ Pin_refl + / 1^ ■ Pin_ref2 at Aref. The photodetector D3 detects O2,i= ^21 ’ Pi^A + A22 ■ Pin_2 at Adi. The photodetector D4 detects O2;2= i421 ■ Pin_refl + A22 ■ Pin_ref2 at Aref. The photodetector D5 detects Orl= Aref ■ Pin_l + Aref ■ Pin_2 at Adi. The photodetector D6 detects Or2= Aref ■ Pin_refl + Aref ■ Pin_ref2 at Aref. In which Aii are transmission factors of the adjusters / modulators; Pin l is optical power of the input optical signal VI; Pin_2 is optical power of the input optical signal V2; Pinrefl is optical power of the input reference optical signal Vrefl; Pin_ref2 is optical power of the input reference optical signal Vref2. The values of can be obtained from the detected values as follows: r   ^1,1-^1,2 ~^r,l + °r,2                                  r   O2,l~°2,2~°r,l^ °r,2 Onorm                                            ^norm The pattern to be searched is encoded in a matrix column; and multiple patterns can be in multiple columns. The data pattern to be searched is the input vector. A reference vector (Vrefl, Vref2) and a reference column (511ca, 511cb) are used to perform a reference subtraction electronically to reveal the multiplication result (RI, R2). This permits to ensure that the accurate pattern match yields the highest output value. The vector V (VI,V2) is compared to the patterns encoded in the primary adjusters Maa, Mab, Mba, Mbb. The modulators Maa, Mab, Mba, Mbb are set to either closed (logic 0) or open (logic 1) depending on the pattern to be searched. The reference adjusters / modulators Mca, Mcb are set to the middle state between open and closed. The reference vector Vref is set to the middle state between open and closed. At the output, the reference subtraction is performed and the result fed to the identifier also referred to as threshold detection unit. Figure 6 is a diagram illustrating the operation of the identifier circuit or threshold detection unit. The identifier includes a comparator for comparting the result of the matrix vector multiplication electronic signal (current or voltage) after reference subtraction to a threshold to identify whether the pattern matches or not. If the threshold is exceeded a pattern match is detected. The deviation from the threshold gives an indication of how many bits match (if an ADC is used instead of a simple comparison between two values). The matrix multiplication circuit may be implemented in different ways. Figure 7 is a diagram of another multiplication circuit. The circuit 700 may be used instead of the circuit 510 in figure 5 in combination with input and output circuits 520 and 530. The circuit 700 has two input ports coupled to input channels 701 and 702, and three output ports coupled to three output channels 791, 792, 793. The coupling between the input channels and output channels is provided by three sets of coupling channels labelled 710, 720, 730, referred to as primary sets. In each primary set the coupling channels are configured to couple the plurality of input channels to a single output channel. The first set 710 has two coupling channels 711, 712 configured to couple the input channels 701, 702 to the first output channel 791. The coupling channel 711 is provided between the first input channel 701 and the first output channel 791; the coupling channel 712 is provided between the second input channel 702 and the first output channel 791. A similar arrangement is shown for the sets 720 and 730. The device 700 is also provided with two secondary sets. In a secondary set the coupling channels are configured to couple a single input channel to a plurality of output channels. The coupling channels 711, 721, 731, form a first secondary set. In this way each input channel may be coupled to a plurality of outputs. It will be appreciated that the above arrangement may be extended to any number of input channels and any number of output channels. Each coupling channel extends between a first coupler, also referred to as input coupler, coupled to an input channel; and a second coupler, also referred to as output coupler, coupled to the corresponding output channel. For instance, the coupling channel 711 extends between the input coupler Cla at the input channel 701 and the output coupler Coutla at the output channel 791. Each coupling channel is provided with both an optical amplifier and an optical attenuator. For example the coupling channel 711 is provided with optical amplifier 761a and optical attenuator 771a. Similarly coupling channel 712 is provided with optical amplifier 761b and optical attenuator 771b. Optionally optical amplifiers 781, 782, 783 may be provided on the output channels 791, 792 and 793. The optical amplifiers may be implemented as a semiconductor optical amplifiers SOAs. The optical attenuators may be Mach Zehnder modulators (MZMs) also referred to as Mach Zehnder interferometers (MZls), or electroabsorption modulators (EAMs), or micro-ring resonators, or a phase-change material (PCM) modulators. In an alternative embodiment at least one or each coupling channel is provided with two optical amplifiers and no optical attenuator. In an alternative embodiment at least one or each or each coupling channel is provided with two optical attenuators and no optical amplifier. In an alternative embodiment at least one or each coupling channel is provided with only one optical attenuator or only one optical amplifier. The combination of amplifier and attenuator to set the pattern increases the dynamic range (ratio between open and closed) and therefore signal to noise ratio to detect the pattern match. The splitting ratios of the couplers used in multiplication circuits of figure 5 and 7 are set to achieve equal splitting of light to all outputs. However, different splitting ratios, may be selected. Figure 8A is a diagram illustrating the splitting ratios set to achieve equal splitting of light to all outputs. The numbers (ratios) indicate what fraction of light is split to the cross port. The adjusters / modulators are programmed to the matrix state. If the matrix values are fixed, there is no need for the programmable adjusters / modulators. Figure 8B is a diagram illustrating a multiplication matrix without any adjuster / modulator. In this case the desired optical attenuation of the optical signal is provided by the splitting ratios. Induced losses are controlled by selecting the splitting ratios appropriately for various couplers of the cell. For instance in the top left cell of figure 8B, instead of coupling 1 / 3 of the light down as in the standard implementation (see Figure 8A), an attenuation coefficient (Al) is applied to the splitting ratio (1 / 3*A1). The light coupled to the column waveguide now is the same as if there was a modulator in state Al. One can also use the second splitting ratio in a cell. Looking at the top left cell in figure 8B if the first splitter is set to 1 / 3 as usual, the second one (currently 1 / 1) can be adjusted to include the transmission factor of the modulator. For a fully closed modulator, the splitting ratio is set to 0 / 1. In this case the light is scattered out of the circuit and not transferred to the column. Figure 8C is a diagram illustrating a multiplication matrix without any adjuster / modulator, and with some cells having no couplers. To achieve maximum dynamic range (previously between open and closed modulator state) one can even remove at least some splitters to encode a logic low (0). This is analogous to a modulator that attenuates the light completely. The splitting ratios illustrated in figures 8B and 8C are provided for example only and would need to be adjusted based on the required data patterns to be searched. The same principle may be applied to the circuit topology of figure 7. When using a fixed matrix with no modulators as shown in figure 8B or 8C, one may still add an additional reference column with matrix reference modulators. Figure 9 shows a modification of the circuit of figure 7. In this example the amplifiers / attenuators have been removed. The optical amplifiers provided on the output channels are optional. A fixed implementation without adjusters / modulators is advantageous for compact and low power applications. This can be achieved when the pattern or patterns to be searched do not change over time. The system described with reference to figures 1 to 9 enables the detection of data patterns as well as correlations in a data stream at ultra-high speed. The pattern detection can happen in a single clock step which in photonic circuits can be down to about 10 ps. This has applications in various domains. The proposed system and method may be used to configure an all-optical switch (optical routing) based on a tag at the start of a packet (data header). Packet based switching is currently done electronically only. A photonic implementation opens-up new applications and significantly reduce network latency and power consumption. The proposed method may also be used in the financial industry, for instance to perform to perform high frequency trading (especially Trade at Settlement (TAS). If a certain bit sequence is detected, a trade is executed. Any gain in latency is most advantageous. The system and method may also apply to many detection systems. The pattern detection can be used as a fast trigger to start further processing. For example, in a particle collider a huge amounts of data are generated, the system could look out for a certain pattern and then start saving data for further processing. Other applications may include content addressable memory (CAM) management. The various waveguides / channels described above with reference to figures 3 to 9 may be integrated or fibre based. The system as describe with reference to figures 1 to 9 may be implemented using an integrated optical circuit such as a photonic integrated circuit (PIC). A skilled person will appreciate that variations of the disclosed arrangements are possible without departing from the disclosure. Accordingly, the above description of the specific embodiments is made by way of example only and not for the purposes of limitation. It will be clear to the skilled person that minor modifications may be made without significant changes to the operation described.

Claims

1. A system for detecting a pattern in a data stream, the system comprisingan optical multiplication circuit adapted to multiply a plurality of optical input vectors with a pattern matrix; wherein the optical input vectors comprise a set of input signals encoding data values and wherein the pattern matrix comprises target values of the pattern to be detected;wherein upon multiplying each optical input vector with the pattern matrix, the optical multiplication circuit provides a set of multiplication values; anda comparator configured to compare the multiplication values with at least one threshold value to identify the pattern or a similar pattern in the plurality of optical input vectors.

2. The system as claimed in claim 1, wherein the plurality of optical input vectors are multiplied with the pattern matrix sequentially, or wherein the plurality of optical input vectors are multiplied with the pattern matrix in parallel on different wavelength channels, each optical input vector having its own data wavelength.

3. The system as claimed in claim 1 or 2, wherein the comparator is configured to identify the highest multiplication value among the set of multiplication values.

4. The system as claimed in any of the preceding claims comprising an input stage having a light source coupled to at least one wavelength multiplexer, the light source being coupled to each wavelength multiplexer via a reference channel provided with an input reference amplitude adjuster, the light source being configured to provide optical signals at a reference wavelength.

5. The system as claimed in claim 4, wherein each input reference amplitude adjuster is operable in a plurality of states that include a first state for minimum transmission, a second state for maximum transmission, and a middle state for fifty percent transmission, and wherein each input reference amplitude adjuster is set to the middle state.

6. The system as claimed in any of the claims 4 to 6, wherein for each optical input vector, each wavelength multiplexer is configured to receive an optical signal at a data wavelength.

7. The system as claimed in any of the preceding claims, wherein theoptical multiplication circuit comprisesa plurality of input waveguides;a plurality of output waveguides; anda plurality of coupling waveguides, each coupling waveguide being configured to couple an input waveguide to an output waveguide.

8. The system as claimed in claim 7, wherein a plurality of coupling channels comprises an amplitude adjuster, wherein the amplitude adjuster comprises an optical modulator or an optical amplifier or a combination of both.

9. The system as claimed in claim 8, wherein each amplitude adjuster has a transmission factor.

10. The system as claimed in claim 9, comprising a controller configured to set the transmission factor of each amplitude adjuster to encode the pattern to be detected.

11. The system as claimed in any of the preceding claims, wherein the optical multiplication circuit comprises a plurality of cells, the said plurality of cells comprising at least one primary cell and at least one reference cell;the system being configured such that upon sending the said at least one input signal to the multiplication circuit, a first pair of output adjusted signals adjusted by the primary cell, and a second pair of output adjusted signals adjusted by the reference cell are obtained for each input signal;the system further comprising an output circuit adapted to detect the first and second pairs of output adjusted signals; wherein the said at least one input signal forms an input vector, and wherein the transmissions factors of the cells form a coefficient matrix; and to process the first and second pairs of output adjusted signals to obtain a result of a multiplication operation of the input vector with the coefficient matrix.

12. The system as claimed in claim 11, wherein each reference cell has a matrix reference amplitude adjuster having a reference transmission factor.

13. The system as claimed in claim 11 or 12, wherein each primary cell has a primary amplitude adjuster having a primary transmission factor, or wherein at least one primary cell has a coupler and wherein the cell transmission factor is based on splitting ratios of the coupler.

14. The system as claimed in any of the claims 11 to 13, wherein the first pair of output adjusted signals is adjusted by the primary amplitude adjuster, and the second pair of output adjusted signals is adjusted by the reference amplitude adjuster.

15. The system as claimed in claim 11, wherein each matrix reference amplitude adjuster is operable in a plurality of states that include a first state for minimum transmission, a second state for maximum transmission, and a middle state between the first state and the second state, and wherein each matrix reference amplitude adjuster is set to the middle state.

16. The system as claimed in any of the claims 7 to 15, wherein the pattern is fixed, and wherein each coupling channel has a splitting ratio, the fixed pattern being encoded based on splitting ratios of the coupling channels.

17. The system as claimed in any of the preceding claims, comprising a vector generator configured to receive a data stream comprising a set of data values and to provide the plurality of optical input vectors.

18. The system as claimed in claim 17, wherein the vector generator comprises at least one of a format converter and an electronic to optical domain converter.

19. The system as claimed in claim 18, wherein the data stream is received from an electronic domain, and wherein the electronic to optical domain converter is configured to convert the data stream from the electronic domain to the optical domain.

20. The system as claimed in claim 18 or 19, wherein the data stream is a serial data stream, and wherein the format converter is configured to convert the serial data stream into parallel format.

21. The system as claimed in any of the claims claim 18 to 19, wherein the format converter comprises at least one splitter having aninput channel for receiving the data stream and a plurality of output channels, wherein at least one output channel is provided with an optical delay line.

22. The system as claimed in claim 21, wherein the said at least one splitter comprises a plurality of splitters coupled in series, each splitter having a plurality of output channels and wherein one or more output channel is coupled to the next splitter in the series.

23. A method for detecting a pattern in a data stream, the method comprisingreceiving a data stream comprising a set of data values forming one or more optical input vectors;generating a pattern matrix comprising target values of the pattern to be detected;multiplying each input vector with the pattern matrix in the optical domain to obtain a set of multiplication values;comparing the multiplication values with at least one threshold value to identify the pattern or a similar pattern in the plurality of optical input vectors.

24. The method as claimed in claim 23, comprising identifying the highest multiplication value among the set of multiplication values.

25. The method as claimed in claim 23 or 24, wherein the said at last one threshold value comprises a plurality of threshold values, the method comprising setting each threshold value to a predetermined level to identify a degree of similarity between an input vector and the pattern.

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