Display substrate and display device

Abstract

A display substrate and a display device. The display substrate is provided with a display side, and comprises a base substrate (110), a driving circuit layer (120), a first electrode layer and a pixel-defining layer (1017). The driving circuit layer (120) is arranged on the base substrate (110) and comprises a plurality of first gaps (D1), and the plurality of first gaps (D1) allow light from the display side to pass therethrough. The first electrode layer is arranged on the side of the driving circuit layer (120) away from the base substrate (110), and comprises a plurality of first electrode patterns (1041) and a plurality of light-shielding patterns (SH). The pixel-defining layer (1017) is arranged on the side of the first electrode layer away from the base substrate (110) and comprises a plurality of sub-pixel openings (PO), and the plurality of sub-pixel openings (PO) respectively expose the plurality of first electrode patterns (1041). In a direction perpendicular to the base substrate (110), at least some light-shielding patterns (SH) do not overlap with the plurality of sub-pixel openings (PO), and at least some light-shielding patterns (SH) respectively correspond to and at least partially overlap with at least some first gaps (D1) in the plurality of first gaps (D1), so as to at least partially block light from the display side.

Description

Display substrate and display device Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0002] OLED (Organic Light Emitting Diode) display devices have a series of advantages such as self-luminescence, high contrast, high clarity, wide viewing angle, low power consumption, fast response speed, and low manufacturing cost. They have become one of the key development directions of the new generation of display devices and are therefore receiving increasing attention.

[0003] Currently, display devices generally have multiple functions such as fingerprint recognition. In this case, the structure of the display device can be adjusted accordingly according to these functions.

[0004] Summary of the Invention

[0005] At least one embodiment of the present disclosure provides a display substrate, which has a display side and includes a base substrate, a driving circuit layer, a first electrode layer and a pixel defining layer, wherein the driving circuit layer is arranged on the base substrate and includes a plurality of first gaps, and the plurality of first gaps allow light from the display side to pass through, the first electrode layer is arranged on a side of the driving circuit layer away from the base substrate and includes a plurality of first electrode patterns and a plurality of light-shielding patterns, the pixel defining layer is arranged on a side of the first electrode layer away from the base substrate and includes a plurality of sub-pixel openings, and the plurality of sub-pixel openings respectively expose the plurality of first electrode patterns, wherein in a direction perpendicular to the base substrate, at least part of the plurality of light-shielding patterns do not overlap with the plurality of sub-pixel openings, and at least part of the plurality of light-shielding patterns respectively correspond to and at least partially overlap with at least part of the first gaps in the plurality of first gaps to at least partially block the light from the display side.

[0006] For example, in the display substrate provided in at least one embodiment of the present disclosure, the width of the plurality of first gaps is less than or equal to 4.0 micrometers.

[0007] For example, in the display substrate provided by at least one embodiment of the present disclosure, the distance between the plurality of first gaps and the centers of the plurality of sub-pixel openings is less than 33 micrometers.

[0008] For example, in the display substrate provided by at least one embodiment of the present disclosure, at least some of the plurality of light-shielding patterns are integrally connected to the plurality of first electrode patterns.

[0009] For example, in the display substrate provided in at least one embodiment of the present disclosure, each of the multiple first electrode patterns includes a main body and a connecting portion, the planar shape of the main body is a polygon or a figure with an arc-shaped edge, and the planar shape of the multiple shading patterns is a polygon.

[0010] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display substrate has a plurality of sub-pixels, each of the plurality of sub-pixels includes a light-emitting device, and the plurality of first electrode patterns respectively serve as anodes of the light-emitting devices of the plurality of sub-pixels.

[0011] For example, in the display substrate provided by at least one embodiment of the present disclosure, the multiple sub-pixels include red sub-pixels, green sub-pixels and blue sub-pixels, wherein the planar shape of the main part of the first electrode pattern of the light-emitting device of the red sub-pixel is hexagonal, and the shading pattern integrally connected to the first electrode pattern of the light-emitting device of the red sub-pixel is triangular.

[0012] For example, in the display substrate provided in at least one embodiment of the present disclosure, the number of shading patterns integrally connected to the first electrode pattern of the light-emitting device of the red sub-pixel is two, and the two shading patterns integrally connected to the first electrode pattern of the light-emitting device of the red sub-pixel are symmetrically distributed.

[0013] For example, in the display substrate provided in at least one embodiment of the present disclosure, the planar shape of the main part of the first electrode pattern of the light-emitting device of the blue sub-pixel is hexagonal, and the shading pattern integrally connected to the first electrode pattern of the light-emitting device of the blue sub-pixel is triangular or rectangular.

[0014] For example, in the display substrate provided in at least one embodiment of the present disclosure, the number of shading patterns integrally connected to the first electrode pattern of the light-emitting device of the blue sub-pixel is three, and the three shading patterns integrally connected to the first electrode pattern of the light-emitting device of the blue sub-pixel are respectively integrally connected to the three sides of the first electrode pattern of the light-emitting device of the blue sub-pixel.

[0015] For example, in the display substrate provided in at least one embodiment of the present disclosure, the planar shape of the main portion of the first electrode pattern of the green sub-pixel light-emitting device is a pentagon, and the shading pattern integrally connected to the first electrode pattern of the green sub-pixel light-emitting device is rectangular.

[0016] For example, in the display substrate provided by at least one embodiment of the present disclosure, the number of shading patterns integrally connected to the first electrode pattern of the light-emitting device of the green sub-pixel is one or two, and the one or two shading patterns integrally connected to the first electrode pattern of the light-emitting device of the green sub-pixel are respectively integrally connected to one or two sides of the first electrode pattern of the light-emitting device of the green sub-pixel.

[0017] For example, in the display substrate provided by at least one embodiment of the present disclosure, in the corresponding sub-pixel opening and the first electrode pattern, the sub-pixel opening has the same shape as the main body of the first electrode pattern, the first orthographic projection of the sub-pixel opening on the base substrate is located inside the second orthographic projection of the main body of the first electrode pattern on the base substrate, and the minimum distance between the edges of the first orthographic projection and the second orthographic projection is 1.5 microns to 3.5 microns.

[0018] For example, in the display substrate provided by at least one embodiment of the present disclosure, the light-emitting devices of the red sub-pixels and the blue sub-pixels are located in the same row, the light-emitting devices of the green sub-pixels are located in approximately the same row, and the rows where the light-emitting devices of the red sub-pixels and the blue sub-pixels are located are arranged alternately with the row where the light-emitting devices of the green sub-pixels are located.

[0019] For example, in the display substrate provided in at least one embodiment of the present disclosure, the driving circuit layer also includes a plurality of second gaps, which allow light from the display side to pass through, and in a direction perpendicular to the base substrate, the second gaps do not overlap with the plurality of first electrode patterns and the plurality of light-shielding patterns.

[0020] For example, in the display substrate provided by at least one embodiment of the present disclosure, the distance between the plurality of second gaps and the centers of the plurality of sub-pixel openings is greater than 33 micrometers.

[0021] For example, in the display substrate provided in at least one embodiment of the present disclosure, the orthographic projections of the multiple second gaps on the base substrate are respectively located between the orthographic projection of the light-emitting control signal line on the base substrate and the orthographic projection of the reset voltage line closest to the light-emitting control signal line on the base substrate.

[0022] For example, in the display substrate provided by at least one embodiment of the present disclosure, the orthographic projections of at least part of the multiple second gaps on the base substrate are respectively located between the orthographic projections of the light-emitting control signal line for the blue sub-pixel on the base substrate and the orthographic projections of the reset voltage line for the red sub-pixel on the base substrate, wherein the red sub-pixel is located in the next row of the blue sub-pixel and is adjacent to the blue sub-pixel; and / or the orthographic projections of at least part of the multiple second gaps on the base substrate are respectively located between the orthographic projections of the light-emitting control signal line for the red sub-pixel on the base substrate and the orthographic projections of the reset voltage line for the blue sub-pixel on the base substrate, wherein the blue sub-pixel is located in the next row of the red sub-pixel and is adjacent to the red sub-pixel.

[0023] For example, in the display substrate provided by at least one embodiment of the present disclosure, the width of at least some of the plurality of second gaps is greater than 4.0 micrometers.

[0024] For example, in the display substrate provided in at least one embodiment of the present disclosure, the driving circuit layer includes a plurality of pixel driving circuits and a first planarization layer, the first planarization layer is arranged on a side of the plurality of pixel driving circuits away from the base substrate, and includes a plurality of first vias, the plurality of first vias respectively exposing the output ends of the plurality of pixel driving circuits, the first electrode layer is arranged on a side of the first planarization layer away from the base substrate, and the plurality of first electrode patterns are respectively electrically connected to the output ends of the plurality of pixel driving circuits through the plurality of first vias; the display substrate also includes a spacer layer arranged on a side of the pixel defining layer away from the base substrate, the spacer layer includes a plurality of spacers; wherein, in a direction perpendicular to the base substrate, the plurality of spacers do not overlap with the plurality of first vias.

[0025] For example, in the display substrate provided by at least one embodiment of the present disclosure, in a direction parallel to the base substrate, the minimum distance between the plurality of spacers and the plurality of first via holes is greater than 2.0 micrometers.

[0026] For example, in the display substrate provided by at least one embodiment of the present disclosure, the driving circuit layer includes multiple pixel driving circuits, a first planarization layer, a connecting electrode layer, and a second planarization layer. The first planarization layer is arranged on a side of the multiple pixel driving circuits away from the base substrate, and includes multiple first vias, and the multiple first vias respectively expose the output ends of the multiple pixel driving circuits. The connecting electrode layer is arranged on a side of the first planarization layer away from the base substrate, and includes multiple connecting electrodes, and the multiple connecting electrodes are respectively electrically connected to the output ends of the multiple pixel driving circuits through the first vias. The second planarization layer is arranged on a side of the connecting electrode layer away from the base substrate, and includes multiple second vias, and the multiple second vias respectively expose the multiple connecting electrodes; the first electrode layer is arranged on a side of the second planarization layer away from the base substrate, and the multiple first electrode patterns are respectively electrically connected to the multiple connecting electrodes through the multiple second vias; the display substrate also includes a spacer layer arranged on a side of the pixel defining layer away from the base substrate, and the spacer layer includes multiple spacers; wherein, in a direction perpendicular to the base substrate, the multiple spacers do not overlap with the multiple second vias.

[0027] For example, in the display substrate provided by at least one embodiment of the present disclosure, in a direction parallel to the base substrate, the minimum distance between the plurality of spacers and the plurality of second via holes is greater than 2.0 micrometers.

[0028] For example, in the display substrate provided in at least one embodiment of the present disclosure, the height of the plurality of spacers in a direction perpendicular to the base substrate is 1.8 micrometers to 2.4 micrometers.

[0029] For example, in the display substrate provided by at least one embodiment of the present disclosure, in a direction perpendicular to the base substrate, the plurality of pixel driving circuits at least partially overlap with the plurality of sub-pixel openings.

[0030] At least one embodiment of the present disclosure further provides a display device, which includes the display substrate provided by an embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0032] FIG1 is a partial plan view of a display substrate provided by at least one embodiment of the present disclosure;

[0033] FIG2 is a partial plan view of a first electrode layer of a display substrate provided by at least one embodiment of the present disclosure;

[0034] FIG3 is a partial plan view of a driving circuit layer of a display substrate provided by at least one embodiment of the present disclosure;

[0035] FIG4 is a partial cross-sectional schematic diagram of a sub-pixel in a display substrate provided by at least one embodiment of the present disclosure;

[0036] 5 is a partial plan view of the overlapped first electrode layer and the pixel defining layer of a display substrate provided by at least one embodiment of the present disclosure;

[0037] 6 is a schematic diagram illustrating the overlap between a sub-pixel opening and a first electrode pattern of a sub-pixel in a display substrate according to at least one embodiment of the present disclosure;

[0038] FIG7 is a planar arrangement diagram of a plurality of spacers in a display substrate according to at least one embodiment of the present disclosure;

[0039] FIG8 is another partial cross-sectional schematic diagram of a sub-pixel in a display substrate provided by at least one embodiment of the present disclosure;

[0040] FIG9 is a circuit diagram of a pixel driving circuit of a display substrate provided by at least one embodiment of the present disclosure;

[0041] 10 to 14 are partial plan views of sequentially stacked conductive layers of a driving circuit layer of a display substrate according to at least one embodiment of the present disclosure; and

[0042] FIG15 is a partial cross-sectional schematic diagram of a display device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0044] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0045] In a display device with a fingerprint recognition function, the image sensor used for fingerprint recognition is usually combined with the non-display side of the display substrate of the display device. In this case, a light-transmitting gap is required in the display substrate. When a finger touches the display side surface of the display device, the signal light containing fingerprint information reflected by the finger will be transmitted to the image sensor through the above-mentioned light-transmitting gap, so that the image sensor can obtain the signal light for fingerprint collection and recognition operations.

[0046] In the above-mentioned display device, the display substrate needs to have a stable light transmittance to ensure that the image sensor can fully obtain the signal light containing fingerprint information for fingerprint collection and recognition. Generally speaking, the display substrate has a variety of circuit patterns, which are superimposed together so that the display substrate has irregular light-transmitting gaps in some positions. The larger light-transmitting gaps can be used to transmit the signal light containing fingerprint information. Due to errors in the manufacturing process, such as the alignment errors of multiple functional layers and the dimensional errors of the circuit patterns, the smaller light-transmitting gaps are often unstable. The size, number, and existence of the smaller light-transmitting gaps are all uncertain. Therefore, the overall transmittance of the display substrate is unstable, affecting the manufacturing yield of the display substrate.

[0047] At least one embodiment of the present disclosure provides a display substrate and a display device, wherein the display substrate has a display side and includes a base substrate, a driving circuit layer, a first electrode layer and a pixel defining layer, wherein the driving circuit layer is arranged on the base substrate and includes a plurality of first gaps, wherein the plurality of first gaps allow light from the display side to pass through, the first electrode layer is arranged on a side of the driving circuit layer away from the base substrate and includes a plurality of first electrode patterns and a plurality of light-shielding patterns, the pixel defining layer is arranged on a side of the first electrode layer away from the base substrate and includes a plurality of sub-pixel openings, wherein the plurality of sub-pixel openings respectively expose a plurality of first electrode patterns, wherein in a direction perpendicular to the base substrate, at least part of the plurality of light-shielding patterns do not overlap with the plurality of sub-pixel openings, and at least part of the plurality of light-shielding patterns respectively correspond to and at least partially overlap with at least part of the plurality of first gaps, so as to at least partially block the light from the display side.

[0048] In the above-mentioned display substrate provided in the embodiment of the present disclosure, at least a portion of the first gap is blocked by the light-shielding pattern, thereby eliminating the instability of the first gap caused by process fluctuations, thereby avoiding the instability of the overall light transmittance of the display substrate caused by the instability of the first gap, that is, improving the light transmittance stability of the display substrate; on the other hand, the light-shielding pattern and the first electrode pattern are arranged in the same first electrode layer, so that they can be formed using the same material and the same composition process in the preparation process, thereby simplifying the preparation process of the display substrate.

[0049] The display substrate and display device provided by the embodiments of the present disclosure are described in detail below through several specific embodiments.

[0050] At least one embodiment of the present disclosure provides a display substrate, wherein FIG1 shows a partial planar schematic diagram of the display substrate, FIG2 shows a partial planar schematic diagram of the first electrode layer of the display substrate in FIG1 , FIG3 shows a partial planar schematic diagram of the pixel driving circuit of the display substrate in FIG1 , and FIG4 shows a partial cross-sectional schematic diagram of a sub-pixel of the display substrate in FIG1 .

[0051] As shown in Figures 1 to 4, the display substrate has a display side, i.e., the upper side in Figure 4, and a non-display side, i.e., the lower side in Figure 4, and includes a base substrate 110, a driving circuit layer 120, a first electrode layer 1041 and a pixel defining layer 1017, etc.

[0052] The driving circuit layer 120 is disposed on the base substrate and includes a plurality of first gaps D1 that allow light from the display side to pass through. The first electrode layer is disposed on a side of the driving circuit layer 120 away from the base substrate 110 and includes a plurality of first electrode patterns 1041 and a plurality of light-shielding patterns SH. The pixel defining layer 1017 is disposed on a side of the first electrode layer 1041 away from the base substrate 110 and includes a plurality of sub-pixel openings PO that expose the plurality of first electrode patterns 1041.

[0053] In a direction perpendicular to the base substrate 110, that is, in the vertical direction in FIG4 , at least part (for example, all) of the multiple light-shielding patterns SH do not overlap with the multiple sub-pixel openings PO, and at least part (for example, all) of the multiple light-shielding patterns SH respectively correspond to at least part of the first gaps D1 in the multiple first gaps D1 and at least partially overlap, so as to at least partially block the light from the display side.

[0054] Thus, in the embodiment of the present disclosure, at least a portion of the first gap D1 is shielded by the light-shielding pattern SH. This prevents instability in the overall light transmittance of the display substrate caused by instability in the size and number of the first gaps D1, thereby improving the stability of the light transmittance of the display substrate. Furthermore, the light-shielding pattern and the first electrode pattern are provided in the same first electrode layer, allowing them to be formed using the same materials and patterning process during the manufacturing process, thereby simplifying the display substrate manufacturing process.

[0055] For example, in some embodiments, the width of the plurality of first gaps D1 is less than or equal to 4.0 microns, such as less than or equal to 3.0 microns, less than or equal to 2.0 microns, less than or equal to 1.5 microns, or less than or equal to 1.0 micron. The width of the first gap D1 refers to the dimension of the first gap D1 perpendicular to its extension direction. For example, when the first gap D1 is a rectangle (or approximately a rectangle), its width is the length of the short side of the rectangle. When the first gap D1 is an irregular shape, the direction with the longest span of the irregular shape is the extension direction, and the dimension perpendicular to the extension direction is the width of the first gap D1.

[0056] Since the first gap D1 with a smaller width is more likely to have larger process fluctuations during the preparation process, such as large dimensional deviations, the first gap D1 with a smaller width is more likely to cause large deviations in the overall light transmittance of the display substrate. By using the shading pattern SH to block the first gap D1 with a smaller width, the stability of the overall light transmittance of the display substrate can be improved to a greater extent.

[0057] For example, in some embodiments, a distance W1 between the plurality of first gaps D1 and the center of the plurality of sub-pixel openings PO is less than 33 microns. For example, referring to FIG1 , a distance W1 between the edge of the plurality of first gaps D1 away from the plurality of sub-pixel openings PO and the center of the plurality of sub-pixel openings PO is less than 33 microns. In other words, the plurality of first gaps D1 are distributed within a range of 33 microns from the center of the plurality of sub-pixel openings PO.

[0058] For example, in some embodiments, at least some of the plurality of light shielding patterns SH are integrally connected to the plurality of first electrode patterns 1041. In this case, as shown in Figures 1 and 2, the integrally connected first electrode patterns 1041 and light shielding patterns SH form an irregular pattern.

[0059] For example, in some embodiments, a display substrate includes a plurality of sub-pixels arranged in an array, each of which includes a light-emitting device EM. A plurality of first electrode patterns 1041 serve as anodes for the light-emitting devices EM of the plurality of sub-pixels. As shown in FIG4 , the light-emitting devices EM further include a light-emitting material layer 1042 disposed on a side of the first electrode pattern 1041 away from the base substrate 110, and a second electrode layer 1043 disposed on a side of the light-emitting material layer 1042 away from the base substrate 110.

[0060] For example, in some embodiments, as shown in FIG2 , the first electrode pattern 1041 includes a main portion M and a connecting portion CL, wherein the connecting portion CL extends from the main portion M. The main portion M is a portion for driving the light-emitting device to emit light. For example, the light-emitting material layer 1042 directly contacts at least a portion of the main portion M to be driven by the main portion M. The connecting portion CL is used to electrically connect the main portion M to the pixel driving circuit, and the connecting portion CL does not directly contact the portion of the light-emitting material layer 1042 that is used for emitting light.

[0061] For example, as shown in Figure 2, the planar shapes of the main parts M of the multiple first electrode patterns 1041 are polygonal (for example, hexagonal, pentagonal, quadrilateral, etc.) or figures with curved edges (for example, circular, elliptical, mango-shaped, etc.), and the planar shapes of the multiple shading patterns SH are polygonal, for example, triangle or quadrilateral (for example, rectangle, parallelogram, rhombus, etc.).

[0062] For example, in some embodiments, the plurality of sub-pixels include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. For example, as shown in Figures 1 and 2, the planar shape of the main portion M of the first electrode pattern 1041 of the light-emitting device of the red sub-pixel R is a hexagon (hereinafter referred to as a first hexagon), and the light-shielding pattern RSH integrally connected to the first electrode pattern 1041 of the light-emitting device of the red sub-pixel is triangular. For example, the number of light-shielding patterns RSH integrally connected to the first electrode pattern 1041 of the light-emitting device of the red sub-pixel R is two, and the two light-shielding patterns RSH are symmetrically distributed.

[0063] For example, in some embodiments, as shown in Figures 1 and 2, the planar shape of the main portion M of the first electrode pattern 1041 of the light-emitting device of the blue sub-pixel B is a hexagon (hereinafter referred to as a second hexagon), and the second hexagon is, for example, a similar shape to the first hexagon, and the size of the second hexagon is larger than the size of the first hexagon. For example, the shading pattern BSH integrally connected to the first electrode pattern 1041 of the light-emitting device of the blue sub-pixel B is triangular or rectangular. For example, the number of shading patterns BSH integrally connected to the first electrode pattern 1041 of the light-emitting device of the blue sub-pixel B is three, and the three shading patterns BSH are respectively integrally connected to the three sides of the first electrode pattern 1041 of the light-emitting device of the blue sub-pixel B.

[0064] For example, as shown in FIG1 and FIG2 , the three light-shielding patterns BSH include two triangular light-shielding patterns and one rectangular pattern. The two triangular light-shielding patterns are symmetrically distributed, and the rectangular pattern is connected to the left side of the first electrode pattern 1041 and the left side of the triangle.

[0065] For example, in some embodiments, as shown in Figures 1 and 2, the planar shape of the main portion M of the first electrode pattern 1041 of the light-emitting device of the green sub-pixel G is a pentagon, and the light-shielding pattern GSH integrally connected to the first electrode pattern 1041 of the light-emitting device of the green sub-pixel G is rectangular. For example, the number of light-shielding patterns GSH integrally connected to the first electrode pattern 1041 of the light-emitting device of the green sub-pixel G is one or two, and the one or two light-shielding patterns GSH are respectively integrally connected to one or two sides of the first electrode pattern 1041 of the light-emitting device of the green sub-pixel G.

[0066] For example, in some embodiments, one red sub-pixel R, two green sub-pixels G, and one blue sub-pixel B constitute a pixel unit, and the multiple pixel units are arranged in an array on the base substrate 110. For example, as shown in Figures 1 and 2, the first electrode pattern 1041 of the light-emitting device of one of the two green sub-pixels G is connected to a rectangular light-shielding pattern GSH, and the first electrode pattern 1041 of the light-emitting device of the other green sub-pixel G is connected to two rectangular light-shielding patterns GSH.

[0067] For example, the light-emitting devices of the red sub-pixel R and the blue sub-pixel B are located in the same row, and the light-emitting devices of the green sub-pixel G are approximately located in the same row. The rows where the light-emitting devices of the red sub-pixel R and the blue sub-pixel B are located are alternately arranged with the row where the light-emitting device of the green sub-pixel G is located, thereby forming a plurality of periodically arranged pixel units.

[0068] For example, in the embodiment of the present disclosure, the light-emitting devices of the green sub-pixels G are roughly located in the same row, which means that, referring to Figure 5, at least part of the light-emitting devices of any two adjacent green sub-pixels G are located on the same straight line, and the light-emitting devices of the two adjacent green sub-pixels G can be offset relative to the row direction, that is, the line connecting the centers of the light-emitting devices of any two adjacent green sub-pixels G can be a broken line Z.

[0069] For example, Figure 5 shows a schematic plan view of the stack of the first electrode layer and the pixel-defining layer, and Figure 6 shows a schematic plan view of the stack of the main portion of a blue sub-pixel and the sub-pixel opening. In some embodiments, as shown in Figures 5 and 6, in the corresponding sub-pixel opening PO and first electrode pattern 1041, the sub-pixel opening PO and the main portion M of the first electrode pattern 1041 have the same shape. The first orthographic projection of the sub-pixel opening PO on the substrate 110 is located within the second orthographic projection of the main portion M of the first electrode pattern 1041 on the substrate 110, and the minimum distance L1 between the edges of the first orthographic projection and the second orthographic projection is 1.5 microns to 3.5 microns, such as 2.0 microns, 2.5 microns, or 3.0 microns. Thus, the sub-pixel opening PO fully exposes the first electrode pattern 1041. The area defined by the sub-pixel opening PO is the effective light-emitting area of ​​the light-emitting device EM. The light-emitting material layer 1042 is in direct contact with the main portion M of the first electrode pattern 1041 in this area to be driven.

[0070] For example, in some embodiments, as shown in Figure 5, the first electrode pattern 1041 of a green sub-pixel G in each pixel unit may also include a transistor shading pattern TSH, which is used to shield the thin film transistor arranged thereunder (such as the thin film transistor T2 described later) to prevent light from irradiating the thin film transistor and affecting the switching performance of the thin film transistor.

[0071] For example, in some embodiments, as shown in Figures 1 and 3, the driving circuit layer 120 further includes a plurality of second gaps D2. The plurality of second gaps D2 allow light from the display side to pass through. In a direction perpendicular to the base substrate 110, the second gaps D2 do not overlap with the plurality of first electrode patterns 1041 and the plurality of light shielding patterns SH. Thus, the second gaps D2 can allow light from the display side to pass through to the non-display side of the display substrate. For example, when an image sensor S is disposed on the non-display side of the display substrate, the second gaps D2 can transmit signal light containing fingerprint information to the image sensor S.

[0072] For example, in some embodiments, at least some of the plurality of second gaps D2 have a width greater than 1.0 micron, or greater than 1.5 microns, or greater than 2.0 microns, or greater than 3.0 microns, or greater than 4.0 microns. The width of the second gap D2 refers to the dimension of the second gap D2 perpendicular to its extension direction. Thus, the second gap D2 is relatively large, effectively achieving light transmission. Furthermore, due to the large size of the second gap D2, significant deviations during the manufacturing process are unlikely. Even if minor deviations occur, their impact on the overall transmittance stability of the display substrate is minimal.

[0073] For example, in some embodiments, a distance W2 between the plurality of second gaps D2 and the center of the plurality of sub-pixel openings PO is greater than 33 microns. For example, referring to FIG1 , a distance W2 between the edge of the plurality of second gaps D2 away from the sub-pixel opening PO and the center of the sub-pixel opening PO is greater than 33 microns.

[0074] For example, in some embodiments, as shown in FIG1 , the orthographic projections of the plurality of second gaps D2 on the base substrate 110 are respectively located between the orthographic projection of the emission control signal line EM on the base substrate 110 and the orthographic projection of the reset voltage line VINT closest to the emission control signal line EM on the base substrate 110. The connection relationship and purpose of the emission control signal line EM and the reset voltage line VINT will be described in detail later.

[0075] For example, as shown in Figure 1, the orthographic projections of at least part of the multiple second gaps D2 (for example, the second gap D2 on the right side of the figure) on the base substrate 110 are respectively located between the orthographic projections of the light-emitting control signal line EM for the blue sub-pixel B on the base substrate 110 and the orthographic projections of the reset voltage line VINT for the red sub-pixel R on the base substrate 110. The above-mentioned red sub-pixel R is located in the next row of the above-mentioned blue sub-pixel B and is adjacent to the above-mentioned blue sub-pixel B.

[0076] For example, as shown in Figure 1, the orthographic projections of at least part of the multiple second gaps D2 (for example, the second gap D2 on the left side of the figure) on the base substrate 110 are respectively located between the orthographic projections of the light-emitting control signal line EM for the red sub-pixel R and the orthographic projections of the reset voltage line VINT for the blue sub-pixel B on the base substrate 110. The above-mentioned blue sub-pixel B is located in the next row of the above-mentioned red sub-pixel R and is adjacent to the above-mentioned red sub-pixel R.

[0077] That is, in the embodiment of the present disclosure, the plurality of second gaps D2 are located in the gaps between the pixel driving circuits of the blue sub-pixel B and the red sub-pixel R.

[0078] For example, in some embodiments, as shown in FIG4 , the driving circuit layer 120 includes a plurality of pixel driving circuits and a first planarization layer 1016. The pixel driving circuit includes a plurality of thin film transistors and at least one storage capacitor, and may be formed into, for example, a 2T1C (i.e., two thin film transistors and one storage capacitor), a 7T1C (i.e., seven thin film transistors and one storage capacitor), or an 8T2C (i.e., eight thin film transistors and one storage capacitor) structure. The embodiments of the present disclosure do not limit the specific form of the pixel driving circuit.

[0079] For example, FIG4 shows a thin film transistor T electrically connected to the light-emitting device EM and a storage capacitor C. As shown in FIG4 , the thin film transistor T includes an active layer 1021, a gate electrode 1022, a first source-drain electrode 1023, and a second source-drain electrode 1024. The storage capacitor C includes a first capacitor electrode 1031 and a second capacitor electrode 1032. The first capacitor electrode 1031 is provided on the same layer as the gate electrode 1022.

[0080] It should be noted that in the embodiments of the present disclosure, "same-layer setting" means that two functional layers or structural layers are in the same layer and are formed of the same material in the hierarchical structure of the display substrate, that is, in the preparation process, the two functional layers or structural layers can be formed by the same material layer, and the required patterns and structures can be formed by the same composition process.

[0081] For example, as shown in FIG4 , a first planarization layer 1016 is disposed on a side of the plurality of pixel driving circuits away from the base substrate 1011 and includes a plurality of first via holes VH1. The plurality of first via holes VH1 expose the output terminals of the plurality of pixel driving circuits, such as the first source and drain electrodes 1023 of the thin film transistors T. The first electrode layer is disposed on a side of the first planarization layer 1016 away from the base substrate 110, and a plurality of first electrode patterns 1041 are electrically connected to the output terminals of the plurality of pixel driving circuits via the plurality of first via holes VH1. Thus, the pixel driving circuits can control the voltage applied to the first electrode patterns 1041 via the thin film transistors T.

[0082] For example, as shown in FIG4 , the display substrate further includes a spacer layer 1018 disposed on a side of the pixel defining layer 1017 away from the base substrate 110. The spacer layer 1018 includes a plurality of spacers PS. For example, in a direction perpendicular to the base substrate 110, i.e., in the vertical direction in the figure, the height of the plurality of spacers PS is 1.8 μm to 2.4 μm, such as 2.0 μm or 2.2 μm. Thus, the spacers PS can have a sufficient height so that during the preparation process of the display substrate, for example, when forming the light-emitting material layer 1042 by evaporation or other methods, the mask used can be fully supported on the plurality of spacers PS without causing undesirable phenomena such as deformation of the mask and scratching the display substrate structure.

[0083] For example, in some embodiments, the multiple spacers PS do not overlap with the multiple first vias VH1 in a direction perpendicular to the base substrate 110. Because the first vias VH1 are formed by hollowing out part of the material of the first planarization layer 1016, the material above the first vias VH1 is prone to depression. If the spacers PS are formed above the first vias VH1, the spacers PS will sink, thereby reducing the height of the spacers PS relative to the base substrate 110, affecting the support function of the spacers PS. By arranging the multiple spacers PS and the multiple first vias VH1 in a non-overlapping manner, the multiple spacers PS can effectively achieve their support function.

[0084] For example, Figure 7 illustrates a schematic planar arrangement of multiple spacers PS. As shown in Figure 7, in some embodiments, the minimum distance L2 between the multiple spacers PS and the multiple first vias VH1 in a direction parallel to the base substrate 110 is greater than 2.0 microns. Because the sidewalls of the first vias VH1 are typically inclined, the material formed around and above the first vias VH1 is susceptible to depressions. Therefore, by spacing the spacers PS from the first vias VH1 by a certain distance, any impact of the first vias VH1 on the spacers PS can be effectively avoided, ensuring that the spacers PS have sufficient height to fully provide support.

[0085] For example, in other embodiments, Figure 8 illustrates another partial cross-sectional schematic diagram of a sub-pixel on a display substrate. As shown in Figure 8, the driver circuit layer includes multiple pixel driver circuits, a first planarization layer 1016, a connection electrode layer, and a second planarization layer 1019. The specific form of the pixel driver circuit can be found in the above embodiments and will not be further described here.

[0086] As shown in FIG8 , a first planarization layer 1016 is disposed on a side of the plurality of pixel driving circuits away from the base substrate 110 and includes a plurality of first vias VH1. The plurality of first vias VH1 expose the output terminals of the plurality of pixel driving circuits, such as the first source / drain electrodes 1023 of the thin-film transistors T. A connecting electrode layer is disposed on a side of the first planarization layer 1016 away from the base substrate 110 and includes a plurality of connecting electrodes CEL. The plurality of connecting electrodes CEL are electrically connected to the output terminals of the plurality of pixel driving circuits through the first vias VH1. A second planarization layer 1019 is disposed on a side of the connecting electrode layer away from the base substrate 110 and includes a plurality of second vias VH2. The plurality of second vias VH2 expose the plurality of connecting electrodes CEL. A first electrode layer is disposed on a side of the second planarization layer 1019 away from the base substrate 110, and a plurality of first electrode patterns 1041 are electrically connected to the plurality of connecting electrodes CEL through the plurality of second vias VH2.

[0087] As shown in FIG8 , the display substrate further includes a spacer layer 1018 disposed on a side of the pixel defining layer 1017 away from the base substrate 110. The spacer layer 1018 includes a plurality of spacers PS. For example, in a direction perpendicular to the base substrate 110 (i.e., in the vertical direction in the figure), the height of the plurality of spacers PS is 1.8 to 2.4 microns, such as 2.0 or 2.2 microns. For example, in a direction perpendicular to the base substrate 110, the plurality of spacers PS do not overlap with the plurality of second vias VH2. For example, referring to FIG7 , in a direction parallel to the base substrate 110, the minimum distance L2 between the plurality of spacers PS and the plurality of second vias VH2 is greater than 2.0 microns. This effectively prevents any impact of the second vias VH2 on the spacers PS, ensuring that the spacers PS have sufficient height to fully provide support.

[0088] For example, in an embodiment of the present disclosure, in a direction perpendicular to the base substrate 110, multiple pixel driving circuits at least partially overlap with multiple sub-pixel openings PO. At this time, the light-emitting device formed in the sub-pixel opening PO can be a top-emitting light-emitting device.

[0089] For example, as shown in Figures 4 and 8, the display substrate may further include a barrier layer 1012 and a buffer layer 1013 disposed on the base substrate 110. The barrier layer 1012 and the buffer layer 1013 may prevent impurities in the base substrate 110 from entering the multiple functional layers on the display substrate 110, thereby providing protection. For example, the barrier layer 1012 and the buffer layer 1013 may be made of one or more inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0090] For example, as shown in Figures 4 and 8, the display substrate may further include a first gate insulating layer 1014A disposed on the side of the active layer 1021 away from the base substrate 110, a second gate insulating layer 1014B disposed on the side of the gate electrode 1022 and the first capacitor electrode 1031 away from the base substrate 110, and an interlayer insulating layer 1015 disposed on the side of the second capacitor electrode 1032 away from the base substrate 110. For example, the first gate insulating layer 1014A, the second gate insulating layer 1014B, and the interlayer insulating layer 1015 may be made of one or more inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0091] For example, as shown in Figures 4 and 8, the display substrate may further include an encapsulation layer EN disposed on a side of the light-emitting device EM away from the base substrate 110. The encapsulation layer EN may be a composite encapsulation layer including a first inorganic encapsulation layer 1051, a first organic encapsulation layer 1052, and a second inorganic encapsulation layer 1053. The first inorganic encapsulation layer 1051 and the second inorganic encapsulation layer 1053 may be made of one or more inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The first organic encapsulation layer 1052 may be made of one or more organic insulating materials such as resin and polyimide.

[0092] For example, in one embodiment, the pixel driving circuit of the sub-pixel adopts a 7T1C structure. FIG9 shows a circuit diagram of a pixel driving circuit with a 7T1C structure. As shown in FIG9 , the pixel driving circuit with a 7T1C structure includes seven thin-film transistors T1-T7 and a storage capacitor C1, and has a connection relationship as shown in the accompanying figure. The pixel driving circuit has, for example, the following four-stage driving process. In the following description, the seven thin-film transistors T1-T7 are all P-type transistors, i.e., the gate of each transistor is turned on when a low voltage level is connected and is turned off when a high voltage level is connected.

[0093] In the initialization phase 1, the first reset signal RST1 is input, the fourth transistor T4 is turned on, and the reset voltage VINT is applied to the control end (e.g., the gate) of the driving transistor T1; the first light-emitting control signal EM1 is input, the fifth transistor T5 is turned on, and the first voltage VDD is applied to the second node N2.

[0094] For example, in the initialization phase 1, the fourth transistor T4 is turned on by the low level of the first reset signal RST1, and the fifth transistor T5 is turned on by the low level of the first light-emitting control signal EM1; at the same time, the second transistor T2, the third transistor T3, the sixth transistor T6 and the seventh transistor T7 are turned off by the high level signals connected to them.

[0095] In the initialization phase 1, since the fourth transistor T4 is turned on, a reset voltage VINT (a low-level signal, for example, grounded or another low-level signal) can be applied to the gate of the first transistor T1. Simultaneously, since the fifth transistor T5 is turned on, a first voltage VDD (a high-level signal) can be applied to the source of the first transistor T1. Thus, in the initialization phase 1, the voltage VGS between the gate and source of the first transistor T1 can satisfy the following: |VGS|>|Vth| (Vth is the threshold voltage of the first transistor T1, for example, when the first transistor T1 is a P-type transistor, Vth is a negative value), thereby placing the first transistor T1 in an on-state with VGS as a fixed bias.

[0096] In the data writing and compensation phase 2, the scan signal GATE and the data signal DATA are input to turn on the second transistor T2, the driving transistor T1 and the third transistor T3. The data signal DATA is written into the driving transistor T1, and the third transistor T3 performs threshold compensation on the driving transistor T1.

[0097] In the data writing and compensation phase 2, the second transistor T2 and the third transistor T3 are turned on by the low level of the scanning signal GATE, while the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off by the high level signals connected to them.

[0098] During data writing and compensation phase 2, the data signal DATA passes through the second transistor T2, the first transistor T1, and the third transistor T3 to charge the first node N1 (i.e., to charge the storage capacitor C1). This means that the potential of the first node N1 gradually increases. It's easy to understand that since the second transistor T2 is turned on, the potential of the second node N2 remains at Vdata. At the same time, based on the characteristics of the first transistor T1, when the potential of the first node N1 increases to Vdata + Vth, the first transistor T1 is turned off, and the charging process ends. It should be noted that Vdata represents the voltage value of the data signal DATA, and Vth represents the threshold voltage of the first transistor.

[0099] After the data writing and compensation stage 2, the potentials of the first node N1 and the third node N3 are both Vdata+Vth, that is, the voltage information with the data signal DATA and the threshold voltage Vth is stored in the storage capacitor C1, so as to provide grayscale display data and compensate for the threshold voltage of the first transistor T1 itself in the subsequent light-emitting stage.

[0100] In the reset phase 3, the second light emitting control signal EM2 and the second reset signal RST2 are input to turn on the sixth transistor T6 and the seventh transistor T7, and reset the first transistor T1, the third transistor T3 and the sixth transistor T6.

[0101] In reset phase 3, the sixth transistor T6 is turned on by the low level of the second light-emitting control signal EM2, and the seventh transistor T7 is turned on by the low level of the second reset signal RST2; at the same time, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are turned off by the high level respectively connected.

[0102] In reset phase 3, since the reset voltage VINT is a low-level signal (for example, it can be grounded or other low-level signals), the drain of the first transistor T1 is discharged through the sixth transistor T6 and the seventh transistor T7, thereby resetting the potentials of the third node N3 and the fourth node N4 at the same time.

[0103] In reset phase 3, the drain of the first transistor T1 is reset, thereby maintaining it at a fixed potential. This prevents the display effect of the display device using the above pixel circuit from being affected by the uncertainty of the drain potential. Simultaneously, the fourth node N4 is also reset, thereby resetting the OLED, so that the OLED is displayed in a black state and does not emit light before light-emitting phase 4, thereby improving the contrast and other display effects of the display device using the above pixel circuit.

[0104] In the light emitting stage 4, the first light emitting control signal EM1 and the second light emitting control signal EM2 are input to turn on the thin film transistors T5, T6 and the driving circuit thin film transistor T1, and the thin film transistor T6 applies a driving current to the light emitting element 600 to make it emit light.

[0105] In light-emitting stage 4, the fifth transistor T5 is turned on by the low level of the first light-emitting control signal EM1, and the sixth transistor T6 is turned on by the low level of the second light-emitting control signal EM2; the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are turned off by the high level respectively connected to them; at the same time, the potential of the first node N1 is Vdata+Vth, and the potential of the second node N2 is VDD, so the first transistor T1 also remains turned on in this stage.

[0106] As shown in Figure 8, in the light-emitting stage 4, the first electrode pattern (e.g., anode) and the second electrode layer (e.g., cathode) of the light-emitting device D1 are respectively connected to the first voltage VDD (high voltage) and the second voltage VSS (low voltage), thereby emitting light under the action of the driving current flowing through the first transistor T1.

[0107] For example, Figures 10 to 14 show partial plan schematic diagrams of the various conductive layers of the driving circuit layer stacked in sequence, with insulating layers between adjacent conductive layers, such as the above-mentioned gate insulating layer and interlayer insulating layer, etc. These insulating layers have multiple vias for electrical connection. The following embodiments focus on describing each conductive layer, and the insulating layer will not be repeated.

[0108] For example, Figure 10 shows a schematic plan view of the semiconductor layer of the driver circuit layer. The semiconductor layer includes the active layers of thin-film transistors T1-T7. For example, the active layers of thin-film transistors T1-T7 are connected to each other to form an integrated structure. For example, the portion of the semiconductor layer encircled by the dashed line in Figure 10 represents the active layers of thin-film transistors T1-T7 in the pixel driver circuit of a sub-pixel. For example, a first gate insulating layer 1014A is disposed above the semiconductor layer, which is not shown in the figure.

[0109] For example, FIG11 shows a schematic plan view of the first conductive layer of the driver circuit layer superimposed on the semiconductor layer of FIG10 . As shown in FIG11 , the first conductive layer includes the gate of each transistor, the first capacitor plate 1031 of the storage capacitor, and a number of scan lines GATE, emission control lines EM, and reset control lines RST. For example, the gate of each transistor is the portion of the scan line GATE, emission control line EM, and reset control line RST that overlaps with the active layer. For example, each row of sub-pixels is connected to a scan line GATE, two reset control lines RST, and one emission control line EM. A first gate insulating layer 1014B is provided above the first conductive layer (not shown).

[0110] For example, FIG12 shows a schematic plan view of the stacked structure of FIG11 in which the second conductive layer of the driver circuit layer is superimposed. As shown in FIG12 , the second conductive layer includes a second capacitor plate 1032 of the storage capacitor and a plurality of reset voltage lines VINT. An interlayer insulating layer 1015 is disposed above the second conductive layer, which is not shown in the figure.

[0111] For example, FIG13 shows a schematic plan view of the stacked structure of FIG12 in which the third conductive layer of the driving circuit layer is superimposed. As shown in FIG13 , the third conductive layer includes a first power line VDD, a portion of the data line Data, and source and drain electrodes of thin-film transistors T1-T7. A planarization layer 1016 is disposed above the third conductive layer, which is not shown in the figure.

[0112] For example, Figure 14 shows a schematic plan view of the stacked structure of Figure 13 with the fourth conductive layer of the driver circuit layer superimposed on it. As shown in Figure 13, the fourth conductive layer includes another portion of the data lines Data. For example, in some embodiments, the fourth conductive layer may also include a connecting electrode CEL. A planarization layer 1019 is provided above the third conductive layer (not shown). Thus, in this embodiment, the data lines Data are distributed across two conductive layers to facilitate the arrangement of the data lines Data.

[0113] For example, FIG1 shows a schematic plan view of a first electrode layer superimposed on the stacked structure of FIG14 . For details, please refer to the description of FIG1 , which will not be repeated here.

[0114] For example, in an embodiment of the present disclosure, the base substrate 110 can be a rigid substrate such as glass or quartz, or a flexible substrate such as polyimide, and the gate 1022 can be made of a metal material or alloy material such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), for example, formed into a single-layer metal layer structure or a multi-layer metal layer structure, such as a multi-layer metal layer structure such as titanium / aluminum / titanium. The first source-drain electrode 1023 and the first source-drain electrode 1024 can be made of a metal material or alloy material such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), for example, formed into a single-layer metal layer structure or a multi-layer metal layer structure, such as a multi-layer metal layer structure such as titanium / aluminum / titanium. The materials of the first electrode 1031 and the second electrode 1032 include metals or alloy materials such as aluminum, titanium, cobalt, and copper. The active layer 1021 can be made of materials such as polysilicon and metal oxide.

[0115] For example, the first planarization layer 1016 , the second planarization layer 1019 , the pixel defining layer 1017 , the spacer layer 1018 , and the first organic encapsulation layer 1052 of the encapsulation layer EN may be made of organic insulating materials such as polyimide and resin.

[0116] For example, the display substrate may further include other structures in addition to the above structures. For details, please refer to the relevant technology and will not be described in detail here.

[0117] In addition, it should be noted that the embodiments of the present disclosure do not limit the materials of each functional layer, and the materials of each functional layer are not limited to the above examples. In the embodiments of the present disclosure, each thin film transistor can be a P-type thin film transistor or an N-type thin film transistor, and the structure can be a bottom gate type, a top gate type or a dual gate type. The structures shown in the accompanying drawings are only exemplary, and the embodiments of the present disclosure do not limit the specific form of each thin film transistor. For example, in some embodiments, when the thin film transistor is a dual gate type, the display substrate in Figures 4 and 8 has at least one more conductive layer and an insulating layer, and another gate is provided in the conductive layer. At this time, the two gates can be located on the side of the active layer of the thin film transistor close to the base substrate and the side away from the base substrate, respectively.

[0118] At least one embodiment of the present disclosure provides a display device comprising any of the aforementioned display substrates. For example, FIG15 illustrates a partial cross-sectional schematic diagram of the display device. As shown in FIG15 , the display device may further include an image sensor S, which is coupled to the non-display side of the display substrate and configured to receive light transmitted through the second gap D2. For example, in some embodiments, the orthographic projection of the image sensor S on the base substrate 110 at least partially overlaps with the orthographic projection of the second gap D2 on the base substrate 110.

[0119] For example, the image sensor S may be any suitable type of image sensor, such as a charge coupled device (CCD) image sensor, a complementary metal oxide semiconductor (CMOS) image sensor, or a photodiode (e.g., a PIN photodiode). Depending on the needs, the image sensor may sense only light of a certain wavelength (e.g., red light or green light) or all visible light.

[0120] For example, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0121] There are a few points to note:

[0122] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0123] (2) For the sake of clarity, the thickness of layers or regions in the drawings used to describe the embodiments of the present disclosure are exaggerated or reduced, i.e., these drawings are not drawn to scale. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or intervening elements may be present.

[0124] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0125] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate having a display side and comprising: substrate, The driving circuit layer is provided on the base substrate and includes a plurality of first gaps, wherein the plurality of first gaps allow light from the display side to pass through. The first electrode layer is provided on a side of the driving circuit layer away from the base substrate, and includes a plurality of first electrode patterns and a plurality of light shielding patterns. a pixel defining layer, disposed on a side of the first electrode layer away from the base substrate, comprising a plurality of sub-pixel openings, wherein the plurality of sub-pixel openings respectively expose the plurality of first electrode patterns; In which, in a direction perpendicular to the base substrate, at least part of the multiple shading patterns does not overlap with the multiple sub-pixel openings, and at least part of the multiple shading patterns respectively correspond to at least part of the first gaps in the multiple first gaps and at least partially overlap, so as to at least partially block the light from the display side.

2. The display substrate according to claim 1, wherein The width of the plurality of first gaps is less than or equal to 4.0 microns.

3. The display substrate according to claim 1 or 2, wherein: The first gaps are spaced less than 33 micrometers from centers of the sub-pixel openings.

4. The display substrate according to any one of claims 1 to 3, wherein: At least some of the plurality of light-shielding patterns are integrally connected to the plurality of first electrode patterns.

5. The display substrate according to any one of claims 1 to 4, wherein: Each of the plurality of first electrode patterns includes a main body portion and a connecting portion, wherein the main body portion is in a polygonal shape or a shape with an arc-shaped edge. The planar shapes of the plurality of light-shielding patterns are polygonal.

6. The display substrate according to any one of claims 1 to 5, wherein: The display substrate has a plurality of sub-pixels, each of the plurality of sub-pixels includes a light-emitting device, and the plurality of first electrode patterns serve as anodes of the light-emitting devices of the plurality of sub-pixels, respectively.

7. The display substrate according to claim 6, wherein: The plurality of sub-pixels include red sub-pixels, green sub-pixels, and blue sub-pixels, The main body of the first electrode pattern of the light-emitting device of the red sub-pixel has a hexagonal planar shape, and the light-shielding pattern integrally connected to the first electrode pattern of the light-emitting device of the red sub-pixel has a triangular shape.

8. The display substrate according to claim 7, wherein: There are two light shielding patterns integrally connected to the first electrode pattern of the light emitting device of the red sub-pixel, and the two light shielding patterns integrally connected to the first electrode pattern of the light emitting device of the red sub-pixel are symmetrically distributed.

9. The display substrate according to claim 7 or 8, wherein: The main body of the first electrode pattern of the light-emitting device of the blue sub-pixel has a hexagonal planar shape, and the light-shielding pattern integrally connected to the first electrode pattern of the light-emitting device of the blue sub-pixel has a triangular or rectangular shape.

10. The display substrate according to claim 9, wherein: The number of shading patterns integrally connected to the first electrode pattern of the light-emitting device of the blue sub-pixel is three, and the three shading patterns integrally connected to the first electrode pattern of the light-emitting device of the blue sub-pixel are respectively integrally connected to the three sides of the first electrode pattern of the light-emitting device of the blue sub-pixel.

11. The display substrate according to any one of claims 7 to 10, wherein: The main body of the first electrode pattern of the light-emitting device of the green sub-pixel has a pentagonal planar shape, and the light-shielding pattern integrally connected to the first electrode pattern of the light-emitting device of the green sub-pixel has a rectangular shape.

12. The display substrate according to claim 11, wherein: The number of shading patterns integrally connected to the first electrode pattern of the light-emitting device of the green sub-pixel is one or two, and the one or two shading patterns integrally connected to the first electrode pattern of the light-emitting device of the green sub-pixel are respectively integrally connected to one or two sides of the first electrode pattern of the light-emitting device of the green sub-pixel.

13. The display substrate according to any one of claims 1 to 12, wherein: In the corresponding sub-pixel opening and the first electrode pattern, the sub-pixel opening has the same shape as the main body of the first electrode pattern. A first orthographic projection of the sub-pixel opening on the base substrate is located inside a second orthographic projection of the main portion of the first electrode pattern on the base substrate, and a minimum distance between edges of the first orthographic projection and the second orthographic projection is 1.5 microns to 3.5 microns.

14. The display substrate according to any one of claims 7 to 13, wherein: The light-emitting devices of the red sub-pixels and the blue sub-pixels are located in the same row, and the light-emitting devices of the green sub-pixels are located in approximately the same row. The rows where the light-emitting devices of the red sub-pixels and the blue sub-pixels are located are alternately arranged with the row where the light-emitting devices of the green sub-pixels are located.

15. The display substrate according to any one of claims 1 to 14, wherein: The driving circuit layer further includes a plurality of second gaps, wherein the plurality of second gaps allow light from the display side to pass through. In a direction perpendicular to the base substrate, the second gap does not overlap with the plurality of first electrode patterns and the plurality of light shielding patterns.

16. The display substrate according to claim 15, wherein: The distances between the second gaps and the centers of the sub-pixel openings are greater than 33 micrometers.

17. The display substrate according to claim 15 or 16, wherein: The orthographic projections of the plurality of second gaps on the base substrate are respectively located between the orthographic projection of the light emitting control signal line on the base substrate and the orthographic projection of the reset voltage line closest to the light emitting control signal line on the base substrate.

18. The display substrate according to claim 17, wherein: Orthographic projections of at least some of the plurality of second gaps on the base substrate are respectively located between orthographic projections of a light emitting control signal line for a blue sub-pixel and orthographic projections of a reset voltage line for a red sub-pixel on the base substrate, wherein the red sub-pixel is located in a row below and adjacent to the blue sub-pixel; and / or The orthographic projections of at least part of the plurality of second gaps on the substrate are respectively located between the orthographic projections of the light emitting control signal line for the red sub-pixel and the orthographic projections of the reset voltage line for the blue sub-pixel on the substrate, wherein the blue sub-pixel is located in a row below the red sub-pixel and is adjacent to the red sub-pixel.

19. The display substrate according to any one of claims 15 to 18, wherein: The width of at least some of the plurality of second gaps is greater than 4.0 micrometers.

20. The display substrate according to any one of claims 1 to 19, wherein: The driving circuit layer includes: a plurality of pixel driving circuits, and A first planarization layer is provided on a side of the plurality of pixel driving circuits away from the base substrate, and includes a plurality of first via holes, wherein the plurality of first via holes respectively expose output terminals of the plurality of pixel driving circuits. The first electrode layer is provided on a side of the first planarization layer away from the base substrate, and the plurality of first electrode patterns are electrically connected to the output ends of the plurality of pixel driving circuits through the plurality of first via holes respectively; The display substrate further comprises a spacer layer provided on a side of the pixel defining layer away from the base substrate, wherein the spacer layer comprises a plurality of spacers; Wherein, in a direction perpendicular to the base substrate, the plurality of spacers do not overlap with the plurality of first via holes.

21. The display substrate according to claim 20, wherein: In a direction parallel to the base substrate, a minimum distance between the plurality of spacers and the plurality of first via holes is greater than 2.0 micrometers.

22. The display substrate according to any one of claims 1 to 19, wherein: The driving circuit layer includes: multiple pixel driving circuits, A first planarization layer is provided on a side of the plurality of pixel driving circuits away from the base substrate, and includes a plurality of first via holes, wherein the plurality of first via holes respectively expose output terminals of the plurality of pixel driving circuits. a connecting electrode layer, disposed on a side of the first planarization layer away from the base substrate, comprising a plurality of connecting electrodes, wherein the plurality of connecting electrodes are electrically connected to the output terminals of the plurality of pixel driving circuits through the first via holes, and a second planarization layer, disposed on a side of the connection electrode layer away from the base substrate, and comprising a plurality of second via holes, wherein the plurality of second via holes respectively expose the plurality of connection electrodes; The first electrode layer is provided on a side of the second planarization layer away from the base substrate, and the plurality of first electrode patterns are electrically connected to the plurality of connection electrodes through the plurality of second via holes respectively; The display substrate further comprises a spacer layer provided on a side of the pixel defining layer away from the base substrate, wherein the spacer layer comprises a plurality of spacers; Wherein, in a direction perpendicular to the base substrate, the plurality of spacers do not overlap with the plurality of second via holes.

23. The display substrate according to claim 22, wherein: In a direction parallel to the base substrate, a minimum distance between the plurality of spacers and the plurality of second via holes is greater than 2.0 micrometers.

24. The display substrate according to any one of claims 20 to 23, wherein: In a direction perpendicular to the base substrate, the height of the plurality of spacers is 1.8 microns to 2.4 microns.

25. The display substrate according to any one of claims 22 to 24, wherein: In a direction perpendicular to the base substrate, the plurality of pixel driving circuits at least partially overlap with the plurality of sub-pixel openings.

26. A display device comprising the display substrate according to any one of claims 1 to 25.

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