Display panel, display method and display apparatus

Abstract

A display panel (11), a display method and a display apparatus, which belong to the technical field of display. In the display panel (11), extension portions (t22) on a connection line (t2) connected to a signal line (55) in an nth row of sub-pixels (sq) extend to a row of sub-pixels (sq) other than the nth row of sub-pixels (sq). In such a structure, when a light-emitting device in an nth row of sub-pixel (sq) domain is driven, extension portions (t22) in a winding structure (t) connected to a signal line (55) in an nth row of sub-pixel (sq) area are located in another row of sub-pixels (sq), and do not affect a pixel driving circuit (12) in the nth row of sub-pixels (sq); and since a pixel driving circuit (12) in the other row of sub-pixels (sq) is not in a data write state at this time, a voltage change of the extension portions (t22) has a smaller effect on the pixel driving circuit (12) in the other row of sub-pixels (sq), thereby improving the display effect of the display panel (11). The possibility of the problem of uneven brightness occurring is reduced.

Description

Display panel, display method, and display device

[0001] This disclosure claims priority to Chinese patent application No. 202211538257.3 filed on December 1, 2022, entitled “Display Panel, Display Method, and Display Device.” The entire contents of the above case are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a display panel, a display method, and a display device. Background Art

[0003] A display panel is a device that can realize display function.

[0004] A display panel includes a conventional display area and a light-transmitting display area. A plurality of light-emitting devices are arranged in both the conventional display area and the light-transmitting display area, so that both the conventional display area and the light-transmitting display area can display images.

[0005] However, the area near the light-transmitting display area in the conventional display area may have a problem of uneven brightness, resulting in poor display effect of the display panel.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a display panel, a display method, and a display device. The technical solution is as follows:

[0008] According to one aspect of an embodiment of the present application, a display panel is provided, comprising: a substrate having a light-transmitting display area and a regular display area surrounding the light-transmitting display area, the light-transmitting display area and the regular display area having a plurality of sub-pixel areas, the plurality of sub-pixel areas being arranged as a plurality of rows of sub-pixel areas on the substrate, the sub-pixel areas having connected pixel driving circuits and light-emitting devices;

[0009] The conventional display area includes a winding pattern and a plurality of conventional signal lines respectively located in the plurality of rows of sub-pixel areas, wherein the winding pattern and the conventional signal lines are located in different layers;

[0010] The winding pattern includes a plurality of connecting lines respectively located in a plurality of rows of sub-pixel areas, and the connecting lines include a main line extending along the row direction of the sub-pixel area and a plurality of extension portions extending toward adjacent sub-pixel areas. The connecting lines are connected to the conventional signal lines, and the extension portions on the connecting lines to which the conventional signal lines in the nth row of sub-pixels are connected extend toward sub-pixel areas in other rows except the nth row of sub-pixels, where n is an integer greater than zero.

[0011] Optionally, the display panel further comprises a pixel definition layer located on the substrate, the pixel definition layer comprising a blocking area and a plurality of opening areas, the plurality of opening areas being respectively located in the plurality of sub-pixel areas, and an orthographic projection of the extension portion on the substrate being located in an orthographic projection of the blocking area on the substrate;

[0012] The plurality of extensions include at least one disconnecting extension, which is disconnected from the main line.

[0013] Optionally, the extension portion includes at least one sub-segment, and the at least one sub-segment is arranged around the opening area.

[0014] Optionally, the extension portion includes two sub-line segments respectively located on both sides of the opening area in the row direction.

[0015] Optionally, the display panel further includes a power line, and at least one of the disconnecting extension portions is electrically connected to the power line.

[0016] Optionally, the pixel driving circuit includes a storage capacitor located in the sub-pixel area, and a node connection line, wherein the node connection line is connected to one end of the storage capacitor, and the capacitor is connected to a node N1;

[0017] The conventional signal lines in the n-th row of sub-pixel regions are connected to the connection lines of the winding structure corresponding to the n-th row of sub-pixel regions;

[0018] The main line of the connecting line of the winding structure corresponding to the n-th row sub-pixel area is located on the first side of the N1 node of the n-th row sub-pixel area, and the extension part of the connecting line of the winding structure corresponding to the n-th row sub-pixel area extends to the sub-pixel area of ​​the adjacent row on the second side of the n-th row sub-pixel area, and the first side and the second side are two sides in the direction perpendicular to the row direction.

[0019] Optionally, the conventional signal lines in the n-th row of sub-pixel regions are connected to the connection lines of the winding structures corresponding to the sub-pixel regions in other rows of the multiple rows of sub-pixel regions except the n-th row of sub-pixel regions.

[0020] Optionally, the display panel further includes a jumper lead, one end of which is connected to a conventional signal line in the nth row sub-pixel area, and the other end of which is connected to a connecting line of a winding structure corresponding to sub-pixel areas in other rows except the nth row sub-pixel area.

[0021] Optionally, the jumper lead and the winding structure are in the same layer structure.

[0022] Optionally, the conventional signal line in the nth row of sub-pixel regions is connected to the connection line of the winding structure corresponding to the (n+x)th row of sub-pixel regions in the multiple rows of sub-pixel regions, where x is an integer greater than zero.

[0023] Optionally, the conventional signal line in the n-th row of sub-pixel regions is connected to the connection line of the winding structure corresponding to the nx-th row of sub-pixel regions in the multiple rows of sub-pixel regions, where x is an integer greater than zero.

[0024] Optionally, the winding pattern further includes a plurality of winding lines extending around the light-transmitting display area, and ends of the winding lines are connected to the connecting lines.

[0025] Optionally, the conventional signal line includes a gate line, and the connecting line is connected to the gate line.

[0026] Optionally, the display panel includes a source-drain metal pattern, and the winding pattern and the source-drain metal pattern are in the same layer structure.

[0027] Optionally, the light-emitting devices in the light-transmitting display area are connected to the pixel driving circuits in a one-to-one correspondence.

[0028] Optionally, the pixel driving circuit in the light-transmitting display area is connected to at least two light-emitting devices.

[0029] Optionally, the density of the light-emitting devices in the light-transmitting display area is lower than the density of the light-emitting devices in the conventional display area.

[0030] According to another aspect of the present application, a display panel is provided, comprising: a light-transmitting display area and a conventional display area surrounding the light-transmitting display area;

[0031] The light-transmitting display area and the conventional display area have a plurality of sub-pixel areas, the plurality of sub-pixel areas are arranged into a plurality of rows of sub-pixel areas, and the sub-pixel areas have connected pixel driving circuits and light-emitting devices;

[0032] The conventional display area includes a winding pattern, and the light-transmitting display area includes a plurality of light-transmitting area signal lines, wherein the light-transmitting area signal lines and the winding pattern are located in different layers;

[0033] The winding pattern includes a plurality of winding structures corresponding to the multiple rows of sub-pixel areas respectively, the winding structure corresponding to the nth row of sub-pixel areas in the multiple rows of sub-pixel areas includes a winding line extending around the light-transmitting display area, and a connecting line located in the nth row of sub-pixels, the connecting line is connected to the end of the winding line, and the connecting line includes a main line extending along the row direction of the nth row of sub-pixel areas and a plurality of extensions extending toward the sub-pixel area, the connecting lines of the multiple winding structures are respectively connected to a plurality of light-transmitting area signal lines, and the extensions on the connecting lines connected to the light-transmitting area signal lines in the nth row of sub-pixels extend to other rows of sub-pixel areas except the nth row of sub-pixels, and n is an integer greater than zero.

[0034] According to another aspect of the present application, a display device is provided, which includes an optical device and the above-mentioned display panel, wherein the optical device is located on the back of the display panel, and the orthographic projection on the display panel has an overlapping area with the light-transmitting display area of ​​the display panel.

[0035] According to another aspect of the present application, a display method of a display panel is provided, for controlling the above-mentioned display panel, the method comprising:

[0036] When driving the light-emitting devices in the n-th row of sub-pixel regions, a first potential is applied to the regular signal lines in the n-th row of sub-pixel regions at a first moment, so as to charge the pixel driving circuit in the n-th sub-pixel region. At least a portion of the pixel driving circuit in the sub-pixel region where the extension portion is located is affected by the first potential and jumps to the first potential. The sub-pixel region where the extension portion is located is a sub-pixel region among the multiple rows of sub-pixel regions in the display panel, excluding the n-th row of sub-pixel regions.

[0037] At a second moment, a second potential is loaded to the conventional signal line in the n-th row sub-pixel area to stop charging the pixel driving circuit in the n-th row sub-pixel area, and at least part of the pixel driving circuit in the sub-pixel area where the extension portion is located is affected by the second potential and jumps to the second potential.

[0038] According to another aspect of an embodiment of the present application, a display panel control device is provided, for controlling the above-mentioned display panel, the display panel control device comprising:

[0039] a first control component, configured to apply a first potential to a regular signal line in the n-th row of sub-pixel regions at a first moment when driving the light-emitting devices in the n-th row of sub-pixel regions, so as to charge a pixel driving circuit in the n-th sub-pixel region, and cause at least a portion of the pixel driving circuit in the sub-pixel region where the extension portion is located to jump to the first potential under the influence of the first potential, wherein the sub-pixel region where the extension portion is located is a sub-pixel region among the multiple rows of sub-pixel regions in the display panel, excluding the n-th row of sub-pixel regions;

[0040] A second control component is used to load a second potential to the conventional signal line in the n-th row sub-pixel area at a second moment to stop charging the pixel driving circuit in the n-th row sub-pixel area, and at least part of the pixel driving circuit in the sub-pixel area where the extension portion is located is affected by the second potential and jumps to the second potential.

[0041] According to another aspect of an embodiment of the present application, a computer storage medium is provided, in which at least one instruction, at least one program, a code set or an instruction set is stored. The at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by a processor to implement the display method of the display panel as described above.

[0042] According to another aspect of an embodiment of the present application, a computer program product or computer program is provided, comprising computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the methods provided in the various optional implementations described above.

[0043] The beneficial effects of the technical solutions provided in the embodiments of the present application include at least:

[0044] By extending the extension portion of the connection line connected to the signal line in the n-th row of sub-pixel regions toward sub-pixel regions in other rows except the n-th row of sub-pixel regions, when driving the light-emitting devices in the n-th row of sub-pixel regions, the extension portion of the winding structure connected to the signal line in the n-th row of sub-pixel regions is located in sub-pixel regions in other rows, and does not affect the pixel driving circuit in the n-th row of sub-pixel regions. Moreover, since the pixel driving circuit in the other rows of sub-pixel regions is not in a data writing state at this time, the voltage change on the extension portion has less impact on the pixel driving circuit in the other rows of sub-pixel regions, thereby improving the display effect of the display panel and reducing the possibility of uneven brightness. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0046] FIG1 is a schematic structural diagram of a display panel;

[0047] FIG2 is an enlarged structural schematic diagram of the display panel shown in FIG1 ;

[0048] FIG3 is a schematic diagram of a display screen of the display panel shown in FIG1 ;

[0049] FIG4 is a schematic diagram of a potential of the display panel shown in FIG1 ;

[0050] FIG5 is a schematic structural diagram of a display panel according to an embodiment of the present application;

[0051] FIG6 is a schematic diagram of a partially enlarged structure of the display panel shown in FIG5 ;

[0052] FIG7 is a schematic cross-sectional view of the display panel shown in FIG6 ;

[0053] FIG8 shows a circuit structure diagram of a pixel driving circuit;

[0054] FIG9 is a layout diagram of a partial structure of a display panel provided in an embodiment of the present application;

[0055] FIG10 is a disassembled and merged diagram of a portion of the display panel shown in FIG9 ;

[0056] FIG11 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0057] FIG12 is a layout diagram corresponding to a portion of the structure of the display panel shown in FIG11 ;

[0058] FIG13 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0059] FIG14 is a layout corresponding to the display panel shown in FIG13 ;

[0060] FIG15 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0061] FIG16 is a structural diagram of another display panel provided in an embodiment of the present application;

[0062] FIG17 is a flow chart of a display method of a display panel provided in an embodiment of the present application;

[0063] FIG18 is a block diagram of a control device for a display panel provided in an embodiment of the present application.

[0064] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0065] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0066] Currently, to increase the screen-to-body ratio of a display device, the display panel in the display device can be designed as a partially light-transmitting display panel. The orthographic projection of the photosensitive surface of the optical device in the display device on the display panel can be located within the partially light-transmitting area, and the optical device in the display device is located on the side opposite the display surface of the display panel.

[0067] This display panel structure has a translucent display area and a regular display area. The translucent display area can also be called the Full Display with Camera (FDC) area. Multiple light-emitting devices are installed in both the regular and translucent display areas, allowing them to display images.

[0068] The multiple light-emitting devices located in the light-transmitting display area are coupled one-to-one with some pixel driving circuits in the multiple pixel driving circuits in the conventional display area on both sides of the light-transmitting display area. The some pixel driving circuits are used to control the picture display in the light-transmitting display area.

[0069] Among them, multiple light-emitting devices located in the translucent display area can be connected to multiple pixel driving circuits in the corresponding conventional display area through multiple connecting lines, and a part of each of the multiple connecting lines is located in the translucent display area, and the other part is located in the conventional display area.

[0070] As shown in FIG1 , FIG1 is a schematic diagram of the structure of a display panel, and FIG2 is an enlarged schematic diagram of the structure of the display panel shown in FIG1 ( FIG2 may be an enlarged schematic diagram of the structure of the dotted box x1 in FIG1 ). Referring to FIG1 and FIG2 , the display panel 11 includes a light-transmitting display area q1 and a conventional display area q2 surrounding the light-transmitting display area. The light-transmitting display area q1 and the conventional display area q2 have multiple sub-pixel areas, and the multiple sub-pixel areas are arranged into multiple rows of sub-pixel areas.

[0071] The display panel further includes a pixel driving circuit 12 and a winding pattern 13 . Both the pixel driving circuit 12 and the winding pattern 13 are located in the normal display area q2 . The winding pattern 13 includes a plurality of winding structures 131 corresponding to a plurality of rows of sub-pixel areas.

[0072] The winding structure 131 corresponding to the n-th row sub-pixel area in the multi-row sub-pixel area includes a surrounding line 1311 extending around the translucent display area q1, and a connecting line 1312 located in the n-th row sub-pixel area, the connecting line 1312 is connected to the surrounding line 1311, and the connecting line 1312 includes a main line 1a extending along the row direction f1 of the n-th row sub-pixel and a plurality of extension portions 1b extending toward the sub-pixel area, the translucent display area q1 has a plurality of translucent area gate lines 1g located in the multi-row sub-pixel area, the connecting lines 1312 of the plurality of winding structures 131 are respectively connected to the plurality of translucent area gate lines 1g, and the extension portion 1b on the connecting line 1312 connected to the translucent area gate line 1g in the n-th row sub-pixel area extends toward the n-th row sub-pixel area.

[0073] The pixel driver circuit in each sub-pixel region may include a storage capacitor, one end of which is connected to node N1 in the pixel driver circuit. Node N1 is susceptible to interference from other circuit structures. As shown in FIG2 , the distance between node N1 and extension 1b in some sub-pixel regions is too close, causing the potential of node N1 to be affected by extension 1b, resulting in uneven brightness in these sub-pixel regions compared to other regions. For example, FIG3 is a schematic diagram of a display screen of the display panel shown in FIG1 , and FIG4 is a schematic diagram of a potential of the display panel shown in FIG1 . FIG4 shows that in the nth row sub-pixel region, the potential of node N1 is affected by gate line 1g at tt1 and tt2, causing it to jump, thereby affecting the normal illumination of light-emitting units in the vicinity of the light-transmitting display region. Referring to FIG3 , FIG3 is a schematic diagram of a display panel displaying a pure color image h , wherein the edge of the light-transmitting display region q has a ring of uneven brightness traces m1 . This problem can be referred to as annular brightness unevenness (mura).

[0074] The embodiments of the present application provide a display panel, a display method, and a display device, which can solve the problems existing in the above-mentioned related technologies.

[0075] FIG5 is a schematic structural diagram of a display panel according to an embodiment of the present application. FIG6 is a partially enlarged structural diagram of the display panel shown in FIG5 ( FIG6 is an enlarged structural diagram of the dashed box x2 in FIG5 ). FIG7 is a schematic cross-sectional structural diagram of the display panel shown in FIG6 (the cross-sectional position may be AA). Referring to FIG5 , FIG6 and FIG7 , the display panel includes:

[0076] A substrate 51 is provided with a light-transmitting display area q1 and a conventional display area q2 surrounding the light-transmitting display area. The light-transmitting display area q1 and the conventional display area q2 each contain a plurality of sub-pixel areas sq. The plurality of sub-pixel areas sq are arranged as a plurality of rows of sub-pixel areas on the substrate. The sub-pixel areas sq each have connected pixel driving circuits 52 and light-emitting devices 53. FIG6 illustrates the plurality of sub-pixel areas sq in a row of sub-pixel areas. The division method of the sub-pixel areas in other rows can refer to this row of sub-pixel areas.

[0077] The normal display area q2 includes a winding pattern 54 and a plurality of normal signal lines 55 respectively located in a plurality of rows of sub-pixel areas. The winding pattern 54 and the normal signal lines 55 are located in different layers.

[0078] The winding pattern 54 includes a plurality of connecting lines t2 located in a plurality of rows of sub-pixels, each of which includes a main line t21 extending along the row direction f1 of the sub-pixel region and a plurality of extensions t22 extending toward adjacent sub-pixel regions. The connecting line t2 is connected to the conventional signal line 55, and the extension t22 on the connecting line t2 connected to the conventional signal line 55 in the n-th row of sub-pixels extends toward sub-pixel regions in rows other than the n-th row of sub-pixels, where n is an integer greater than zero. In the embodiments of the present application, the light-emitting device may include an organic light-emitting diode or other device capable of electroluminescence.

[0079] In summary, the display panel provided by the embodiment of the present application extends the extension portion of the connection line connected to the signal line in the n-th row sub-pixel region to the sub-pixel regions of other rows except the n-th row sub-pixel region. Under such a structure, when driving the light-emitting device in the n-th row sub-pixel region, the extension portion of the winding structure connected to the signal line in the n-th row sub-pixel region is located in the sub-pixel regions of other rows, and does not affect the pixel driving circuit in the n-th row sub-pixel region. Moreover, since the pixel driving circuit in the sub-pixel regions of other rows is not in a data writing state at this time, the voltage change on the extension portion has little effect on the pixel driving circuit in the sub-pixel regions of other rows, thereby improving the display effect of the display panel and reducing the possibility of uneven brightness.

[0080] The winding pattern 54 further includes a plurality of winding wires t1 extending around the light-transmitting display area q1, with the ends of the winding wires t1 connected to the connecting wires t2. A winding wire t1 and the connecting wires t2 connected to the winding wires t1 may constitute a winding structure t. Furthermore, the conventional signal lines include conventional gate lines, and the connecting wires t2 may be connected to the conventional gate lines.

[0081] In addition, in the display panel provided in the embodiment of the present application, other areas except the area where the winding pattern 54 is located may also have a pattern on the same layer as the winding pattern 54 (which may be called a dummy pattern, and the dummy may be connected to the power line), and the embodiment of the present application does not limit this.

[0082] In another optional embodiment, referring to FIG. 5 , the display panel includes: a light-transmitting display area q1 and a conventional display area q2 surrounding the light-transmitting display area q1 .

[0083] The light-transmitting display area q1 and the normal display area q2 include a plurality of sub-pixel areas sq, which are arranged into a plurality of rows of sub-pixel areas. The sub-pixel areas sq include pixel driving circuits 52 and light-emitting devices 53 connected thereto.

[0084] The conventional display area q2 includes a winding pattern 54 , and the light-transmitting display area q1 includes a plurality of light-transmitting area signal lines 56 . The light-transmitting area signal lines 56 and the winding pattern 54 are located in different layers.

[0085] The winding pattern 54 includes a plurality of winding structures t corresponding to multiple rows of sub-pixel areas respectively. The winding structure t corresponding to the n-th row of sub-pixel areas in the multiple rows of sub-pixel areas includes a winding line t1 extending around the light-transmitting display area q1, and a connecting line t2 located in the n-th row of sub-pixels. The connecting line t2 is connected to the end of the winding line t1, and the connecting line t2 includes a main line t21 extending along the row direction f1 of the n-th row of sub-pixel areas and a plurality of extension portions t22 extending toward the sub-pixel area. The connecting lines t2 of the multiple winding structures t are respectively connected to multiple light-transmitting area signal lines 56, and the extension portion t22 on the connecting line t2 connected to the light-transmitting area signal line 56 in the n-th row of sub-pixels extends to other rows of sub-pixel areas except the n-th row of sub-pixels, where n is an integer greater than zero.

[0086] In summary, the display panel provided by the embodiment of the present application extends the extension portion of the connection line connected to the signal line in the n-th row sub-pixel region to the sub-pixel regions of other rows except the n-th row sub-pixel region. Under such a structure, when driving the light-emitting device in the n-th row sub-pixel region, the extension portion of the winding structure connected to the signal line in the n-th row sub-pixel region is located in the sub-pixel regions of other rows, and does not affect the pixel driving circuit in the n-th row sub-pixel region. Moreover, since the pixel driving circuit in the sub-pixel regions of other rows is not in a data writing state at this time, the voltage change on the extension portion has little effect on the pixel driving circuit in the sub-pixel regions of other rows, thereby improving the display effect of the display panel and reducing the possibility of uneven brightness.

[0087] Referring to FIG. 7 , the display panel further includes a pixel definition layer 57 located on a substrate 51. The pixel definition layer 57 includes a blocking region 57a ​​and multiple opening regions 57b. The multiple opening regions 57b are respectively located in multiple sub-pixel regions. The orthographic projection of the extension portion t22 on the substrate 51 is located within the orthographic projection of the blocking region 57a ​​on the substrate 51. In other words, the extension portion t22 does not affect the aperture ratio of the display panel.

[0088] In the embodiment of the present application, the conventional signal line 55 may be a gate line or other signal line in a conventional display area, and the light-transmitting area signal line 56 may be a gate line or other signal line in a light-transmitting display area.

[0089] In an exemplary embodiment, in the display panel provided by the embodiments of the present application, the light-emitting devices in the light-transmitting display area are connected to the pixel driving circuits in a one-to-one correspondence. That is, the Yege pixel driving circuit drives one light-emitting device, or the pixel driving circuit in the light-transmitting display area is connected to at least two light-emitting devices. In other words, a single pixel driving circuit can drive multiple light-emitting devices. Furthermore, the density of light-emitting devices in the light-transmitting display area can be lower than that in a conventional display area, thereby improving the transmittance of the light-transmitting display area.

[0090] In the embodiment of the present application, there are at least two ways to extend the extension portion t22 on the connection line t2 connected to the signal line in the nth row of sub-pixel areas to sub-pixel areas in other rows except the nth row of sub-pixel areas, which are described below respectively.

[0091] The first method is shown in FIG6 , wherein the pixel driving circuit 52 includes a storage capacitor located in the sub-pixel region and a node N1 connected to one end of the storage capacitor (the position of N1 is marked in the figure).

[0092] The normal signal line 55 in the n-th row of sub-pixel regions is connected to the connection line t2 of the winding structure t corresponding to the n-th row of sub-pixel regions.

[0093] The main line t21 of the connecting line t2 of the winding structure t corresponding to the n-th row of sub-pixel regions is located on the first side of the node N1 of the n-th row of sub-pixel regions. The extension t22 of the connecting line t2 of the winding structure t corresponding to the n-th row of sub-pixel regions extends toward the adjacent row of sub-pixel regions on the second side of the n-th row of sub-pixel regions. The first side and the second side are two sides in a direction f2 perpendicular to the row direction f1. In the structure shown in FIG6 , the first side is the upper side, and the second side is the lower side.

[0094] As can be seen from FIG6 , the main line t21 of the connection line t2 in the sub-pixel region of the n-th row is located in the sub-pixel region of the n-th row, but the extension t22 of the connection line t2 extends into the sub-pixel region of the n+1-th row. With this structure, the extension t22 is far away from the node N1 in the sub-pixel region of the n-th row and does not affect the potential of the node N1 in the sub-pixel region of the n-th row. In other words, the electrical signal of the signal line in the sub-pixel region of the n-th row is prevented from affecting the potential of the node N1 in the sub-pixel region of the n-th row, thereby reducing the possibility of generating a ring mura problem near the FDC region.

[0095] Figure 6 shows a situation where the main line t21 of the connecting line t2 of the winding structure t corresponding to the n-th row sub-pixel area is located on the upper side of the N1 node of the n-th row sub-pixel area, and the extension t22 of the connecting line t2 of the winding structure t corresponding to the n-th row sub-pixel area extends toward the sub-pixel area of ​​the adjacent row below the n-th row sub-pixel area. However, it may also be a structure where the main line t21 of the connecting line t2 of the winding structure t corresponding to the n-th row sub-pixel area is located on the lower side of the N1 node of the n-th row sub-pixel area, and the extension t22 of the connecting line t2 of the winding structure t corresponding to the n-th row sub-pixel area extends toward the sub-pixel area of ​​the adjacent row above the n-th row sub-pixel area. The embodiments of the present application do not limit this.

[0096] It should be noted that in the display panel provided in the embodiments of the present application, the sub-pixel regions can be arranged in rows and columns, for example, they can be arranged in multiple rows and columns, wherein each row of sub-pixel regions can include multiple sub-pixel regions arranged along the row direction. As shown in FIG6 , the area between two adjacent main lines t21 can be a row of sub-pixel regions. Of course, the sub-pixel regions can also be divided in other ways, and the embodiments of the present application are not limited thereto.

[0097] Please refer to Figure 8, which shows a circuit structure diagram of a pixel driving circuit. The pixel driving circuit has a 7T1C structure, which may include seven thin film transistors (TFTs), wherein the gate of the third thin film transistor T3 is connected to the first node N1, the source of the third thin film transistor T3 is connected to the second node N2, and the drain of the third thin film transistor T3 is connected to the third node N3.

[0098] A gate electrode of the fourth thin film transistor T4 is connected to the gate line G, a source electrode of the fourth thin film transistor T4 is connected to the data signal line D, and a drain electrode of the fourth thin film transistor T4 is connected to the second node N2.

[0099] A gate electrode of the second thin film transistor T2 is connected to the gate line G, a source electrode of the second thin film transistor T2 is connected to the third node N3 , and a drain electrode of the second thin film transistor T2 is connected to the first node N1 .

[0100] A gate of the first thin film transistor T1 is connected to the reset signal line R, a drain of the first thin film transistor T1 is connected to the first reference signal line V1, and a source of the first thin film transistor T1 is connected to the first node N1.

[0101] The gate of the fifth thin film transistor T5 and the gate of the sixth thin film transistor T6 are connected to the light-emitting signal line EM, the source of the fifth thin film transistor T5 is connected to the constant high potential VDD, the drain of the fifth thin film transistor T5 is connected to the second node N2, the source of the sixth thin film transistor T6 is connected to the third node N3, the drain of the sixth thin film transistor T6 is connected to the anode of the light-emitting device EL, and the cathode of the light-emitting device 117 is connected to the low potential VSS.

[0102] A gate of the seventh thin film transistor T7 is connected to the gate line G, a drain of the seventh thin film transistor T7 is connected to the second reference signal line V2, and a source of the seventh thin film transistor T7 is connected to the anode of the light emitting device EL.

[0103] One end of the storage capacitor Cst1 may be connected to the first node N1 , and the other end of the storage capacitor Cst1 may be connected to the constant high potential VDD.

[0104] The N1 node is easily affected by potential changes of other structures, which in turn causes the brightness of the light-emitting unit driven by the pixel driving circuit to change.

[0105] Of course, the pixel driving circuit in the display panel provided in the embodiment of the present application may also have other structures, and the embodiment of the present application is not limited to this.

[0106] In the first method, the conventional signal line 55 in the nth row sub-pixel area is connected to the connection line t2 of the winding structure t corresponding to the same row sub-pixel area, and the extension portion t22 is extended to the adjacent row sub-pixel area to avoid the extension portion t22 from affecting the N1 node in the current row sub-pixel area.

[0107] Specifically, when the conventional signal line 55 is a gate line, when driving the light-emitting device in the n-th row sub-pixel area, the control component can load a first potential to the gate line in the n-th row sub-pixel area at a first moment, so as to charge the pixel driving circuit in the n-th sub-pixel area, and the N1 node of the pixel driving circuit in the n+1-th row sub-pixel area where the extension portion is located is affected by the first potential and jumps to the first potential.

[0108] At a second moment, a second potential is applied to the gate line in the n-th row of sub-pixel regions to stop charging the pixel driving circuit in the n-th sub-pixel region. Node N1 of the pixel driving circuit in the (n+1)-th row of sub-pixel regions, where the extension portion is located, is affected by the second potential and jumps to the second potential. One of the first potential and the second potential is a high potential, and the other is a low potential.

[0109] During the aforementioned driving process, the sub-pixel region in the n+1th row is in a light-emitting state, not a charging state. Furthermore, the potential of node N1 quickly transitions to the first potential and then to the second potential. These two transitions cancel each other out, leaving the brightness of the light-emitting devices in the sub-pixel region in the n+1th row largely unaffected. This prevents the appearance of ring-shaped mura near the FDC region, improving the display quality of the display panel.

[0110] Figure 9 is a layout of a partial structure of a display panel provided in an embodiment of the present application. Please refer to Figure 9. The display panel includes a stacked gate line pattern g2 (the gate line pattern g2 may belong to a conventional signal line), a source-drain metal pattern s1, and a connecting line t2. Among them, the gate line pattern g2 includes a gate line located in the conventional display area q2, and the gate line pattern g2 may be connected to the light-transmitting area gate line (the light-transmitting area gate line may belong to the light-transmitting area signal line) in the light-transmitting display area q1 at the junction of the conventional display area q2 and the light-transmitting display area q1. In addition, the gate line pattern g2 may be connected to the connecting line t2 at the junction of the conventional display area q2 and the light-transmitting display area q1. The source-drain metal pattern s1 may include an N1 node. In Figure 9, the structure with the same fill pattern is a same-layer structure.

[0111] As can be seen from FIG9 , the main line t21 of the connection line t2 in the sub-pixel region of the n-th row is located in the sub-pixel region of the n-th row, but the extension t22 of the connection line t2 extends into the sub-pixel region of the n+1-th row. With this structure, the extension t22 is far away from the N1 node in the sub-pixel region of the n-th row and will not affect the potential of the N1 node in the sub-pixel region of the n-th row. In other words, the electrical signal of the gate line in the sub-pixel region of the n-th row is prevented from affecting the potential of the N1 node in the sub-pixel region of the n-th row, thereby reducing the possibility of generating a ring mura problem near the FDC region.

[0112] In addition, in an embodiment of the present application, the winding pattern can be a same-layer structure as the source-drain metal pattern in the display panel, and the display panel can include multiple layers of source-drain metal patterns. The winding pattern can be a same-layer structure as the second source-drain metal pattern in the display panel (the second source-drain metal pattern can be located above the source-drain metal pattern s1 in the above-mentioned Figure 9), or the winding pattern can be a same-layer structure as other structures in the display panel, and the embodiment of the present application does not limit this.

[0113] In addition, the gate line pattern g2 in Figure 9 may include gate lines g21a, gate lines g21b and gate lines g21c, where the gate line g21a may be a gate signal line), the gate line g21b may be an emission control line, and the gate line g21c may be a reset signal line.

[0114] FIG10 is a disassembled and merged layout of a portion of the display panel shown in FIG9 ( FIG10 may be a layout of a portion of the structure within the dashed box kx in FIG9 ). Referring to FIG9 and FIG10 , the pixel drive circuit may include an active layer pattern 5a, a first conductive pattern 5b, and a second conductive pattern 5c. The first conductive pattern 5b may include a first plate c1 of a storage capacitor, a gate line g21a (gate line g21a may be a gate signal line), a gate line g21b (gate line g21b may be an emission control line), and a gate line g21c (gate line g21c may be a reset signal line). The second conductive pattern 5c may include a second plate c2 of a capacitor structure. The third conductive pattern 5d may include a data signal line 5d1, a power line 58, a node connection line 5d2, and a source and drain.

[0115] Gate line g21a can connect to connection structure 5d3 (which can be a source / drain metal layer) at the junction of the normal display area q2 and the light-transmitting display area q1, and is electrically connected to connection line t2 through connection structure 5d3. The main line t21 of connection line t2 extends along the row direction, and the extension t22 extends downward to the sub-pixel area of ​​the next row.

[0116] In addition, Figure 10 also shows a plurality of thin film transistors (T1 to T7), and the circuit structure of these plurality of thin film transistors can be referred to Figure 8. In addition, in the embodiment of the present application, T (uppercase) 2 represents the second thin film transistor, and t (lowercase) 2 represents the connecting wire in the winding structure.

[0117] Please refer to Figure 11 for the second method. Figure 11 is a schematic diagram of the structure of another display panel provided by an embodiment of the present application. Among them, the conventional signal line 55 in the n-th row sub-pixel area is connected to the connection line t2 of the winding structure corresponding to the other row sub-pixel areas except the n-th row sub-pixel area in the multi-row sub-pixel area. Under such a structure, when driving the light-emitting device in the n-th row sub-pixel area, the extension t22 in the winding structure connected to the n-th row conventional signal line 55 is located in the other row sub-pixel areas, and will not affect the pixel driving circuit in the n-th row sub-pixel area. Since the pixel driving circuit in the other row sub-pixel areas is not in the data writing state at this time, the voltage change on the extension t22 has little effect on the pixel driving circuit in the other row sub-pixel areas, thereby improving the display effect of the display panel. The possibility of generating uneven brightness problems is reduced.

[0118] In an embodiment of the present application, a method for dividing a row of sub-pixel regions may be shown in FIG11 , wherein the lower boundary of the sub-pixel regions in the nth row may be located below the main line t21 in the nth row. In other display panels provided in an embodiment of the present application, the method for dividing the sub-pixel regions may refer to FIG11 , and will not be further described in detail in the following embodiments of the present application.

[0119] In an exemplary embodiment, the extension portion t22 includes a plurality of at least one sub-segment t221, each of which is arranged around the opening region q4. In the structure shown in FIG11 , the number of sub-segments t221 is two, with two sub-segments t221 located on either side of the opening region q4 in the row direction f1.

[0120] In an exemplary embodiment, the conventional signal line 55 in the n-th row sub-pixel region is connected to the connection line of the winding structure corresponding to the n+x-th row sub-pixel region in the multi-row sub-pixel region, where x is an integer greater than zero. Figure 11 shows the situation where the conventional signal line 55 in the n-th row sub-pixel region is connected to the connection line of the winding structure corresponding to the n+1-th row sub-pixel region in the multi-row sub-pixel region, but the embodiment of the present application is not limited to this. Exemplarily, the conventional signal line 55 in the n-th row sub-pixel region can also be connected to the connection line of the winding structure corresponding to the n+2-th row sub-pixel region in the multi-row sub-pixel region, or the conventional signal line 55 in the n-th row sub-pixel region can also be connected to the connection line of the winding structure corresponding to the n+3-th row sub-pixel region in the multi-row sub-pixel region, etc.

[0121] The circuit structure further includes a jumper wire j1, one end of which is connected to the conventional signal line 55 in the n-th row of sub-pixel regions, and the other end of which is connected to the connecting wire t2 of the winding structure corresponding to the sub-pixel regions in other rows except the n-th row of sub-pixel regions. The connecting wire j1 can be on the same layer as the connecting wire t2.

[0122] It should be noted that, in the display panel provided in the embodiment of the present application, the connection line t2 can be connected to the conventional signal line 55 through the source-drain metal pattern below.

[0123] Please refer to Figure 12, which is a layout corresponding to some structures in the display panel shown in Figure 11, wherein the conventional gate line g21 in the n-th row sub-pixel area (the conventional gate line g21 is a gate line located in the conventional display area and belongs to a conventional signal line) is connected to the connecting line t2 of the winding structure corresponding to the n+1-th row sub-pixel area in the multi-row sub-pixel area. Under such a structure, when driving the light-emitting device in the n-th row sub-pixel area, the extension in the winding structure connected to the conventional signal line 55 in the n-th row sub-pixel area is located in the n+1-th row sub-pixel area, which will not affect the pixel driving circuit in the n-th row sub-pixel area, and because the pixel driving circuit in the other rows of sub-pixel areas is not in a data writing state at this time, the voltage change on the extension has little effect on the pixel driving circuit in the other rows of sub-pixel areas, thus improving the display effect of the display panel. The possibility of generating uneven brightness is reduced. It should be noted that Figure 12 only shows the connection point where the conventional gate line g21 is connected to the main line t21 of the connecting line, but does not limit the structure of the conventional gate line.

[0124] Another structure similar to the display panel shown in FIG11 can be shown in FIG13 , which is a schematic diagram of the structure of another display panel provided by an embodiment of the present application. In this structure, the conventional signal line 55 in the n-th row of sub-pixel regions is connected to the connecting line of the winding structure corresponding to the nx-th row of sub-pixel regions in the multi-row sub-pixel region, where x is an integer greater than zero, for example, x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, etc.

[0125] FIG13 shows a situation where a conventional gate line g21a (conventional gate line g21a belongs to a conventional signal line 551) in the n+1th row sub-pixel region is connected to a connection line t2 of a winding structure corresponding to the n-1th row sub-pixel region in a multi-row sub-pixel region, but the embodiment of the present application is not limited to this (the conventional gate line g21b in the n+2th row sub-pixel region is connected to a connection line t2 of a winding structure corresponding to the nth row sub-pixel region in a multi-row sub-pixel region). For example, the conventional signal line 551 in the nth row sub-pixel region can also be connected to a connection line of a winding structure corresponding to the n-2th row sub-pixel region in a multi-row sub-pixel region, or the conventional signal line 551 in the nth row sub-pixel region can also be connected to a connection line of a winding structure corresponding to the n-3th row sub-pixel region in a multi-row sub-pixel region, etc.

[0126] With this structure, when driving the light-emitting devices in the nth row of sub-pixel regions, the extension of the winding structure connected to the conventional signal line 55 in the n+1th row of sub-pixel regions is located in the n-1th row of sub-pixel regions, and does not affect the pixel driving circuit in the nth row of sub-pixel regions. Furthermore, since the pixel driving circuits in the other rows of sub-pixel regions are not in a data writing state at this time, the voltage change on the extension has little effect on the pixel driving circuits in the other rows of sub-pixel regions, thereby improving the display effect of the display panel and reducing the possibility of uneven brightness.

[0127] Please refer to FIG14, which is a layout corresponding to the display panel shown in FIG13, wherein the conventional gate line g21a (conventional gate line g21a belongs to the conventional signal line 551) in the n+1th row sub-pixel region is connected to the connection line t2 of the winding structure corresponding to the n-1th row sub-pixel region in the multi-row sub-pixel region. With such a structure, when driving the light-emitting device in the nth row sub-pixel region, the extension portion of the winding structure connected to the conventional gate line g21a in the n+1th row sub-pixel region is located in the n-1th row sub-pixel region, and will not affect the pixel driving circuit in the n+1th row sub-pixel region. Moreover, since the pixel driving circuits in the other rows of sub-pixel regions are not in the data writing state at this time, the voltage change on the extension portion has little effect on the pixel driving circuits in the other rows of sub-pixel regions, thereby improving the display effect of the display panel and reducing the possibility of uneven brightness.

[0128] Exemplarily, as shown in Figure 15, Figure 15 is a schematic structural diagram of another display panel provided by an embodiment of the present application. In an exemplary embodiment, the multiple extensions t22 include at least one disconnected extension t22a, and the disconnected extension t22a is disconnected from the main circuit t21. In the display panels provided by the above embodiments of the present application, any display panel may include a disconnected extension. In the display panel, the winding pattern includes a plurality of disconnected extensions t22a, and the disconnected extension t22a is disconnected from the main circuit t21. Under such a structure, the disconnected extension t22a does not receive a signal, so that when the signal of a conventional signal line (such as a gate line) jumps, the disconnected extension t22a is little affected, further reducing the impact on the potential of point N1.

[0129] In addition, as shown in Figure 16, Figure 16 is a structural layout diagram of another display panel provided by an embodiment of the present application, wherein the display panel also includes a power line 58 (the power line 58 can be located in the source-drain metal pattern s1), and at least one disconnect extension t22a is electrically connected to the power line 58. The power line 58 carries a regulated signal. Connecting the disconnect extension t22a to the power line 58 can prevent the isolated structure of the disconnect extension t22a from generating parasitic capacitance due to voltage changes of other signal lines. In Figure 16, the disconnect extension t22a is connected to the power line 58 at the ts position.

[0130] It should be noted that FIG16 only shows a case where one row of sub-pixel regions has a disconnected extension portion t22a, and the disconnected extension portion t22a is connected to the power line 58. Sub-pixel regions in other rows may also have a similar structure, and the embodiment of the present application does not limit this.

[0131] In summary, the display panel provided by the embodiment of the present application extends the extension portion of the connection line connected to the signal line in the n-th row sub-pixel region to the sub-pixel regions of other rows except the n-th row sub-pixel region. Under such a structure, when driving the light-emitting device in the n-th row sub-pixel region, the extension portion of the winding structure connected to the signal line in the n-th row sub-pixel region is located in the sub-pixel regions of other rows, and does not affect the pixel driving circuit in the n-th row sub-pixel region. Moreover, since the pixel driving circuit in the sub-pixel regions of other rows is not in a data writing state at this time, the voltage change on the extension portion has little effect on the pixel driving circuit in the sub-pixel regions of other rows, thereby improving the display effect of the display panel and reducing the possibility of uneven brightness.

[0132] FIG17 is a flow chart of a method for displaying a display panel provided in an embodiment of the present application. The method can be used to control any of the display panels provided in the above embodiments. The method may include the following steps:

[0133] Step 1711: When driving the light-emitting devices in the n-th row of sub-pixel regions, a first potential is applied to the normal signal lines in the n-th row of sub-pixel regions at a first moment.

[0134] In this way, the pixel driving circuit in the nth sub-pixel area can be charged, and at least part of the circuit of the pixel driving circuit in the sub-pixel area where the extension part is located is affected by the first potential and jumps to the first potential. The sub-pixel area where the extension part is located is a sub-pixel area in the multiple rows of sub-pixel areas in the display panel except the nth row of sub-pixel areas.

[0135] Step 1712: at a second moment, a second potential is applied to the normal signal line in the n-th row of sub-pixel regions to stop charging the pixel driving circuit in the n-th sub-pixel region.

[0136] The conventional signal lines may include conventional gate lines.

[0137] At least a portion of the pixel driving circuit in the sub-pixel region where the extension portion is located is affected by the second potential and jumps to the second potential. One of the first potential and the second potential is a high potential, and the other is a low potential. For example, the first potential can be a low potential, used to turn on the switch to start charging, and the second potential can be a high potential, used to turn off the switch to stop charging.

[0138] During the aforementioned driving process, the light-emitting devices in sub-pixel regions in rows other than the nth row are in a light-emitting state, not a charging state. Furthermore, the potential of node N1 quickly transitions to the first potential and then to the second potential. These two transitions cancel each other out, and the brightness of the light-emitting devices in these sub-pixel regions is essentially unaffected. This prevents the appearance of ring-shaped mura near the FDC region, improving the display quality of the display panel.

[0139] In summary, the display method of the display panel provided by the embodiment of the present application extends the extension portion of the connecting line connected to the signal line in the n-th row sub-pixel region to the sub-pixel regions of other rows except the n-th row sub-pixel region. Under such a structure, when driving the light-emitting device in the n-th row sub-pixel region, the extension portion of the winding structure connected to the signal line in the n-th row sub-pixel region is located in the sub-pixel regions of other rows, and will not affect the pixel driving circuit in the n-th row sub-pixel region. Moreover, since the pixel driving circuit in the sub-pixel regions of other rows is not in a data writing state at this time, the voltage change on the extension portion has little effect on the pixel driving circuit in the sub-pixel regions of other rows, thereby improving the display effect of the display panel and reducing the possibility of uneven brightness.

[0140] FIG18 is a block diagram of a display panel control device provided in an embodiment of the present application. The display panel control device can be used to control any of the display panels provided in the above embodiments. The display panel control device 1800 may include:

[0141] a first control component 1810 configured to apply a first potential to a regular signal line in the n-th row of sub-pixel regions at a first moment when driving the light-emitting devices in the n-th row of sub-pixel regions, so as to charge the pixel driving circuit in the n-th sub-pixel region, and cause at least a portion of the pixel driving circuit in the sub-pixel region where the extension portion is located to jump to the first potential under the influence of the first potential. The sub-pixel region where the extension portion is located is a sub-pixel region among the multiple rows of sub-pixel regions in the display panel, excluding the n-th row of sub-pixel regions;

[0142] The second control component 1820 is used to load a second potential to the conventional signal line in the n-th row sub-pixel area at a second moment to stop charging the pixel driving circuit in the n-th sub-pixel area, and at least part of the pixel driving circuit in the sub-pixel area where the extension portion is located is affected by the second potential and jumps to the second potential.

[0143] In summary, the control device for a display panel provided in an embodiment of the present application extends the extension portion of the connection line connected to the signal line in the n-th row sub-pixel region to the sub-pixel regions of other rows except the n-th row sub-pixel region. Under such a structure, when driving the light-emitting device in the n-th row sub-pixel region, the extension portion of the winding structure connected to the signal line in the n-th row sub-pixel region is located in the sub-pixel regions of other rows, and does not affect the pixel driving circuit in the n-th row sub-pixel region. Moreover, since the pixel driving circuit in the sub-pixel regions of other rows is not in a data writing state at this time, the voltage change on the extension portion has little effect on the pixel driving circuit in the sub-pixel regions of other rows, thereby improving the display effect of the display panel and reducing the possibility of uneven brightness.

[0144] In addition, an embodiment of the present application also provides a display device, which includes an optical device and a display panel provided by the above embodiment. The optical device is located on the back of the display panel (the back of the display panel is the other side of the display panel opposite to the display surface), and there is an overlapping area between the orthographic projection on the display panel and the light-transmitting display area of ​​the display panel.

[0145] The optical device can be used to obtain light information from the environment directly in front of the display panel through the light-transmitting display area of ​​the display panel, and to emit light to the environment directly in front of the display panel. The optical device can include a visible light camera, an infrared camera, a dot matrix projector, etc., which is not limited in the embodiments of the present application.

[0146] In addition, an embodiment of the present application also provides a display device, which includes a processor, a memory, and a display panel, wherein the memory stores at least one instruction, at least one program, a code set, or an instruction set, and the at least one instruction, at least one program, a code set, or an instruction set is loaded and executed by the processor to implement the display method of the display panel provided in the above embodiment.

[0147] An embodiment of the present application also provides a computer storage medium, which stores at least one instruction, at least one program, code set or instruction set, and the at least one instruction, at least one program, code set or instruction set is loaded and executed by a processor to implement the display method of the display panel provided in the above embodiment.

[0148] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0149] In this application, the terms "first", "second", "third", "fourth", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more, unless otherwise clearly defined.

[0150] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0151] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0152] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0153] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: The display panel includes: a substrate having a light-transmitting display area and a regular display area surrounding the light-transmitting display area, the light-transmitting display area and the regular display area having a plurality of sub-pixel areas, the plurality of sub-pixel areas being arranged as a plurality of rows of sub-pixel areas on the substrate, and the sub-pixel areas having connected pixel driving circuits and light-emitting devices; The conventional display area includes a winding pattern and a plurality of conventional signal lines respectively located in the plurality of rows of sub-pixel areas, wherein the winding pattern and the conventional signal lines are located in different layers; The winding pattern includes a plurality of connecting lines respectively located in a plurality of rows of sub-pixel areas, and the connecting lines include a main line extending along the row direction of the sub-pixel area and a plurality of extension portions extending toward adjacent sub-pixel areas. The connecting lines are connected to the conventional signal lines, and the extension portions on the connecting lines to which the conventional signal lines in the nth row of sub-pixels are connected extend toward sub-pixel areas in other rows except the nth row of sub-pixels, where n is an integer greater than zero.

2. The display panel according to claim 1, wherein: The display panel further includes a pixel definition layer located on the substrate, the pixel definition layer including a blocking area and a plurality of opening areas, the plurality of opening areas being respectively located in the plurality of sub-pixel areas, and an orthographic projection of the extension portion on the substrate being located in an orthographic projection of the blocking area on the substrate; The plurality of extensions include at least one disconnecting extension, which is disconnected from the main line.

3. The display panel according to claim 2, wherein: The extension portion includes at least one sub-segment, and the at least one sub-segment is arranged around the opening area.

4. The display panel according to claim 3, wherein: The extension portion includes two sub-line segments respectively located on both sides of the opening area in the row direction.

5. The display panel according to claim 2, wherein: The display panel further includes a power line, and at least one of the disconnecting extensions is electrically connected to the power line.

6. The display panel according to claim 1, wherein: The pixel driving circuit includes a storage capacitor located in the sub-pixel area, and a node connection line, wherein the node connection line is connected to one end of the storage capacitor, and the capacitor is connected to a node N1; The conventional signal lines in the n-th row of sub-pixel regions are connected to the connection lines of the winding structure corresponding to the n-th row of sub-pixel regions; The main line of the connecting line of the winding structure corresponding to the n-th row sub-pixel area is located on the first side of the N1 node of the n-th row sub-pixel area, and the extension part of the connecting line of the winding structure corresponding to the n-th row sub-pixel area extends to the sub-pixel area of ​​the adjacent row on the second side of the n-th row sub-pixel area, and the first side and the second side are two sides in the direction perpendicular to the row direction.

7. The display panel according to claim 1, wherein: The conventional signal lines in the n-th row of sub-pixel regions are connected to the connection lines of the winding structures corresponding to the sub-pixel regions in other rows of the multiple rows of sub-pixel regions except the n-th row of sub-pixel regions.

8. The display panel according to claim 7, wherein: The display panel also includes a jumper wire, one end of which is connected to the conventional signal line in the nth row of sub-pixel areas, and the other end of which is connected to the connecting wire of the winding structure corresponding to the sub-pixel areas in other rows except the nth row of sub-pixel areas.

9. The display panel according to claim 8, wherein: The jumper lead and the winding structure are in the same layer structure.

10. The display panel according to claim 7, wherein: The conventional signal lines in the n-th row of sub-pixel regions are connected to the connection lines of the winding structure corresponding to the (n+x)-th row of sub-pixel regions in the multiple rows of sub-pixel regions, where x is an integer greater than zero.

11. The display panel according to claim 7, wherein: The conventional signal line in the n-th row of sub-pixel regions is connected to the connection line of the winding structure corresponding to the nx-th row of sub-pixel regions in the multiple rows of sub-pixel regions, where x is an integer greater than zero.

12. The display panel according to any one of claims 1 to 11, characterized in that: The winding pattern further includes a plurality of winding lines extending around the light-transmitting display area, and ends of the winding lines are connected to the connecting lines.

13. The display panel according to any one of claims 1 to 11, characterized in that: The conventional signal lines include conventional gate lines, and the connecting lines are connected to the conventional gate lines.

14. The display panel according to any one of claims 1 to 11, characterized in that: The display panel includes a source-drain metal pattern, and the winding pattern and the source-drain metal pattern are in the same layer structure.

15. The display panel according to any one of claims 1 to 11, characterized in that: The light-emitting devices in the light-transmitting display area are connected to the pixel driving circuits in a one-to-one correspondence.

16. The display panel according to any one of claims 1 to 11, characterized in that: The pixel driving circuit in the light-transmitting display area is connected to at least two light-emitting devices.

17. The display panel according to any one of claims 1 to 11, characterized in that: The density of the light-emitting devices in the light-transmitting display area is lower than the density of the light-emitting devices in the conventional display area.

18. A display panel, characterized in that: The display panel comprises: a light-transmitting display area and a conventional display area surrounding the light-transmitting display area; The light-transmitting display area and the conventional display area have a plurality of sub-pixel areas, the plurality of sub-pixel areas are arranged into a plurality of rows of sub-pixel areas, and the sub-pixel areas have connected pixel driving circuits and light-emitting devices; The conventional display area includes a winding pattern, and the light-transmitting display area includes a plurality of light-transmitting area signal lines, wherein the light-transmitting area signal lines and the winding pattern are located in different layers; The winding pattern includes a plurality of winding structures corresponding to the plurality of rows of sub-pixel areas respectively, the winding structure corresponding to the n-th row of sub-pixel areas in the plurality of rows of sub-pixel areas includes a winding line extending around the light-transmitting display area, and a connecting line located in the n-th row of sub-pixels, the connecting line is connected to the end of the winding line, and the connecting line includes a main line extending along the row direction of the n-th row of sub-pixel areas and a plurality of extensions extending toward the sub-pixel areas, the connecting lines of the plurality of winding structures are respectively connected to a plurality of light-transmitting area signal lines, and the extensions on the connecting lines connected to the light-transmitting area signal lines in the n-th row of sub-pixels extend toward sub-pixel areas of other rows except the n-th row of sub-pixels, where n is An integer greater than zero.

19. A display device, characterized in that: The display device includes an optical device and a display panel according to any one of claims 1 to 18, wherein the optical device is located on the back of the display panel, and an orthographic projection of the optical device on the display panel overlaps with a light-transmitting display area of ​​the display panel.

20. A display method for a display panel, characterized in that: For controlling the display panel according to any one of claims 1 to 18, the method comprising: When driving the light-emitting devices in the n-th row of sub-pixel regions, a first potential is applied to the regular signal lines in the n-th row of sub-pixel regions at a first moment, so as to charge the pixel driving circuit in the n-th sub-pixel region. At least a portion of the pixel driving circuit in the sub-pixel region where the extension portion is located is affected by the first potential and jumps to the first potential. The sub-pixel region where the extension portion is located is a sub-pixel region among the multiple rows of sub-pixel regions in the display panel, excluding the n-th row of sub-pixel regions. At a second moment, a second potential is loaded to the conventional signal line in the n-th row sub-pixel area to stop charging the pixel driving circuit in the n-th row sub-pixel area, and at least part of the pixel driving circuit in the sub-pixel area where the extension portion is located is affected by the second potential and jumps to the second potential.

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