Amplifier for a CATV network

Abstract

An amplifier 40, configured to transfer Time Division Duplex (TDD) signals, includes a signal input 50, a signal output 52, and a gain block 42. Switches 46, 44 are disposed between the signal input and the signal output and are moveable between a first position, in which downstream TDD signals passing from the signal input to the signal output are routed through the gain block, and a second position, in which upstream TDD signals passing from the signal output to the signal input are routed through the gain block. There may be two switches, each comprising a first and a second contact; when the switches contact their respective first contact the downstream signal is routed through the gain block and when the switches contact their respective second contact the upstream signal is routed through the gain block. The switches may be responsive to a timing circuit 48 matched to a clock signal associated with a TDD signal, and they may be operable when the signal direction is changed. The gain block may introduce a gain of 60dB or more. The amplifier may, for example, be used to transmit high frequency signals, e.g., 5G wireless communications, over transmission cable in a CATV network.

Description

An TDD signal like 5G is a wide band signal (1.5 to 4 GHz) that either goes up or down. An example is given in Figure 1 where the horizontal axis is time and the vertical axis frequency. During time slots 10, there is a downstream signal, during time slots 12 the signal direction is changed and during this very brief period the signaling is silenced, and during the time slots 14 there is an upstream signal. The loss on the cable section can easily be 60dB and therefore a 60dB amplifier is needed to refresh the signals as data propagates downstream across the network. As the loss in the upstream signal is the same as the loss in the downstream at any one frequency, a 60dB or more gain amplifier in the upstream is also needed. An amplifier 20 could be constructed as in Figure 2 where downstream gain block 22 provides amplification gain of 60dB to the downstream signals and upstream gain block 24 provides amplification gain of 60dB to the upstream signals. Switches 26, 28 on input 30 and output 32 control the signal direction through downstream gain block 22 and upstream gain block 24, with signal only passing through one gain block t a time. In Figure 2, the signal goes to downstream gain block 22 and therefore the signal will have gain in the downstream. During the change time slots 12, switches 26, 28 switch the signal in response to timing circuit 34 synchronised by the TDD clock signal to allow upstream signal in time slot 14 to pass through upstream gain block 24. As the loop gain is 120dB due to each gain block providing a gain of 60dB, the isolation that switches 26, 28 have to create has to be a little bit greater than 120dB to prevent oscillation. This is very difficult to achieve, particularly over time and with temperature variations. To address this isolation issue, a TDD amplifier 40 is provided as shown in Figure 3 having a single gain block 42 used to provide amplification for upstream and downstream signals at different times, i.e. temporally separated signals. Switches 44, 46 responsive to timing circuit 48 determine which of input 50 or output 52 of amplifier 40 will go to input 54 of gain block 42. Each switch 44, 46 has a first and second contact between which it moves to establish alternate signal paths. When switches 44, 46 are disposed in a first position contacting first contacts 54, 54’ as shown in Figure 3, downstream signals passing from input 50 to output 52 are routed through gain block 42 as can be seen by arrow 60 in Figure 4 showing the path of the downstream signals. When switches 44, 46 have been switched to their alternate second position to contact second contacts 56, 56’, being activated by timing circuit 48 then upstream signals passing from output 52 to input 50 are routed through gain block 42 as shown by arrow 62, see Figure 5. Thus by using switches 44, 46, a single gain block 42 can be used to amplify either the upstream signals or the downstream signals at different times, so avoiding issues with isolation and oscillation as seen when using two gain blocks and a loop gain of 120dB. To improve stability of gain block 42 during switching, an additional terminator circuit 70 may be added to terminate gain block 42 during switching, see Figure 6. During switching time slot 12, gain block 42 is terminated by moving switch 72 from contact 74 to contact 76, then switches 44, 46 move to switch the direction of the amplifier. The termination switch 72 is then released to move back to contact 74 and restore the connection between gain block 42 and switch 46 and allow passage of signal through gain block 42. With this TDD amplifier, a gain block of 60dB or more can be used as required without any isolation issues. The direction of the gain block follows the TDD signal via the timing clock circuit. During the change time 12, the amplifier alters amplification direction. This TDD amplifier can be placed parallel to an FDD DOCSIS amplifier as FDD DOCSIS signals are below 1.2 GHz and the TDD signals are on a higher frequency. If an operator decides to require more or less frequency bandwidth for DOCSIS, the TDD signal can move up or down as well. Figure 7 shows one possible combination of an FDD amplifier and a parallel TDD amplifier combined within a single unit 80 with triplex filters 82, 84 at input 86 and output 88. Triplex filters 82, 84 separate upstream and downstream FDD signals to pass through an FDD upstream gain block 90 and an FDD downstream gain block 92, whilst TDD signals are routed via TDD amplifier 40 within unit 80.

Claims

1. An amplifier configured to transfer Time Division Duplex (TDD) signals, the amplifier comprising a signal input and a signal output and a gain block, wherein switches disposed between the signal input and the signal output are moveable between a first position in which downstream TDD signals passing from the signal input to the signal output are routed through the gain block and a second position in which upstream TDD signals passing from the signal output to the signal input are routed through the gain block.

2. An amplifier according to Claim 1, wherein there are two switches each comprising a first contact and a second contact, such that when the switches contact their respective first contacts the downstream signal is routed through the gain block and when the switches contact their respective second contact the upstream signal is routed through the gain block.

3. An amplifier according to Claim 1 or Claim 2, wherein the switches are operable during a time period when the signal direction of a TDD signal is changed.

4. An amplifier according to any of the preceding claims, wherein the switches are responsive to a timing circuit matched to a clock signal associated with a TDD signal.

5. An amplifier according to any of the preceding claims, further comprising a termination circuit connectable to the gain block and operable to terminate the gain block as the switches move from the first position to the second position.

6. An amplifier according to any of the preceding claims, wherein the gain block introduces a gain of 60dB or more.

7. An amplifier according to any of the preceding claims, comprising a single gain block to amplify TDD signals.

8. An amplifier according to any of the preceding claims when combined with an FDD amplifier.

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