Data packet transmission method and apparatus, and terminal device

Abstract

Disclosed in the present application are a data packet transmission method and apparatus, and a terminal device. The terminal device comprises a main controller, a hardware accelerator, a USB controll

Description

[0002] The present disclosure relates to the technical field of communication, and in particular to a data packet transmission method and apparatus, and a terminal device. BACKGROUND

[0003] At present, a smart phone has a function of providing Internet access to a Personal Computer (PC) through a Universal Serial Bus (USB) line. Connection and communication modes between devices are shown in FIG. 1. The smart phone is connected to a base station of an operator through a wireless communication technology (such as 5G, 4G, and the like) so as to access the Internet. In addition, the smart phone may share the ability to access the Internet with a device such as a PC that does not have the ability to access the Internet through a USB line, so that the device such as the PC has the ability to access the Internet. The smart phone serves as a bridge to build interaction between the PC and the base station of the operator. The smart phone acquires a network data packet from the base station of the operator through the wireless communication technology, and then transmits the network data packet to the PC through the USB line. Similarly, the smart phone acquires the network data packet from the PC through the USB line, and then transmits the network data packet to the base station of the operator through the wireless communication technology. In the process of uplink and downlink transmission of the network data packet, the conversion of data formats and the change in physical communication modes are involved.

[0004] As shown in FIG. 2, the communication link of the network data packet usually consists of a wireless communication module, a master controller (such as a Central Processing Unit (CPU)), and a USB controller inside the chip 10. The master controller, as an intermediate bridge between the wireless communication module and the USB controller, is responsible for operations such as parsing, re-encapsulation, and circulation of the network data packet. When the smart phone enables a USB function, the smart phone may register USB receive interrupts in a kernel i and wait for the USB receive interrupts to be triggered, and register USB transmit interrupts and wait for the data to be sent (a sending idle state). In the process of interaction between the smart phone and the PC, USB receive interrupts and USB transmit interrupts may occur. Specifically, USB receive interrupts may occur when the PC sends data to the Internet, and USB transmit interrupts may occur when the PC receives data from the Internet. Each interrupt may cause the kernel to trigger the context switch, stop the task that was originally being executed, and switch to USB receive interrupts or USB transmit interrupts to execute the task, thereby resulting in CPU resource consumption. In the process of network communication with a small bandwidth, a frequency of triggering interrupts is not high, and the number of interrupts is small, which has a little impact on the performance of the CPU. However, with the rapid growth of the communication bandwidth, large-bandwidth network communication leads to frequent USB interrupts, and a large number of USB interrupts may seriously affect the performance of the CPU, thereby affecting communication performance, and causing the communication rate to be much lower than the peak. At the same time, this may lead to an increase in CPU power consumption, thereby leading to severe overheating, shortening the battery life of the smart phone, and affecting the user experience. SUMMARY

[0005] The technical problem to be solved by the present disclosure is to overcome the defect that a large number of USB interrupts have an impact on the performance and power consumption of the master controller in the prior art, and provide a data packet transmission method and apparatus, and a terminal device.

[0006] The present disclosure solves the foregoing technical problem through the following technical solution.

[0007] A first aspect of the present disclosure provides a data packet transmission method, which is applied to a master controller in a terminal device, where the terminal device further includes a hardware accelerator, a Universal Serial Bus (USB) controller, and a wireless communication module, and the data packet transmission method includes the following step:

[0008] sending a first startup instruction to the hardware accelerator in response to connection with an external device through a USB interface; where the first startup instruction is used to instruct the hardware accelerator to parse and encapsulate a network data packet received by the USB controller, and transmit the encapsulated network data packet through the wireless communication module.

[0009] Optionally, the hardware accelerator includes a register module, a storage module, and a state machine, and prior to sending the first startup instruction to the hardware accelerator, the method further includes the following steps:

[0010] configuring the register module according to the USB controller; and

[0011] loading an instruction set that is set according to the USB controller into the storage module; where the state machine is configured to execute instructions in the instruction set.

[0012] Optionally, the data packet transmission method includes the following step: sending a second startup instruction to the USB controller in response to connection with the external device through the USB interface; where the second startup instruction is used to instruct to allow the USB controller to be identified by the external device.

[0013] Optionally, before the USB controller sends the second startup instruction, the method further includes the following steps:

[0014] initializing the USB controller; and

[0015] configuring a port that is in the USB controller and that is configured to communicate with the hardware accelerator.

[0016] Optionally, the data packet transmission method further includes the following step: sending a first stop instruction to the hardware accelerator in response to disconnection from the external device; where the first stop instruction is used to instruct the hardware accelerator to stop operation.

[0017] Optionally, the data packet transmission method further includes the following step: sending a first cleaning instruction to the hardware accelerator in response to disconnection from the external device; where the first cleaning instruction is used to instruct to clean data in the register module and the storage module.

[0018] Optionally, the data packet transmission method further includes the following step: sending a second stop instruction to the USB controller in response to disconnection from the external device; where the second stop instruction is used to instruct the USB controller to stop operation.

[0019] Optionally, the data packet transmission method further includes the following step: sending a second cleaning instruction to the USB controller in response to disconnection from the external device; where the second cleaning instruction is used to instruct to clean resources in the USB controller.

[0020] A second aspect of the present disclosure provides a data packet transmission method, which is applied to a hardware accelerator in a terminal device, where the terminal device further includes a master controller, a Universal Serial Bus (USB) controller, and a wireless communication module, and the data packet transmission method includes the following steps:

[0021] detecting whether the USB controller receives a network data packet in response to a first startup instruction sent by the master controller;

[0022] reading the network data packet from the USB controller in response to detecting that the USB controller receives the network data packet;

[0023] parsing and encapsulating the network data packet; and

[0024] transmitting the encapsulated network data packet through the wireless communication module.

[0025] Optionally, detecting whether the USB controller receives a network data packet specifically includes:

[0026] if the data read from a target register of the USB controller is consistent with the locally pre-stored data, detecting that the USB controller receives the network data packet, and otherwise, detecting that the USB controller fails to receive the network data packet.

[0027] A third aspect of the present disclosure provides a data packet transmission method, which is applied to a terminal device, where the terminal device includes a hardware accelerator, a master controller, a Universal Serial Bus (USB) controller, and a wireless communication module; and the data packet transmission method includes the following steps:

[0028] sending, by the master controller, a first startup instruction to the hardware accelerator in response to connection with an external device through a USB interface; and

[0029] detecting, by the hardware accelerator, whether the USB controller receives a network data packet in response to the first startup instruction, and when it is detected that the USB controller receives the network data packet, reading the network data packet from the USB controller, parsing and encapsulating the network data packet, and transmitting the encapsulated network data packet through the wireless communication module.

[0030] A fourth aspect of the present disclosure provides a data packet transmission apparatus, which is applied to a master controller in a terminal device, where the terminal device further includes a hardware accelerator, a Universal Serial Bus (USB) controller, and a wireless communication module, and the data packet transmission apparatus includes:

[0031] a first startup module, which is configured to send a first startup instruction to the hardware accelerator in response to connection with an external device through a USB interface; where the first startup instruction is used to instruct the hardware accelerator to parse and encapsulate a network data packet received by the USB controller, and transmit the encapsulated network data packet through the wireless communication module.

[0032] Optionally, the hardware accelerator includes a register module, a storage module, and a state machine. The data packet transmission apparatus further includes a first configuration module, which is configured to, prior to sending the first startup instruction to the hardware accelerator, configure the register module according to the USB controller; and load an instruction set that is set according to the USB controller into the storage module; where the state machine is configured to execute instructions in the instruction set.

[0033] Optionally, the data packet transmission apparatus further includes a second startup module, which is configured to send a second startup instruction to the USB controller in response to connection with the external device through the USB interface; where the second startup instruction is used to instruct to allow the USB controller to be identified by the external device.

[0034] Optionally, the data packet transmission apparatus further includes a second configuration module, which is configured to, before the USB controller sends the second startup instruction, initialize the USB controller; and configure a port that is in the USB controller and that is configured to communicate with the hardware accelerator.

[0035] Optionally, the data packet transmission apparatus further includes a first stop module, which is configured to send a first stop instruction to the hardware accelerator in response to disconnection from the external device; where the first stop instruction is used to instruct the hardware accelerator to stop operation.

[0036] Optionally, the data packet transmission apparatus further includes a first cleaning module, which is configured to send a first cleaning instruction to the hardware accelerator in response to disconnection from the external device; where the first cleaning instruction is used to instruct to clean data in the register module and the storage module.

[0037] Optionally, the data packet transmission apparatus further includes a second stop module, which is configured to send a second stop instruction to the USB controller in response to disconnection from the external device; where the second stop instruction is used to instruct the USB controller to stop operation.

[0038] Optionally, the data packet transmission apparatus further includes a second cleaning module, which is configured to send a second cleaning instruction to the USB controller in response to disconnection from the external device; where the second cleaning instruction is used to instruct to clean resources in the USB controller.

[0039] A fifth aspect of the present disclosure provides a data packet transmission apparatus, which is applied to a hardware accelerator in a terminal device, where the terminal device further includes a master controller, a Universal Serial Bus (USB) controller, and a wireless communication module, and the data packet transmission apparatus includes:

[0040] a detection module, which is configured to detect whether the USB controller receives a network data packet in response to a first startup instruction sent by the master controller;

[0041] a reading module, which is configured to read the network data packet from the USB controller in response to detecting that the USB controller receives the network data packet;

[0042] a processing module, which is configured to parse and encapsulate the network data packet; and

[0043] a transmission module, which is configured to transmit the encapsulated network data packet through the wireless communication module.

[0044] Optionally, the detection module is specifically configured to, if the data read from a target register of the USB controller is consistent with the locally pre-stored data, detect that the USB controller receives the network data packet, and otherwise, detect that the USB controller fails to receive the network data packet.

[0045] A sixth aspect of the present disclosure provides a data packet transmission apparatus, including a hardware accelerator, a master controller, a Universal Serial Bus (USB) controller, and a wireless communication module; where

[0046] the master controller is configured to send a first startup instruction to the hardware accelerator in response to connection with an external device through a USB interface; and

[0047] the hardware accelerator is configured to detect whether the USB controller receives a network data packet in response to the first startup instruction, and when it is detected that the USB controller receives the network data packet, read the network data packet from the USB controller, parse and encapsulate the network data packet, and transmit the encapsulated network data packet through the wireless communication module.

[0048] Optionally, the hardware accelerator includes a register module, a storage module, and a state machine. The master controller is further configured to, prior to sending the first startup instruction to the hardware accelerator, configure the register module according to the USB controller; and load an instruction set that is set according to the USB controller into the storage module; where the state machine is configured to execute instructions in the instruction set.

[0049] Optionally, the master controller is further configured to send a second startup instruction to the USB controller in response to connection with the external device through the USB interface; where the second startup instruction is used to instruct to allow the USB controller to be identified by the external device.

[0050] Optionally, the master controller is further configured to, before the USB controller sends the second startup instruction, initialize the USB controller; and configure a port that is in the USB controller and that is configured to communicate with the hardware accelerator.

[0051] Optionally, the master controller is further configured to send a first stop instruction to the hardware accelerator in response to disconnection from the external device; where the first stop instruction is used to instruct the hardware accelerator to stop operation.

[0052] Optionally, the master controller is further configured to send a first cleaning instruction to the hardware accelerator in response to disconnection from the external device; where the first cleaning instruction is used to instruct to clean data in the register module and the storage module.

[0053] Optionally, the master controller is further configured to send a second stop instruction to the USB controller in response to disconnection from the external device; where the second stop instruction is used to instruct the USB controller to stop operation.

[0054] Optionally, the master controller is further configured to send a second cleaning instruction to the USB controller in response to disconnection from the external device; where the second cleaning instruction is used to instruct to clean resources in the USB controller.

[0055] Optionally, the hardware accelerator is specifically configured to, if the data read from a target register of the USB controller is consistent with the locally pre-stored data, detect that the USB controller receives the network data packet, and otherwise, detect that the USB controller fails to receive the network data packet.

[0056] A seventh aspect of the present disclosure provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor, when executing the computer program, implements the data packet transmission method according to the first aspect or the second aspect.

[0057] An eighth aspect of the present disclosure provides a chip, which is applied to a terminal device, where the chip is configured to implement the data packet transmission method according to the first aspect or the second aspect.

[0058] A ninth aspect of the present disclosure provides a chip module, which is applied to a terminal device, where the chip module includes a chip, and the chip is configured to implement the data packet transmission method according to the first aspect or the second aspect.

[0059] A tenth aspect of the present disclosure provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements steps of the data packet transmission method according to the first aspect or the second aspect.

[0060] An eleventh aspect of the present disclosure provides a computer program product, including a computer program, where the computer program, when executed by a processor, implements steps of the data packet transmission method according to the first aspect or the second aspect.

[0061] On the basis of the common knowledge in the field, the foregoing optional conditions may be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0062] The positive and progressive effects of the present disclosure are as follows. The network data packet sent by the external device is received by the USB controller, and the network data packet is processed by the hardware accelerator. This communication link will no longer trigger USB receive interrupts, which may not cause the master controller to perform the context switch, and may eliminate an impact of a large number of USB receive interrupts on the performance and power consumption of the master controller, thereby improving the user experience of using the terminal device. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] FIG. 1 is a schematic diagram of connection and communication modes between a smart phone and a PC in the prior art.

[0064] FIG. 2 is a schematic diagram of a connection between a chip and an external device in the prior art.

[0065] FIG. 3 is a schematic diagram of a connection between a terminal device and an external device according to an embodiment of the present disclosure.

[0066] FIG 4 is a schematic structural diagram of a hardware accelerator according to Embodiment 1 of the present disclosure.

[0067] FIG. 5 is a flowchart of a method after a terminal device is connected with an external device according to Embodiment 1 of the present disclosure.

[0068] FIG. 6 is a flowchart of a method after a terminal device is disconnected from an external device according to Embodiment 1 of the present disclosure.

[0069] FIG. 7 is a flowchart of a data packet transmission method according to Embodiment 2 of the present disclosure.

[0070] FIG. 8 is a flowchart of a data packet transmission method according to Embodiment 3 of the present disclosure.

[0071] FIG. 9 is a schematic structural diagram of a terminal device according to Embodiment 4 of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0072] The present disclosure is further illustrated below by using embodiments, but it is not limited to the scope of the embodiments.

[0073] A terminal device in the embodiment of the present disclosure may refer to various forms such as User Equipment (UE), an access terminal, a user unit, a subscriber station, a mobile radio station, a Mobile Station (MS), a Mobile Terminal (MT), a remote station, a remote terminal, a mobile device, a user terminal, a wireless communication device, a user agent, or a user device. The terminal device may also be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Assistant, (PDA for short), a handheld device with a wireless communication function, a computer with a wireless transceiver function, a Virtual Reality (VR) terminal device, an Augmented Reality (AR) Terminal device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in smart home, a computing device, or other processing devices connected to a wireless modem, a vehicle-mounted device, a wearable device, a terminal device in the 5G network, or a terminal device in the future evolved Public Land Mobile Network (PLMN), which is not limited in the embodiment of the present disclosure.

[0074] The data packet transmission method according to the embodiment of the present disclosure can achieve the USB function, which may also be referred to as USB shared connection, allowing a user to share the network of the terminal device with an external device through a USB data line. The external device may be a PC, a notebook computer, and the like. It should be noted that when the data packet transmission method according to the embodiment of the present disclosure is used to achieve the USB function, there is no need to register USB receive interrupts and USB transmit interrupts in the kernel.

[0075] The data packet transmission method according to the embodiment of the present disclosure may be implemented by a data packet transmission apparatus. The data packet transmission apparatus may be implemented in the form of software and / or hardware. The data packet transmission apparatus may include part or all of the terminal device, which may be specifically a single chip, a chip module or a terminal device, or a chip or a chip module integrated in the terminal device.

[0076] Each module / unit included in the data packet transmission apparatus described in the embodiment of the present disclosure may be a software module / unit, a hardware module / unit, or partially a software module / unit and partially a hardware module / unit. For example, each module / unit contained in each device or product applied to or integrated in a chip may be implemented in the form of hardware such as a circuit, or at least some modules / units may be implemented in the form of a software program. The software program operates on the processor integrated in the chip, and the remaining modules / units may be implemented in the form of hardware such as a circuit. Each module / unit contained in each device or product applied to or integrated in a chip module may be implemented in the form of hardware such as a circuit. Different modules / units may be located in the same component (such as a chip and a circuit module) or different components of the chip module, or at least some modules / units may be implemented in the form of a software program. The software program operates on the processor integrated in the chip module, and the remaining modules / units may be implemented in the form of hardware such as a circuit. Each module / unit contained in each device or product applied to or integrated in a terminal device may be implemented in the form of hardware such as a circuit. Different modules / units may be located in the same component (such as a chip and a circuit module) or different components in the terminal device, or at least some modules / units may be implemented in the form of a software program. The software program operates on the processor integrated in the terminal device, and the remaining modules / units may be implemented in the form of hardware such as a circuit.

[0077] Embodiment 1

[0078] The data packet transmission method according to this embodiment may be implemented by a data packet transmission apparatus. The data packet transmission apparatus may be implemented in the form of software and / or hardware. The data packet transmission apparatus may include part or all of the master controller in the terminal device. As shown in FIG. 3, the terminal device 20 includes a master controller, a hardware accelerator, a USB controller, and a wireless communication module. The master controller is separately connected with the hardware accelerator, the USB controller, and the wireless communication module. The hardware accelerator is separately connected with the USB controller and the wireless communication module.

[0079] The data packet transmission method according to this embodiment is described below with the master controller in the terminal device as an execution subject. The data packet transmission method according to this embodiment may include the following step S11.

[0080] Sil, a first startup instruction is sent to the hardware accelerator in response to connection with an external device through a USB interface; where the first startup instruction is used to instruct the hardware accelerator to parse and encapsulate a network data packet received by the USB controller, and transmit the encapsulated network data packet through the wireless communication module.

[0081] Specifically, the USB controller in the terminal device may establish a connection with the external device through the USB interface. In a specific implementation, the hardware accelerator may transmit the encapsulated network data packet to a base station through the wireless communication module. The parsing operation may specifically refer to parsing a Remote Network Driver Interface Specification (RNDIS) protocol. The part about the RNDIS protocol in the network data packet is removed. The encapsulation operation may specifically refer to encapsulating the parsed network data packet according to the wireless communication protocol (that is, the protocol corresponding to the wireless communication module).

[0082] In this embodiment, the network data packet sent by the external device is received by the USB controller, and the uplink network data packet is processed by the hardware accelerator. This communication link will no longer trigger USB receive interrupts, which may not cause the master controller to perform the context switch, and may eliminate an impact of a large number of USB receive interrupts on the performance and power consumption of the master controller, thereby improving the user experience of using the terminal device.

[0083] In an optional implementation, the first startup instruction is also used to instruct the hardware accelerator to parse and encapsulate the network data packet received by the wireless communication module, and transmit the encapsulated network data packet through the USB controller.

[0084] In a specific implementation, the hardware accelerator may transmit the encapsulated network data packet to the external device through the USB controller. The parsing operation may specifically refer to parsing the wireless communication protocol (that is, the protocol corresponding to the wireless communication module). The part about the wireless communication protocol in the network data packet is removed. The encapsulation operation may specifically refer to encapsulating the parsed network data packet according to the RNDIS protocol.

[0085] In this implementation, the network data packet sent by the base station is received by the wireless communication module, and the downlink network data packet is processed by the hardware accelerator. This communication link will no longer trigger USB transmit interrupts, which may not cause the master controller to perform the context switch, and may eliminate an impact of a large number of USB transmit interrupts on the performance and power consumption of the master controller, thereby improving the user experience of using the terminal device.

[0086] In an optional implementation, as shown in FIG. 4, the hardware accelerator includes a register module, a storage module, and a state machine. In this implementation, prior to sending the first startup instruction to the hardware accelerator in step Sil, the following steps S101 to SI02 are further included.

[0087] Step S101, the register module is configured according to the USB controller.

[0088] In a specific implementation of step S101, an address of the register in the USB controller requiring operation by the hardware accelerator may be written into the register module, and a data address requiring operation by the hardware accelerator may also be written into the register module.

[0089] S102, an instruction set that is set according to the USB controller is loaded into the storage module; where the state machine is configured to execute instructions in the instruction set.

[0090] The register module includes a plurality of registers. Each register is configured to store data information, specifically, data information of initialization configuration, such as an address of the register in the USB controller, and temporary data information acquired by the state machine according to the instruction, such as a return value of the register in the USB controller.

[0091] The storage module is a readable and writable memory area, specifically, a Random Access Memory (RAM), a Cache, a Flash memory, and the like.

[0092] In a specific implementation, different instruction sets are set according to different USB controllers, in which the number of instructions in the instruction set, the execution order of instructions, the execution content of instructions, the length of instructions, and the like may be flexibly set. The execution content of instructions generally includes operations such as reading, writing, data saving, data comparison, and the like. In a specific example, each register has a length of 64 bits. Each instruction has a length fixed at 8 Bytes.

[0093] For example, the USB controller is a DWC3 controller (a USB 3.x controller), and an instruction set including the following instructions is set:

[0094] write the value of Reg 1 into DEPCMDPARO(l);

[0095] write the value of Reg2 into DEPCMDPAR1 (1);

[0096] write Reg3 to DEPCMDPAR2(1);

[0097] write the value of Reg4 into DEPCMD(l);

[0098] read the value of DEPCMD(l) and write the value into RegO; and

[0099] judge whether the data in RegO is equal to the data pre-stored in Reg5, if not, continue to read the value of DEPCMD(l); and if so, read the value of GEVNTCOUNT(l) and place the value into RegO.

[00100] Reg0, Regl, Reg 2, Reg 3, Reg4 and Reg5 are all registers in the register module of the hardware accelerator. DEPCMDPAR0, DEPCMDPAR1, DEPCMDPAR2, DEPCMD and GEVNTCOUNT are all registers in the DWC3 controller. In this example, the state machine sequentially reads the instructions in the instruction set to execute corresponding tasks. After reading the last instruction, if the returned result is Yes, it is detected that the DWC3 controller has received the network data packet, and subsequently, the state machine may parse, encapsulate and transmit the value of GEVNTCOUNT(l), that is, the network data packet.

[00101] In an optional implementation, the data packet transmission method further includes step SI2: sending a second startup instruction to the USB controller in response to connection with the external device through the USB interface; where the second startup instruction is used to instruct to allow the USB controller to be identified by the external device. In this implementation, allowing the USB controller to be identified by the external device means allowing the external device to enumerate the terminal device where the USB controller is located, that is, starting the USB controller. At this time, the external device may send a network data packet to the USB controller. The external device is equivalent to a USB host, and the terminal device where the USB controller is located is equivalent to a USB slave.

[00102] It should be noted that the execution order of the foregoing steps S12 and Silis not limited. The foregoing steps S12 and Sil may be executed at the same time, or the foregoing step Sil may be executed before the foregoing step SI2, or the foregoing step S12 may be executed before the foregoing step Sil.

[00103] In an optional implementation, before the USB controller sends the second startup instruction in step SI2, the following steps S201 to S202 are further included.

[00104] Step S201, the USB controller is initialized. Specifically, data requiring memory resources such as a global register, a port and an events in the USB controller may be initialized.

[00105] Step S202, a port that is in the USB controller and that is configured to communicate with the hardware accelerator is configured. After configuring the port, the hardware accelerator performs data communication with the USB controller through the port.

[00106] In an optional implementation, in order to reduce the power consumption of the hardware accelerator, the data packet transmission method further includes step S13: sending a first stop instruction to the hardware accelerator in response to disconnection from the external device; where the first stop instruction is used to instruct the hardware accelerator to stop operation. In this implementation, after the USB connection between the terminal device and the external device is disconnected, the operation of the hardware accelerator is stopped. Specifically, the operation of the state machine is stopped, and the state machine is restored to the initial state.

[00107] In an optional implementation, the data packet transmission method further includes step S14: sending a first cleaning instruction to the hardware accelerator in response to disconnection from the external device; where the first cleaning instruction is used to instruct to clean data in the register module and the storage module. In this implementation, after the USB connection between the terminal device and the external device is disconnected, the data in the hardware accelerator is cleaned, including the data stored in the register module and the storage module.

[00108] In an optional implementation, in order to reduce the power consumption of the USB controller, the data packet transmission method further includes step SI5: sending a second stop instruction to the USB controller in response to disconnection from the external device; where the second stop instruction is used to instruct the USB controller to stop operation. In the specific implementation, it is also necessary to clean the resources that prevent the USB controller from stopping operation in advance. Taking the DWC3 controller as an example, the value of GEVNTCOUNT(l) is set to 0, and all ports are prohibited from data transmission. In this implementation, the operation of the USB controller is stopped after the USB connection between the terminal device and the external device is disconnected.

[00109] In an optional implementation, the data packet transmission method further includes step SI6: sending a second cleaning instruction to the USB controller in response to disconnection from the external device; where the second cleaning instruction is used to instruct to clean resources in the USB controller. In this implementation, after the USB connection between the terminal device and the external device is disconnected, the resources in the USB controller are cleaned, which may specifically include releasing the memory occupied resources such as events, cleaning the data in the register, and the like.

[00110] It should be noted that after the USB connection between the terminal device and the external device is disconnected, if the data in the hardware accelerator is not cleaned, the foregoing steps S101 and SI02 need only be executed once without being executed repeatedly. After the USB connection between the terminal device and the external device is disconnected, if the resources in the USB controller are not cleaned, the foregoing steps S201 and S202 need only be executed once without being executed repeatedly.

[00111] FIG. 5 is a flowchart of a method after a terminal device is connected with an external device. As shown in FIG. 5, in response to connection between the terminal device and the external device through the USB interface, the register module in the hardware accelerator is configured, the set instruction set is loaded into the storage module in the hardware accelerator, and the hardware accelerator is started by sending the first startup instruction. In response to the connection between the terminal device and the external device through the USB interface, the USB controller is initialized, a port is configured, and the USB controller is started by sending the second startup instruction.

[00112] FIG. 6 is a flowchart of a method after a terminal device is disconnected from an external device. As shown in FIG. 6, in response to disconnection of the terminal device from the external device, a first stop instruction and a first cleaning instruction are sent to the hardware accelerator to stop the operation of the hardware accelerator and clean the data in the hardware accelerator. In response to disconnection of the terminal device from the external device, a second stop instruction and a second cleaning instruction are sent to the USB controller to stop the operation of the USB controller and clean the resources in the USB controller.

[00113] This embodiment further provides a data packet transmission apparatus, which is applied to a master controller in a terminal device. The terminal device further includes a hardware accelerator, a USB controller, and a wireless communication module. The data packet transmission apparatus includes a first startup module, which is configured to send a first startup instruction to the hardware accelerator in response to connection with an external device through a USB interface; where the first startup instruction is used to instruct the hardware accelerator to parse and encapsulate a network data packet received by the USB controller, and transmit the encapsulated network data packet through the wireless communication module.

[00114] In an optional implementation, the hardware accelerator includes a register module, a storage module, and a state machine. The data packet transmission apparatus further includes a first configuration module, which is configured to, prior to sending the first startup instruction to the hardware accelerator, configure the register module according to the USB controller; and load an instruction set that is set according to the USB controller into the storage module; where the state machine is configured to execute instructions in the instruction set.

[00115] In an optional implementation, the data packet transmission apparatus further includes a second startup module, which is configured to send a second startup instruction to the USB controller in response to connection with the external device through the USB interface; where the second startup instruction is used to instruct to allow the USB controller to be identified by the external device.

[00116] In an optional implementation, the data packet transmission apparatus further includes a second configuration module, which is configured to, before the USB controller sends the second startup instruction, initialize the USB controller; and configure a port that is in the USB controller and that is configured to communicate with the hardware accelerator.

[00117] In an optional implementation, the data packet transmission apparatus further includes a first stop module, which is configured to send a first stop instruction to the hardware accelerator in response to disconnection from the external device; where the first stop instruction is used to instruct the hardware accelerator to stop operation.

[00118] In an optional implementation, the data packet transmission apparatus further includes a first cleaning module, which is configured to send a first cleaning instruction to the hardware accelerator in response to disconnection from the external device; where the first cleaning instruction is used to instruct to clean data in the register module and the storage module.

[00119] In an optional implementation, the data packet transmission apparatus further includes a second stop module, which is configured to send a second stop instruction to the USB controller in response to disconnection from the external device; where the second stop instruction is used to instruct the USB controller to stop operation.

[00120] In an optional implementation, the data packet transmission apparatus further includes a second cleaning module, which is configured to send a second cleaning instruction to the USB controller in response to disconnection from the external device; where the second cleaning instruction is used to instruct to clean resources in the USB controller.

[00121] Embodiment 2

[00122] FIG. 7 is a flowchart of a data packet transmission method according to this embodiment. The data packet transmission method according to this embodiment may be implemented by a data packet transmission apparatus. The data packet transmission apparatus may be implemented in the form of software and / or hardware. The data packet transmission apparatus may include part or all of the hardware accelerator in the terminal device. As shown in FIG. 3, the terminal device 20 includes a master controller, a hardware accelerator, a USB controller, and a wireless communication module. The master controller is separately connected with the hardware accelerator, the USB controller, and the wireless communication module. The hardware accelerator is separately connected with the USB controller and the wireless communication module. It should be noted that the master controller is configured to implement the data packet transmission method in Embodiment 1.

[00123] The data packet transmission method according to this embodiment is described below with the hardware accelerator in the terminal device as an execution subject. As shown in FIG. 7, the data packet transmission method according to this embodiment may include the following steps S21 to S24.

[00124] Step S21, it is detected whether the USB controller receives a network data packet in response to a first startup instruction sent by the master controller. The master controller sends a first startup instruction to the hardware accelerator in response to connection with an external device through a USB interface.

[00125] Step S22, the network data packet is read from the USB controller in response to detecting that the USB controller receives the network data packet.

[00126] Step S23, the network data packet is parsed and encapsulated. The parsing operation may specifically refer to parsing the RNDIS protocol. The part about the RNDIS protocol in the network data packet is removed. The encapsulation operation may specifically refer to encapsulating the parsed network data packet according to the wireless communication protocol (that is, the protocol corresponding to the wireless communication module).

[00127] Step S24, the encapsulated network data packet is transmitted through the wireless communication module. In a specific implementation, the hardware accelerator may transmit the encapsulated network data packet to the base station through the wireless communication module.

[00128] In this embodiment, the network data packet sent by the external device is received by the USB controller, and the network data packet is processed by the hardware accelerator after the master controller starts the hardware accelerator. This communication link will no longer trigger USB receive interrupts, which may not cause the master controller to perform the context switch, and may eliminate an impact of a large number of USB receive interrupts on the performance and power consumption of the master controller, thereby improving the user experience of using the terminal device.

[00129] In an optional implementation, in response to the first startup instruction sent by the master controller, the hardware accelerator parses and encapsulates the network data packet received by the wireless communication module, and transmits the encapsulated network data packet through the USB controller. In a specific implementation, the hardware accelerator may transmit the encapsulated network data packet to the external device through the USB controller. The parsing operation may specifically refer to parsing the wireless communication protocol (that is, the protocol corresponding to the wireless communication module). The part about the wireless communication protocol in the network data packet is removed. The encapsulation operation may specifically refer to encapsulating the parsed network data packet according to the RNDIS protocol.

[00130] In this implementation, the network data packet sent by the base station is received by the wireless communication module, and the downlink network data packet is processed by the hardware accelerator after the master controller starts the hardware accelerator. This communication link will no longer trigger USB transmit interrupts, which may not cause the master controller to perform the context switch, and may eliminate an impact of a large number of USB transmit interrupts on the performance and power consumption of the master controller, thereby improving the user experience of using the terminal device.

[00131] In an optional implementation, the foregoing step S21 specifically includes: if the data read from a target register of the USB controller is consistent with the locally pre-stored data, detecting that the USB controller receives the network data packet, and otherwise, detecting that the USB controller fails to receive the network data packet.

[00132] In a specific implementation, the hardware accelerator includes a register module, a storage module, and a state machine. The master controller may, prior to sending the first startup instruction to the hardware accelerator, configure the register module according to the USB controller; and load an instruction set that is set according to the USB controller into the storage module; where the state machine is configured to execute instructions in the instruction set.

[00133] The master controller may write an address of the register in the USB controller requiring operation by the hardware accelerator into the register module, and may also write a data address requiring operation by the hardware accelerator into the register module. The register module includes a plurality of registers. Each register is configured to store data information, specifically, data information of initialization configuration, such as an address of the register in the USB controller, and temporary data information acquired by the state machine according to the instruction, such as a return value of the register in the USB controller. The storage module is a readable and writable memory area, specifically, a Random Access Memory (RAM), a Cache, a Flash memory, and the like.

[00134] In a specific implementation, different instruction sets are set according to different USB controllers, in which the number of instructions in the instruction set, the execution order of instructions, the execution content of instructions, the length of instructions, and the like may be flexibly set. The execution content of instructions generally includes operations such as reading, writing, data saving, data comparison, and the like. In a specific example, each register has a length of 64 bits. Each instruction has a length fixed at 8 Bytes.

[00135] For example, the USB controller is a DWC3 controller (a USB 3.x controller), and an instruction set including the following instructions is set:

[00136] write the value of Regl into DEPCMDPARO(l);

[00137] write the value of Reg2 into DEPCMDPARl(l);

[00138] write Reg3 to DEPCMDPAR2(1);

[00139] write the value of Reg4 into DEPCMD(l);

[00140] read the value of DEPCMD(l) and write the value into RegO; and

[00141] judge whether the data in RegO is equal to the data pre-stored in Reg5, if not, continue to read the value of DEPCMD(l); and if so, read the value of GEVNTCOUNT(l) and place the value into RegO.

[00142] Reg0, Regl, Reg 2, Reg 3, Reg4 and Reg5 are all registers in the register module of the hardware accelerator. DEPCMDPAR0, DEPCMDPAR1, DEPCMDPAR2, DEPCMD and GEVNTCOUNT are all registers in the DWC3 controller. In this example, the state machine sequentially reads the instructions in the instruction set to execute corresponding tasks. After reading the last instruction, if the returned result is Yes, it is detected that the DWC3 controller has received the network data packet, and subsequently, the state machine may parse, encapsulate and transmit the value of GEVNTCOUNT(l), that is, the network data packet.

[00143] This embodiment further provides a data packet transmission apparatus, which is applied to a hardware accelerator in terminal device. The data packet transmission apparatus includes a detection module, a reading module, a processing module, and a transmission module. The detection module is configured to detect whether the USB controller receives a network data packet in response to a first startup instruction sent by the master controller. The reading module is configured to read the network data packet from the USB controller in response to detecting that the USB controller receives the network data packet. The processing module is configured to parse and encapsulate the network data packet. The transmission module is configured to transmit the encapsulated network data packet through the wireless communication module.

[00144] In an optional implementation, the detection module is specifically configured to, if the data read from a target register of the USB controller is consistent with the locally pre-stored data, detect that the USB controller receives the network data packet, and otherwise, detect that the USB controller fails to receive the network data packet.

[00145] Embodiment 3

[00146] The data packet transmission method according to this embodiment is applied to a terminal device. As shown in FIG. 3, the terminal device 20 includes a master controller, a hardware accelerator, a USB controller, and a wireless communication module. The master controller is separately connected with the hardware accelerator, the USB controller, and the wireless communication module. The hardware accelerator is separately connected with the USB controller and the wireless communication module.

[00147] As shown in FIG. 8, the data packet transmission method according to this embodiment may include the following steps S31 to S32.

[00148] Step S31, the master controller sends a first startup instruction to the hardware accelerator in response to connection with an external device through a USB interface. Specifically, the USB controller in the terminal device may establish a connection with the external device through the USB interface.

[00149] Step S32, the hardware accelerator detects whether the USB controller receives a network data packet in response to the first startup instruction, and when it is detected that the USB controller receives the network data packet, reads the network data packet from the USB controller, parses and encapsulates the network data packet, and transmits the encapsulated network data packet through the wireless communication module.

[00150] In a specific implementation, the hardware accelerator may transmit the encapsulated network data packet to a base station through the wireless communication module. The parsing operation may specifically refer to parsing the RNDIS protocol. The part about the RNDIS protocol in the network data packet is removed. The encapsulation operation may specifically refer to encapsulating the parsed network data packet according to the wireless communication protocol (that is, the protocol corresponding to the wireless communication module).

[00151] In this embodiment, the network data packet sent by the external device is received by the USB controller, and the uplink network data packet is processed by the hardware accelerator after the master controller starts the hardware accelerator. This communication link will no longer 19 trigger USB receive interrupts, which may not cause the master controller to perform the context switch, and may eliminate an impact of a large number of USB receive interrupts on the performance and power consumption of the master controller, thereby improving the user experience of using the terminal device.

[00152] In an optional implementation, in response to the first startup instruction sent by the master controller, the hardware accelerator parses and encapsulates the network data packet received by the wireless communication module, and transmits the encapsulated network data packet through the USB controller. In a specific implementation, the hardware accelerator may transmit the encapsulated network data packet to the external device through the USB controller. The parsing operation may specifically refer to parsing the wireless communication protocol (that is, the protocol corresponding to the wireless communication module). The part about the wireless communication protocol in the network data packet is removed. The encapsulation operation may specifically refer to encapsulating the parsed network data packet according to the RNDIS protocol.

[00153] In this implementation, the network data packet sent by the base station is received by the wireless communication module, and the downlink network data packet is processed by the hardware accelerator after the master controller starts the hardware accelerator. This communication link will no longer trigger USB transmit interrupts, which may not cause the master controller to perform the context switch, and may eliminate an impact of a large number of USB transmit interrupts on the performance and power consumption of the master controller, thereby improving the user experience of using the terminal device.

[00154] It should be noted that for the steps implemented by the master controller and the hardware accelerator in this embodiment and the corresponding effects, refer to the foregoing Embodiments 1 and 2.

[00155] This embodiment further provides a data packet transmission apparatus, including a hardware accelerator, a master controller, a USB controller, and a wireless communication module. The master controller is configured to send a first startup instruction to the hardware accelerator in response to connection with an external device through a USB interface. The hardware accelerator is configured to detect whether the USB controller receives a network data packet in response to the first startup instruction, and when it is detected that the USB controller receives the network data packet, read the network data packet from the USB controller, parse and encapsulate the network data packet, and transmit the encapsulated network data packet through the wireless communication module.

[00156] In an optional implementation, the hardware accelerator includes a register module, a storage module, and a state machine. The master controller is further configured to, prior to sending the first startup instruction to the hardware accelerator, configure the register module according to the USB controller; and load an instruction set that is set according to the USB controller into the storage module; where the state machine is configured to execute instructions in the instruction set.

[00157] In an optional implementation, the master controller is further configured to send a second startup instruction to the USB controller in response to connection with the external device through the USB interface; where the second startup instruction is used to instruct to allow the USB controller to be identified by the external device.

[00158] In an optional implementation, the master controller is further configured to, before the USB controller sends the second startup instruction, initialize the USB controller; and configure a port that is in the USB controller and that is configured to communicate with the hardware accelerator.

[00159] In an optional implementation, the master controller is further configured to send a first stop instruction to the hardware accelerator in response to disconnection from the external device; where the first stop instruction is used to instruct the hardware accelerator to stop operation.

[00160] In an optional implementation, the master controller is further configured to send a first cleaning instruction to the hardware accelerator in response to disconnection from the external device; where the first cleaning instruction is used to instruct to clean data in the register module and the storage module.

[00161] In an optional implementation, the master controller is further configured to send a second stop instruction to the USB controller in response to disconnection from the external device; where the second stop instruction is used to instruct the USB controller to stop operation.

[00162] In an optional implementation, the master controller is further configured to send a second cleaning instruction to the USB controller in response to disconnection from the external device; where the second cleaning instruction is used to instruct to clean resources in the USB controller.

[00163] In an optional implementation, the hardware accelerator is specifically configured to, if the data read from a target register of the USB controller is consistent with the locally pre-stored data, detect that the USB controller receives the network data packet, and otherwise, detect that the USB controller fails to receive the network data packet.

[00164] Embodiment 4

[00165] FIG. 9 is a schematic structural diagram of a terminal device according to this embodiment. The terminal device includes at least one processor and a memory in communication with the at least one processor. The memory stores a computer program executable by the at least one processor. The computer program is executed by the at least one processor, so that the at least one processor can implement the data packet transmission method in Embodiment 1 or Embodiment 2. In one example, the processor is the foregoing master controller, and can implement the data packet transmission method in Embodiment 1. In another example, the processor is the foregoing hardware accelerator, and can implement the data packet transmission method in Embodiment 2. The terminal device 3 shown in FIG. 9 is just an example, which should not bring any restrictions on the function and the application scope of the embodiment of the present disclosure.

[00166] The component of the terminal device 3 may include, but is not limited to, the foregoing at least one processor 4, the foregoing at least one memory 5, and a bus 6 connecting different system components (including the memory 5 and the processor 4).

[00167] The bus 6 includes a data bus, an address bus, and a control bus.

[00168] The memory 5 may include a volatile memory, such as a Random Access Memory (RAM) 51 and / or a cache 52, and may further include a Read-Only Memory (ROM) 53.

[00169] The memory 5 may further include a program / utility 55 with a set of (at least one) program modules 54. Such program modules 54 include, but are not limited to, an operating system, one or more application programs, other program modules and program data. Each or some combination of these examples may include the implementation of a network environment.

[00170] The processor 4 executes various functional applications and data processing by operating the computer program stored in the memory 5, such as the foregoing data packet transmission method.

[00171] The terminal device 3 may also communicate with one or more external devices 7 (such as keyboards, pointing devices, and the like). The communication may be made through an input / output (I / O) interface 8. Moreover, the terminal device 3 may also communicate with one or more networks (for example, a Local Area Network (LAN), a Wide Area Network (WAN) and / or a Public Network, such as the Internet) through a network adapter 9. As shown in FIG. 9, the network adapter 9 communicates with other modules of the terminal device 3 through the bus 6. It should be understood that although not shown in FIG. 9, other hardware and / or software modules may be used in conjunction with the terminal device 3, including but not limited to a microcode, a device driver, a redundant processor, an external disk drive array, a Redundant Array of Independent Disks (RAID) system, a tape drive, a data backup storage system, and the like.

[00172] It should be noted that although several units / modules or sub-uni ts / modules of the terminal device are mentioned in the foregoing detailed description, this division is merely exemplary and not mandatory. In fact, according to the implementation of the present disclosure, the features and functions of two or more units / modules described above may be embodied in one unit / module. On the contrary, the features and functions of one unit / module described above may be further divided to be embodied by a plurality of units / modules.

[00173] Embodiment 5

[00174] This embodiment provides a computer-readable storage medium, on which a computer program is stored. The computer program, when executed by a processor, implements steps of the data packet transmission method in Embodiment 1 or Embodiment 2.

[00175] The computer-readable storage medium may include but not limited to: a portable disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device, or any suitable combination of the above.

[00176] In a possible implementation, the present disclosure may also be implemented in the form of a computer program product, which includes a computer program. The computer program, when executed by a processor, implements steps of the data packet transmission method in Embodiment 1 or Embodiment 2.

[00177] A computer program for executing the present disclosure may be written in any combination of one or more programming languages. The computer program may be completely executed on a terminal device, partially executed on a terminal device, executed as an independent software package, partially executed on a terminal device and partially executed on a remote device, or completely executed on a remote device.

[00178] Although the specific implementations of the present disclosure have been described above, it should be understood by those skilled in the art that this is only an example. The protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make many changes or modifications to these implementations without departing from the principle and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

WHAT IS CLAIMED IS:

1. A data packet transmission method, which is applied to a master controller in a terminal device, wherein the terminal device further comprises a hardware accelerator, a Universal Serial Bus (USB) controller, and a wireless communication module, and the data packet transmission method comprises the following step:sending a first startup instruction to the hardware accelerator in response to connection with an external device through a USB interface; wherein the first startup instruction is used to instruct the hardware accelerator to parse and encapsulate a network data packet received by the USB controller, and transmit the encapsulated network data packet through the wireless communication module.

2. The data packet transmission method according to claim 1, wherein the hardware accelerator comprises a register module, a storage module, and a state machine, and prior to sending the first startup instruction to the hardware accelerator, the method further comprises the following steps:configuring the register module according to the USB controller; andloading an instruction set that is set according to the USB controller into the storage module; wherein the state machine is configured to execute instructions in the instruction set.

3. The data packet transmission method according to claim 1, wherein the data packet transmission method comprises the following step:sending a second startup instruction to the USB controller in response to connection with the external device through the USB interface; wherein the second startup instruction is used to instruct to allow the USB controller to be identified by the external device.

4. The data packet transmission method according to claim 3, wherein before the USB controller sends the second startup instruction, the method further comprises the following steps:initializing the USB controller; andconfiguring a port that is in the USB controller and that is configured to communicate with the hardware accelerator.

5. The data packet transmission method according to claim 1, wherein the data packet transmission method further comprises the following step:sending a first stop instruction to the hardware accelerator in response to disconnection from the external device; wherein the first stop instruction is used to instruct the hardware accelerator to stop operation.

6. The data packet transmission method according to claim 2, wherein the data packet transmission method further comprises the following step:sending a first cleaning instruction to the hardware accelerator in response to disconnection from the external device; wherein the first cleaning instruction is used to instruct to clean data in the register module and the storage module.

7. The data packet transmission method according to claim 3, wherein the data packet transmission method further comprises the following step:sending a second stop instruction to the USB controller in response to disconnection from the external device; wherein the second stop instruction is used to instruct the USB controller to stop operation.

8. The data packet transmission method according to claim 4, wherein the data packet transmission method further comprises the following step:sending a second cleaning instruction to the USB controller in response to disconnection from the external device; wherein the second cleaning instruction is used to instruct to clean resources in the USB controller.

9. A data packet transmission method, which is applied to a hardware accelerator in a terminal device, wherein the terminal device further comprises a master controller, a Universal Serial Bus (USB) controller, and a wireless communication module, and the data packet transmission method comprises the following steps:detecting whether the USB controller receives a network data packet in response to a first startup instruction sent by the master controller;reading the network data packet from the USB controller in response to detecting that the USB controller receives the network data packet;parsing and encapsulating the network data packet; andtransmitting the encapsulated network data packet through the wireless communication module.

10. The data packet transmission method according to claim 9, wherein detecting whether the USB controller receives a network data packet specifically comprises:if the data read from a target register of the USB controller is consistent with the locally prestored data, detecting that the USB controller receives the network data packet, and otherwise, detecting that the USB controller fails to receive the network data packet.

11. A data packet transmission method, which is applied to a terminal device, wherein the terminal device comprises a hardware accelerator, a master controller, a Universal Serial Bus (USB) controller, and a wireless communication module; and the data packet transmission methodcomprises the following steps:sending, by the master controller, a first startup instruction to the hardware accelerator in response to connection with an external device through a USB interface; anddetecting, by the hardware accelerator, whether the USB controller receives a network data packet in response to the first startup instruction, and when it is detected that the USB controller receives the network data packet, reading the network data packet from the USB controller, parsing and encapsulating the network data packet, and transmitting the encapsulated network data packet through the wireless communication module.

12. A data packet transmission apparatus, which is applied to a master controller in a terminal device, wherein the terminal device further comprises a hardware accelerator, a Universal Serial Bus (USB) controller, and a wireless communication module, and the data packet transmission apparatus comprises:a first startup module, which is configured to send a first startup instruction to the hardware accelerator in response to connection with an external device through a USB interface; wherein the first startup instruction is used to instruct the hardware accelerator to parse and encapsulate a network data packet received by the USB controller, and transmit the encapsulated network data packet through the wireless communication module.

13. A data packet transmission apparatus, which is applied to a hardware accelerator in a terminal device, wherein the terminal device further comprises a master controller, a Universal Serial Bus (USB) controller, and a wireless communication module, and the data packet transmission apparatus comprises:a detection module, which is configured to detect whether the USB controller receives a network data packet in response to a first startup instruction sent by the master controller;a reading module, which is configured to read the network data packet from the USB controller in response to detecting that the USB controller receives the network data packet;a processing module, which is configured to parse and encapsulate the network data packet; anda transmission module, which is configured to transmit the encapsulated network data packet through the wireless communication module.

14. A data packet transmission apparatus, comprising a hardware accelerator, a master controller, a Universal Serial Bus (USB) controller, and a wireless communication module; whereinthe master controller is configured to send a first startup instruction to the hardware accelerator in response to connection with an external device through a USB interface; andthe hardware accelerator is configured to detect whether the USB controller receives a network data packet in response to the first startup instruction, and when it is detected that the USB controller receives the network data packet, read the network data packet from the USB controller, parse and encapsulate the network data packet, and transmit the encapsulated network data packet through the wireless communication module.

15. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the data packet transmission method according to any one of claims 1 to 10.

16. A chip, which is applied to a terminal device, wherein the chip is configured to implement the data packet transmission method according to any one of claims 1 to 10.

17. A chip module, which is applied to a terminal device, wherein the chip module comprises a chip, and the chip is configured to implement the data packet transmission method according to any one of claims 1 to 10.

18. A computer-readable storage medium, on which a computer program is stored, wherein the computer program, when executed by a processor, implements steps of the data packet transmission method according to any one of claims 1 to 10.

19. A computer program product, comprising a computer program, wherein the computer program, when executed by a processor, implements steps of the data packet transmission method according to any one of claims 1 to 10.PCT / CN2024 / 137496A. CLASSIFICATION OF SUBJECT MATTERH04L12 / 02(2006.01)i; G06F13 / 38(2006.01)iAccording to International Patent Classification (IPC) or to both national classification and IPCB. FIELDS SEARCHEDMinimum documentation searched (classification system followed by classification symbols) I PC: 11041. H04W G06FDocumentation searched other than minimum documentation to the extent that such documents are included in the fields searchedElectronic data base consulted during the international search (name of data base and, where practicable, search terms used)CNTXT, ENTXT, ENTXTC, TWTXT, VEN: ¢0, ¢^, iM Wf JO,®f, , cable+, USB, lighting, Hardware, Accelerat+, CPU, GPU, interrupt, registerDOCUMENTS CONSIDERED TO BE RELEVANTCategory* Citation of document, with indication, where appropriate, of the relevant passages Relevant to claim No. X CN 103678244 A (ZHOU SONG) 26 March 2014 (2014-03-26) description, paragraphs [0034]-[0040], and figure 3 1,9,11-19 PX A CN 118574109 A (XIAMEN ZIGUANG ZHANRUI TECHNOLOGY CO., LTD.) 30 August 2024 (2024-08-30) claims 1-19 CN 116232779 A (WUXI MUCHUANG INTEGRATED CIRCUIT DESIGN CO., LTD.) 06 June 2023 (2023-06-06) entire document 1-19 1-19 A TW 200823671 A (VIA TECHNOLOGIES, INC.) 01 June 2008 (2008-06-01) entire document 1-19| | Further documents are listed in the continuation of Box C. | J | See patent family annex.* Special categories of cited documents: “T” later document published after the international filing date or priority “A” document defining the general state of the art which is not considered date and not in conflict with the application but cited to understand the to be of particular- relevance principle or theory underlying the invention “D” document cited by the applicant in the international application “X” document of particular- relevance; the claimed invention cannot be “E” earlier application orpatent but published on or after the international considered novel or cannot be considered to involve an inventive step filing date when the document is taken alone “L” document which may throw doubts on priority claim(s) or which is “Y” document of particular relevance; the claimed invention cannot be cited to establish the publication date of another citation or other considered to involve an inventive step when the document is special reason (as specified) combined with one or more other such documents, such combination “O” document referring to an oral disclosure, use, exhibition or other being obvious to a person skilled in the art means document member of the same patent family “P” document published prior to the international filing date but later than the priority date claimed Date of the actual completion of the international search 13 February 2025 Date of mailing of the international search report 01 March 2025 Name and mailing address of the ISA / CN China National Intellectual Property Administration (ISA / CN) China No. 6, Xitucheng Road, Jimenqiao, Haidian District, Beijing 100088 Authorized officer Telephone No.Form PCT / ISA / 210 (second sheet) (July 2022)INTERNATIONAL SEARCH REPORT Information on patent family membersInternational application No.PCT / CN2024 / 137496Patent document cited in search report Publication date (day / month / year) Patent family member, s) Publication date (day / month / year) CN 103678244 A 26 March 2014 US 2014075063 Al 13 March 2014 US 10176133 B2 08 January 2019 CN 103678244 B 05 September 2017 CN 118574109 A 30 August 2024 None CN 116232779 A 06 June 2023 None TW 200823671 A 01 June 2008 TWI 356307 B 11 January 2012 CN 101136001 A 05 March 2008 CN 10051199 C 08 July 2009 US 2008126611 Al 29 May 2008 US 7702820 B2 20 April 2010

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