Multiplication of sparse matrix and a dense matrix to determine an output matrix on a processing unit
The described processing unit efficiently multiplies sparse and dense matrices by allocating threads to output matrix sections and using specialized caches, addressing inefficiencies in existing technologies and reducing latency and power consumption.
Patent Information
- Authority / Receiving Office
- GB · GB
- Patent Type
- Applications
- Current Assignee / Owner
- IMAGINATION TECH LTD
- Filing Date
- 2025-08-01
- Publication Date
- 2026-07-01
AI Technical Summary
Existing processing units face inefficiencies in performing matrix multiplications, particularly when dealing with sparse and dense matrices, leading to increased processing latency, power consumption, and memory bandwidth requirements.
A processing unit is configured with an execution module and caches to efficiently multiply sparse and dense matrices by allocating threads to sections of the output matrix, utilizing a sellpack format for sparse matrix data and a texture cache for dense matrix access, allowing for vectorized operations and element-wise addition of multiplication results.
This approach reduces processing latency, power consumption, and memory bandwidth by optimizing the matrix multiplication process, especially for sparse-dense matrix operations common in neural networks.
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Abstract
Citation Information
Patent Citations
Apparatus and method for matrix computation
US20190266217A1