A method of adding binary strings and a circuit therefor
Patent Information
- Authority / Receiving Office
- HK · HK
- Patent Type
- Patents
- Current Assignee / Owner
- 林志华
- Filing Date
- 2025-12-03
- Publication Date
- 2026-07-10
AI Technical Summary
Existing binary adders propagate carries inefficiently, leading to errors and performance issues in binary addition operations.
A method to format binary strings by rearranging zero and non-zero bits to eliminate carry propagation, implemented using fixed logic circuitry, and an adder design with multiple circuits to add pairs of binary substrings.
The method effectively prevents carry propagation, reducing errors and enhancing the accuracy and efficiency of binary addition operations.
Smart Images
Figure 00000001_0000 
Figure 00000001_0001 
Figure 00000002_0000
Description
This method eliminates carry effects from the upstream adder by splitting a binary string into pairs of binary substrings and formatting these substrings by rearranging the zero and non-zero bits. This formatting method eliminates carry before it propagates. The transformation process removes all adjacent non-zero bits from the substrings, ensuring that there is at least one zero bit between every two non-zero bits. Any carry resulting from the addition of addends is captured by the zero bit at the next position and is not propagated. Other formatting conditions include: the sum of the formatted substrings equals the value of the binary string; and for any corresponding position in the formatted substring pair, the values cannot both be non-zero. This method is implemented using fixed logic circuitry. The invention also discloses an adder for binary strings comprising multiple adder circuits arranged such that each adder circuit simultaneously adds bits at corresponding positions in a pair of binary substrings with other adder circuits.