Successive approximation analog-to-digital converter

Abstract

The application provides a successive approximation type analog-digital converter, which comprises a first switch and a second switch, a first capacitor array type digital-analog converter, a second capacitor array type digital-analog converter, a successive approximation logic module which outputs a multi-bit digital signal, a comparator, a first input end of the comparator being connected with an output end of the first capacitor array type digital-analog converter through the first switch, and a second input end of the comparator being connected with an output end of the second capacitor array type digital-analog converter through the second switch, a first pre-charge circuit which works before the first switch is turned on and charges the first input end of the comparator based on an output voltage of the first capacitor array type digital-analog converter, and a second pre-charge circuit which works before the second switch is turned on and charges the second input end of the comparator based on an output voltage of the second capacitor array type digital-analog converter. In this way, the amount of charge loss can be reduced, and the precision of the successive approximation type analog-digital converter is improved.

Description

[Technical Field]

[0001] This invention relates to the field of analog-to-digital converters, and particularly to a successive approximation analog-to-digital converter. [Background Technology]

[0002] Analog-to-digital converters (ADCs) are widely used in the electronics field. Successive approximation register (SAR) ADCs are a common type of ADC. A successive approximation ADC typically includes one or more digital-to-analog converters (DACs). These DACs usually come in two forms: resistor arrays and capacitor arrays. Resistor array DACs consume quiescent current, while capacitor array DACs do not. Therefore, in some low-power applications, capacitor array DACs are often used.

[0003] For a detailed explanation of the principles and specifications of SAR ADCs, please refer to the paper titled "10-bit 50MSs SAR ADC With a Monotonic Capacitor Switching Procedure" (IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.45, NO.4, APRIL 2010), published in April 2010. Additionally, Chinese patent application number 201510855497.X, published on March 9, 2016, also discloses a successive approximation analog-to-digital converter.

[0004] Figure 1 This is a circuit block diagram of a successive approximation analog-to-digital converter in the form of a 10-bit capacitor array, as described in the prior art. Figure 1As shown, it generates ten-bit digital signals D0 to D9. The capacitor array type analog-to-digital converter (ADC) consists of a capacitor array and operates using a charge distribution mechanism. Each clock cycle (CK is the clock signal), it successively compares signals through a comparator to generate a comparison result signal CO. The successive approximation logic module SAR logic generates digital signals D0 to D9 based on the comparison result signal CO and controls the outputs DACP and DACN of the first and second capacitor array type ADCs. These outputs are then input to the positive and negative inputs of comparator Comp via the first switch S1 and the second switch S2. Because parasitic capacitance exists at the positive and negative inputs of comparator Comp, these parasitic capacitances need to be charged during actual operation, resulting in a loss of charge on the capacitors in the capacitor array type ADC. This loss of charge leads to errors. To further improve the accuracy of the ADC, this loss of charge needs to be reduced.

[0005] Therefore, there is an urgent need to propose an improved successive approximation analog-to-digital converter to solve the above problems. [Summary of the Invention]

[0006] One of the objectives of this invention is to provide an improved successive approximation analog-to-digital converter (ADC) that can reduce the charge loss on capacitors in a capacitor array ADC caused by the need to charge the parasitic capacitance between the positive and negative input terminals of the comparator, thereby improving the accuracy of the successive approximation ADC.

[0007] To achieve the above objectives, according to a first aspect of the present invention, a successive approximation analog-to-digital converter (ADC) is provided, comprising: a first switch, which is alternately turned on and off under the control of a clock signal; a second switch, which is alternately turned on and off under the control of a clock signal; a first capacitor array ADC that receives a first differential input signal; a second capacitor array ADC that receives a second differential input signal; a successive approximation logic module that outputs a multi-bit digital signal, the digital signal being provided to the first capacitor array ADC and the second capacitor array ADC; a comparator, the first input of which is connected to the output of the first capacitor array ADC via the first switch, the second input of which is connected to the output of the second capacitor array ADC via the second switch, and the output of which is connected to the input of the successive approximation logic module; a first pre-charge circuit that operates before the first switch is turned on, charging the first input of the comparator based on the output voltage of the first capacitor array ADC; and a second pre-charge circuit that operates before the second switch is turned on, charging the second input of the comparator based on the output voltage of the second capacitor array ADC.

[0008] Compared with the prior art, the present invention can reduce the charge loss on the capacitors in the capacitor array type digital-to-analog converter caused by charging the parasitic capacitance between the positive and negative input terminals of the comparator by pre-charging the first and second input terminals of the comparator, thereby improving the accuracy of the successive approximation type analog-to-digital converter. [Attached Image Description]

[0009] The invention will be more readily understood in conjunction with the accompanying drawings and the following detailed description, wherein the same reference numerals correspond to the same structural components, wherein:

[0010] Figure 1 This is a circuit block diagram of a successive approximation analog-to-digital converter in the form of a 10-bit capacitor array in the prior art;

[0011] Figure 2 This is a circuit block diagram of a successive approximation analog-to-digital converter in one embodiment of the present invention.

[0012] Figure 3 This is a circuit block diagram of another embodiment of the successive approximation analog-to-digital converter of the present invention;

[0013] Figure 4 This is a schematic diagram of the waveforms of the two clock signals in this invention;

[0014] Figure 5 This is a schematic diagram of the circuit structure of a capacitor array type digital-to-analog converter in one embodiment of the present invention.

Detailed Implementation Methods

[0015] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0016] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic associated with that embodiment that is included in at least one implementation of the invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it necessarily a single or alternative embodiment that is mutually exclusive with other embodiments. "A plurality of" or "several" in this invention means two or more. "And / or" in this invention means "and" or "or".

[0017] One objective of this invention is to improve the accuracy of successive approximation analog-to-digital converters (SAR ADCs) by reducing the charge loss on capacitors in capacitor array digital-to-analog converters (DACs) caused by the need to charge the parasitic capacitance between the positive and negative input terminals of the comparator. Generally, comparators employ a differential input stage structure to ensure high comparison accuracy. In this structure, the differential input pairs (i.e., the pair of MOS transistors receiving the differential input) often exhibit mismatch during manufacturing; that is, the manufacturing differences between the two MOS transistors receiving the differential input are inversely proportional to their area. The larger the area of ​​the two differential input MOS transistors, the smaller the mismatch voltage. Therefore, larger dimensions are generally used to achieve high comparator accuracy. However, a larger area implies larger parasitic capacitance. Based on the above explanation, larger input parasitic capacitance leads to greater charge loss at the output of the capacitor array DAC, resulting in a decrease in the accuracy of the capacitor array DAC, and consequently, a decrease in the overall accuracy of the successive approximation SAR ADC.

[0018] Figure 2 This is a circuit block diagram of the successive approximation analog-to-digital converter 100 in one embodiment of the present invention. Figure 2 As shown, the successive approximation analog-to-digital converter includes: a first switch S1, a second switch S2, a first capacitor array digital-to-analog converter (CAP DAC) 110, a second capacitor array digital-to-analog converter 120, a comparator 130, a successive approximation logic module 140, a first pre-charge circuit 150, and a second pre-charge circuit 160. Figure 1 In comparison, the successive approximation analog-to-digital converter 100 of the present invention adds a first pre-charge path 150 and a second pre-charge path 160.

[0019] The first switch S1 is alternately turned on and off under the control of the clock signal CK; the second switch S2 is alternately turned on and off under the control of the clock signal CK. The first switch S1 and the second switch S2 are turned on and off synchronously. Figure 4 The diagram shows the waveforms of the two clock signals CK and CK-Pre in this invention. In one embodiment, when the clock signal CK is high, the corresponding sampling switches S1 and S2 are turned on; when the clock signal CK is low, the corresponding sampling switches S1 and S2 are turned off. Alternatively, in another embodiment, the corresponding switches S1 and S2 can be turned on when the clock signal CK is low.

[0020] A first capacitor array type digital-to-analog converter 110 receives a first differential input signal VIP. A second capacitor array type digital-to-analog converter 120 receives a second differential input signal VIN. As described in the background, each capacitor array type digital-to-analog converter includes a capacitor array and operates using a charge-sharing mechanism.

[0021] The successive approximation logic module 140 outputs multi-bit digital signals D0-D9. In this embodiment, it is a 10-bit digital signal; in other embodiments, the digital signal can be a 3, 4, 7, or 12-bit digital signal. The digital signals D0-D9 are provided to the first capacitor array digital-to-analog converter 110 and the second capacitor array digital-to-analog converter 120. The first input terminal of comparator 130 is connected to the output terminal DACP of the first capacitor array digital-to-analog converter 110 via a first switch S1, and its second input terminal is connected to the output terminal DACN of the second capacitor array digital-to-analog converter 120 via a second switch S2. Its output terminal CO is connected to the input terminal of the successive approximation logic module 140. The non-inverting input terminal of comparator 130 is the first input terminal, and the inverting input terminal is the second input terminal.

[0022] The first pre-charge circuit 150 operates before the first switch S1 is turned on, charging the first input terminal of the comparator 130 based on the output voltage DACP of the first capacitor array digital-to-analog converter 110. The second pre-charge circuit 150 operates before the second switch S2 is turned on, charging the second input terminal of the comparator 130 based on the output voltage DACN of the second capacitor array digital-to-analog converter 120.

[0023] like Figure 2 As shown, the first pre-charge circuit 150 includes a first operational amplifier OP1 and a third switch S3. One input terminal of the first operational amplifier S3 is connected to the output terminal DACP of the first capacitor array digital-to-analog converter 110, and the other input terminal of the first operational amplifier OP1 is connected to its output terminal. The output terminal of the first operational amplifier OP1 is connected to the first input terminal of the comparator 130 through the third switch S3. The second pre-charge circuit 160 includes a second operational amplifier OP2 and a fourth switch S4. One input terminal of the second operational amplifier OP2 is connected to the output terminal of the second capacitor array digital-to-analog converter 120, and the other input terminal of the second operational amplifier OP2 is connected to its output terminal. The output terminal of the second operational amplifier OP2 is connected to the second input terminal of the comparator 130 through the fourth switch S4. The third switch S3 and the fourth switch S4 are turned on for a period of time before the first switch S1 and the second switch S2 are turned on, and are turned off when the first switch S1 and the second switch S2 are turned on. The third switch S3 and the fourth switch S4 are controlled by the pre-charge clock signal CK-Pre, such as... Figure 4 As shown, before the clock signal CK jumps to a high level, the precharge clock signal CK-Pre jumps to a high level first. When the clock signal CK jumps to a high level, the precharge clock signal CK-Pre jumps to a low level. At this time, the corresponding switch controlled by the clock signal being high level is turned on as an example.

[0024] The successive approximation analog-to-digital converter 100 also includes an oscillator 170, which outputs the clock signal CK and the precharge clock signal CK-Pre. The successive approximation logic module 140 also has a reset input terminal RST, which can receive the reset signal RST, and a flag output terminal Flag.

[0025] The following is an introduction Figure 2 The working principle of the successive approximation analog-to-digital converter 100.

[0026] Before each time the clock signal CK changes from low to high (at which time comparator 130 is started, connecting DACP to VP and DACN to VN), the first operational amplifier OP1 is used to precharge the first input terminal VP to the voltage of DACP by controlling the precharge clock signal CK-Pre, and the second operational amplifier OP2 is used to precharge the second input terminal VN to the voltage of DACN by controlling the precharge clock signal CK-Pre. Figure 2 In the circuit, switches S1 and S2 are turned on when the clock signal CK is high; switches S1 and S2 are turned off when the clock signal CK is low.

[0027] In the design, the area of ​​the differential input pair transistors of the first operational amplifier OP1 and the second operational amplifier OP2 is smaller than that of the differential input pair transistors of the comparator Comp. Therefore, the parasitic capacitance of the differential input pair transistors of the first operational amplifier OP1 and the second operational amplifier OP2 is smaller than that of the differential input pair transistors of the comparator Comp, thus achieving a smaller input capacitance effect. Although the smaller differential input pair transistors of operational amplifier OP1 cause a certain error between its positive and negative input terminals, resulting in a certain error between the voltage of the first input terminal VP after pre-charging and the DACP voltage (but this error is generally small, for example, less than 20mV), the voltage dynamic range of DACP is generally large in general applications, possibly from 0 to VDD (where VDD is the power supply voltage). The pre-charging method will greatly reduce the charge loss caused by the input capacitance of the comparator Comp. The charge formula is: Q = C * ΔV, where Q is the required charge, C is the input parasitic capacitance of the comparator Comp, and ΔV is the required charging voltage. If a higher voltage needs to be charged to the input of comparator Comp, a larger ΔV will result in a larger charge required, thus introducing a larger error. In a design example, if the input parasitic capacitances of operational amplifiers OP1 and OP2 are 1 / 4 of that of comparator Comp, ΔV = 1.2V, but an additional 10mV (= 0.01V) precharge voltage difference is introduced between the precharge voltage and the voltage difference between DACP or DACN, then the required charging charge (i.e., charge loss) is:

[0028] Q' = (C / 4).ΔV + 0.01C = 0.31C, where C is the value of the input parasitic capacitance of the comparator Comp.

[0029] and Figure 1 The required charging charge (i.e., charge loss) for the scheme is:

[0030] Q = C.ΔV = 1.2C, where C is the value of the input parasitic capacitance of the comparator Comp.

[0031] Therefore, the present invention can achieve a smaller charge loss.

[0032] Figure 3 This is a circuit block diagram of another embodiment of the successive approximation analog-to-digital converter of the present invention. Figure 2 compared to, Figure 3 The specific circuit structures of the first precharge path 150 and the second precharge path 160 in the successive approximation analog-to-digital converter are different. For example... Figure 3 As shown, the first pre-charge circuit 150 includes a first redundant capacitor array type digital-to-analog converter (DummyDAC1), a first operational amplifier (OP1), and a third switch (S3). The first redundant capacitor array type digital-to-analog converter (DummyDAC1) receives a first differential input signal VIP and a digital signal output by the successive approximation logic module 140. One input terminal of the first operational amplifier (OP1) is connected to the output terminal of the first redundant capacitor array type digital-to-analog converter (DummyDAC1), and the other input terminal of the first operational amplifier (OP1) is connected to its output terminal. The output terminal of the first operational amplifier (OP1) is connected to the first input terminal of the comparator Comp through the third switch (S3). The second pre-charge circuit 160 includes a second redundant capacitor array digital-to-analog converter (Dummy DAC2), a second operational amplifier (OP2), and a fourth switch (S4). The Dummy DAC2 receives the second differential input signal VIN and the digital signal output by the successive approximation logic module 140. One input terminal of the second operational amplifier (OP2) is connected to the output terminal of the Dummy DAC2, and the other input terminal of the second operational amplifier (OP2) is connected to its output terminal. The output terminal of the second operational amplifier (OP2) is connected to the first input terminal of the comparator Comp via the fourth switch (S4). The third switch (S3) and the fourth switch (S4) are turned on for a period of time before the first switch (S1) and the second switch (S2) are turned on, and are turned off when the first switch (S1) and the second switch (S2) are turned on.

[0033] and Figure 2 compared to, Figure 3In the successive approximation analog-to-digital converter (ADC), the first pre-charge circuit 150 and the second pre-charge circuit 160 are respectively augmented with a first redundant capacitor array ADC (Dummy DAC1) and a second redundant capacitor array ADC (Dummy DAC2). Specifically, the first redundant capacitor array ADC (Dummy DAC1) mimics the first capacitor array ADC (Dummy DAC1) 110, such that the voltage signal DACP2 output by the first redundant capacitor array ADC (Dummy DAC1) is equivalent to the voltage signal DACP output by the first capacitor array ADC 110. Similarly, the second redundant capacitor array ADC (Dummy DAC2) mimics the second capacitor array ADC 120, such that the voltage signal DACN2 output by the second redundant capacitor array ADC 120 is equivalent to the voltage signal DACN output by the second redundant capacitor array ADC 120.

[0034] This further removes... Figure 2 The effect of input parasitic capacitances on operational amplifiers OP1 and OP2. In the example above, Figure 3 The required charging charge (i.e., charge loss) for the implementation method in the example is:

[0035] Q* = 0.01C = 0.01C, where C is the value of the input parasitic capacitance of comparator Comp.

[0036] In one area-saving implementation, the values ​​of each capacitor in the capacitor array of the first redundant capacitor array type digital-to-analog converter (Dummy DAC1) are smaller than the corresponding values ​​of the capacitors in the capacitor array of the first redundant capacitor array type digital-to-analog converter (Dummy DAC1), and the values ​​of each capacitor in the capacitor array of the second redundant capacitor array type digital-to-analog converter (Dummy DAC2) are smaller than the corresponding values ​​of the capacitors in the capacitor array of the second redundant capacitor array type digital-to-analog converter (Dummy DAC2). This can save area for both the first redundant capacitor array type digital-to-analog converter (Dummy DAC1) and the second redundant capacitor array type digital-to-analog converter (Dummy DAC2).

[0037] As mentioned above, Figure 1 The detailed structure of the capacitor array type digital-to-analog converter described herein can be found in existing technologies. However, for ease of understanding, a brief introduction to the detailed working principle of the successive approximation type analog-to-digital converter will still be provided here.

[0038] Figure 1VIP and VIN are differential input signals. VIP is the positive input terminal of the differential input signal, and VIN is the negative input terminal of the negative differential input signal. For an actual example, the variation range of VIP is 0 to 1200 mV, and the variation range of VIN is also 0 to 1200 mV. The equivalent variation range of the differential input signal is -1200 mV to +1200 mV. When VIP is 0 V and VIN is +1200 mV, the equivalent value of the differential input signal VIP - VIN = 0 - (+1200 mV) = -1200 mV; when VIN is 0 V and VIP is +1200 mV, the equivalent value of the differential input signal VIP - VIN = (+1200 mV) - 0 = +1200 mV. The function of the successive approximation analog-to-digital converter is to quantize the input signal into a digital signal. For simplicity, here an example of 3-bit quantization is used (it is 10-bit in the figure), that is, the differential signal range is equally divided into 3 = 8 equal parts, as shown in the following table:

[0039]

[0040]

[0041] The following uses an example to introduce the principle of successive approximation comparison.

[0042] Example 1:

[0043] For example, VIP = +100 mV, VIN = +1100 mV, VIP - VIN = -1000 mV

[0044] Step 1: Sample VIP to DACP (through switch S1), sample VIN to DACN, compare DACP and DACN (through comparator 130), and get logic 0 (indicating DACP < DACN). This is the highest bit.

[0045] Step 2: Connect and change the connection of the highest bit capacitor in the CAP DAC (capacitor array type digital-to-analog converter) corresponding to VIN, so that the voltage of DACN decreases by VREF / 2. VREF is the voltage value of the reference voltage REF. In the corresponding example, VREF should be designed to be 1200 mV. Therefore, DACN becomes (+1100 mV) - 600 mV = +500 mV, and the CAP DAC corresponding to VIP remains unchanged, that is, DACP = +100 mV. Compare DACP with DACN and get logic 0 (indicating DACP < DACN). This is the second highest bit.

[0046] Step 3: Connect and change the connection of the second-highest capacitor in the CAP DAC corresponding to VIN, so that the voltage of DACN decreases by VREF / 4. VREF is the voltage value of the reference voltage REF. In the corresponding example, VREF should be designed as 1200 mV. Therefore, DACN becomes (+500 mV) - 300 mV = +200 mV, while the CAP DAC corresponding to VIP remains unchanged, that is, DACP = +100 mV. Compare DACP and DACN, and get logic 0 (indicating DACP < DACN). This is the least significant bit.

[0047] Finally, the combined number obtained is: 000.

[0048] Example 2:

[0049] For example, VIP = +200 mV, VIN = +1000 mV, VIP - VIN = -800 mV

[0050] Step 1: Sample VIP to DACP, sample VIN to DACN, compare DACP and DACN, and get logic 0 (indicating DACP < DACN). This is the most significant bit.

[0051] Step 2: Connect and change the connection of the highest capacitor in the CAP DAC corresponding to VIN, so that the voltage of DACN decreases by VREF / 2. VREF is the voltage value of the reference voltage REF. In the corresponding example, VREF should be designed as 1200 mV. Therefore, DACN becomes (+1000 mV) - 600 mV = +400 mV, while the CAP DAC corresponding to VIP remains unchanged, that is, DACP = +200 mV. Compare DACP and DACN, and get logic 0 (indicating DACP < DACN). This is the second most significant bit.

[0052] Step 3: Connect and change the connection of the second-highest capacitor in the CAP DAC corresponding to VIN, so that the voltage of DACN decreases by VREF / 4. VREF is the voltage value of the reference voltage REF. In the corresponding example, VREF should be designed as 1200 mV. Therefore, DACN becomes (+400 mV) - 300 mV = +100 mV, while the CAP DAC corresponding to VIP remains unchanged, that is, DACP = +200 mV. Compare DACP and DACN, and get logic 1 (indicating DACP < DACN). This is the least significant bit.

[0053] Finally, the combined number obtained is: 001.

[0054] Example 3:

[0055] For example, VIP = +400 mV, VIN = +800 mV, VIP - VIN = -400 mV

[0056] Step 1: Sample VIP to DACP, sample VIN to DACN, compare DACP and DACN, and obtain logic 0 (indicating DACP < DACN). This is the highest bit.

[0057] Step 2: Connect and change the connection of the highest-bit capacitor in the CAP DAC corresponding to VIN, so that the voltage of DACN decreases by VREF / 2, where VREF is the voltage value of the reference voltage REF. In the corresponding example, VREF should be designed as 1200 mV. Therefore, DACN becomes (+800 mV) - 600 mV = +200 mV, while the CAP DAC corresponding to VIP remains unchanged, that is, DACP = +400 mV. Compare DACP and DACN, and obtain logic 1 (indicating DACP < DACN). This is the second-highest bit.

[0058] Step 3: Connect and change the connection of the second-highest-bit capacitor in the CAP DAC corresponding to VIP, so that the voltage of DACP decreases by VREF / 4, where VREF is the voltage value of the reference voltage REF. In the corresponding example, VREF should be designed as 1200 mV. Therefore, DACP becomes (+400 mV) - 300 mV = +100 mV, while the CAP DAC corresponding to VIN remains unchanged, maintaining the value in the previous step, that is, DACN = +200 mV. Compare DACP and DACN, and obtain logic 0 (indicating DACP < DACN). This is the lowest bit.

[0059] Finally, the combined number obtained is: 010.

[0060] Figure 5 It is a schematic diagram of the circuit structure of a capacitive array digital-to-analog converter in an embodiment. In this example, taking the implementation method of the capacitive array digital-to-analog converter corresponding to VIP as an example, when the first sampling clock signal Sample is at a high level, VIP is sampled to DACP through the switch S53, and then the sampling clock signal Sample becomes low. After that, DACP works by relying on the charge distribution on the capacitor. Initially, Q1 and Q0 are reset to a high level. Control S51 to connect the negative electrode of C1 to the reference voltage REF (for example, designed as 1200 mV), and control S0 to connect the negative electrode of C50 to the reference voltage REF (for example, designed as 1200 mV). The capacitance value design ratio satisfies: C1:C0:Cd = 2:1:1. Assuming the total capacitance value Ct = C1 + C0 + Cd, then C1 = Ct / 2, C0 = Cd = Ct / 4

[0061] If the negative electrode of C1 is switched from REF to ground, then the voltage of DACP after the switch satisfies:

[0062] (VIP - VREF).Ct = (DACP - 0).C1 + (DACP - VREF).(C0 + Cd)

[0063] Substituting C1 = Ct / 2 and C0 = Cd = Ct / 4, we simplify to get:

[0064] DACP = VIP - VREF / 2;

[0065] If the negative terminal of C0 is switched from REF to ground, the voltage of DACP after the switch will satisfy:

[0066] (VIP-VREF).Ct=(DACP-VREF).C1+(DACP-VREF).Cd+(DACP-0).C0

[0067] Substituting C1 = Ct / 2 and C0 = Cd = Ct / 4, we simplify to get:

[0068] DACP = VIP - VREF / 4.

[0069] like Figure 5 As shown, each capacitor array type digital-to-analog converter includes an internal sampling switch S53 connected between its input and output terminals, and multiple capacitors C1, C0, and Cd connected in parallel to its output terminal. At least some of the capacitors have their other ends selectively connected to ground or a reference voltage terminal REF, depending on the digital bits in the digital signal output by the successive approximation logic module. Figure 5 As shown, the digital bits D1 and D2 in the digital signal output by the successive approximation logic module control one of switches S51b and S51 to be turned on and the other to be turned off through flip-flops, and one of switches S50b and S50 to be turned on and the other to be turned off, so as to connect capacitors C1 and C0 to the ground terminal or the reference voltage terminal REF.

[0070] In this invention, terms such as "connection," "linked," "connected," and "joined" that indicate electrical connection, unless otherwise specified, refer to direct or indirect electrical connections. A direct electrical connection refers to a direct connection between two or more objects without any intervening objects, while an indirect electrical connection refers to a connection between two or more objects with one or more intervening objects (such as electrical components or units like resistors, capacitors, inductors, switches, and filters).

[0071] The foregoing description has fully disclosed the specific embodiments of the present invention. It should be noted that any modifications made to the specific embodiments of the present invention by those skilled in the art do not depart from the scope of the claims. Accordingly, the scope of the claims is not limited to the specific embodiments described.

Claims

1. A successive approximation analog-to-digital converter, characterized in that, It includes: The first switch is alternately turned on and off under the control of a clock signal; The second switch is alternately turned on and off under the control of a clock signal; A first capacitor array type digital-to-analog converter receives a first differential input signal; The second capacitor array type digital-to-analog converter receives the second differential input signal; The successive approximation logic module outputs a multi-bit digital signal, which is provided to a first capacitor array digital-to-analog converter and a second capacitor array digital-to-analog converter. The comparator has its first input terminal connected to the output terminal of the first capacitor array digital-to-analog converter via a first switch, its second input terminal connected to the output terminal of the second capacitor array digital-to-analog converter via a second switch, and its output terminal connected to the input terminal of the successive approximation logic module. The first pre-charging circuit operates before the first switch is turned on, charging the first input terminal of the comparator based on the output voltage of the first capacitor array digital-to-analog converter. and The second pre-charging circuit operates before the second switch is turned on, charging the second input terminal of the comparator based on the output voltage of the second capacitor array digital-to-analog converter. The first pre-charge circuit includes a first operational amplifier and a third switch. One input terminal of the first operational amplifier is connected to the output terminal of the first capacitor array digital-to-analog converter, and the other input terminal of the first operational amplifier is connected to its output terminal. The output terminal of the first operational amplifier is connected to the first input terminal of the comparator through the third switch. The second pre-charge circuit includes a second operational amplifier and a fourth switch. One input terminal of the second operational amplifier is connected to the output terminal of the second capacitor array digital-to-analog converter, and the other input terminal of the second operational amplifier is connected to its output terminal. The output terminal of the second operational amplifier is connected to the second input terminal of the comparator through the fourth switch. The third and fourth switches are turned on for a period of time before the first and second switches are turned on, and are turned off when the first and second switches are turned on.

2. The successive approximation analog-to-digital converter according to claim 1, characterized in that, The area of ​​the differential input pair transistors of the first operational amplifier and the second operational amplifier is smaller than the area of ​​the differential input pair transistors of the comparator.

3. The successive approximation analog-to-digital converter according to claim 1, characterized in that, The first pre-charge circuit includes a first redundant capacitor array digital-to-analog converter, a first operational amplifier, and a third switch. The first redundant capacitor array digital-to-analog converter receives a first differential input signal and a digital signal output by the successive approximation logic module. One input terminal of the first operational amplifier is connected to the output terminal of the first redundant capacitor array digital-to-analog converter, and the other input terminal of the first operational amplifier is connected to its output terminal. The output terminal of the first operational amplifier is connected to the first input terminal of the comparator through the third switch. The second pre-charge circuit includes a second redundant capacitor array digital-to-analog converter, a second operational amplifier, and a fourth switch. The second redundant capacitor array digital-to-analog converter receives a second differential input signal and a digital signal output by the successive approximation logic module. One input terminal of the second operational amplifier is connected to the output terminal of the second capacitor array digital-to-analog converter, and the other input terminal of the second operational amplifier is connected to its output terminal. The output terminal of the second operational amplifier is connected to the first input terminal of the comparator through the fourth switch. The third and fourth switches are turned on for a period of time before the first and second switches are turned on, and are turned off when the first and second switches are turned on.

4. The successive approximation analog-to-digital converter according to claim 3, characterized in that, The first redundant capacitor array type digital-to-analog converter mimics the first capacitor array type digital-to-analog converter, making the voltage signal output by the first redundant capacitor array type digital-to-analog converter equivalent to the voltage signal output by the first capacitor array type digital-to-analog converter. The second redundant capacitor array type digital-to-analog converter mimics the second capacitor array type digital-to-analog converter, making the voltage signal output by the second redundant capacitor array type digital-to-analog converter equivalent to the voltage signal output by the second capacitor array type digital-to-analog converter.

5. The successive approximation analog-to-digital converter according to claim 3, characterized in that, The area of ​​the differential input pair transistors of the first operational amplifier and the second operational amplifier is smaller than the area of ​​the differential input pair transistors of the comparator.

6. The successive approximation analog-to-digital converter according to claim 4, characterized in that, In the first redundant capacitor array type digital-to-analog converter, the value of each capacitor in the capacitor array is smaller than the value of the corresponding capacitor in the capacitor array of the first capacitor array type digital-to-analog converter. The values ​​of each capacitor in the capacitor array of the second redundant capacitor array type digital-to-analog converter are smaller than the values ​​of the corresponding capacitors in the capacitor array of the second capacitor array type digital-to-analog converter.

7. The successive approximation analog-to-digital converter according to any one of claims 1-6, characterized in that, Each capacitor array digital-to-analog converter includes an internal sampling switch connected between its input and output, and multiple capacitors connected in parallel to its output. At least some of the capacitors have their other ends selectively connected to ground or a reference voltage terminal depending on the digital bits in the digital signal output by the successive approximation logic module.

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