Transistor with self-aligned body tie

Abstract

To provide a parasitic effect lower than that in a body connection structure by a transistor with a self-aligned body tie.SOLUTION: A transistor 100 includes a source 120 and a drain 122 mounted in a first type of active region 214, a gate 124 mounted to the source and the drain, and a body mounted in the first type of active region and substantially covered with the gate. The transistor further includes a body tie 118 mounted in a second type of active region and including a connection part that is covered with the gate substantially and engaged with the body. The size of the first type of active region and the second type of active region can be determined so that gaps 216 and 218 are provided between them on each side of the gate.SELECTED DRAWING: Figure 8H

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the priority of U.S. Provisional Application No. 63 / 168,887, titled "Transistor with Self - Aligned Body Tie", filed on March 31, 2021, the disclosure of which is hereby expressly incorporated by reference in its entirety.

[0002] Technical Field This disclosure relates to transistors having a self - aligned body tie.

Background Art

[0003] Description of Related Art In metal - oxide - semiconductor field - effect transistors (MOSFETs) such as silicon - on - insulator transistors, a floating - body configuration can provide lower parasitic effects than a body - connected configuration. Thus, floating - body silicon - on - insulator transistors tend to provide better performance than body - connected silicon - on - insulator transistors. However, the floating - body effect can limit the practical use of floating - body silicon - on - insulator transistors.

Summary of the Invention

Means for Solving the Problems

[0004] Summary of the Invention According to some embodiments, the disclosure relates to a transistor comprising a source and a drain, each mounted within a first type of active region; a gate mounted relative to the source and the drain; and a body mounted within the first type of active region and substantially covered by the gate. The transistor further comprises a body tie, which includes a connecting portion mounted within a second type of active region and substantially covered by the gate and engaging with the body, wherein the first and second active regions are sized to provide a gap between them on each side of the gate.

[0005] In some embodiments, the first type of active region may include an N+ active region, and the second type of active region may include a P+ active region. In some embodiments, the gate may have a shape symmetrical with respect to a line along the width direction of the gate. In some embodiments, the gate may have an I-shape that covers the connection portion between the body and the body tie.

[0006] In some embodiments, the connection portion of the body tie can be aligned with the body based on the shape of the gate. In some embodiments, the aligned configuration between the connection portion of the body tie and the body may result from the formation of a gap between the first active region and the second active region on either side of the gate. In some embodiments, the aligned engagement between the connection portion of the body tie and the body may be the only engagement between the body tie and the body.

[0007] In some teachings, the present disclosure relates to a method for manufacturing a transistor. The method includes the steps of forming or providing a first type of active region and a second type of active region; mounting a source and drain having the first type of active region; forming a body tie having the second type of active region; and forming a gate relative to the source and drain. The method further includes the step of sizing one or both of the first and second type of active regions to provide a gap between the first and second type of active regions on either side of the gate such that the connection portion of the body tie that engages with the body is substantially covered by the gate.

[0008] In some embodiments, the first type of active region may include an N+ active region, and the second type of active region may include a P+ active region. In some embodiments, the step of forming the gate may include the step of forming a gate with a shape symmetrical with respect to a line along the width direction of the gate. In some embodiments, the gate may have an I-shape that covers the connection portion between the body and the body tie.

[0009] In some embodiments, the dimensioning step may include removing a portion of the first type of active region using a mask that protects the gate during the removal step to provide a gap on both sides of the gate. In some embodiments, by forming the gap using a mask that protects the gate, the connection portion of the body below the gate and the connection portion of the body tie below the gate can be aligned with each other based on the shape of the gate. In some embodiments, the aligned engagement between the connection portion of the body tie and the body may be the only engagement between the body tie and the body.

[0010] According to some embodiments, the disclosure relates to a semiconductor die comprising a substrate and one or more transistors mounted on the substrate. Each transistor includes a source and a drain, each mounted as a first type of active region, and a gate mounted relative to the source and drain such that the application of a voltage to the gate results in the formation of a conductive channel between the source and the drain. The transistor further includes a body configured to provide a conductive channel when a voltage is applied to the gate. The body is mounted within the first type of active region and substantially covered by the gate. The transistor further includes a body tie, which includes a connecting portion mounted as a second type of active region and substantially covered by the gate, engaging with the body, wherein the first and second active regions are sized to provide a gap between them on each side of the gate.

[0011] In some embodiments, the substrate may include a silicon-on-insulator substrate. In some embodiments, each transistor may be configured as a radio frequency transistor. In some embodiments, each transistor may be configured as a digital cell transistor or a switching transistor.

[0012] In some embodiments, the disclosure relates to a package module comprising a package substrate and a semiconductor die mounted on the package substrate. The semiconductor die comprises one or more transistors. Each transistor comprises a source and a drain, each mounted as a first type of active region, and a gate mounted relative to the source and drain such that the application of a voltage to the gate results in the formation of a conductive channel between the source and the drain. The transistor further comprises a body configured to provide a conductive channel when a voltage is applied to the gate. The body is mounted within the first type of active region and substantially covered by the gate. The transistor further comprises a body tie, which comprises a connecting portion mounted as a second type of active region and substantially covered by the gate, engaging with the body, wherein the first and second active regions are sized to provide a gap between them on each side of the gate.

[0013] In some embodiments, the disclosure relates to an electronic device including a power supply and an integrated circuit mounted on a semiconductor die and powered by the power supply. The integrated circuit includes one or more transistors. Each transistor includes a source and a drain, each mounted as a first type of active region, and a gate mounted relative to the source and drain such that the application of a voltage to the gate results in the formation of a conductive channel between the source and the drain. The transistor further includes a body configured to provide a conductive channel when a voltage is applied to the gate. The body is mounted within the first type of active region and substantially covered by the gate. The transistor further includes a body tie, which includes a connecting portion mounted as a second type of active region and substantially covered by the gate, engaging with the body, wherein the first and second active regions are sized to provide a gap between them on each side of the gate.

[0014] In some embodiments, the integrated circuit may include a switching circuit, and each of one or more transistors may be implemented as a switching transistor. In some embodiments, the electronic device may be a wireless device.

[0015] In some embodiments, each of one or more transistors can be implemented as a digital cell.

[0016] For the purpose of summarizing this disclosure, specific aspects, advantages, and novel features of the present invention are described herein. It should be understood that not all of such advantages are necessarily achieved according to any particular embodiment of the present invention. Accordingly, the present invention may be embodied or performed to achieve or optimize one advantage or group of advantages as taught herein, without necessarily achieving other advantages that may be taught or suggested herein. [Brief explanation of the drawing]

[0017] [Figure 1] This specification shows a transistor having one or more of the features described herein. [Figure 2] In some embodiments, the transistor shown in Figure 1 can be implemented in a circuit and / or device. [Figure 3] An example of a silicon-on-insulator (SOI) transistor with a T-shaped gate and a conventional body-tie configuration is shown. [Figure 4A] Figure 3 shows a cross-sectional view. [Figure 4B] Figure 3 shows a cross-sectional view. [Figure 5] Another example of a silicon-on-insulator (SOI) transistor with an L-shaped gate and a conventional body-tie configuration is shown. [Figure 6A] This is a plan view of an exemplary silicon-on-insulator (SOI) transistor having a self-aligned body-tie configuration. [Figure 6B]Perspective view of an exemplary silicon-on-insulator (SOI) transistor having a self-aligned body tie configuration. [Figure 7A] Shows a cross-sectional view shown in FIG. 6A. [Figure 7B] Shows a cross-sectional view shown in FIG. 6A. [Figure 7C] Shows a cross-sectional view shown in FIG. 6A. [Figure 7D] Shows a cross-sectional view shown in FIG. 6A. [Figure 8A] Shows an example of a process that can be utilized to manufacture a transistor having a self-aligned body tie or body connection. [Figure 8B] Shows an example of a process that can be utilized to manufacture a transistor having a self-aligned body tie or body connection. [Figure 8C] Shows an example of a process that can be utilized to manufacture a transistor having a self-aligned body tie or body connection. [Figure 8D] Shows an example of a process that can be utilized to manufacture a transistor having a self-aligned body tie or body connection. [Figure 8E] Shows an example of a process that can be utilized to manufacture a transistor having a self-aligned body tie or body connection. [Figure 8F] Shows an example of a process that can be utilized to manufacture a transistor having a self-aligned body tie or body connection. [Figure 8G] Shows an example of a process that can be utilized to manufacture a transistor having a self-aligned body tie or body connection. [Figure 8H] Shows an example of a process that can be utilized to manufacture a transistor having a self-aligned body tie or body connection. [Figure 9] Illustrates that in some embodiments, a transistor having one or more features described herein can be implemented on a device such as a die. [Figure 10]In some embodiments, the die / device shown in Figure 9 may include one or more transistors configured as switches. [Figure 11] In some embodiments, the die / device shown in Figure 9 may include one or more transistors configured as a digital cell. [Figure 12] In some embodiments, it is shown that a transistor having one or more of the features described herein can be mounted in a package module. [Figure 13] This specification shows an exemplary wireless device having one or more of the advantageous features described herein. [Modes for carrying out the invention]

[0018] Detailed description of several embodiments Headings provided herein, where present, are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.

[0019] Figure 1 shows a transistor 100 having one or more of the features described herein. Figure 2 shows that in some embodiments, the transistor 100 of Figure 1 can be implemented in a circuit and / or device 102. Thus, the circuit / device 102 can benefit from one or more of the features of the transistor 100. Examples of such transistors and associated circuits / devices are described in more detail herein.

[0020] In metal-oxide-semiconductor field-effect transistors (MOSFETs), such as silicon-on-insulator (SOI) transistors, the floating-body (FB) configuration can provide lower parasitic components (e.g., parasitic capacitance) than the body-connected (BC) configuration. Therefore, FB SOI transistors tend to offer better performance than BC SOI transistors. However, the floating-body effect can limit the practical applications of FB SOI transistors.

[0021] Floating Body (FB) FET designs offer higher cutoff frequencies (f) for amplifier applications such as low-noise amplifiers on SOI. T ) and higher transconductance (g m It should be noted that FB FETs are a common choice due to their performance characteristics, such as those mentioned above. However, FB FETs can suffer from long settling times due to body potential drift after transient events. Notable mechanisms causing slow settling behavior include the lack of minority carrier supply when majority carriers are injected into or removed from the FB FET body during transient events. If the disappearance of excess majority carriers relies solely on diffusion processes, the body typically takes longer to reach equilibrium.

[0022] It should also be noted that conventional body-tie SOI FETs commonly use T-gate or L-gate configurations for body-tie connections. In an SOI FET, the body refers to the silicon region below the gate, and the body-tie region refers to the silicon region with injections such as P+ injection. The body-tie acts as a source of minority carriers to extinguish majority carriers when the equilibrium state of the body is disturbed after a transient event. However, T-gate or L-gate body-tie SOI FETs introduce a larger gate area required to prevent the N+ and P+ regions from short-circuiting each other, and therefore the gate is used as a buffer to isolate the N+ and P+ regions.

[0023] In the aforementioned body-tie SOI FET configuration, the large gate area results in a large excess gate-source capacitance (Cgs) compared to, for example, an FB SOI FET, and such a large Cgs is typically f T and g m These parameters are limited. In addition, an additional source / drain-body junction capacitance is introduced into the body tie configuration of the T-gate or L-gate.

[0024] Figure 3 shows an example of a silicon-on-insulator (SOI) transistor 10 having a T-shaped gate and a conventional body-tie configuration. Figures 4A and 4B show cross-sectional views of the transistor shown in Figure 3. Figure 5 shows another example of a silicon-on-insulator (SOI) transistor 10 having an L-shaped gate and a conventional body-tie configuration.

[0025] In Figures 3 and 4, the exemplary transistor 10 is shown to include an N+ injection region 14 and a P+ injection region 12 formed on an insulating layer 28 (e.g., a buried oxide (BOX) layer). The N+ injection region 14 may include an N+ active region 20 and an N+ active region 22. Such active regions can function as the source (S) and drain (D) of the transistor 10. The P+ injection region 12 may include a body tie 18 for the transistor 10.

[0026] In the examples of Figures 3 and 4, the gate structure 24 is shown to be implemented across the aforementioned regions 20, 22, and 18. In some embodiments, such a gate may include, for example, a polysilicon material. As shown in Figures 4A and 4B, the body 26 may be at least partially between the two N+ active regions 20, 22 and at least partially below the gate 24. Typically, an insulating layer, such as a gate oxide layer 25, may be present between the gate 24 and the body 26.

[0027] Figure 3 shows an example where the gate 24 has a T-shape. Figure 5 shows another example of a silicon-on-insulator (SOI) transistor 10 having an L-shaped gate 24. In the example of Figure 5, the exemplary transistor 10 is shown to include N+ injection regions 14 and P+ injection regions 12 formed on an insulating layer 28 (e.g., a buried oxide (BOX) layer). The N+ injection region 14 may include N+ active regions 20 and N+ active regions 22. Such active regions can function as the source (S) and drain (D) of the transistor 10. The P+ injection region 12 may include a body tie 18 for the transistor 10.

[0028] In the example in Figure 5, the L-shaped gate structure 24 is shown to be implemented across the aforementioned regions 20, 22, and 18. In some embodiments, such a gate may include, for example, a polysilicon material. Similar to the example in Figure 3, the body may be at least partially between the two N+ active regions 20, 22 and at least partially below the gate 24. Typically, an insulating layer, such as a gate oxide layer, may be present between the gate 24 and the body.

[0029] Figures 6A and 6B show a plan view and perspective view of an example of a silicon-on-insulator (SOI) transistor 100 having a self-aligned body-tie configuration. Figures 7A to 7D show the cross-sectional view shown in Figure 6A.

[0030] Referring to Figures 6 and 7, the transistor 100 is shown to include an N+ injection region 114 and a P+ injection region 112 formed on an insulating layer 128 (e.g., a buried oxide (BOX) layer). The N+ injection region 114 may include an N+ active region 120 and an N+ active region 122. Such active regions can function as the source (S) and drain (D) of the transistor 100. The P+ injection region 112 may include a body tie 118 for the transistor 100.

[0031] In the examples of Figures 6 and 7, the gate structure 124 is shown to be implemented across the aforementioned regions 120, 122, and 118. In some embodiments, such a gate may include, for example, a polysilicon material. As shown in Figures 6B and 7A-7C, the body 126 may be at least partially between the two N+ active regions 120, 122 and at least partially below the gate 124. Typically, an insulating layer, such as a gate oxide layer 125, may be present between the gate 124 and the body 126.

[0032] Figures 6 and 7 show that in some embodiments, the transistor 100 can be configured such that the P+ region 112 and the N+ region 114 are separated in a region not covered by the gate, thereby demonstrating that the connection of the body 126 to the body tie region 118 is only present under the gate 124. For example, a portion of the N+ active region 120 may be removed or absent to define the gap 117, and a portion of the N+ active region 122 may be removed or absent to define the gap 119, so that the N+ active regions 120 and 122 do not directly physically engage with the body tie region 118, rather than through the body 126 under the gate 124. With this configuration, the transistor 100 can have virtually no transient effects and substantially lower Cgs compared to transistors with conventional body tie configurations, such as the T-gate and L-gate examples in Figures 3 to 5.

[0033] For illustrative purposes, the exemplary transistors in Figures 6 and 7 may be referred to as having self-aligning body ties or body connections, for the reason that such body connections have substantially the same width and can be aligned with the gate during the manufacturing process. Examples related to such manufacturing processes are described in more detail herein.

[0034] It should be noted that in some embodiments, transistors having self-aligned body ties or body connections, such as those shown in the examples of Figures 6 and 7, can achieve the smallest or substantially reduced capacitance Cgs possible at technical scale without such constraints from T-gate or L-gate patterning requirements. It should also be noted that, in the aforementioned transistors having self-aligned body ties or body connections, little to no additional source / drain-body junction capacitance is introduced in the self-aligned body tie process compared to FB FETs.

[0035] Figures 8A to 8H show examples of processes that can be used to manufacture transistors with self-aligned body ties or body connections, as shown in the examples in Figures 6 and 7.

[0036] Figure 8A shows process steps that allow for the formation of an active silicon region 200 on an insulating layer 128, such as a buried oxide (BOX) layer, to form assembly 201. Figure 8B shows process steps that allow for the formation of a gate assembly 202 on the active region 200 of assembly 201 in Figure 8A, to form assembly 204. In some embodiments, such a gate assembly may include a gate structure comprising a polysilicon material and an insulating layer, such as a gate oxide layer, mounted between the polysilicon material and the active region 200.

[0037] Figure 8C shows a process step in which a hard mask 206 can be formed on the gate assembly (202 in Figure 8B) to form assembly 208. Such a hard mask can protect the gate assembly during one or more subsequent etching steps.

[0038] Figure 8D shows process steps that allow a mask to be formed to define a portion of the active region 200 to be removed in order to form assembly 212. For example, a mask 210a can be formed over a portion of the active region 200 that will become a body tie (118 in Figures 6 and 7) and the corresponding portion of the hard mask 206, and a mask 210b can be formed over a portion of the active region 200 that will become a source and drain (120, 122 in Figures 6 and 7) and the corresponding portion of the hard mask 206. Such exemplary masks are shown to leave uncovered portions to be removed from the active region 200.

[0039] Figure 8E shows process steps that can remove unmasked portions of the active region (200 in Figure 8D) in order to form assembly 220. For example, a silicon etching process can be performed to substantially remove the unmasked portions of the active region 200 that are not covered by the masks 210a and 210b in Figure 8D, thereby forming gaps 216 and 218 on both sides of the hard mask gate assembly, and thereby forming an etched active region 214. Such a silicon etching process can be performed and stopped at the BOX layer 128. It should be noted that such an etching process for forming gaps 216 and 218 in the active region 200 will result in the body tie (118 in Figures 6 and 7) connections to the body beneath the gate assembly becoming self-aligned with respect to the gate assembly.

[0040] Figure 8F shows a process step in which the masks 210a and 210b in Figure 8E can be removed to form assembly 222. It is shown that such mask removal exposes the etched active region 214.

[0041] Figure 8G shows a process step in which the hard mask 206 of Figure 8F can be removed to form assembly 224. Such removal of the hard mask is shown to expose the gate assembly 202.

[0042] Figure 8H shows process steps that allow P+ and N+ injection to be performed to form P+ injection regions and N+ injection regions 112, 114, thereby forming the gate 124, source and drain 120, 122, and body tie 118 as described herein. As also described herein, gaps 216, 218 allow the body tie 118 to connect self-aligningly to the body below the gate 124.

[0043] It should be noted that transistors as described herein with reference to Figures 6-8 can offer several desirable features. For example, such transistors can be implemented with little to no increase in gate-source capacitance and junction capacitance. In another example, the source node and body node of the transistor do not need to be butted against each other as in the L-gate configuration of Figure 5, thereby allowing for a greater degree of freedom in the body bias configuration. In yet another example, the transistor design can eliminate or reduce the drift or hysteresis behavior of floating-body transistors without significant performance degradation. In yet another example, the transistor design can improve the speed of embodiments such as cell blocks due to the reduced gate load compared to conventional T-gate or L-gate body-tie transistor designs.

[0044] Figure 9 shows that in some embodiments, one or more transistors 100 having one or more of the features described herein can be mounted on a device 102 such as a die 300. Such a die may include a substrate 302 such as a silicon-on-insulator (SOI) substrate.

[0045] Figures 10 and 11 show examples of the die / device 300 / 102 of Figure 9. Figure 10 shows that in some embodiments, the die / device 300 / 102 may include one or more transistors 100, as described herein, configured as switches. In some embodiments, such switches may be configured as RF switches.

[0046] Figure 11 shows that in some embodiments, the die / device 300 / 102 may include one or more transistors 100, as described herein, configured for digital applications. For example, one or more digital cells may be implemented with transistors having one or more of the features described herein.

[0047] Figure 12 shows that in some embodiments, one or more transistors having one or more of the features described herein can be mounted on a package module 400. Such a package module may include a package substrate 402 configured to accept multiple components. At least some of the components mounted on the package substrate 402 may include dies 300, such as one or more of the exemplary dies 300 shown in Figures 9 to 11.

[0048] In some implementations, devices and / or circuits having one or more features described herein may be included in RF devices such as wireless devices. Such devices and / or circuits can be directly implemented in wireless devices in the modular form described herein or in any combination thereof. In some embodiments, such wireless devices may include, for example, mobile phones, smartphones, handheld wireless devices with or without telephone functionality, wireless tablets, and the like.

[0049] Figure 13 shows an exemplary wireless device 900 having one or more of the advantageous features described herein. In the context of various transistors as described herein, a switch 920 based on such transistors can be implemented in module 910. It will be understood that transistors having one or more of the features described herein may also be used in other parts of wireless devices.

[0050] In an exemplary wireless device 900, a PA assembly 916 having multiple power amplifiers (PAs) can provide one or more amplified RF signals to a switch 920 (via an assembly of one or more duplexers 918), and the switch 920 can route the amplified RF signals to one or more antennas. The PA 916 can receive corresponding unamplified RF signals from a transceiver 914, which can be configured and operated in known ways. The transceiver 914 can also be configured to process the received signals. The transceiver 914 is shown to interact with a baseband subsystem 910 configured to provide conversion between user-appropriate data and / or voice signals and RF signals suitable for the transceiver 914. The transceiver 914 is also shown to connect to a power management component 906 configured to manage power for the operation of the wireless device 900. Such a power management component can also control the operation of the baseband subsystem 910 and module 910.

[0051] The baseband subsystem 910 is shown to be connected to a user interface 902 to facilitate various inputs and outputs of voice and / or data provided to and received from the user. The baseband subsystem 910 can also be connected to a memory 904 configured to store data and / or instructions to facilitate the operation of the radio device and / or to provide information storage to the user.

[0052] In some embodiments, the duplexer 918 can enable simultaneous transmission and reception operations using a common antenna (e.g., 924). In Figure 13, the received signal is shown to be routed to an “Rx” path which may include, for example, one or more low-noise amplifiers (LNAs).

[0053] Several other wireless device configurations may utilize one or more of the features described herein. For example, the wireless device does not need to be a multiband device. In another example, the wireless device may include additional antennas, such as diversity antennas, as well as additional connectivity features such as Wi-Fi, Bluetooth®, and GPS.

[0054] Unless the context clearly requires otherwise, words such as “comprise” and “comprising” throughout the specification and claims should be interpreted in a comprehensive sense, as opposed to an exclusive or exhaustive sense; that is, “not limited but includes.” The term “combined” as commonly used herein refers to two or more elements that are directly connected or that can be connected by one or more intermediate elements. Furthermore, the words “as specified herein,” “above,” “below,” and words of similar meaning, when used in this application, refer to the entire application and not to any particular part thereof. Where the context allows, words used in the above descriptions, whether singular or plural, may also include plural or singular. The word “or” in relation to a list of two or more items encompasses all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0055] The above detailed description of embodiments of the present invention is not intended to be exhaustive or to limit the invention to the exact forms disclosed above. Specific embodiments and examples of the present invention are described above for illustrative purposes, but as those skilled in the art will recognize, a variety of equivalent modifications are possible within the scope of the invention. For example, while processes or blocks are presented in a given order, alternative embodiments may perform routines having steps in a different order, or use systems having blocks, and some processes or blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these processes or blocks may be carried out in a variety of different ways. Also, while processes or blocks may be shown as being executed sequentially, these processes or blocks may instead be executed simultaneously or at different times.

[0056] The teachings of the present invention provided herein can be applied to systems other than those described above. Further embodiments can be provided by combining elements and operations of the various embodiments described above.

[0057] While several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of this disclosure. In fact, the novel methods and systems described herein can be implemented in various other forms, and various omissions, substitutions, and modifications of the forms of the methods and systems described herein can be made without departing from the spirit of this disclosure. The appended claims and their equivalents are intended to encompass forms or modifications that fall within the scope and spirit of this disclosure.

Claims

1. A transistor, a source and a drain each implemented within a first type of active region; a gate mounted to the source and the drain; a body implemented in the first type of active area and substantially covered by the gate; a body tie implemented within the second type of active area; a connection portion connecting the body tie to the body, the connection portion and the gate being dimensioned such that the connection portion is exclusively under each portion of the gate and each portion of the gate is exclusively over the connection portion.

2. The transistor of claim 1 , wherein the first type active area comprises an N+ active area and the second type active area comprises a P+ active area.

3. The transistor according to claim 2 , wherein the gate has a shape that is symmetrical with respect to a line along a width direction of the gate.

4. The transistor of claim 3 , wherein the gate has an I-shape that covers the body and the connecting portion.

5. The transistor of claim 1, wherein the connection portion is aligned with the body based on the shape of the gate.

6. A transistor as described in claim 5, wherein the first active region and the second active region are dimensioned such that the matching configuration between the connection portion and the body is provided by the gap between the first active region and the second active region on either side of the gate.

7. 1. A method for fabricating a transistor, comprising: forming or providing a first type of active region and a second type of active region; implementing sources and drains in the first type of active area; forming a body tie on the second type active region; forming gates for the source and the drain; and dimensioning the connection portions and the gate such that connection portions connecting the body tie to the body are only below each portion of the gate and each portion of the gate is only above the connection portions.

8. 8. The method of claim 7, wherein the first type active area comprises an N+ active area and the second type active area comprises a P+ active area.

9. 9. The method of claim 8, wherein said step of forming said gate comprises forming a gate symmetrically shaped with respect to a line along a width direction of said gate.

10. The method of claim 9 , wherein the gate has an I-shape that covers the connecting portion of the body and the body tie.

11. 8. The method of claim 7, wherein said step of dimensioning comprises removing portions of said first type active area to provide said gaps on either side of said gate, using a mask that protects said gate during said removing step.

12. 12. The method of claim 11, wherein forming a gap between the first and second type active regions on either side of the gate with a mask that protects the gate causes the body under the gate and the connecting portion under the gate to align with each other based on a shape of the gate.

13. 1. A semiconductor die comprising: A substrate; a semiconductor die mounted on the substrate, each transistor including a source and a drain each implemented in an active area of ​​a first type, a gate implemented relative to the source and the drain, a body implemented in the active area of ​​the first type and substantially covered by the gate, and a body tie implemented in an active area of ​​a second type, the transistor further including a connection portion connecting the body tie to the body, the connection portion and the gate being dimensioned such that the connection portion is exclusively under each portion of the gate and each portion of the gate is exclusively over the connection portion.

14. The semiconductor die of claim 13 , wherein the substrate comprises a silicon-on-insulator substrate.

15. The semiconductor die of claim 13 , wherein each transistor is configured as a radio frequency transistor.

16. The semiconductor die of claim 13 , wherein each transistor is configured as a digital cell transistor or a switching transistor.

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