Semiconductor device, display device, and electronic device

Abstract

To provide a semiconductor device that performs stable operations.SOLUTION: A semiconductor device has first to tenth transistors, and first to fourth capacitors. Gates of the first and fourth transistors are electrically connected to each other, and first terminals of the first, second, fifth, and eighth transistors are electrically connected to a first terminal of the fourth capacitor. A second terminal of the fifth transistor is electrically connected to a gate of the sixth transistor and a first terminal of the second capacitor, and a second terminal of the eighth transistor is electrically connected to a gate of the ninth transistor and a first terminal of the third capacitor. The gates of the second, seventh, and tenth transistors are electrically connected to a first terminal of each of the third and fourth transistors and a first terminal of the first capacitor. First terminals of the sixth and seventh transistors are electrically connected to a second terminal of the second capacitor, and first terminals of the ninth and tenth transistors are electrically connected to a second terminal of the third capacitor.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device, a display device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof. [Background technology]

[0003] In recent years, improvements have been made in various aspects of display devices included in electronic devices for XR (Extended Reality or Cross Reality), such as VR (Virtual Reality) and AR (Augmented Reality), mobile phones (e.g., smartphones), tablet information terminals, and notebook PCs (personal computers). For example, display devices have been developed with higher resolution, improved color reproducibility (NTSC ratio), smaller driver circuits, and reduced power consumption.

[0004] For example, in order to improve the display quality of display devices, development is underway to reduce variations in the characteristics of drive transistors included in pixels. In particular, Patent Document 1 describes an invention of a pixel circuit having a circuit that corrects the threshold voltage of a drive transistor.

[0005] Further, there is a technique of using a transistor in which an oxide semiconductor is used as a semiconductor thin film as a switching element included in a pixel circuit of a display device.

[0006] Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors. In addition to silicon-based semiconductor materials, oxide semiconductors have also attracted attention. Known oxide semiconductors include not only oxides of single-component metals such as indium oxide and zinc oxide, but also oxides of multi-component metals. Among multi-component metal oxides, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) has been particularly active.

[0007] Transistors using IGZO as an active layer have an extremely low off-state current (see Non-Patent Document 1), and LSIs and display devices that utilize this property have been reported (see Non-Patent Documents 2 and 3). Patent Document 2 also discloses an invention in which a transistor containing IGZO in the active layer is used in the pixel circuit of a display device. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2017-10000 A [Patent Document 2] Japanese Patent Application Laid-Open No. 2010-156963 [Non-patent literature]

[0009] [Non-Patent Document 1] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7 [Non-patent document 2] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p.T216-T217 [Non-patent document 3] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p.626-629 Summary of the Invention [Problem to be solved by the invention]

[0010] In manufacturing a semiconductor device, the channel formation regions of multiple transistors in the semiconductor device may be made of the same material, which may shorten the manufacturing process of the semiconductor device. Specifically, for example, the material may be a metal oxide such as IGZO.

[0011] However, while n-type semiconductors can be fabricated using metal oxides containing indium (e.g., In oxide) or metal oxides containing zinc (e.g., Zn oxide), fabricating p-type semiconductors is difficult due to mobility and reliability considerations. Therefore, when fabricating a semiconductor device, it is preferable to use a unipolar circuit composed of transistors containing n-type semiconductors (n-channel transistors).

[0012] Furthermore, an n-channel transistor containing a metal oxide in the channel formation region is likely to have a low threshold voltage due to the influence of the manufacturing process, etc. In other words, the leakage current that flows when the transistor is in the off state is likely to be large. Therefore, a semiconductor device including a transistor with a large leakage current may not operate as expected depending on the situation.

[0013] An object of one embodiment of the present invention is to provide a semiconductor device that operates stably.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a display device including the above-described semiconductor device.An object of one embodiment of the present invention is to provide an electronic device including the above-described display device.An object of one embodiment of the present invention is to provide a novel semiconductor device, a novel display device, or a novel electronic device.

[0014] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. [Means for solving the problem]

[0015] (1) One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. A first gate of the first transistor is electrically connected to a first gate of the fourth transistor, and one of a source or a drain of the first transistor is electrically connected to one of a source or a drain of the second transistor, one of a source or a drain of the fifth transistor, one of a source or a drain of the eighth transistor, and a first terminal of the fourth capacitor. The other of the source or the drain of the fifth transistor is electrically connected to a first gate of the sixth transistor and a first terminal of the second capacitor. The other of the source or the drain of the eighth transistor is electrically connected to a first gate of the ninth transistor and a first terminal of the third capacitor. A first gate of the second transistor is electrically connected to a first terminal of the first capacitor, one of a source or a drain of the third transistor, one of a source or a drain of the fourth transistor, a first gate of the seventh transistor, and a first gate of the tenth transistor. One of a source or a drain of the seventh transistor is electrically connected to one of a source or a drain of the sixth transistor and the second terminal of the second capacitor. One of a source or a drain of the tenth transistor is electrically connected to one of a source or a drain of the ninth transistor and the second terminal of the third capacitor.

[0016] (2) Another embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a first capacitor, a second capacitor, and a third capacitor. A first gate of the first transistor is electrically connected to one of a source or a drain of the eleventh transistor, and the other of the source or the drain of the eleventh transistor is electrically connected to a first gate of the fourth transistor. The other of the source or the drain of the first transistor is electrically connected to one of a source or a drain of the second transistor, one of a source or a drain of the fifth transistor, and one of a source or a drain of the eighth transistor. The other of the source or the drain of the fifth transistor is electrically connected to a first gate of the sixth transistor and a first terminal of the second capacitor. The other of the source or the drain of the eighth transistor is electrically connected to a first gate of the ninth transistor and a first terminal of the third capacitor. A first gate of the second transistor is electrically connected to a first terminal of the first capacitor, one of a source or a drain of the third transistor, one of a source or a drain of the fourth transistor, a first gate of the seventh transistor, and a first gate of the tenth transistor. One of a source or a drain of the seventh transistor is electrically connected to one of a source or a drain of the sixth transistor and the second terminal of the second capacitor. One of a source or a drain of the tenth transistor is electrically connected to one of a source or a drain of the ninth transistor and the second terminal of the third capacitor.

[0017] (3) Alternatively, in one embodiment of the present invention, in the above-described (2), a first gate of the eleventh transistor may be electrically connected to a second gate of the eleventh transistor.

[0018] (4) Another embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a first capacitor, a second capacitor, and a third capacitor. A first gate of the first transistor is electrically connected to one of a source or a drain of the eleventh transistor and one of a source or a drain of the twelfth transistor, and the other of the source or the drain of the eleventh transistor is electrically connected to a first gate of the eleventh transistor, a first gate of the fourth transistor, and the other of the source or the drain of the twelfth transistor. The one of the source or the drain of the first transistor is electrically connected to one of a source or a drain of the second transistor, one of a source or a drain of the fifth transistor, and one of a source or a drain of the eighth transistor. The other of the source or drain of the fifth transistor is electrically connected to the first gate of the sixth transistor and the first terminal of the second capacitor. The other of the source or drain of the eighth transistor is electrically connected to the first gate of the ninth transistor and the first terminal of the third capacitor. The first gate of the second transistor is electrically connected to the first terminal of the first capacitor, one of the source or drain of the third transistor, one of the source or drain of the fourth transistor, the first gate of the seventh transistor, and the first gate of the tenth transistor. One of the source or drain of the seventh transistor is electrically connected to one of the source or drain of the sixth transistor and the second terminal of the second capacitor. One of the source or drain of the tenth transistor is electrically connected to one of the source or drain of the ninth transistor and the second terminal of the third capacitor. The other of the source or drain of the sixth transistor is electrically connected to the first gate of the twelfth transistor.

[0019] (5) Alternatively, in one embodiment of the present invention, in any one of the above (1) to (4), a first gate of the fifth transistor may be electrically connected to a second gate of the fifth transistor, and a first gate of the eighth transistor may be electrically connected to a second gate of the eighth transistor.

[0020] (6) Another embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a first capacitor, a second capacitor, and a third capacitor. A first gate of the first transistor is electrically connected to a first gate of the fourth transistor, and one of a source or a drain of the first transistor is electrically connected to one of a source or a drain of the second transistor, one of a source or a drain of the fifth transistor, and one of a source or a drain of the eighth transistor. The other of the source or the drain of the fifth transistor is electrically connected to a first gate of the sixth transistor and a first terminal of the second capacitor. The other of the source or the drain of the eighth transistor is electrically connected to a first gate of the ninth transistor and a first terminal of the third capacitor. A first gate of the second transistor is electrically connected to a first terminal of the first capacitor, one of a source or a drain of the third transistor, one of a source or a drain of the fourth transistor, a first gate of the seventh transistor, a first gate of the tenth transistor, a second gate of the fifth transistor, and a second gate of the eighth transistor. One of a source or a drain of the seventh transistor is electrically connected to one of a source or a drain of the sixth transistor and the second terminal of the second capacitor. One of a source or a drain of the tenth transistor is electrically connected to one of a source or a drain of the ninth transistor and the second terminal of the third capacitor.

[0021] (7) Another embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a sixth transistor, a seventh transistor, a ninth transistor, a tenth transistor, a first capacitor, a second capacitor, and a third capacitor. A first gate of the first transistor is electrically connected to a first gate of the fourth transistor, and one of a source or a drain of the first transistor is electrically connected to one of a source or a drain of the second transistor, a first gate of the sixth transistor, a first terminal of the second capacitor, a first gate of the ninth transistor, and a first terminal of the third capacitor. The first gate of the second transistor is electrically connected to the first terminal of the first capacitor, one of a source or a drain of the third transistor, one of a source or a drain of the fourth transistor, a first gate of the seventh transistor, and a first gate of the tenth transistor. One of a source or a drain of the seventh transistor is electrically connected to one of a source or a drain of the sixth transistor and a second terminal of the second capacitor. One of the source or the drain of the tenth transistor is electrically connected to one of the source or the drain of the ninth transistor and the second terminal of the third capacitor.

[0022] (8) Alternatively, in one embodiment of the present invention, in any one of the above (1) to (7), a first gate of the first transistor may be electrically connected to a second gate of the first transistor, a first gate of the third transistor may be electrically connected to a second gate of the third transistor, a first gate of the sixth transistor may be electrically connected to a second gate of the sixth transistor, and a first gate of the ninth transistor may be electrically connected to a second gate of the ninth transistor.

[0023] (9) Alternatively, in one embodiment of the present invention, in any one of the above (1) to (8), the second gate of the seventh transistor may be electrically connected to the other of the source and the drain of the seventh transistor, and the second gate of the tenth transistor may be electrically connected to the other of the source and the drain of the tenth transistor.

[0024] (10) Alternatively, according to one embodiment of the present invention, in any one of the above (1) to (9), the second transistor and the fourth transistor may each have a multi-gate structure.

[0025] (11) Another embodiment of the present invention is a display device including a gate driver circuit having a shift register including the semiconductor device according to any one of (1) to (10) above, a source driver circuit, and a pixel array.

[0026] (12) Another embodiment of the present invention is an electronic device including the display device described above in (11) and a housing.

[0027] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are each an example of a semiconductor device. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device or may include a semiconductor device.

[0028] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connection relationships other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, and layers).

[0029] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, and a load) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0030] Note that if both an element and a power supply line (for example, VDD (high power supply potential), VSS (low power supply potential), GND (ground potential), or a wiring that provides a desired potential) are arranged between X and Y, it is not specified that X and Y are electrically connected. Note that if only a power supply line is arranged between X and Y, there is no other element between X and Y, so X and Y are directly connected. Therefore, if only a power supply line is arranged between X and Y, it can also be said that "X and Y are electrically connected." However, if both an element and a power supply line are arranged between X and Y, it can be said that X and the power supply line are electrically connected (through the element) and Y and the power supply line are electrically connected, but X and Y are not specified as being electrically connected. Note that, for example, if X and the gate of a transistor are electrically connected and Y and the source of the transistor are electrically connected, it is not specified that X and Y are electrically connected. Furthermore, if X and the gate of a transistor are electrically connected and Y and the drain of the transistor are electrically connected, it is not specified that X and Y are electrically connected. For example, if X and the drain of a transistor are electrically connected and Y and the source of the transistor are electrically connected, it is specified that X and Y are electrically connected. Note that if a capacitive element is disposed between X and Y, it may or may not be specified that X and Y are electrically connected. For example, in the configuration of a digital circuit or logic circuit, if a capacitive element is disposed between X and Y, it may not be specified that X and Y are electrically connected. On the other hand, for example, in the configuration of an analog circuit, if a capacitive element is disposed between X and Y, it may be specified that X and Y are electrically connected.

[0031] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (e.g., inverters, NAND circuits, and NOR circuits), signal conversion circuits (e.g., digital-to-analog conversion circuits, analog-to-digital conversion circuits, and gamma correction circuits), potential level conversion circuits (e.g., power supply circuits such as step-up circuits or step-down circuits, and level shifter circuits that change the potential level of a signal), voltage sources, current sources, switching circuits, amplifier circuits (e.g., circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, and buffer circuits), signal generation circuits, memory circuits, and control circuits) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, X and Y are considered to be functionally connected if a signal output from X is transmitted to Y.

[0032] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., when X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., when X and Y are connected without another element or circuit between them).

[0033] For example, it can be expressed as follows: "X, Y, the source (sometimes referred to as either the first terminal or the second terminal) and the drain (sometimes referred to as the other of the first terminal or the second terminal) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source of the transistor, the drain of the transistor, and Y." Or, it can be expressed as follows: "The source of the transistor is electrically connected to X, the drain of the transistor is electrically connected to Y, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y through the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are provided in this order." By specifying the order of connections in the circuit configuration using expressions similar to these examples, it is possible to distinguish between the source and drain of the transistor and determine the technical scope. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

[0034] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both wiring and an electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0035] Furthermore, in this specification and the like, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification and the like, a "resistance element" is intended to include a wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be, for example, 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0036] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. The terms "capacitive element," "parasitic capacitance," and "gate capacitance" can sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" can sometimes be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." The term "pair of electrodes" in "capacitance" can also be replaced with "pair of conductors," "pair of conductive regions," or "pair of regions." The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It can also be, for example, 1 pF or more and 10 μF or less.

[0037] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" may be interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of a transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0038] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Furthermore, when operating in the saturation region, the multi-gate structure can provide a voltage-current characteristic with a flat slope, whereby the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing a voltage-current characteristic with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0039] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors electrically connected in series. For example, when a circuit diagram shows one capacitor, this includes two or more capacitors electrically connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors electrically connected in series, with the gates of the transistors electrically connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors electrically connected in series or parallel, with the gates of the transistors electrically connected to each other.

[0040] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration and device structure. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0041] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0042] Furthermore, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0043] Furthermore, "electric current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of positively charged bodies is occurring" can be rephrased as "electrical conduction of negatively charged bodies is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "electric current" refers to the phenomenon of charge transfer (electrical conduction) accompanying the movement of carriers. Examples of carriers include electrons, holes, anions, cations, and complex ions. The carriers vary depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, and vacuums). Furthermore, the "direction of current" in wiring refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current flow and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified, the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0044] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0045] Furthermore, in this specification, terms indicating arrangement such as "above" and "below" may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "an insulator located on the upper surface of a conductor" can be rephrased as "an insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0046] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0047] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0048] Furthermore, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, in some cases or depending on the situation, the terms "film" and "layer" may not be used and may be replaced with other terms. For example, the terms "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" or "insulating film" may be changed to the term "insulator".

[0049] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, terms such as "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from multiple "electrodes," "wirings," and "terminals" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0050] Furthermore, in this specification and the like, terms such as "wiring," "signal line," or "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." The term "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, the term "signal" may be changed to the term "potential."

[0051] In this specification and the like, the term "impurities" in semiconductors refers to, for example, elements other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is silicon, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (excluding oxygen and hydrogen).

[0052] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Therefore, a switch may have two or more terminals for passing a current in addition to a control terminal. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific type as long as it can control a current.

[0053] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source electrode and drain electrode. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0054] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0055] In this specification, etc., a device fabricated using a metal mask or FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In this specification, etc., a device fabricated without using a metal mask or FMM may be referred to as a device with an MML (metal maskless) structure.

[0056] In this specification, a structure in which different light-emitting layers are formed or different light-emitting layers are painted for each color light-emitting device (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. In this specification, a light-emitting device that can emit white light may be referred to as a white light-emitting device. In addition, a white light-emitting device can be combined with a colored layer (e.g., a color filter) to form a full-color display device.

[0057] Light-emitting devices can be broadly divided into single-structure and tandem-structure devices. A single-structure device has one light-emitting unit between a pair of electrodes, and the light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission, two or more light-emitting layers may be selected so that the light emitted from each of the two or more light-emitting layers has a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary, a configuration in which the entire light-emitting device emits white light can be obtained. The same applies to light-emitting devices having three or more light-emitting layers.

[0058] A tandem-structured device preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. To obtain white light, light from the light-emitting layers of the multiple light-emitting units may be combined to obtain white light. The configuration for obtaining white light is the same as that of the single-structured device. In a tandem-structured device, it is preferable to provide an intermediate layer such as a charge-generating layer between the multiple light-emitting units.

[0059] Furthermore, when comparing the above-mentioned white light-emitting device (single structure or tandem structure) with a light-emitting device having an SBS structure, the light-emitting device having an SBS structure can reduce power consumption compared to the white light-emitting device. If you want to keep power consumption low, it is preferable to use a light-emitting device having an SBS structure. On the other hand, the manufacturing process of a white light-emitting device is simpler than that of a light-emitting device having an SBS structure, so it is preferable because it can reduce manufacturing costs or increase manufacturing yields.

[0060] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0061] According to one embodiment of the present invention, a semiconductor device that operates stably can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a display device including the above-described semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, an electronic device including the above-described display device can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device, a novel display device, or a novel electronic device can be provided.

[0062] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Note that the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0063] [Figure 1] 1A and 1B are circuit diagrams showing configuration examples of a semiconductor device. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of the display device. [Figure 3] 3A and 3B are circuit diagrams showing configuration examples of a semiconductor device. [Figure 4] FIG. 4 is a timing chart showing an example of the operation of the semiconductor device. [Figure 5] FIG. 5 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 6] 6A and 6B are circuit diagrams showing configuration examples of a semiconductor device. [Figure 7] 7A and 7B are circuit diagrams showing configuration examples of a semiconductor device. [Figure 8] FIG. 8 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 9] 9A and 9B are circuit diagrams showing configuration examples of a semiconductor device. [Figure 10] 10A and 10B are circuit diagrams showing configuration examples of a semiconductor device. [Figure 11] FIG. 11 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 12] 12A and 12B are circuit diagrams showing configuration examples of a semiconductor device. [Figure 13] FIG. 13 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 14] 14A and 14B are circuit diagrams showing configuration examples of a semiconductor device. [Figure 15] 15(A) and 15(B) are circuit diagrams showing configuration examples of a semiconductor device. [Figure 16] FIG. 16 is a circuit diagram showing a configuration example of a semiconductor device. [Figure 17] FIG. 17 is a layout diagram showing a configuration example of a semiconductor device. [Figure 18] FIG. 18 is a cross-sectional view showing a configuration example of a display device. [Figure 19] FIG. 19 is a block diagram showing an example of the configuration of a display device. [Figure 20] FIG. 20 is a block diagram showing an example of the configuration of an imaging device. [Figure 21] 21(A) and 21(B) are circuit diagrams showing examples of imaging pixels. [Figure 22] FIG. 22 is a block diagram showing an example of the configuration of a display device. [Figure 23] FIG. 23 is a block diagram showing an example of the configuration of a display device. [Figure 24] FIG. 24 is a cross-sectional view showing a configuration example of a display device. [Figure 25] 25(A) to 25(D) are schematic diagrams showing configuration examples of light-emitting devices. [Figure 26] FIG. 26 is a cross-sectional view showing a configuration example of a display device. [Figure 27] 27(A) and 27(B) are cross-sectional views showing examples of the configuration of a display device. [Figure 28] 28(A) and 28(B) are cross-sectional views showing examples of the configuration of a display device. [Figure 29] 29(A) and 29(B) are cross-sectional views showing examples of the configuration of a display device. [Figure 30]30(A) and 30(B) are cross-sectional views showing examples of the configuration of a display device. [Figure 31] 31A to 31F are cross-sectional views showing an example of a method for manufacturing a display device. [Figure 32] FIG. 32(A) is a circuit diagram showing an example of the configuration of a pixel circuit included in a display device, and FIG. 32(B) is a schematic perspective view showing an example of the configuration of a pixel circuit included in a display device. [Figure 33] 33(A) to 33(D) are circuit diagrams showing configuration examples of pixel circuits included in a display device. [Figure 34] 34(A) to 34(D) are circuit diagrams showing configuration examples of pixel circuits included in a display device. [Figure 35] 35(A) and 35(B) are plan views showing configuration examples of a light-emitting device and a light-receiving device included in a display device. [Figure 36] 36A to 36D are cross-sectional views showing examples of the configuration of a light-emitting device, a light-receiving device, and a connection electrode included in a display device. [Figure 37] 37(A) to 37(G) are plan views showing examples of pixels. [Figure 38] 38(A) to 38(F) are plan views showing examples of pixels. [Figure 39] 39(A) to 39(H) are plan views showing examples of pixels. [Figure 40] 40(A) to 40(D) ​​are plan views showing examples of pixels. [Figure 41] 41(A) to 41(D) are plan views showing an example of a pixel, and FIG. 41(E) is a cross-sectional view showing an example of a display device. [Figure 42] 42(A) and 42(B) are diagrams showing configuration examples of a display module. [Figure 43] 43(A) to 43(F) are diagrams showing configuration examples of electronic devices. [Figure 44] 44(A) to 44(D) are diagrams showing configuration examples of electronic devices. [Figure 45] 45(A) to 45(C) are diagrams showing configuration examples of electronic devices. [Figure 46] 46(A) to 46(H) are diagrams showing configuration examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0064] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can constitute a channel formation region of a transistor having one or more functions selected from an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0065] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0066] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0067] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even part of the content) described in that embodiment and another content (or even part of the content) described in one or more other embodiments.

[0068] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0069] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0070] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0071] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m,n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m,n]" is added to the reference numeral in the drawings, etc., the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0072] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0073] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described.

[0074] 2 shows a structural example of a display device including a semiconductor device according to one embodiment of the present invention. The display device DSP includes, for example, a driver circuit GD, a driver circuit SD, and a pixel array PA.

[0075] Note that Figure 2 shows only the driving circuit GD, the driving circuit SD, the pixel array PA, the wiring GL[1], the wiring GL[m], the wiring SL[1], the wiring SL[n], the pixel circuit PX[1,1], the pixel circuit PX[m,1], the pixel circuit PX[1,n], and the pixel circuit PX[m,n].

[0076] The pixel array PA includes, for example, a plurality of pixel circuits PX. The pixel circuits PX are arranged in a matrix of m rows and n columns in the pixel array PA.

[0077] 2 indicates the address of the pixel circuit. For example, the pixel circuit PX[1,1] indicates the pixel circuit PX arranged at row 1, column 1 in the pixel array PA. For example, the pixel circuit PX[m,1] indicates the pixel circuit PX arranged at row m, column 1 in the pixel array PA. For example, the pixel circuit PX[1,n] indicates the pixel circuit PX arranged at row 1, column n in the pixel array PA. For example, the pixel circuit PX[m,n] indicates the pixel circuit PX arranged at row m, column n in the pixel array PA.

[0078] Furthermore, the pixel circuit PX arranged in the i-th row and j-th column (i is an integer between 1 and m, and j is an integer between 1 and n) of the pixel array PA is referred to as pixel circuit PX[i,j] (not shown). As an example, the pixel circuit PX[i,j] is electrically connected to a wiring GL[i]. As an example, the pixel circuit PX[i,j] is electrically connected to a wiring SL[j].

[0079] For example, the driver circuit GD is electrically connected to the wirings GL[1] to GL[m], and the driver circuit SD is electrically connected to the wirings SL[1] to SL[n].

[0080] For example, each of the wirings GL[1] to GL[m] may be a wiring extending in the row direction in the pixel array PA. The [x] attached to the wiring GL indicates the row number to which the wiring extends. For example, the symbol GL[1] refers to a wiring extending in the first row in the pixel array PA. For example, the symbol GL[m] refers to a wiring extending in the mth row in the pixel array PA.

[0081] For example, each of the wirings SL[1] to SL[n] may be a wiring extending in the column direction in the pixel array PA. The symbol [y] attached to the wiring GL indicates the column number to which the wiring extends. For example, the symbol GL[1] refers to a wiring extending in the first column in the pixel array PA. The symbol GL[n] refers to a wiring extending in the nth column in the pixel array PA.

[0082] The pixel circuits PX may be pixel circuits to which one or more selected from a liquid crystal display device, a light-emitting device containing an organic EL material, and a light-emitting device containing a light-emitting diode (e.g., a micro LED) are applied. In this embodiment, the pixel circuits PX of the pixel array PA are described as being applied with a light-emitting device containing an organic EL material. In particular, the luminance of light emitted from a light-emitting device capable of emitting light with high luminance is, for example, 500 cd / m 2 or more, preferably 1000 cd / m 2 More than 10000cd / m 2 or less, more preferably 2000 cd / m 2 More than 5000cd / m 2 The following can be set: Note that pixel circuits that can be applied to the pixel circuit PX and the like will be described in detail in the fourth embodiment.

[0083] For example, the driving circuit GD has a function of selecting a pixel circuit PX to which image data is to be sent in the pixel array PA of the display device DSP. For this reason, the driving circuit GD can be called a gate driver circuit or the like.

[0084] As described above, the wiring GL electrically connecting the driving circuit GD and the pixel circuit PX functions as, for example, a wiring for transmitting a selection signal. Note that the wiring GL may function as, for example, a wiring for supplying a constant potential instead of a wiring for transmitting a selection signal.

[0085] For example, the drive circuit SD has a function of transmitting image data to the pixel circuits PX in the pixel array PA of the display device DSP, and therefore the drive circuit SD can be called a source driver circuit or the like.

[0086] As described above, the wiring SL electrically connecting the drive circuit SD and the pixel circuit PX functions as, for example, a wiring that transmits image data as a signal. Note that the wiring SL may function as, for example, a wiring that supplies a constant potential instead of a wiring that transmits image data.

[0087] 2 may have wirings other than the wirings GL[1] to GL[m] and the wirings SL[1] to SL[n] extended thereto. For example, the display device DSP may have wirings extended thereto that apply a constant potential to be supplied to the pixel circuits PX.

[0088] Next, an example of the configuration of the drive circuit GD will be described.

[0089] Fig. 3A illustrates a configuration example of a driver circuit GD according to one embodiment of the present invention, which can be applied to the display device DSP in Fig. 2. The driver circuit GD illustrated in Fig. 3A includes, for example, circuits 100[1] to 100[m].

[0090] Each of the circuits 100[1] to 100[m] has, for example, a terminal IT, a terminal OT, a terminal CLK1, a terminal CLK2, and a terminal GT.

[0091] In each of the circuits 100[1] to 100[m], for example, the terminal CLK1 is electrically connected to the wiring CL1, the terminal CLK2 is electrically connected to the wiring CL2, and the terminal PWC is electrically connected to the wiring PL.

[0092] Each of the wirings CL1, CL2, and PL functions as a wiring that applies a variable potential (sometimes referred to as a pulse voltage in this specification) such as a clock signal. Note that one or more selected from the wirings CL1, CL2, and PL may be a wiring that applies a constant potential instead of a variable potential.

[0093] A terminal OT of the circuit 100[k] (k is an integer between 1 and m-1) is electrically connected to, for example, a terminal IT of the circuit 100[k+1].

[0094] The terminal GT of the circuit 100[i] is electrically connected to, for example, the wiring GL[i].

[0095] For example, each of the circuits 100[1] to 100[m] has a function of holding information input to a terminal IT and a function of outputting the held information to one or both of a terminal OT and a terminal GT.

[0096] For example, the circuit 100[i] has a function of outputting the information held in the circuit 100[i] to the terminal OT when a variable potential is input to the terminal CLK1. For example, the circuit 100[i] has a function of outputting the information held in the circuit 100[i] to the terminal GT when a variable potential is input to the terminal PWC. For example, the circuit 100[i] has a function of resetting the information held in the circuit 100[i] when a variable potential is input to the terminal CLK2. Preferably, the circuit 100[i] is configured such that after the information held in the circuit 100[i] is reset, new information is input to the terminal IT of the circuit 100[i], thereby holding the new information in the circuit 100[i].

[0097] As described above, in the circuits 100[1] to 100[m], after information is input to the terminal IT of the circuit 100[1], a variable potential is input to the terminals CLK1 and CLK2 at appropriate timing, thereby allowing the information to be sequentially transmitted to the circuits 100[2] and subsequent circuits. Furthermore, after information is input to the terminal IT of the circuit 100[1], a variable potential is input to the terminal PWC at appropriate timing, allowing the information held in each of the circuits 100[1] to 100[m] to be output from the terminal GT of each of the circuits 100[1] to 100[m]. For this reason, in this specification and the like, the configuration of the circuits 100[1] to 100[m] can be referred to as a shift register.

[0098] The information may be, for example, a selection signal for selecting a pixel circuit PX in the pixel array PA to which image data is written. In FIG. 3A, the selection signal is illustrated as a signal SS.

[0099] In the driver circuit GD shown in FIG. 3A, the terminal OT is illustrated in the circuit 100[m]. However, since the circuits 100[1] to 100[m] are configured as shift registers, the circuit 100[m] may not be provided with the terminal OT.

[0100] Furthermore, the configuration of the driver circuit GD that can be applied to the display device DSP of Fig. 2 is not limited to Fig. 3(A). For example, the configuration of the driver circuit GD that can be applied to the display device DSP of Fig. 2 may be the driver circuit GD shown in Fig. 3(B).

[0101] The driver circuit GD in FIG. 3B differs from the driver circuit GD in FIG. 3A in that it includes circuits BF[1] to BF[m].

[0102] In the driver circuit GD of Figure 3(B), the input terminals of the circuits BF[1] to BF[m] are electrically connected to the terminals GT of the circuits 100[1] to 100[m] in a one-to-one relationship, and the output terminals of the circuits BF[1] to BF[m] are electrically connected to the wirings GL[1] to GL[m] in a one-to-one relationship.

[0103] Each of the circuits BF[1] to BF[m] can include an amplifier circuit such as a buffer circuit, an inverter circuit, or a latch circuit. Specifically, each of the circuits BF[1] to BF[m] can have a function of referring to the potential of the terminal GT and outputting the amplified potential to the wiring GL.

[0104] 3A and 3B, wirings other than the wirings CL1, CL2, and PL may be extended. For example, wirings that apply a constant potential for driving each of the circuits 100[1] to 100[m] may be extended.

[0105] <Configuration example 1> Next, examples of specific circuit configurations of the circuits 100[1] to 100[m] of the driver circuits GD in each of FIGS. 3A and 3B will be described.

[0106] 1A shows a configuration example of a circuit that can be applied to the circuits 100[1] to 100[m] of the driver circuits GD in each of FIGS. 3A and 3B, which are semiconductor devices of one embodiment of the present invention. The circuit 100A1 includes, for example, transistors MN1 to MN10 and capacitors C1, C2, and C3. The circuit 100A1 also includes, for example, terminals IT, PWC, CLK1, CLK2, GT, and OT.

[0107] It is preferable to use, for example, OS transistors as the transistors MN1 to MN10. In particular, the metal oxide contained in the channel formation region of the OS transistor is, for example, an In-M-Zn oxide containing indium, an element M, and zinc (the element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium). Alternatively, the transistor may be a transistor having silicon in the channel formation region (hereinafter referred to as a Si transistor). The silicon may be, for example, single crystal silicon, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, or polycrystalline silicon. Examples of transistors that can be used other than OS transistors and Si transistors include transistors containing germanium (Ge) or the like in a channel formation region, transistors containing a compound semiconductor such as zinc selenide (ZnSe), cadmium sulfide (CdS), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), or silicon germanium (SiGe) in a channel formation region, transistors containing carbon nanotubes in a channel formation region, and transistors containing an organic semiconductor in a channel formation region.

[0108] The transistors MN1 to MN10 shown in FIG. 1A are, for example, n-channel transistors with a multi-gate structure having gates above and below the channel, and each of the transistors MN1 to MN10 has a first gate and a second gate. However, for convenience, in this specification and the like, the first gate may be distinguished as a gate (sometimes referred to as a front gate) and the second gate as a back gate. Furthermore, in this specification and the like, the first gate and the second gate are interchangeable, and therefore the term "gate" may be interchangeable with the term "back gate." Similarly, the term "back gate" may be interchangeable with the term "gate." As a specific example, a connection configuration in which "the gate is electrically connected to a first wiring, and the back gate is electrically connected to a second wiring" may be replaced with a connection configuration in which "the back gate is electrically connected to the first wiring, and the gate is electrically connected to the second wiring."

[0109] In addition, in the semiconductor device of one embodiment of the present invention, the connection configuration of the second gate of the transistor may be changed within the scope of solving the problem. Although the second gate and the connection destination of the second gate are illustrated in each of the transistors MN1 to MN10 in FIG. 1A, for example, when a wiring, a terminal, or a circuit element is electrically connected to both the first gate and the second gate of the same transistor, the configuration may be changed so that the wiring, the terminal, or the circuit element is electrically connected to either the first gate or the second gate.

[0110] Furthermore, the semiconductor device of one embodiment of the present invention does not depend on the structure of the transistors included in the semiconductor device. For example, each of the transistors MN1 to MN10 illustrated in FIG. 1A may have a structure without a back gate, that is, a single-gate transistor. Furthermore, some of the transistors may have a back gate, and other transistors may have a structure without a back gate.

[0111] This also applies to transistors described elsewhere in the specification or transistors illustrated in other drawings, as well as to transistors illustrated in FIG. 1A.

[0112] The first terminal of transistor MN1 is electrically connected to wiring VDE1, the second terminal of transistor MN1 is electrically connected to the first terminal of transistor MN2, the first terminal of transistor MN5, and the first terminal of transistor MN8, and the first gate of transistor MN1 is electrically connected to the second gate of transistor MN1, the first gate of transistor MN4, and terminal IT.

[0113] In addition, the first terminal of transistor MN3 is electrically connected to wiring VDE2, the second terminal of transistor MN3 is electrically connected to the first gate of transistor MN2, the first terminal of capacitor C1, the first terminal of transistor MN4, the first gate of transistor MN7, and the first gate of transistor MN10, and the first gate of transistor MN3 is electrically connected to the second gate of transistor MN3 and terminal CLK2.

[0114] The second terminal of transistor MN5 is electrically connected to the first gate of transistor MN6, the second gate of transistor MN6, and the first terminal of capacitor C2, the first gate of transistor MN5 is electrically connected to the second gate of transistor MN5 and wiring VDE3, the first terminal of transistor MN6 is electrically connected to terminal CLK1, and the second terminal of transistor MN6 is electrically connected to the second terminal of capacitor C2, the first terminal of transistor MN7, and terminal OT.

[0115] The second terminal of transistor MN8 is electrically connected to the first gate of transistor MN9, the second gate of transistor MN9, and the first terminal of capacitor C3, and the first gate of transistor MN8 is electrically connected to the second gate of transistor MN8 and the wiring VDE4. The first terminal of transistor MN9 is electrically connected to terminal PWC, and the second terminal of transistor MN9 is electrically connected to the second terminal of capacitor C3, the first terminal of transistor MN10, and terminal GT.

[0116] The second terminal of the transistor MN2 is electrically connected to the wiring VSE1, and the second gate of the transistor MN2 is electrically connected to the wiring BG1. The second terminal of the capacitor C1 is electrically connected to the wiring VSE2. The second terminal of the transistor MN4 is electrically connected to the wiring VSE3, and the second gate of the transistor MN4 is electrically connected to the wiring BG2. The second terminal of the transistor MN7 is electrically connected to the second gate of the transistor MN7 and the wiring VSE4. The second terminal of the transistor MN10 is electrically connected to the second gate of the transistor MN10 and the wiring VSE5.

[0117] 1A, the electrical connection point between the second terminal of transistor MN1, the first terminal of transistor MN2, the first terminal of transistor MN5, and the first terminal of transistor MN8 is illustrated as node N1. Also, in FIG. 1A, the electrical connection point between the second terminal of transistor MN3, the first gate of transistor MN2, the first terminal of capacitor C1, the first terminal of transistor MN4, the first gate of transistor MN7, and the second gate of transistor MN10 is illustrated as node N2.

[0118] For example, each of the wirings VDE1 to VDE4 functions as a wiring that applies a constant potential. The constant potential can be, for example, a high-level potential. The wirings VDE1 to VDE4 may be applied with the same constant potential or different constant potentials. Two or more selected wirings from each of the wirings VDE1 to VDE4 may be applied with the same constant potential, and the remaining wirings may be applied with a potential different from the constant potential. Two or more wirings among the wirings VDE1 to VDE4 that apply the same constant potential may be the same wiring. For example, if the wirings VDE1 and VDE2 apply the same constant potential, the wirings VDE1 and VDE2 may be the same wiring.

[0119] Furthermore, one or more selected from the wirings VDE1 to VDE4 may be wirings that apply a variable potential instead of a constant potential.

[0120] For example, each of the wirings VSE1 to VSE5 functions as a wiring that applies a constant potential. The constant potential can be, for example, a low-level potential, a ground potential, or a negative potential. The wirings VSE1 to VSE5 may be applied with the same constant potential or different constant potentials. Two or more selected wirings from each of the wirings VSE1 to VSE5 may be applied with the same constant potential, and the remaining wirings may be applied with a potential different from the constant potential. Two or more wirings from each of the wirings VSE1 to VSE5 that apply the same constant potential may be the same wiring. For example, when the wirings VSE1 and VSE2 apply the same constant potential, the wirings VSE1 and VSE2 may be the same wiring.

[0121] Furthermore, one or more of the wirings VSE1 to VSE5 may be wirings that apply a variable potential instead of a constant potential.

[0122] For example, the wiring BG1 and the wiring BG2 each function as a wiring that applies a constant potential. The constant potential can be, for example, a low-level potential, a ground potential, or a negative potential. The wiring BG1 and the wiring BG2 may be applied with the same constant potential or different constant potentials. Furthermore, when the wiring BG1 and the wiring BG2 each apply with the same constant potential, the wiring BG1 and the wiring BG2 may be the same wiring.

[0123] One or both of the wirings BG1 and BG2 may be wirings that apply a variable potential instead of a constant potential.

[0124] <<Example 1>> Here, an example of the operation of the circuit 100A1 shown in FIG. 1A will be described.

[0125] 4 is a timing chart showing an example of the operation of the circuit 100A1. The timing chart shown in FIG. 4 shows, as an example, fluctuations in the potentials of the terminal IT, the terminal PWC, the terminal CLK1, the terminal CLK2, the node N1, the node N2, the terminal GT, and the terminal OT. In FIG. 4, the high-level potential is V High and the low level potential is V Low It is written as follows.

[0126] Note that the timing chart of Figure 4 is intended to simply explain the operation of circuit 100A1, so the length of the input period and the length of the output period of the signals shown in the timing chart of Figure 4 may differ from the actual circuit operation.

[0127] In this operation example, the constant potentials provided by the wirings VDE1 to VDE4 are equal to each other at high level potentials (V High ) The constant potentials applied to the wirings VSE1 to VSE5 are set to the same low-level potential (V Low ) and the constant potential given by the wiring BG1 is a low level potential (V LL ), and the constant potential given by the wiring BG2 is the low level potential (V Low) Note that V LL is V Low In particular, V LL is preferably a negative potential.

[0128] In addition, V High and V Low Each of the V High and V Low It is preferable that the potential difference between these potentials be higher than the threshold voltages of the transistors MN1 to MN10.

[0129] [From time T1 to time T2] Between time T1 and time T2, terminal IT is connected to V Low is applied to the terminal PWC, and V Low is applied to terminal CLK1, and V Low is applied to terminal CLK2, and V Low Also, for example, V is given to node N2. High -V th_MN3 It is assumed that V th_MN3 is the threshold voltage of transistor MN3.

[0130] The first gate of transistor MN3 is connected to V from terminal CLK2. Low is applied to the first terminal of the transistor MN3, and V High is given, and the potential of the second terminal (node ​​N2) of transistor MN3 is V High -V th_MN3 At this time, the potential of the second terminal of the transistor MN3 is lower than the potential of the first terminal, so the second terminal of the transistor MN3 becomes the source. Also, the gate-source voltage of the transistor MN3 is V Low -(V High -V th_MN3 ) V th_MN3 is within the appropriate range of threshold voltage, V Low -(V High -V th_MN3 ) becomes lower than 0V, so that transistor MN3 is turned off.

[0131] The potential of the first gate (node ​​N2) of transistor MN2 is V High -V th_MN3 The second terminal of the transistor MN2 is connected to the V Low , the transistor MN2 is turned on. This brings the node N1 and the wiring VSE1 into a conductive state, and the potential of the node N1 rises to V Low This becomes:

[0132] In addition, the potential of the first gate (terminal IT) of transistor MN1 is V Low and the potential of the second terminal (node ​​N1) of the transistor MN1 is V Low Therefore, the transistor MN1 is turned off.

[0133] The first gate of the transistor MN5 is connected to the V High is given, and the potential of the first terminal (node ​​N1) of the transistor MN5 becomes V Low Therefore, the transistor MN5 is turned on. As a result, the line VSE1 and the first gate of the transistor MN6 are electrically connected, and the potential of the first gate of the transistor MN6 becomes V Low This becomes:

[0134] The first gate of the transistor MN8 is connected to the V High is given, and the potential of the first terminal (node ​​N1) of the transistor MN8 becomes V Low Therefore, the transistor MN8 is turned on. As a result, the line VSE1 and the first gate of the transistor MN9 are electrically connected, and the potential of the first gate of the transistor MN9 is V Low This becomes:

[0135] The potential of the first gate (node ​​N2) of transistor MN7 is V High -V th_MN3 The second terminal of the transistor MN7 is connected to the V Lowis applied, the transistor MN7 is turned on. Therefore, the terminal OT and the wiring VSE4 are in a conductive state, and the potential of the terminal OT becomes V Low This becomes:

[0136] Also, the potential of the first gate of transistor MN6 is V Low and the potential of the second terminal (terminal OT) of the transistor MN6 is V Low Therefore, the transistor MN6 is turned off.

[0137] The potential of the first gate (node ​​N2) of transistor MN10 is V High -V th_MN3 The second terminal of the transistor MN10 is connected to the V Low is applied, the transistor MN10 is turned on. As a result, the terminal GT and the wiring VSE5 are electrically connected, and the potential of the terminal GT becomes V Low This becomes:

[0138] Also, the potential of the first gate of transistor MN9 is V Low and the potential of the second terminal (terminal GT) of the transistor MN9 is V Low Therefore, the transistor MN9 is turned off.

[0139] The potential of the first gate (terminal IT) of transistor MN4 is V Low The second terminal of the transistor MN4 is connected to the V Low is applied, the transistor MN4 is turned off.

[0140] Here, consider the case where transistor MN1, transistor MN3, transistor MN4, transistor MN6, or transistor MN9, which is in the off state, is normally on.

[0141] In this specification and the like, "normally on" refers to a state in which a channel exists even when no voltage is applied to the gate, and a current flows through the transistor. Alternatively, "normally on" refers to a state in which a channel exists even when the gate-source voltage is 0 V, and a current flows through the transistor. Furthermore, "normally off" refers to a state in which no current flows through the transistor when no potential is applied to the gate or when a ground potential is applied to the gate. Furthermore, "normally off" in an OS transistor refers to a state in which the current flowing through the transistor per 1 μm of channel width is 1×10 at room temperature when no potential is applied to the gate or when a ground potential is applied to the gate. -20 A or less, 1 x 10 at 85°C -18 A or less, or 1 x 10 at 125°C -16 This means that it is A or below.

[0142] When the transistor MN1 is normally on, a current flows from the wiring VDE1 to the node N1. Therefore, the potential of the node N1 is V Low In addition, a short-circuit current flows between the wiring VDE1 and the wiring VSE1, which may increase the power consumption of the circuit 101A1. Note that even if the transistor MN1 is normally on, the potential of the node N1 may be higher than V Low If the source-drain current of transistor MN2 does not vary significantly from the source-drain current of transistor MN1 (for example, if the source-drain current of transistor MN2 is greater than the source-drain current of transistor MN1), circuit 101A1 may operate normally.

[0143] In transistor MN3, the gate-source voltage of transistor MN3, V Low -(V High -V th_MN3 ) is the threshold voltage V th_MN3 Since the voltage Vcc is lower than the reference voltage Vcc, even if the transistor MN3 is normally on, the transistor MN3 is in an off state.

[0144] When the transistor MN4 is normally on, a current flows from the node N2 to the wiring VSE3. Therefore, the potential of the node N2 is V High -V th_MN3 In some cases, the potential of the node N2 may be lower than the threshold voltage of the transistor MN4. As a means for preventing a decrease in the potential of the node N2, it is preferable to increase the capacitance of the capacitor C1, for example. Alternatively, it is also possible to increase the number of capacitors electrically connected to the node N2, for example. Alternatively, it is preferable to increase the threshold voltage of the transistor MN4 by lowering the potential of the wiring BG2 electrically connected to the second gate of the transistor MN4, for example.

[0145] The potential at the first terminal of transistor MN6 is V Low and the potential of the second terminal (terminal OT) of the transistor MN6 is V Low Therefore, even if the transistor MN6 is normally on, the potential of the terminal OT does not change.

[0146] Similarly, the potential at the first terminal of transistor MN9 is V Low and the potential of the second terminal (terminal GT) of transistor MN9 is V Low Therefore, even if the transistor MN9 is normally on, the potential of the terminal GT does not change.

[0147] [From time T2 to time T3] Between time T2 and time T3, V High is given.

[0148] In the transistor MN3, the first gate of the transistor MN3 is connected to V from the terminal CLK2. High is applied to the first terminal of the transistor MN3, and V High At this time, for example, the potential of the second terminal (node ​​N2) of the transistor MN3 is V High -V th_MN3 When the voltage VDE2 is lower than the threshold voltage VDE1, the transistor MN3 is turned on, and therefore conduction is established between the wiring VDE2 and the node N2.

[0149] When the transistor MN3 is in an on state, a current flows from the wiring VDE2 to the node N2, and the potential of the node N2 increases. th_MN3 Therefore, the potential of node N2 (the second terminal of transistor MN3) is V High -V th_MN3 When the voltage rises to , transistor MN3 is turned off.

[0150] In addition, between time T2 and time T3, V High After this is applied, V is applied to the CLK2 pin. Low This gives the gate-source voltage of transistor MN3 as V Low -(V High -V th_MN3 ) and V th_MN3 is within the appropriate range of threshold voltage, transistor MN3 is in the off state.

[0151] By the above operation, the circuit 100A1 outputs V High is applied, the potential of node N2 is V High -V th_MN3 You can refresh yourself.

[0152] [From time T3 to time T4] Between time T3 and time T4, terminal IT is connected to V Low is applied to the terminal PWC, and V Low is applied to terminal CLK1, and V Low is applied to terminal CLK2, and V Low The potentials input to the terminals IT, PWC, CLK1, and CLK2 from time T3 to time T4 are equal to the potentials input to the terminals IT, PWC, CLK1, and CLK2 from time T1 to time T2, respectively. Therefore, for an operation example of the circuit 100A1 from time T3 to time T4, refer to the description of the operation example from time T1 to time T2.

[0153] [From time T4 to time T5] Between time T4 and time T5, terminal IT is connected to V High is given.

[0154] The first gate of transistor MN4 is connected to V from terminal IT. High is applied to the second terminal of transistor MN4, and the voltage V is applied to the second terminal of transistor MN4 from the line VSE3 to V Low , the transistor MN4 is turned on. This brings the node N2 and the wiring VSE3 into a conductive state, and the potential of the node N2 rises to V High -V th_MN3 From V Low changes to.

[0155] Furthermore, from the above, the potential of the first gate (node ​​N2) of transistor MN2 is V Low and the second terminal of the transistor MN2 receives V Low is applied, the transistor MN2 is turned off.

[0156] Furthermore, from the above, the potential of the first gate (node ​​N2) of the transistor MN7 is V Low The second terminal of the transistor MN7 is connected to the V Low is applied, the transistor MN7 is turned off.

[0157] Furthermore, from the above, the potential of the first gate (node ​​N2) of the transistor MN10 is V Low The second terminal of the transistor MN10 is connected to the V Low is applied, the transistor MN10 is turned off.

[0158] The first gate of transistor MN1 is connected to V from terminal IT. High is applied to the first terminal of the transistor MN1, and V High is given, and the potential of the second terminal (node ​​N2) of transistor MN1 is V LowAt this time, the transistor MN1 is turned on, so that the line VDE1 and the node N1 are electrically connected.

[0159] When the transistor MN1 is in an on state, a current flows from the wiring VDE1 to the node N1, and the potential of the node N1 increases. th_MN1 As a result, the potential of node N1 (the second terminal of transistor MN1) becomes V High -V th_MN1 When the voltage rises to , transistor MN1 is turned off.

[0160] Between time T4 and time T5, V High is input, the potential V of node N1 (the second terminal of transistor MN1) High -V th_MN1 If the voltage drops for some reason, the transistor MN1 turns on again, current flows from the wiring VDE1 to the node N1, and the potential of the node N1 (the second terminal of the transistor MN1) rises to V High -V th_MN1 Also, the potential at the second terminal of transistor MN1 rises to V High -V th_MN1 When the voltage rises to , transistor MN1 turns off again.

[0161] The first gate of transistor MN5 is connected to VDE3 High is applied to the first terminal (node ​​N1) of transistor MN5, and V High -V th_MN1 The potential at the second terminal of transistor MN5 is V Low At this time, the potential of the second terminal of transistor MN5 is lower than the potential of the first terminal, so the second terminal of transistor MN5 becomes the source, and transistor MN5 is turned on. This brings the connection between node N1 and the first gate of transistor MN6 into conduction.

[0162] When the transistor MN5 is in an on state, a current flows from the node N1 to the first gate of the transistor MN6, and the potential of the first gate of the transistor MN6 becomes high. th_MN5 For example, V th_MN5 V th_MN1 When the threshold voltage is equal to or greater than V, the potential of the first gate of the transistor MN6 is V High -V th_MN5 When the voltage rises to V, the transistor MN5 is turned off. th_MN5 V th_MN1 When the threshold voltage of the transistor MN6 is less than V High -V th_MN1 At this time, the gate-source voltage V High -(V High -V th_MN1 )=V th_MN1 is the threshold voltage V of transistor MN5 th_MN5 Since the voltage V is higher than V, the transistor MN5 is turned on. In this configuration example, it is preferable that the transistor MN5 is turned off between time T4 and time T5 in this operation example. th_MN5 is V th_MN1 It is preferable that the threshold voltage is equal to or higher than V th_MN5 In this example of operation, the potential of the second terminal of the transistor MN5 (the first gate of the transistor MN6) is preferably V High -V th_MN5 When it reaches (V th_MN5 V th_MN1 This section explains the cases where the

[0163] The potential of the first gate of transistor MN6 is V High -V th_MN5 The first terminal of the transistor MN6 is connected to V from the terminal CLK1. Low is given, and the potential of the second terminal of transistor MN6 is V LowAt this time, the first or second terminal of the transistor MN6 becomes the source, and the transistor MN6 is turned on. This causes a state of conduction between the terminal CLK1 and the terminal OT. Note that, before time T4, the terminal CLK1 has had V Low Therefore, the potential of the second terminal (terminal OT) of transistor MN6 is V Low It remains unchanged.

[0164] The first gate of transistor MN8 is connected to VDE4 High is applied to the first terminal (node ​​N1) of transistor MN8, and V High -V th_MN1 is given, and the potential of the second terminal of transistor MN8 is V Low At this time, the potential of the second terminal of transistor MN8 is lower than the potential of the first terminal, so the second terminal of transistor MN8 becomes the source, and transistor MN8 is turned on. This brings the state of conduction between node N1 and the first gate of transistor MN9.

[0165] When the transistor MN8 is in the on state, a current flows from the node N1 to the first gate of the transistor MN9, and the potential of the first gate of the transistor MN9 becomes high. th_MN8 For example, V th_MN8 V th_MN1 When the threshold voltage is equal to or greater than V, the potential of the first gate of transistor MN9 is V High -V th_MN8 When the voltage rises to V, the transistor MN8 is turned off. th_MN8 V th_MN1 When the threshold voltage of transistor MN9 is less than V High -V th_MN1 At this time, the gate-source voltage V High -(V High -V th_MN1 )=V th_MN1 is the threshold voltage V of transistor MN8 th_MN8Since the voltage V is higher than V, the transistor MN8 is turned on. In this configuration example, it is preferable that the transistor MN8 is turned off between time T4 and time T5 in this operation example. th_MN8 is V th_MN1 It is preferable that the threshold voltage is equal to or higher than V th_MN8 It is more preferable that the potential of the second terminal of the transistor MN8 (the first gate of the transistor MN9) is V High -V th_MN8 When it reaches (V th_MN8 V th_MN1 This section explains the cases where the

[0166] The potential of the first gate of transistor MN9 is V High -V th_MN8 The first terminal of the transistor MN9 is connected to the V Low is given, and the potential at the second terminal of transistor MN9 is V Low At this time, the first terminal or the second terminal of the transistor MN9 becomes the source, and the transistor MN9 is turned on. This brings the terminal PWC and the terminal GT into a conductive state. Note that, before time T4, the terminal PWC has been connected to V Low is given, the potential at terminal OT is V Low It remains unchanged.

[0167] In addition, between time T4 and time T5, V High After the voltage is applied, V is applied to the terminal IT. Low This gives the gate-source voltage of transistor MN1 as V Low -(V High -V th_MN1 ) and V th_MN1 is within the appropriate range of threshold voltage, transistor MN1 is in the off state.

[0168] The first gate of transistor MN4 is connected to V from terminal IT. Low The second terminal of transistor MN4 is supplied with V from line VSE3.Low , the transistor MN4 is turned off. This causes the node N2 to have a potential V Low is maintained.

[0169] [From time T5 to time T6] Between time T5 and time T6, V High is given.

[0170] The potential of the first gate of transistor MN6 is V High -V th_MN5 The first terminal of the transistor MN6 is connected to V from the terminal CLK1. High is given, and the potential of the second terminal of transistor MN6 is V Low The threshold voltage of transistor MN6 is V th_MN6 The gate-source voltage of transistor MN6 is V High -V Low -V th_MN5 is the threshold voltage of transistor MN6, V th_MN6 When the voltage Vout becomes higher than 1, the transistor MN6 is turned on, which brings the terminal CLK1 and the terminal OT into a conductive state.

[0171] When transistor MN6 is in the on state, current flows from terminal CLK1 to terminal OT, causing the potential of the second terminal (terminal OT) of transistor MN6 to rise. Furthermore, as the potential of the second terminal (terminal OT) of transistor MN6 rises, the potential of the first gate of transistor MN6 also rises due to capacitive coupling by capacitor C2. Therefore, the potential of the second terminal (terminal OT) of transistor MN6 rises to V High -V th_MN6 In this example, the potential V High In addition, the potential of the first gate of the transistor MN6 at this time is equal to (V High -V th_MN5 )+(V High -V Low )=2V High -V Low -V th_MN5In this operation example, increasing the gate potential in accordance with an increase in the potential of the first terminal or the second terminal of the transistor using capacitive coupling is called bootstrap.

[0172] Here, consider the case where the transistor MN1, the transistor MN3, or the transistor MN4, which is in the OFF state between time T5 and time T6, is in the normally ON state.

[0173] In transistor MN1, the gate-source voltage of transistor MN1, V Low -(V High -V th_MN1 ) is the threshold voltage V th_MN1 Since the voltage Vcc is lower than the voltage Vcc, even if the transistor MN1 is normally on, the transistor MN1 is in an off state.

[0174] When the transistor MN3 is normally on, a current flows from the wiring VDE2 to the node N2. Therefore, the potential of the node N2 is V Low In addition, when the potential of the node N2 increases, the potential of the first gate of the transistor MN2 also increases. Even if the transistor MN3 is normally on, the potential of the node N2 may be higher than V Low If the potential at node N2 rises slightly from , the gate-source voltage of transistor MN3 may fall below the threshold voltage, turning transistor MN3 off. Also, if the threshold voltage of transistor MN2 is sufficiently large, transistor MN2 can maintain the off state even if the potential at node N2 rises due to the normally-on characteristics of transistor MN3, and as a result, circuit 101A1 may operate normally.

[0175] In the transistor MN4, the potential of the first terminal (node ​​N2) of the transistor MN4 is V Low and the potential of the second terminal (wire VSE3) of the transistor MN4 is V LowTherefore, even if the transistor MN4 is normally on, the potential of the node N2 does not change.

[0176] [From time T6 to time T7] Between time T6 and time T7, V is applied to the terminal PWC. High is given.

[0177] The potential of the first gate of transistor MN9 is V High -V th_MN8 The first terminal of the transistor MN9 is connected to the V High is given, and the potential at the second terminal of transistor MN9 is V Low The threshold voltage of transistor MN9 is V th_MN9 The gate-source voltage of transistor MN9 is V High -V Low -V th_MN8 is the threshold voltage of transistor MN9, V th_MN9 When the voltage Vcc becomes higher than 1, the transistor MN9 is turned on, thereby bringing the terminal PWC and the terminal GT into a conductive state.

[0178] When transistor MN9 is in the on state, current flows from terminal PWC to terminal GT, causing the potential of the second terminal (terminal GT) of transistor MN9 to rise. Furthermore, as the potential of the second terminal (terminal GT) of transistor MN9 rises, the potential of the first gate of transistor MN9 also rises due to capacitive coupling by capacitor C3. This bootstrap causes the potential of the second terminal (terminal GT) of transistor MN9 to rise to V High -V th_MN8 In this example, the potential V High In addition, the potential of the first gate of the transistor MN9 at this time is equal to (V High -V th_MN8 )+(V High -V Low )=2V High -V Low -V th_MN8 The maximum value of the

[0179] In addition, between time T6 and time T7, V High After the voltage is applied, the voltage at the terminal PWC is V Low As a result, the potential of the second terminal (terminal GT) of the transistor MN9 becomes V Low The gate-source voltage is V High -V th_MN8 This becomes:

[0180] Incidentally, in the case where transistor MN1, transistor MN3, or transistor MN4, which is in the off state between time T6 and time T7, is normally on, please refer to the description of the operation example between time T5 and time T6.

[0181] [From time T8 to time T9] Between time T8 and time T9, V Low is given.

[0182] The potential of the first gate of transistor MN6 is 2V. High -V Low -V th_MN5 The first terminal of the transistor MN6 is connected to V from the terminal CLK1. Low is given, and the potential of the second terminal of transistor MN6 is V High At this time, the potential of the first terminal of transistor MN6 becomes lower than the potential of the second terminal, so the first terminal of transistor MN6 becomes the source, and transistor MN6 is turned on. This causes conduction between terminal CLK1 and terminal OT.

[0183] When the transistor MN6 is in the ON state, a current flows from the terminal OT to the terminal CLK1, and the potential of the terminal OT becomes low. In this operation example, the potential of the terminal OT finally becomes equal to the potential V given by the terminal CLK1. Low Therefore, the potential of the first gate of the transistor MN6 is equal to V High -Vth_MN5 shall be reduced to

[0184] [From time T9 to time T10] Between time T9 and time T10, V High At this time, the operation of circuit 101A1 from time T9 to time T10 is the same as the operation from time T2 to time T3.

[0185] For example, V High is applied, the transistor MN3 is turned on, and the potential of the node N2 rises to V Low From V High -V th_MN3 As a result, the transistors MN2, MN7, and MN10 are turned on, and the potentials of the node N1, the terminal OT, and the terminal GT change to V Low This becomes:

[0186] Furthermore, the potential of node N1 is V Low As a result, the potentials of the second terminal of transistor MN5 (the first gate of transistor MN6) and the second terminal of transistor MN8 (the first gate of transistor MN9) also drop to V Low Therefore, the potentials of the first terminal and the second terminal of the transistor MN5 are reduced to V Low Similarly, when the potentials of the first and second terminals of the transistor MN8 are V Low This becomes:

[0187] [After time T10] After time T10, for example, V Low The variable potential of V is input, and the potential of node N1 is V Low and the potential of node N2 is V High -V th_MN3 After that, V is applied to terminal IT. High Without inputting V to terminal CLK1 or terminal PWC HighA specific example of operation will be described below.

[0188] [From time T11 to time T12] Between time T11 and time T12, V High is given.

[0189] The potential of the first gate of transistor MN6 is V Low The first terminal of the transistor MN6 is connected to V from the terminal CLK1. High is given, and the potential of the second terminal of transistor MN6 is V Low At this time, the potential of the second terminal of transistor MN6 is lower than the potential of the first terminal, so the second terminal of transistor MN6 becomes the source, and transistor MN6 is turned off. This causes a non-conduction state between terminal CLK1 and terminal OT.

[0190] The potential of the first gate of transistor MN7 is V High -V th_MN3 The second terminal of the transistor MN7 is connected to the V Low is applied, the transistor MN7 is turned on. This brings the terminal OT and the wiring VSE4 into a conductive state, and the potential of the terminal OT rises to V Low This becomes:

[0191] In addition, between time T11 and time T12, V High After this is applied, V is applied to the CLK1 pin. Low The potential of the first gate of transistor MN6 is V Low The first terminal of the transistor MN6 is connected to V from the terminal CLK1. Low is given, and the potential of the second terminal of transistor MN6 is V Low Therefore, if the threshold voltage of the transistor MN6 is within an appropriate range, the transistor MN6 will be in an off state.

[0192] As mentioned above, V is connected to the CLK2 pin. LowThe variable potential of V is input, and the potential of node N1 is V Low and the potential of node N2 is V High -V th_MN3 After that, V is applied to terminal IT. High Without inputting V to terminal CLK1 High Even if V is applied to the terminal CLK1, the transistor MN6 remains in the off state. Low , the transistor MN6 remains in the off state.

[0193] [From time T12 to time T13] Between time T12 and time T13, V is applied to the terminal PWC. High is given.

[0194] The potential of the first gate of transistor MN9 is V Low The first terminal of the transistor MN9 is connected to the V High is given, and the potential at the second terminal of transistor MN9 is V Low At this time, the potential of the second terminal of transistor MN9 is lower than the potential of the first terminal, so the second terminal of transistor MN9 becomes the source, and transistor MN9 is turned off. This causes a non-conduction state between terminal PWC and terminal GT.

[0195] The potential of the first gate of transistor MN10 is V High -V th_MN3 The second terminal of the transistor MN10 is connected to the V Low is applied, the transistor MN10 is turned on. This brings the terminal GT and the wiring VSE5 into a conductive state, and the potential of the terminal GT rises to V Low This becomes:

[0196] In addition, between time T12 and time T13, V High After the voltage is applied, the voltage at the terminal PWC is V Low The potential of the first gate of transistor MN9 is V Low The first terminal of the transistor MN9 is connected to the VLow is given, and the potential at the second terminal of transistor MN9 is V Low Therefore, the transistor MN9 is turned off.

[0197] As mentioned above, V is connected to the CLK2 pin. Low The variable potential of V is input, and the potential of node N1 is V Low and the potential of node N2 is V High -V th_MN3 After that, V is applied to terminal IT. High Without inputting V, connect the PWC terminal High Even if V is applied to the terminal PWC, the transistor MN9 remains in the off state. Low Even if a voltage is applied, transistor MN9 remains off.

[0198] <<Comparison 1>> Here, the circuit 100A1 is compared with the circuit 101 shown in FIG.

[0199] 5 has a circuit configuration that served as the basis for development of the circuit 100A1 in FIG. 1A and the circuits described in Configuration Examples 2 to 8 below. For example, when comparing the circuit configurations of the circuit 101 and the circuit 100A1, the circuit 100A1 has a configuration in which the second gate of the transistor MN7 is electrically connected to the second terminal of the transistor MN7 and the second gate of the transistor MN10 is electrically connected to the second terminal of the transistor MN10, whereas the circuit 101 has a configuration in which the second gate of the transistor MN7 is electrically connected to a wiring BG1 and the second gate of the transistor MN10 is electrically connected to a wiring BG1.

[0200] The operation of the circuit 101 can be the same as the operation example of the circuit 100A1 described above.

[0201] Here, consider the case where the transistor MN7 or the transistor MN10, which is in the OFF state between time T5 and time T6 in the above example of operation, is in the normally ON state.

[0202] In the circuit 101, when the transistor MN7 is normally on, a current flows from the terminal OT to the wiring VSE4. High In addition, a short-circuit current flows between the terminal CLK1 and the wiring VSE4, which may increase the power consumption of the circuit 101. Note that even if the transistor MN7 is normally on, the potential of the terminal OT may be lower than V High If the source-drain current of transistor MN6 does not vary significantly from the source-drain current of transistor MN7 (for example, if the source-drain current of transistor MN6 is greater than the source-drain current of transistor MN7), then circuit 101 may operate normally.

[0203] In the circuit 101, the potential of the first terminal (terminal GT) of the transistor MN10 is V Low and the potential of the second terminal (wire VSE5) of the transistor MN10 is V Low Therefore, even if the transistor MN10 is normally on, the potential of the terminal GT does not change.

[0204] 5, the second gates of the transistors MN2, MN7, and MN10 are electrically connected to the wiring BG1. Therefore, in order to make the transistor MN2 normally off, for example, a negative potential (V LL), transistors MN7 and MN10 may also be normally-off. As described above, even if transistors MN7 and MN10 are normally-on, the circuit 101 may operate normally, and a negative potential from wiring BG1 need not be applied to the second gates of transistors MN7 and MN10. Furthermore, if transistors MN7 and MN10 are operated as normally-off, the amount of current flowing through transistors MN7 and MN10 when they are on may be reduced, which may slow down the operating speed of the circuit 101. For this reason, it is preferable that the potential applied to the second gates of transistors MN7 and MN10 be different from the potential applied to the second gate of transistor MN2.

[0205] 1A, the second gate of the transistor MN7 is electrically connected to the wiring VSE4, and the second gate of the transistor MN10 is electrically connected to the wiring VSE5. Therefore, a potential as low as the negative potential applied by the wiring BG1 can be prevented from being applied to the second gates of the transistors MN7 and MN10. As a result, unlike the circuit 101, the circuit 100A1 allows only the transistor MN2 of the transistors MN2, MN7, and MN10 to be normally off. Therefore, the amount of current flowing when the transistors MN7 and MN10 in the circuit 100A1 are on can be larger than the amount of current flowing when the transistors MN7 and MN10 in the circuit 101 are on. As described above, by applying the circuit 100A1 of FIG. 1(A) to each of the circuits 100[1] to 100[m] of the driver circuit GD of FIG. 3(A) or FIG. 3(B), the drive speed of the driver circuit GD can be increased more than by applying the circuit 101 of FIG. 5.

[0206] The semiconductor device of one embodiment of the present invention is not limited to the structure shown in Fig. 1A. For example, the structure of the semiconductor device of one embodiment of the present invention may be changed depending on the situation as long as the object is solved.

[0207] For example, in the circuit 100A1 of FIG. 1(A), if the potential of the node N2 can be sufficiently maintained by the capacitor C1, the circuit 100A1 may be modified to a configuration in which the second gate of the transistor MN4 is not provided, as shown in the circuit 100A2 of FIG. 1(B).

[0208] 1A may be modified to have the same configuration as the circuit 100A3 shown in Fig. 6A. The circuit 100A3 shown in Fig. 6A differs from the circuit 100A1 in Fig. 1A in that the second gate of the transistor MN7 is electrically connected to a wiring BG2 and the second gate of the transistor MN10 is electrically connected to a wiring BG2.

[0209] 6A, the second gate of transistor MN2 is electrically connected to wiring BG1, and the second gates of transistors MN7 and MN10 are electrically connected to wiring BG2. Therefore, even if a constant potential is applied to wiring BG1, the constant potential is not applied to the second gates of transistors MN7 and MN10. In other words, the threshold voltage of transistor MN2 and the threshold voltages of transistors MN7 and MN10 can be controlled independently. As a result, for example, by applying a negative potential to the second gate of transistor MN2 and applying ground potential or a low-level potential (a potential higher than the negative potential) to the second gates of transistors MN7 and MN10, the off-state current of transistors MN7 and MN10 can be made larger than the off-state current of transistor MN2. Therefore, by applying the circuit 100A3 of FIG. 6(A) to each of the circuits 100[1] to 100[m] of the driving circuit GD of FIG. 3(A) or FIG. 3(B), the driving speed of the driving circuit GD can be increased, similar to the circuit 100A1 of FIG. 1(A).

[0210] 1A may be modified to have the structure of a circuit 100A4 shown in Fig. 6B. In the circuit 100A4 shown in Fig. 6B, the second gates of the transistors MN7 and MN3 are electrically connected to a wiring BG3.

[0211] For example, the wiring BG3 functions as a wiring that applies a constant potential, similar to the wirings BG1 and BG2. The constant potential may be, for example, a low-level potential, a ground potential, or a negative potential. The wiring BG3 may also be a wiring that applies a variable potential instead of a constant potential.

[0212] 6A, the circuit 100A4 in FIG. 6B also allows the threshold voltage of the transistor MN2 and the threshold voltages of the transistors MN7 and MN10 to be controlled independently, as in the circuit 100A3 in FIG. 6A. Thus, for example, by applying a negative potential to the second gate of the transistor MN2 from the wiring BG1 and applying ground potential or a low-level potential (a potential higher than the negative potential) to the second gates of the transistors MN7 and MN10 from the wiring BG3, the off-state currents of the transistors MN7 and MN10 can be made larger than the off-state current of the transistor MN2. Therefore, by applying the circuit 100A4 in FIG. 6A to each of the circuits 100[1] to 100[m] of the driver circuit GD in FIG. 3A or 3B, the drive speed of the driver circuit GD can be increased, as in the circuit 100A1 in FIG. 1A.

[0213] <Configuration example 2> Next, an example of a circuit configuration that can be applied to the circuits 100[1] to 100[m] of the driver circuit GD in each of FIGS. 3A and 3B, which is different from the circuit described in Configuration Example 1, will be described.

[0214] 7A shows an example of a circuit configuration that can be applied to the circuits 100[1] to 100[m] of the driver circuits GD in each of FIGS. 3A and 3B, which are semiconductor devices of one embodiment of the present invention. The circuit 100B1 has a modified circuit configuration of the circuit 100A1 in FIG. 1A and differs from the circuit 100A1 in that it includes a capacitor C4.

[0215] In addition, the circuit 100B1 is configured such that the second gates of the transistors MN7 and MN10 are electrically connected to the wiring BG1, but the connection destinations of the second gates of the transistors MN7 and MN10 in the circuit 100B1 may be changed to match the configuration of any one of the circuit 100A1 in FIG. 1(A), the circuit 100A3 in FIG. 6(A), and the circuit 100A4 in FIG. 6(B).

[0216] For example, a first terminal of the capacitor C4 is electrically connected to the second terminal of the transistor MN1, the first terminal of the transistor MN2, the first terminal of the transistor MN5, and the first terminal of the transistor MN8, and a second terminal of the capacitor C4 is electrically connected to the wiring VSE6.

[0217] For example, the wiring VSE6 functions as a wiring that applies a constant potential, similar to the wirings VSE1 to VSE5. The constant potential can be, for example, a low-level potential, a ground potential, or a negative potential. When the constant potential applied by the wiring VSE6 is equal to the potential applied by one or more selected from the wirings VSE1 to VSE5, the wiring VSE6 and the wiring VSE6 may be the same wiring.

[0218] The wiring VSE6 may be a wiring that applies a variable potential instead of a constant potential.

[0219] The operation of the circuit 100B1 can be the same as the operation of the circuit 100A1 described above.

[0220] <<Comparison 2>> Here, similarly to the first configuration example, differences in configuration and operation between the circuit 100B1 shown in FIG. 7A and the circuit 101 shown in FIG. 5 will be described.

[0221] As described above, the circuit 100B1 in FIG. 7A has a configuration including the capacitance C4, but the circuit 101 in FIG. 5 does not have the capacitance C4.

[0222] Consider the case where the transistor MN2, which is in the OFF state between time T5 and time T6 in the above example of operation, is normally ON.

[0223] In the circuit 101, when the transistor MN2 is normally on, a current flows from the node N1 to the wiring VSE1. High -V th_MN1 In particular, the potential of the node N1 may be lower than V High-V th_MN1 If the voltage drops below 1 V, one or both of the transistors MN5 and MN8 will be turned on, and the potential of the first gate of one or both of the transistors MN6 and MN9 will drop, which may reduce the effect of the bootstrap described above, and this may cause the circuit 101 to malfunction.

[0224] 7A, the first terminal of the capacitor C4 is electrically connected to the second terminal of the transistor MN1, the first terminal of the transistor MN2, the first terminal of the transistor MN5, and the first terminal of the transistor MN8, so that when the transistor MN2 is normally on, the potential of the first terminal of the capacitor C4 (node ​​N1) is less likely to drop. This allows the circuit 100B1 to operate more stably than the circuit 101.

[0225] Therefore, by applying the circuit 100B1 of FIG. 7(A) to each of the circuits 100[1] to 100[m] of the driving circuit GD of FIG. 3(A) or FIG. 3(B), the driving circuit GD can operate more stably than by applying the circuit 101 of FIG. 5.

[0226] In the circuit 100B1 of FIG. 7(A), if the potential of the node N1 can be sufficiently maintained by the capacitor C4, the circuit 100B1 may be modified to a configuration in which the second gate is not provided in the transistor MN2, as shown in the circuit 100B2 of FIG. 7(B).

[0227] <Configuration example 3> 8 illustrates an example of a circuit configuration that can be applied to the circuits 100[1] to 100[m] of the driver circuit GD in each of FIGS. 3(A) and 3(B), which are semiconductor devices of one embodiment of the present invention, different from the circuit 100A1 in FIG. 1(A), the circuit 100A2 in FIG. 1(B), the circuit 100A3 in FIG. 6(A), the circuit 100A4 in FIG. 6(B), and the circuit 100B1 in FIG. 7(A).

[0228] Circuit 100C has a circuit configuration that is a modification of circuit 100A1 of Figure 1(A), and differs from circuit 100A1 in that the first gate of transistor MN5 is electrically connected to wiring VME1 and the first gate of transistor MN8 is electrically connected to wiring VME2.

[0229] In addition, the circuit 100C has a configuration in which the second gates of the transistors MN7 and MN10 are electrically connected to the wiring BG1, but the connection destinations of the second gates of the transistors MN7 and MN10 in the circuit 100C may be changed to match the configuration of any one of the circuit 100A1 in FIG. 1(A), the circuit 100A3 in FIG. 6(A), and the circuit 100A4 in FIG. 6(B).

[0230] The wiring VME1 and the wiring VME2 each function as a wiring that applies a constant potential, for example. However, the constant potential is preferably lower than the potential applied by the wirings VDE1 to VDE4, for example. Note that the constant potentials applied by the wirings VME1 and VME2 may be equal to each other or different from each other. For example, when the constant potential applied by each of the wirings VDE1 and VDE2 is 5 V, the constant potential applied by each of the wirings VME1 and VME2 is preferably 4 V.

[0231] The operation of the circuit 100C can be the same as the operation of the circuit 100A1 described above.

[0232] <<Comparison 3>> Here, similarly to the first and second configuration examples, differences in configuration and operation between the circuit 100C shown in FIG. 8 and the circuit 101 shown in FIG. 5 will be described.

[0233] The circuit 100C in FIG. 8 differs from the circuit 101 in FIG. 5 in that the first gate of the transistor MN5 is electrically connected to the line VME1, and the first gate of the transistor MN8 is electrically connected to the line VME2.

[0234] Consider the case where the transistor MN5, which is in the OFF state between time T5 and time T6 in the above example of operation, is normally ON.

[0235] In the circuit 101, when the transistor MN5 is normally on, the charge held in the second terminal of the transistor MN5 (the first gate of the transistor MN6) flows to the node N1, and as a result, the potential of the second terminal of the transistor MN5 (the first gate of the transistor MN6) becomes 2V. High -V Low -V th_MN5 Therefore, the effect of the bootstrap described above becomes smaller, and the potential of the terminal OT becomes lower than V High It may be lower than that.

[0236] Also, consider the case where transistor MN8, which is in the OFF state between time T6 and time T7 in the above example of operation, is normally ON.

[0237] In the circuit 101, when the transistor MN8 is normally on, the charge held in the second terminal of the transistor MN8 (the first gate of the transistor MN9) flows to the node N1, and as a result, the potential of the second terminal of the transistor MN8 (the first gate of the transistor MN9) becomes 2V High -V Low -V th_MN8 Therefore, the effect of the bootstrap described above becomes smaller, and the potential of the terminal GT becomes lower than V High It may be lower than that.

[0238] On the other hand, in the circuit 100C of FIG. 8, the potentials applied to the first gates of the transistors MN5 and MN8 (the potentials applied by the wirings VME1 and VME2) are lower than the potential applied by the wiring VDE1. This allows the transistors MN5 and MN8 to turn off more quickly when the potential of the node N1 is increased, compared to the configuration of the circuit 101 of FIG. 5. Furthermore, even after the transistors MN5 and MN8 turn off, the potential of the node N1 ideally increases to the potential difference between the potential applied by the wiring VDE1 and the threshold voltage of the transistor MN1. This causes the gate-source voltages of the transistors MN5 and MN8 to be lower than 0 V, thereby further reducing the off-state currents of the transistors MN5 and MN8. This allows the potential of the first gates of the transistors MN6 and MN9 to be maintained for a longer period of time.

[0239] At this time, the potential of the first gate of transistor MN6 is the difference between the potential provided by line VME1 and the threshold voltage of transistor MN5, and the potential of the first gate of transistor MN9 is the difference between the potential provided by line VME2 and the threshold voltage of transistor MN9. Therefore, the potentials of the first gates of transistors MN6 and MN9 in circuit 100C of Fig. 8 are lower than the potentials of the first gates of transistors MN6 and MN9 in circuit 101 of Fig. 5, but the potentials of the first gates of transistors MN6 and MN9 in circuit 100C of Fig. 8 can be boosted by bootstrap using capacitors C2 and C3.

[0240] Therefore, by applying the circuit 100C of FIG. 8 to each of the circuits 100[1] to 100[m] of the driving circuit GD of FIG. 3(A) or FIG. 3(B), the driving circuit GD can operate more stably than by applying the circuit 101 of FIG. 5.

[0241] <Configuration Example 4> 9A illustrates a circuit configuration example that can be applied to the circuits 100[1] to 100[m] of the driver circuits GD in each of FIGS. 3A and 3B, which are semiconductor devices of one embodiment of the present invention, different from the circuits described in Configuration Examples 1 to 3.

[0242] The circuit 100D1 has a circuit configuration that is a modification of the circuit 100A1 of Figure 1(A), and differs from the circuit 100A1 in that the second gate of the transistor MN5 is electrically connected to the wiring VSE7 and the second gate of the transistor MN8 is electrically connected to the wiring VSE8.

[0243] In addition, the circuit 100D1 has a configuration in which the second gates of the transistors MN7 and MN10 are electrically connected to the wiring BG1, but the connection destinations of the second gates of the transistors MN7 and MN10 in the circuit 100D1 may be changed to match the configuration of any one of the circuit 100A1 in FIG. 1(A), the circuit 100A3 in FIG. 6(A), and the circuit 100A4 in FIG. 6(B).

[0244] The wiring VSE7 and the wiring VSE8 function as wirings that apply a constant potential, similar to the wirings VSE1 to VSE5. The constant potential can be, for example, a low-level potential, a ground potential, or a negative potential. When the constant potential applied by the wiring VSE7 is equal to the potential applied by one or more selected from the wirings VSE1 to VSE5 and the wiring VSE8, the wiring VSE7 and the wiring VSE8 may be the same wiring. When the constant potential applied by the wiring VSE8 is equal to the potential applied by one or more selected from the wirings VSE1 to VSE5 and the wiring VSE7, the wiring VSE8 and the wiring VSE8 may be the same wiring.

[0245] Alternatively, one or both of the wirings VSE7 and VSE8 may be wirings that apply a variable potential instead of a constant potential.

[0246] The operation of the circuit 100D1 can be the same as the operation of the circuit 100A1 described above.

[0247] <<Comparison 4>> Here, similarly to the first to third structural examples, differences in the configuration and operation between the circuit 100D1 shown in FIG. 9A and the circuit 101 shown in FIG. 5 will be described.

[0248] 9A, the second gate of transistor MN5 is electrically connected to the wiring VSE7, and the second gate of transistor MN8 is electrically connected to the wiring VSE8. Also, the circuit 101 in FIG. 5 has a configuration in which the second gate of transistor MN5 is electrically connected to the first gate of transistor MN5, and the second gate of transistor MN8 is electrically connected to the first gate of transistor MN8.

[0249] Consider the case where the transistor MN5, which is in the OFF state between time T5 and time T6 in the above example of operation, is normally ON.

[0250] In the circuit 101, when the transistor MN5 is normally on, as shown in the above comparison 3, the potential of the second terminal of the transistor MN5 (the first gate of the transistor MN6) is 2V. High -V Low -V th_MN5 The effect of the bootstrap described above becomes smaller, and the potential of the terminal OT becomes lower than V High It may be lower than that.

[0251] Also, consider the case where transistor MN8, which is in the OFF state between time T6 and time T7 in the above example of operation, is normally ON.

[0252] In the circuit 101, when the transistor MN8 is normally on, as shown in the above comparison 3, the potential of the second terminal of the transistor MN8 (the first gate of the transistor MN9) is 2V High -VLow -V th_MN8 The effect of the bootstrap described above becomes smaller, and the potential of the terminal GT becomes lower than V High It may be lower than that.

[0253] On the other hand, unlike the transistors MN5 and MN8 in the circuit 101 in FIG. 5, the threshold voltages of the transistors MN5 and MN8 in the circuit 100D1 in FIG. 9A can be varied by the potentials applied to the wirings VSE7 and VSE8. For example, by setting the potentials applied to the wirings VSE7 and VSE8 to a low-level potential, ground potential, or negative potential, the threshold voltages of the transistors MN5 and MN8 can be increased, and the transistors MN5 and MN8 can be changed from normally-on to normally-off. This allows the amount of off-state current of the transistors MN5 and MN8 in the circuit 100D1 to be smaller than the amount of off-state current of the transistors MN5 and MN8 in the circuit 101. That is, the potential of the first gates of the transistors MN6 and MN9 can be maintained for a long time.

[0254] 9B. The circuit 100D2 differs from the circuit 100D1 in that, for example, the second gate of the transistor MN5 is electrically connected to the wiring BG2 and the second gate of the transistor MN8 is electrically connected to the wiring BG2.

[0255] By applying a ground potential, a low-level potential, or a negative potential to the wiring BG2, the transistors MN5 and MN8 can be normally off in the circuit 100D2 as in the circuit 100D1.

[0256] 10A. The circuit configuration of the circuit 100D1 may be changed to the circuit configuration of the circuit 100D3 shown in FIG. 10A. The circuit 100D3 differs from the circuit 100D1 in that, for example, the second gates of the transistors MN5 and MN8 are electrically connected to the wiring BG3.

[0257] For the wiring BG3, the description of the wiring BG3 applied to the circuit 100A4 described in the first configuration example will be taken into consideration.

[0258] By applying a ground potential, a low-level potential, or a negative potential to the wiring BG3, the transistors MN5 and MN8 can be normally off in the circuit 100D3 as in the circuit 100D1.

[0259] 10B. The circuit 100D4 differs from the circuit 100D1 in that, for example, the second gates of the transistors MN5 and MN8 are electrically connected to the first gate of the transistor MN2, the first terminal of the capacitor C1, the first terminal of the transistor MN4, the first gate of the transistor MN7, and the first gate of the transistor MN10.

[0260] 10B, for example, when a low-level potential is input to terminal IT and a high-level potential is input to terminal CLK2, transistor MN1 is in the off state, transistor MN3 is in the on state, and transistor MN4 is in the off state, so that the potentials of the first gate of transistor MN2, the first terminal of capacitor C1, the first terminal of transistor MN4, the first gate of transistor MN7, and the first gate of transistor MN10 become high. At this time, transistors MN5 and MN8 are each normally on and in the on state. Furthermore, because the first gate of transistor MN2 is at a high-level potential, transistor MN2 is in the on state, and the first gates of transistors MN6 and MN9 are at a low-level potential.

[0261] Furthermore, for example, when a high-level potential is input to terminal IT and a low-level potential is input to terminal CLK2, transistor MN3 is in the off state and transistor MN4 is in the on state, so the potentials of the first gate of transistor MN2, the first terminal of capacitor C1, the first terminal of transistor MN4, the first gate of transistor MN7, and the first gate of transistor MN10 are low-level potential. At this time, transistors MN5 and MN8 are normally off. At this time, transistor MN1 is in the on state, transistor MN2 is in the off state, transistor MN5 is in the on state, and transistor MN8 is in the on state, so the potentials of the first gates of transistors MN6 and MN8 become high. Then, when the potentials of the first terminals (node ​​N1) of transistors MN5 and MN8 reach a predetermined level, transistors MN5 and MN8 are turned off.

[0262] As described above, by configuring the circuit 100D4, the transistors MN5 and MN8 can be temporarily set to normally-off at the necessary timing during operation of the circuit 100D4, and therefore the potential of the first gates of the transistors MN6 and MN9 can be maintained for a long time.

[0263] As described above, by applying the circuit 100D1 of FIG. 9(A), the circuit 100D2 of FIG. 9(B), the circuit 100D3 of FIG. 10(A), or the circuit 100D4 of FIG. 10(B) to each of the circuits 100[1] to 100[m] of the driver circuit GD of FIG. 3(A) or FIG. 3(B), the driver circuit GD can operate more stably than by applying the circuit 101 of FIG. 5.

[0264] <Configuration example 5> FIG. 11 illustrates a configuration example of a circuit that can be applied to the circuits 100[1] to 100[m] of the driver circuit GD in each of FIGS. 3(A) and 3(B), which are semiconductor devices of one embodiment of the present invention, different from the circuits described in Configuration Examples 1 to 4.

[0265] Circuit 100E has a circuit configuration that is a modification of circuit 100A1 of Figure 1(A), and differs from circuit 100A1 in that the second gate of transistor MN5 is electrically connected to the first terminal of transistor MN5 and the second gate of transistor MN8 is electrically connected to the first terminal of transistor MN8.

[0266] In addition, the circuit 100E is configured such that the second gates of the transistors MN7 and MN10 are electrically connected to the wiring BG1, but the connection destinations of the second gates of the transistors MN7 and MN10 in the circuit 100E may be changed to match the configuration of any one of the circuit 100A1 in FIG. 1(A), the circuit 100A3 in FIG. 6(A), and the circuit 100A4 in FIG. 6(B).

[0267] The operation of the circuit 100E can be the same as the operation of the circuit 100A1 described above.

[0268] <<Comparison 5>> Here, similarly to the first to fourth configuration examples, differences in configuration and operation between the circuit 100E shown in FIG. 11 and the circuit 101 shown in FIG. 5 will be described.

[0269] As described above, the circuit 100E in Fig. 11 has a configuration in which the second gate of transistor MN5 is electrically connected to the first terminal of transistor MN5, and the second gate of transistor MN8 is electrically connected to the first terminal of transistor MN8. Also, the circuit 101 in Fig. 5 has a configuration in which the second gate of transistor MN5 is electrically connected to the first gate of transistor MN5, and the second gate of transistor MN8 is electrically connected to the first gate of transistor MN8.

[0270] When the operation example of the timing chart of Figure 4 is applied as the operation of circuit 101, during the period when a high-level potential is input to terminal IT (from time T4 to time T5), the potential of node N1 (the electrical connection point between the second terminal of transistor MN1, the first terminal of transistor MN2, the first terminal of transistor MN5, and the first terminal of transistor MN8) increases, and when the gate-source voltages of transistors MN5 and MN8 become smaller than their respective threshold voltages, transistors MN5 and MN8 are turned off.

[0271] In this case, when the configuration of circuit 101 is changed to the configuration of circuit 100E, the potentials of the second gates of transistors MN5 and MN8 become equal to the potential of node N1. That is, the potentials of the second gates (node ​​N1) of transistors MN5 and MN8 in circuit 100E are lower than the potentials of the second gates of transistors MN5 and MN8 in the above-described operational example. Therefore, the threshold voltages of transistors MN5 and MN8 in circuit 100E are higher than the threshold voltages of transistors MN5 and MN8 in circuit 101. Therefore, by changing the configuration of circuit 101 to that of circuit 100E, transistors MN5 and MN8 are more likely to be turned off during the period when a high-level potential is input to terminal IT and the potential of node N1 rises (the period from time T4 to time T5), thereby reducing the amount of off-state current of transistors MN5 and MN8. That is, the potentials of the first gates of transistors MN6 and MN9 can be maintained for a longer period.

[0272] Therefore, by applying the circuit 100E of FIG. 11 to each of the circuits 100[1] to 100[m] of the driving circuit GD of FIG. 3(A) or FIG. 3(B), the driving circuit GD can operate more stably than by applying the circuit 101 of FIG. 5.

[0273] <Configuration Example 6> FIG. 12A illustrates a configuration example of a circuit that can be applied to the circuits 100[1] to 100[m] of the driver circuit GD in each of FIGS. 3A and 3B, which are semiconductor devices of one embodiment of the present invention, different from the circuits described in Configuration Examples 1 to 5.

[0274] 1A, the circuit 100F1 differs from the circuit 100A1 in that it includes a transistor MN11 and a capacitor C5. Specifically, the circuit 100F1 has a configuration in which a first terminal of the transistor MN11 is electrically connected to the terminal IT, a second terminal of the transistor MN11 is electrically connected to a first gate of the transistor MN1, a second gate of the transistor MN1, and a first terminal of the capacitor C5, and a first gate of the transistor MN11 is electrically connected to a second gate of the transistor MN11 and a wiring VDE5. The second terminal of the capacitor C5 is electrically connected to a second terminal of the transistor MN1, a first terminal of the transistor MN2, a first terminal of the transistor MN5, and a first terminal of the transistor MN8.

[0275] In addition, the circuit 100F1 is configured such that the second gates of the transistors MN7 and MN10 are electrically connected to the wiring BG1, but the connection destinations of the second gates of the transistors MN7 and MN10 in the circuit 100F1 may be changed to match the configuration of any one of the circuit 100A1 in FIG. 1(A), the circuit 100A3 in FIG. 6(A), and the circuit 100A4 in FIG. 6(B).

[0276] The wiring VDE5 functions as a wiring that applies a constant potential, similar to the wirings VDE1 to VDE4. The constant potential can be, for example, a high-level potential. When the constant potential applied by the wiring VDE5 is equal to the potential applied by one or more selected from the wirings VDE1 to VDE4, the wiring VDE5 and the wiring VDE4 may be the same wiring.

[0277] The wiring VDE5 may be a wiring that applies a variable potential instead of a constant potential.

[0278] The operation of the circuit 100F1 can be the same as the operation of the circuit 100A1 described above.

[0279] <<Comparison 6>> Here, similarly to the first to fifth structural examples, differences in the structure and operation between the circuit 100F1 shown in FIG. 12A and the circuit 101 shown in FIG. 5 will be described.

[0280] As described above, the circuit 100F1 in Fig. 12A includes the transistor MN11 and the capacitor C5, while the circuit 101 in Fig. 5 does not include the transistor MN11 or the capacitor C5.

[0281] When the operation example of the timing chart of Figure 4 is applied as the operation of circuit 101, during the period when a high-level potential is input to terminal IT (from time T4 to time T5), the potential of node N1 (the electrical connection point between the second terminal of transistor MN1, the first terminal of transistor MN2, the first terminal of transistor MN5, and the first terminal of transistor MN8) increases, and when the gate-source voltages of transistors MN5 and MN8 become smaller than their respective threshold voltages, transistors MN5 and MN8 are turned off.

[0282] On the other hand, when the operation example of the timing chart of FIG. 4 is applied as the operation of the circuit 100F1, during the period (from time T4 to time T5) when a high-level potential is input to the terminal IT, the potentials of the first terminal of the transistor MN11 and the second terminal of the transistor MN11 (the first gate of the transistor MN1) become high. Furthermore, when the gate-source voltage of the transistor MN11 becomes lower than the threshold voltage of the transistor MN11, the transistor MN11 is turned off. Furthermore, since the gate-source voltage of the transistor MN1 becomes higher than the threshold voltage of the transistor MN1, the transistor MN1 is turned on, and the potential of the node N1 becomes higher. At this time, because the transistor MN11 is turned off, the potential of the first gate of the transistor MN1 further increases due to the bootstrap by the capacitor C5. As a result, the gate-source voltage of the transistor MN1 becomes sufficiently higher than the threshold voltage, and the potential of the node N1 is boosted to the potential provided by the line VDE1.

[0283] That is, the potential of the node N1 is increased by applying a high-level potential to the terminal IT more in the circuit 100F1 in FIG. 12A than in the circuit 101 in FIG.

[0284] As a result, in the circuit 100F1, the potential of each of the first terminals of the transistors MN5 and MN8 increases to the potential provided by the wiring VDE1, and therefore the difference between the gate-source voltage and the threshold voltage when the transistors MN5 and MN8 are in the off state becomes larger than in the configuration of the circuit 101. Therefore, the amount of off-state current of each of the transistors MN5 and MN8 in the circuit 100F1 can be made smaller than the amount of off-state current of each of the transistors MN5 and MN8 in the circuit 101. In other words, the potential of each of the first gates of the transistors MN6 and MN9 can be maintained for a long time.

[0285] The circuit configuration of the circuit 100F1 may be changed to the circuit configuration of a circuit 100F2 shown in Fig. 12(B) The circuit 100F2 differs from the circuit 100F1 in the connection configuration of the transistor MN11 and in the presence of a transistor MN12.

[0286] Specifically, a first gate of transistor MN11 is not electrically connected to wiring VDE5 and is electrically connected to a second gate of transistor MN11. A first terminal of transistor MN12 is electrically connected to a first gate of transistor MN1, a second gate of transistor MN1, and a second terminal of transistor MN11, a second terminal of transistor MN12 is electrically connected to terminal IT, a first terminal of transistor MN11, and a first gate of transistor MN4, a first gate of transistor MN12 is electrically connected to terminal CLK1, and a second gate of transistor MN12 is electrically connected to wiring BG1.

[0287] When a low-level potential is input to terminal CLK1 and transistor MN12 is in the off state, a high-level potential is input to terminal IT, causing the potential of the first gate of transistor MN1 to become the high-level potential applied to terminal IT minus the threshold voltage of transistor MN11. Furthermore, because transistor MN11 is diode-connected, when the potential of the second terminal of transistor MN11 becomes the high-level potential applied to terminal IT minus the threshold voltage of transistor MN11, transistor MN11 is turned off. Thereafter, transistor MN1 is turned on, and the potential of node N1 is increased by bootstrap at capacitor C5. For details about this operation, see the description of the operation of circuit 100F1.

[0288] To set the potential of the first gate of transistor MN1 to a low-level potential, for example, a low-level potential may be input to terminal IT and a high-level potential may be input to terminal CLK1. This corresponds to the operation from time T5 to time T9 in the exemplary operation of circuit 100A of embodiment 1. This operation turns on transistor MN12, establishing conduction between terminal IT and the first gate of transistor MN1, thereby setting the potential of the first gate of transistor MN1 to a low-level potential. At this time, the gate-source voltage of transistor MN1 becomes lower than the threshold voltage of transistor MN1, so transistor MN1 is turned off, node N1 is in a floating state, and capacitor C5 holds the high-level potential applied from wiring VDE1.

[0289] By applying the configuration of circuit 100F2, as with circuit 100F1, the amount of off-state current of each of transistors MN5 and MN8 of circuit 100F2 can be made smaller than the amount of off-state current of each of transistors MN5 and MN8 of circuit 101, and the potential of each of the first gates of transistors MN6 and MN9 can be maintained for a longer period of time.

[0290] As described above, by applying the circuit 100F1 of FIG. 12(A) or the circuit 100F2 of FIG. 12(B) to each of the circuits 100[1] to 100[m] of the driver circuit GD of FIG. 3(A) or FIG. 3(B), the driver circuit GD can operate more stably than by applying the circuit 101 of FIG. 5.

[0291] <Configuration Example 7> FIG. 13 illustrates a configuration example of a circuit that can be applied to the circuits 100[1] to 100[m] of the driver circuit GD in each of FIGS. 3(A) and 3(B), which are semiconductor devices of one embodiment of the present invention, different from the circuits described in Configuration Examples 1 to 6.

[0292] The circuit 100G has a circuit configuration that is a modification of the circuit 100A1 of FIG. 1A, and differs from the circuit 100A1 in that it does not include the transistors MN5 and MN8.

[0293] In addition, the circuit 100G is configured such that the second gates of the transistors MN7 and MN10 are electrically connected to the wiring BG1, but the connection destinations of the second gates of the transistors MN7 and MN10 in the circuit 100G may be changed to match the configuration of any one of the circuit 100A1 in FIG. 1(A), the circuit 100A3 in FIG. 6(A), and the circuit 100A4 in FIG. 6(B).

[0294] By omitting transistor MN5, the parasitic capacitance around the first gate of transistor MN6 can be reduced. Similarly, by omitting transistor MN8, the parasitic capacitance around the first gate of transistor MN8 can be reduced.

[0295] Furthermore, the circuit configuration of circuit 100G is preferably designed to minimize the parasitic capacitance around the first gates (node ​​N1) of transistors MN6 and MN9. Specifically, for example, it is preferable to shorten the wiring that electrically connects the first gates of transistors MN6 and MN9 to the second terminal of transistor MN1 and the first terminal of transistor MN2.

[0296] By reducing the parasitic capacitance around the first gates (node ​​N1) of transistors MN6 and MN9, the boost in potential of the first gates of transistors MN6 and MN9 due to bootstrap in capacitors C2 and C3 can be increased, thereby increasing the driving capabilities of transistors MN6 and MN9, so that the potential from terminal CLK1 is output to terminal OT with almost no drop, and the potential from terminal PWC is output to terminal GT with almost no drop.

[0297] As described above, by applying the circuit 100G of FIG. 13 to each of the circuits 100[1] to 100[m] of the driver circuit GD of FIG. 3(A) or FIG. 3(B), the driver circuit GD can operate more stably than by applying the circuit 101 of FIG. 5.

[0298] <Configuration Example 8> The circuit 100AA1 in FIG. 14(A), the circuit 100AA2 in FIG. 14(B), the circuit 100AA3 in FIG. 15(A), the circuit 100AA4 in FIG. 15(B), and the circuit 100AA5 in FIG. 16 are modified examples of the circuit 100A1 described in Configuration Example 1. The circuit 100AA1, the circuit 100AA2, the circuit 100AA3, the circuit 100AA4, and the circuit 100AA5 can be applied to the circuits 100[1] to 100[m] of the driver circuit GD in FIG. 3(A) and FIG. 3(B), which are semiconductor devices of one embodiment of the present invention.

[0299] As an example, the circuit 100AA1 in FIG. 14A has a configuration in which the transistors MN2 and MN4 in the circuit 100A1 in FIG. 1A are each a multi-gate transistor.

[0300] Specifically, for example, transistor MN2 includes transistor MN2a and transistor MN2b, with the first terminal of transistor MN2a and the first terminal of transistor MN2b electrically connected to each other, the first gates of transistor MN2a and transistor MN2b electrically connected to each other, and the second gates of transistor MN2a and transistor MN2b electrically connected to each other. Therefore, the first gates of transistor MN2a and transistor MN2b function as the first gate of transistor MN2, and the second gates of transistor MN2a and transistor MN2b function as the second gate of transistor MN2. Furthermore, the second terminal of transistor MN2a corresponds to the first terminal of transistor MN2, and the second terminal of transistor MN2b corresponds to the second terminal of transistor MN2.

[0301] Also, for example, transistor MN4 has transistor MN4a and transistor MN4b, where the first terminal of transistor MN4a and the first terminal of transistor MN4b are electrically connected to each other, the first gates of transistor MN4a and transistor MN4b are electrically connected to each other, and the second gates of transistor MN4a and transistor MN4b are electrically connected to each other. Therefore, the first gates of transistor MN4a and transistor MN4b function as the first gate of transistor MN4, and the second gates of transistor MN4a and transistor MN4b function as the second gate of transistor MN4. Also, the second terminal of transistor MN4a corresponds to the first terminal of transistor MN4, and the second terminal of transistor MN4b corresponds to the second terminal of transistor MN4.

[0302] By using a multi-gate transistor for transistor MN2, it is possible to reduce the off-state current that flows between the first and second terminals of transistor MN2 when transistor MN2 is in the off state. Similarly, by using a multi-gate transistor for transistor MN4, it is possible to reduce the off-state current that flows between the first and second terminals of transistor MN4 when transistor MN4 is in the off state.

[0303] Although the transistor MN2 and the transistor MN4 in the circuit 100AA1 shown in FIG. 14(A) are each a multi-gate transistor having two transistors, the transistor MN2 and the transistor MN4 may also be a multi-gate transistor having three or more transistors.

[0304] In addition, in the circuit 100AA1 shown in FIG. 14A, the transistors MN2 and MN4 are multi-gate transistors. However, in the configuration of the circuit 100AA1, one or more selected from the transistors MN1 to MN10 may be multi-gate transistors.

[0305] Furthermore, multi-gate transistors can be applied not only to the transistor MN2 and the transistor MN4 of the circuit 100AA1 shown in FIG. 14A, but also to transistors shown in other drawings in this specification.

[0306] Note that the circuit 100AA1 is configured such that the second gate of the transistor MN7 is electrically connected to the second terminal of the transistor MN7 and the second gate of the transistor MN10 is electrically connected to the second terminal of the transistor MN10, but the second gates of the transistors MN7 and MN10 in the circuit 100AA1 may be electrically connected to the wiring BG1. Alternatively, the connection destinations of the second gates of the transistors MN7 and MN10 in the circuit 100AA1 may be changed to match the configuration of either the circuit 100A3 in FIG. 6A or the circuit 100A4 in FIG. 6B.

[0307] As an example, the circuit 100AA2 of Figure 14(B) has a configuration in which the connections of the first gate and second gate of each of transistors MN2, MN4, MN7, and MN10 of the circuit 100A1 of Figure 1(A) are swapped.

[0308] 14(B), for example, the first gate of transistor MN2 is electrically connected to wiring BG1, and the second gate of transistor MN2 is electrically connected to the first terminal of capacitor C1, the second terminal of transistor MN3, the first terminal of transistor MN4, the second gate of transistor MN7, and the second gate of transistor MN10. Also, for example, the first gate of transistor MN4 is electrically connected to wiring BG2. Also, for example, the first gate of transistor MN7 is electrically connected to the second terminal of transistor MN7 and wiring VSE4. Also, for example, the first gate of transistor MN10 is electrically connected to the second terminal of transistor MN10 and wiring VSE5.

[0309] As shown in circuit 100AA2 of Figure 14(B), even if the connections of the first gate and second gate of each of transistors MN2, MN4, MN7, and MN10 are interchanged, circuit 100AA2 may be able to perform the desired operation, similar to circuit 100A1.

[0310] In the circuit 100AA2 shown in FIG. 14(B), the connections of the first gate and second gate of each of transistors MN2, MN4, MN7, and MN10 are swapped, but in the circuit 100AA2, the connections of the first gate and second gate of transistors other than those mentioned above may also be swapped.

[0311] In addition, the connections of the first gate and the second gate may be swapped not only for transistor MN2, transistor MN4, transistor MN7, and transistor MN10 of circuit 100AA2 shown in FIG. 14(B), but also for transistors shown in other drawings in this specification.

[0312] Note that the circuit 100AA2 has a configuration in which the second gate of the transistor MN7 is electrically connected to the second terminal of the transistor MN7 and the second gate of the transistor MN10 is electrically connected to the second terminal of the transistor MN10, but the second gates of the transistors MN7 and MN10 in the circuit 100AA2 may be electrically connected to the wiring BG1. Alternatively, the connection destinations of the second gates of the transistors MN7 and MN10 in the circuit 100AA2 may be changed to match the configuration of either the circuit 100A3 in FIG. 6A or the circuit 100A4 in FIG. 6B.

[0313] In the circuit 100AA3 of FIG. 15(A), as an example, the second gate is not provided in each of the transistors MN1, MN3, MN5, MN6, MN8, and MN9.

[0314] By electrically connecting the first gate and the second gate of the same transistor to each other, the on-state current of the transistor can be increased. On the other hand, if it is not necessary to increase the on-state current of the transistor, the second gate of the transistor may not be provided. Specifically, for example, in the circuit 100A1 of FIG. 1A, if the on-state currents of the transistors MN1, MN3, MN5, MN6, MN8, and MN9 are sufficiently high, the transistors may not be provided with second gates, as shown in the circuit 100AA3 of FIG. 15A.

[0315] Note that the circuit 100AA3 has a configuration in which the second gate of the transistor MN7 is electrically connected to the second terminal of the transistor MN7 and the second gate of the transistor MN10 is electrically connected to the second terminal of the transistor MN10, but the second gates of the transistors MN7 and MN10 in the circuit 100AA3 may be electrically connected to the wiring BG1. Alternatively, the connection destinations of the second gates of the transistors MN7 and MN10 in the circuit 100AA3 may be changed to match the configuration of either the circuit 100A3 in FIG. 6A or the circuit 100A4 in FIG. 6B.

[0316] As an example, the circuit 100AA4 in FIG. 15(B) has a configuration in which the n-channel transistors MN1 to MN10 in the circuit 100A1 in FIG. 1(A) are replaced with p-channel transistors MP1 to MP10.

[0317] As the transistors MP1 to MP10, for example, p-channel transistors having an SOI (Silicon On Insulator) structure can be used.

[0318] Specifically, the first terminal of transistor MP1 is electrically connected to wiring VSE11, the second terminal of transistor MP1 is electrically connected to the first terminal of transistor MP2, the first terminal of transistor MP5, and the first terminal of transistor MP8, and the first gate of transistor MP1 is electrically connected to the second gate of transistor MP1, terminal IT, and the first gate of transistor MP4.

[0319] In addition, the first terminal of transistor MP3 is electrically connected to wiring VSE12, the second terminal of transistor MP3 is electrically connected to the first gate of transistor MP2, the first terminal of capacitor C1, the first terminal of transistor MP4, the first gate of transistor MP7, and the first gate of transistor MP10, and the first gate of transistor MP3 is electrically connected to the second gate of transistor MP3 and terminal CLK2.

[0320] The second terminal of the transistor MP5 is electrically connected to the first gate of the transistor MP6, the second gate of the transistor MP6, and the first terminal of the capacitor C2, and the first gate of the transistor MP5 is electrically connected to the second gate of the transistor MP5 and the wiring VSE13. The first terminal of the transistor MP6 is electrically connected to the terminal CLK1, and the second terminal of the transistor MP6 is electrically connected to the second terminal of the capacitor C2, the first terminal of the transistor MP7, and the terminal OT.

[0321] The second terminal of the transistor MP8 is electrically connected to the first gate of the transistor MP9, the second gate of the transistor MP9, and the first terminal of the capacitor C3, and the first gate of the transistor MP8 is electrically connected to the second gate of the transistor MP8 and the wiring VSE14. The first terminal of the transistor MP9 is electrically connected to the terminal PWC, and the second terminal of the transistor MP9 is electrically connected to the second terminal of the capacitor C3, the first terminal of the transistor MP10, and the terminal GT.

[0322] The second terminal of the transistor MP2 is electrically connected to the wiring VDE11, and the second gate of the transistor MP2 is electrically connected to the wiring BG11. The second terminal of the capacitor C1 is electrically connected to the wiring VDE12. The second terminal of the transistor MP4 is electrically connected to the wiring VDE13, and the second gate of the transistor MP4 is electrically connected to the wiring BG12. The second terminal of the transistor MP7 is electrically connected to the second gate of the transistor MP7 and the wiring VDE14. The second terminal of the transistor MP10 is electrically connected to the second gate of the transistor MP10 and the wiring VDE15.

[0323] As an example, each of the wirings VDE11 to VDE15 functions as a wiring that applies a constant potential, similar to the wirings VDE1 to VDE4 described in Configuration Example 1. The constant potential may be, for example, a high-level potential. The wirings VDE11 to VDE15 may be applied with the same constant potential or different constant potentials. Two or more selected wirings from each of the wirings VDE11 to VDE15 may be applied with the same constant potential, and the remaining wirings may be applied with a different potential. Among the wirings VDE11 to VDE15, two or more wirings that apply the same constant potential may be the same wiring. For example, if the wirings VDE11 and VDE12 apply the same constant potential, the wirings VDE11 and VDE12 may be the same wiring.

[0324] Furthermore, one or more selected from the wirings VDE1 to VDE15 may be wirings that apply a variable potential instead of a constant potential.

[0325] As an example, each of the wirings VSE11 to VSE14 functions as a wiring that applies a constant potential, similar to the wirings VSE1 to VSE5 described in Configuration Example 1. The constant potential may be, for example, a low-level potential or a ground potential. The wirings VSE11 to VSE14 may be applied with the same constant potential or different constant potentials. Two or more selected wirings from each of the wirings VSE11 to VSE14 may be applied with the same constant potential, and the remaining wirings may be applied with a different potential. Among the wirings VSE11 to VSE14, two or more wirings that apply the same constant potential may be the same wiring. For example, if the wirings VSE11 and VSE12 apply the same constant potential, the wirings VSE11 and VSE12 may be the same wiring.

[0326] Furthermore, one or more of the wirings VSE11 to VSE14 may be wirings that apply a variable potential instead of a constant potential.

[0327] For example, the wirings BG11 and BG12 function as wirings that apply a constant potential, similar to the wirings BG1 and BG2 described in Configuration Example 1. The constant potential may be, for example, a high-level potential. Note that the wirings BG11 and BG12 may be applied with the same constant potential or different constant potentials. Furthermore, when the wirings BG11 and BG12 are wirings that apply the same constant potential, the wirings BG11 and BG12 may be the same wiring.

[0328] Alternatively, one or both of the wirings BG11 and BG12 may be wirings that apply a variable potential instead of a constant potential.

[0329] As shown in circuit 100AA4 of Figure 15(B), by changing transistors MN1 to MN10 in the configuration of circuit 100A1 to transistors MP1 to MP10, changing wiring VDE1 to wiring VDE4 to wiring VSE11 to wiring VSE14, and changing wiring VSE1 to wiring VSE5 to wiring VDE11 to wiring VDE15, circuit 100AA4 may be able to perform the desired operation, similar to circuit 100A1.

[0330] 1A, the transistors MN1 to MN10 are replaced with transistors MP1 to MP10. However, the polarities of the n-channel and p-channel transistors included in the circuits shown in other drawings in this specification may also be changed. When the polarities of the transistors are changed, the magnitude of the constant potentials applied to the wirings VDE1 to VDE4, the wirings VSE1 to VSE5, the wirings BG1, and the wiring BG2 may also be changed.

[0331] In the circuit 100AA4, the second gate of the transistor MP7 is electrically connected to the second terminal of the transistor MP7, and the second gate of the transistor MP10 is electrically connected to the second terminal of the transistor MP10. However, the second gates of the transistors MP7 and MP10 in the circuit 100AA4 may be electrically connected to a wiring BG11. Alternatively, the second gates of the transistors MP7 and MP10 in the circuit 100AA4 may be electrically connected to a wiring BG12, as in the circuit 100A3 of FIG. 6A. Alternatively, the second gates of the transistors MP7 and MP10 in the circuit 100AA4 may be electrically connected to a new wiring, as in the circuit 100A4 of FIG. 6B. The new wiring may be a wiring that applies a constant potential, such as a high-level potential, or a variable potential.

[0332] As an example, the circuit 100AA5 in FIG. 16 has a configuration in which the transistors MN8 to MN10, the capacitor C3, and the terminal GT are not provided in the circuit 100A1 in FIG. 1A.

[0333] The circuit 100AA5 in FIG. 16 does not have a terminal GT, and therefore outputs a signal only to the terminal OT, not to the terminal GT. For example, by combining the circuit 100A1 in FIG. 1A and the circuit 100AA5 in FIG. 16 to form a shift register such as that shown in FIGS. 3A and 3B, the shift register can be configured so that no signal is output from the terminal GT of the circuit 100 to which the circuit 100AA5 is applied. Note that the shift register may be used to adjust the timing of a clock signal input to the shift register and signals output from the terminals OT, GT, etc. Furthermore, the timing adjustment can be performed during the design stage of the shift register.

[0334] Furthermore, the circuit 100AA5 in Figure 16 is configured such that the transistors MN8 to MN10, the capacitor C3, and the terminal GT are not provided in the circuit 100A1 in Figure 1(A), but it may be changed to a configuration in which the transistors MN5 to MN7, the capacitor C2, and the terminal OT are not provided instead (not shown).

[0335] 3A and 3B, a shift register of a unipolar circuit having only n-channel transistors (a unipolar circuit having only p-channel transistors in the case of the circuit 100AA4 in FIG. 15B) can be configured by using the circuit 100A1 described in the above-described Configuration Examples 1 to 8 for the shift register of the driver circuit GD. In particular, by applying any one of the circuit configurations of Configuration Examples 1 to 8 or a circuit configuration combining two or more circuits selected from Configuration Examples 1 to 8 to the shift register, a circuit with stable operation can be realized.

[0336] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0337] (Embodiment 2) In this embodiment, a specific circuit configuration of the circuit 100A1 described in the above embodiment will be described.

[0338] Fig. 17 is a layout diagram (plan view) showing an example of the circuit configuration of the circuit 100A1 of Fig. 1(A). Also, in Fig. 17, the circuit 100A1 includes, as an example, a conductor GEM, a conductor BGM, a conductor PLG, a conductor SDM, and a semiconductor SMC. Note that Fig. 17 does not show the insulators included in the circuit 100A1.

[0339] As an example, the conductor BGM is located below the semiconductor SMC. Also, as an example, the semiconductor SMC is located below the conductor GEM. Also, as an example, the conductor GEM is located below the conductor SDM. That is, in FIG. 17, the circuit 100A1 is formed in the order of the conductor BGM, the semiconductor SMC, the conductor GEM, and the conductor SDM from the bottom up.

[0340] A portion of the conductor BGM functions as the second gate of each of the transistors MN1 to MN10, for example. Also, a portion of the conductor GEM functions as the first gate of each of the transistors MN1 to MN10, for example.

[0341] The conductor BGM, semiconductor SMC, conductor GEM, and conductor SDM can each be formed using, for example, a photolithography method. Specifically, when forming the conductor BGM, for example, a conductive material that will become the conductor BGM can be formed using a film formation method such as a sputtering method, a CVD (Chemical Vapor Deposition) method, a PLD (Pulsed Laser Deposition) method, or an ALD (Atomic Layer Deposition) method, and then a desired pattern can be formed using a photolithography method. The semiconductor SMC, conductor GEM, and conductor SDM can also be formed using the same method as above.

[0342] Furthermore, an insulator may be provided between the conductor BGM and the semiconductor SMC, between the semiconductor SMC and the conductor GEM, and between the conductor GEM and the conductor SDM. In particular, the insulator provided between the conductor BGM and the semiconductor SMC may function as a first gate insulating film (sometimes referred to as a back-gate insulating film), and the insulator provided between the semiconductor SMC and the conductor GEM may function as a second gate insulating film (sometimes referred to as a gate insulating film or a front-gate insulating film).

[0343] Furthermore, the conductor PLG is located between the conductor BGM and the conductor GEM, between the conductor BGM and the conductor SDM, between the conductor GEM and the conductor SDM, or between the semiconductor SMC and the conductor SDM, and functions as wiring or a plug that electrically connects them. The conductor PLG is formed, for example, by forming an opening in the insulator and filling the opening with a conductive material that will become the conductor PLG. After the conductor PLG is formed, it may be planarized by a planarization process using a chemical mechanical polishing method or the like to align the film surfaces of the conductor PLG and the surrounding insulator.

[0344] 17 includes, as an example, a part of each of the conductor BGM, the semiconductor SMC, the conductor GEM, and the insulator. In other words, the transistors MN1 to MN10 are configured with materials such as a part of the conductor BGM, a part of the semiconductor SMC, a part of the conductor GEM, and a part of the insulator.

[0345] 17 includes a portion of the conductor BGM and a portion of the conductor GEM. Also, the capacitances C2 and C3 included in the circuit 100A1 of FIG. 17 include a portion of the conductor BGM and a portion of the conductor SDM. It is preferable that an insulator with a high dielectric constant be provided between the conductor BGM and the conductor GEM included in the capacitance C1. Similarly, it is preferable that an insulator with a high dielectric constant be provided between the conductor BGM and the conductor SDM included in the capacitance C2 and the capacitance C3.

[0346] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0347] (Embodiment 3) In this embodiment, a structural example of a display device in which a semiconductor device of one embodiment of the present invention and a display portion are combined will be described.

[0348] 18 is a cross-sectional view of a display device according to one embodiment of the present invention. The display device 10 includes a pixel layer PXAL, a wiring layer LINL, and a circuit layer SICL.

[0349] The wiring layer LINL is provided on the circuit layer SICL, and the pixel layer PXAL is provided on the wiring layer LINL.

[0350] The circuit layer SICL has a substrate BS, a drive circuit region DRV, and a functional circuit region MFNC.

[0351] The substrate BS can be, for example, a semiconductor substrate (e.g., a single-crystal substrate) made of silicon or germanium. In addition to semiconductor substrates, the substrate BS can also be, for example, an SOI (Silicon-On-Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate with stainless steel foil, a tungsten substrate, a substrate with tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as an acrylic resin. Examples of the material include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Examples of the material include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. If the manufacturing process of the display device 10 includes a heat treatment, it is preferable to use a material with high heat resistance for the substrate BS.

[0352] For example, when the substrate BS is a semiconductor substrate made of silicon, the transistors included in the drive circuit region DRV and the functional circuit region MFNC can be Si transistors.

[0353] Furthermore, for example, when the substrate BS is a glass substrate, the transistors included in the driver circuit region DRV and the functional circuit region MFNC can be OS transistors.

[0354] The drive circuit region DRV and the functional circuit region MFNC are provided on a substrate BS.

[0355] The drive circuit region DRV has, as an example, a drive circuit for driving pixels included in a pixel layer PXAL, which will be described later. Note that a specific configuration example of the drive circuit region DRV will be described later.

[0356] For example, the functional circuit region MFNC may include a GPU (Graphics Processing Unit). Furthermore, if the display device 10 includes a touch panel, the functional circuit region MFNC may include a sensor controller that controls a touch sensor included in the touch panel. Furthermore, if a light-emitting device using an EL material is used as the display element of the display device 10, the functional circuit region MFNC may include an EL correction circuit. Furthermore, if a liquid crystal element is used as the display element of the display device 10, the functional circuit region MFNC may include a gamma correction circuit.

[0357] The wiring layer LINL is provided on the circuit layer SICL.

[0358] The wiring layer LINL has wirings. The wirings included in the wiring layer LINL function as wirings that electrically connect, for example, a drive circuit included in a drive circuit region DRV provided below the wiring layer LINL and a circuit included in a pixel layer PXAL provided above the wiring layer LINL.

[0359] The pixel layer PXAL has, for example, a plurality of pixels, which may be arranged in a matrix in the pixel layer PXAL.

[0360] Each of the multiple pixels can express one or more colors. In particular, the multiple colors can be, for example, three colors: red (R), green (G), and blue (B). Alternatively, the multiple colors can be, for example, red (R), green (G), and blue (B) plus two or more colors selected from cyan, magenta, yellow, and white. Each pixel expressing a different color is called a sub-pixel, and when white is expressed by multiple sub-pixels of different colors, the multiple sub-pixels are sometimes collectively referred to as a pixel. For convenience, in this specification and other descriptions, a sub-pixel will be referred to as a pixel.

[0361] Fig. 19 is a block diagram showing an example of the configuration of the display device 10 shown in Fig. 18. The display device 10 shown in Fig. 19 has, as an example, a display unit DIS and a circuit unit SIC. Although Fig. 19 shows a sensor PDA, the sensor PDA may be disposed inside or outside the display device 10.

[0362] In FIG. 19, thick solid lines indicate multiple wirings or bus wirings.

[0363] 19, the display unit DIS has, as an example, a plurality of pixel circuits PX arranged in a matrix. The pixel circuits PX may be, for example, pixel circuits to which one or more selected from a liquid crystal display device, a light-emitting device containing an organic EL material, and a light-emitting device containing a light-emitting diode such as a micro LED are applied. In this embodiment, the pixel circuits PX of the display unit DIS will be described as being applied with a light-emitting device containing an organic EL material. Pixel circuits that can be applied to the display unit DIS, pixel circuits PX, etc. will be described in detail in embodiment 4.

[0364] In addition, in FIG. 19, the circuit section SIC has a drive circuit area DRV and a functional circuit area MFNC.

[0365] The drive circuit region DRV functions as a peripheral circuit for driving the display unit DIS, for example. Specifically, the drive circuit region DRV has, for example, a source driver circuit 11, a digital-to-analog conversion circuit 12, a gate driver circuit 13, and a level shifter 14. The source driver circuit 11 corresponds to, for example, the drive circuit SD in FIG. 2, and the gate driver circuit 13 corresponds to, for example, the drive circuit GD in FIG. 2.

[0366] 19, the functional circuit area MFNC may include, for example, a memory device that stores image data to be displayed on the display unit DIS, a decoder that restores encoded image data, a GPU (Graphics Processing Unit) that processes image data, a power supply circuit, a correction circuit, or a CPU. In FIG. 19, the functional circuit area MFNC includes, for example, a memory device 21, a GPU (AI accelerator) 22, an EL correction circuit 23, a timing controller 24, a CPU (NoffCPU (registered trademark)) 25, a sensor controller 26, and a power supply circuit 27.

[0367] Furthermore, the display device 10 in FIG. 19 is configured such that, as an example, bus wiring BSL is electrically connected to each of the circuits included in the drive circuit region DRV and the circuits included in the functional circuit region MFNC.

[0368] For example, the source driver circuit 11 has a function of transmitting image data to the pixel circuits PX included in the display unit DIS. Therefore, the source driver circuit 11 is electrically connected to the pixel circuits PX via wiring SL.

[0369] The digital-analog conversion circuit 12 has a function of converting image data that has been digitally processed by a GPU, a correction circuit, etc., which will be described later, into analog data. The image data that has been converted into analog data is transmitted to the display unit DIS via the source driver circuit 11. Note that the digital-analog conversion circuit 12 may be included in the source driver circuit 11, or the image data may be transmitted in the following order: source driver circuit 11, digital-analog conversion circuit 12, and display unit DIS.

[0370] For example, the gate driver circuit 13 has a function of selecting a pixel circuit PX to which image data is to be sent in the display unit DIS, and is therefore electrically connected to the pixel circuit PX via a wiring GL.

[0371] The level shifter 14 has a function of converting signals input to the source driver circuit 11, the digital-to-analog conversion circuit 12, the gate driver circuit 13, etc., to appropriate levels, for example.

[0372] For example, the storage device 21 has a function of storing image data to be displayed on the display unit DIS. The storage device 21 can be configured to store image data as digital data or analog data.

[0373] Furthermore, when image data is stored in the storage device 21, it is preferable to use a nonvolatile memory as the storage device 21. In this case, for example, a NAND type memory or the like can be used as the storage device 21.

[0374] Furthermore, when temporary data generated by the GPU 22, the EL correction circuit 23, the CPU 25, etc. is stored in the storage device 21, it is preferable to use a volatile memory as the storage device 21. In this case, for example, an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), etc. can be used as the storage device 21.

[0375] As an example, the GPU 22 has a function of performing processing to draw image data read from the storage device 21 on the display unit DIS. In particular, the GPU 22 is configured to perform pipeline processing in parallel, so that it can process image data to be displayed on the display unit DIS at high speed. The GPU 22 can also function as a decoder to restore encoded images.

[0376] The functional circuit region MFNC may also include multiple circuits capable of improving the display quality of the display unit DIS. For example, such circuits may include a correction circuit (a circuit for correcting color or dimming) that detects color unevenness in an image displayed on the display unit DIS and corrects the color unevenness to produce an optimal image. Furthermore, if a light-emitting device using an organic electroluminescent (EL) material is used in the pixels of the display unit DIS, the functional circuit region MFNC may also include an EL correction circuit. The luminance of a light-emitting device using an organic EL material is determined by the amount of current flowing through the light-emitting device. Therefore, if the amount of current flowing through the light-emitting device changes due to transistor characteristics or the like, the luminance of the light-emitting device will also change unintentionally. The EL correction circuit measures the amount of current flowing through the light-emitting device, compares it with the desired amount, and adjusts the amount of current flowing through the light-emitting device as necessary. This allows the luminance of the light-emitting device to be optimized. In this embodiment, since the pixel circuits PX of the display unit DIS are described as being applied with light-emitting devices containing organic EL materials, the functional circuit region MFNC includes an EL correction circuit 23 as an example.

[0377] Furthermore, artificial intelligence may be used for the image correction described above. For example, the current flowing through a display device (or the voltage applied to the display device) provided in the pixel may be monitored and acquired, and the image displayed on the display unit DIS may be acquired by an image sensor or the like, and the current (or voltage) and the image may be treated as input data for an artificial intelligence calculation (for example, an artificial neural network), and the output result may be used to determine whether or not to correct the image.

[0378] Furthermore, the calculations of the artificial intelligence can be applied not only to image correction but also to up-conversion processing of image data. As a result, by up-converting low-resolution image data to match the resolution of the display unit DIS, it is possible to display high-quality images on the display unit DIS. The calculations of the artificial intelligence can also be applied to down-conversion processing of image data.

[0379] The above-mentioned artificial intelligence calculations can be performed using the GPU 22 included in the functional circuit area MFNC. That is, the GPU 22 can be used to perform various correction calculations (such as a circuit 22a that corrects color unevenness and a circuit 22b that performs up-conversion processing).

[0380] In this specification, a GPU that performs artificial intelligence calculations is referred to as an AI accelerator. That is, in this specification, a GPU provided in the functional circuit area MFNC may be described as an AI accelerator.

[0381] The timing controller 24 has a function of varying the frame rate at which images are displayed on the display unit DIS, for example. For example, when a still image is displayed on the display unit DIS, the display device 10 can be driven by the timing controller 24 at a lower frame rate. Also, for example, when a moving image is displayed on the display unit DIS, the display device 10 can be driven by the timing controller 24 at an increased frame rate. In other words, by providing the timing controller 24 in the display device 10, the frame rate can be changed depending on whether the image is a still image or a moving image. In particular, when a still image is displayed on the display unit DIS, the display device 10 can be operated at a lower frame rate, thereby reducing the power consumption of the display device 10.

[0382] The CPU 25 has the function of performing general-purpose processing, such as running an operating system, controlling data, performing various calculations, and running programs. In the display device 10, the CPU 25 has the role of issuing commands such as writing or reading image data to or from the storage device 21, correcting image data, or issuing commands to a sensor (described later). The CPU 25 may also have the function of transmitting control signals to one or more circuits selected from circuits included in the functional circuit area MFNC, such as the storage device, GPU, correction circuit, timing controller, and high-frequency circuit.

[0383] The CPU 25 may also have a circuit (hereinafter referred to as a backup circuit) that temporarily backs up data. It is preferable that the backup circuit be able to retain the data even if, for example, the supply of power supply voltage is stopped. For example, when a still image is displayed on the display unit DIS, the CPU 25 can suspend its function until an image different from the current still image is displayed. Therefore, by temporarily saving data being processed by the CPU 25 to the backup circuit and then stopping the supply of power supply voltage to the CPU 25, the dynamic power consumption of the CPU 25 can be reduced. In this specification, a CPU having a backup circuit is referred to as an Noff CPU.

[0384] As an example, the sensor controller 26 has a function of controlling the sensor PDA. In addition, in Fig. 19, a line SNCL is illustrated as a line for electrically connecting the sensor PDA and the sensor controller 26.

[0385] The sensor PDA may be, for example, a touch sensor that can be provided above, below, or inside the display unit DIS.

[0386] Alternatively, the sensor PDA may be, for example, an illuminance sensor. In particular, by obtaining the intensity of external light illuminating the display unit DIS using the illuminance sensor, it is possible to change the brightness (luminance) of the image displayed on the display unit DIS in accordance with the external light. For example, when the external light is bright, the luminance of the image displayed on the display unit DIS can be increased to improve the visibility of the image. Conversely, when the external light is dark, the luminance of the image displayed on the display unit DIS can be decreased to reduce power consumption.

[0387] Alternatively, the sensor PDA may be, for example, an image sensor, which may acquire an image or the like and display the image on the display unit DIS.

[0388] For example, the power supply circuit 27 has a function of generating voltages to be supplied to circuits included in the drive circuit area DRV, circuits included in the functional circuit area MFNC, pixels included in the display unit DIS, etc. The power supply circuit 27 may also have a function of selecting the circuit to which to supply voltage. For example, the power supply circuit 27 can reduce the power consumption of the entire display device 10 by stopping the voltage supply to the CPU 25, GPU 22, etc. while a still image is being displayed on the display unit DIS.

[0389] <Image sensor configuration example> Here, an image sensor that can be used in the sensor PDA of the display device 10 will be described.

[0390] As an image sensor applicable to the sensor PDA, for example, an imaging device IM shown in FIG. 20 can be used.

[0391] 20 is a block diagram showing an example of the circuit configuration of the imaging device IM. The imaging device IM includes an imaging section 31, a first driving circuit section 33, a second driving circuit section 34, a readout circuit section 35, and a control circuit section 36. The first driving circuit section 33, the second driving circuit section 34, the readout circuit section 35, and the control circuit section 36 may be collectively referred to as a "functional circuit." The functional circuit may be a variety of circuits such as a shift register, a level shifter, an inverter, a latch, an analog switch, or a logic circuit.

[0392] The transistors used in the imaging unit 31 and functional circuits of the imaging device IM may be n-channel transistors or p-channel transistors. Both n-channel transistors and p-channel transistors may be used. The imaging unit 31 and functional circuits may have a CMOS structure that combines n-channel transistors and p-channel transistors.

[0393] The imaging section 31 includes imaging pixels 32 arranged in a matrix of m rows and n columns (m and n are each an integer of 1 or greater). The imaging section 31 is electrically connected to the first drive circuit section 33 via a plurality of wirings 41. The imaging section 31 is also electrically connected to the readout circuit section 35 via a plurality of wirings 42. The readout circuit section 35 is electrically connected to the second drive circuit section 34 via a plurality of wirings 43. For example, the imaging pixel 32 arranged in the i-th row (where i is an integer of 1 to m) is electrically connected to the first drive circuit section 33 via the i-th wiring 41. The imaging pixel 32 arranged in the j-th column (where j is an integer of 1 to n) is electrically connected to the readout circuit section 35 via the j-th wiring 42.

[0394] 20, the imaging pixel 32 arranged in the first row and first column is indicated as imaging pixel 32[1,1], the imaging pixel 32 arranged in the mth row and nth column is indicated as imaging pixel 32[m,n], and the imaging pixel 32 arranged in the ith row and jth column is indicated as imaging pixel 32[i,j].

[0395] It should be noted that the wirings connected to one imaging pixel 32 are not limited to the wiring 41 and the wiring 42. Wires other than the wiring 41 and the wiring 42 may be connected to the imaging pixel 32.

[0396] The pixel density (also referred to as "resolution") of the imaging unit 31 is preferably 100 ppi to 10,000 ppi, and more preferably 1,000 ppi to 10,000 ppi. For example, the resolution may be 2,000 ppi to 6,000 ppi, or 3,000 ppi to 5,000 ppi.

[0397] There is no particular limitation on the aspect ratio of the imaging section 31. The imaging section 31 of the imaging device IM can accommodate various aspect ratios, such as 1:1 (square), 4:3, 16:9, and 16:10.

[0398] The diagonal size of the imaging unit 31 may be between 0.1 inches and 100 inches, or may be 100 inches or larger depending on the situation.

[0399] The control circuit 36 ​​has a function of controlling the operation of the circuits included in the imaging device IM. The first drive circuit 33 has a function of selecting the imaging pixels 32 for each row. The imaging pixels 32 in the row selected by the first drive circuit 33 output imaging data to the readout circuit 35 via wiring 42.

[0400] The readout circuit unit 35 holds the imaging data supplied from the imaging pixels 32 for each column and performs noise removal processing, etc. As the noise removal processing, for example, CDS (Correlated Double Sampling) processing, etc. The readout circuit unit 35 may also have a function of amplifying the imaging data or a function of analog-to-digital conversion of the imaging data.

[0401] The second drive circuit section 34 has a function of sequentially selecting the imaging data held in the readout circuit section 35 and outputting the imaging data from the output terminal OUT to the outside.

[0402] One or more selected from the first drive circuit unit 33, the second drive circuit unit 34, the readout circuit unit 35, and the control circuit unit 36 ​​may be provided with, for example, the shift register shown in Fig. 3(A) or 3(B) described in embodiment 1. Furthermore, as the circuits 100[1] to 100[m] of the shift register, for example, the circuit 100A1 described in configuration examples 1 to 8 of embodiment 1 may be applied.

[0403] <Example of imaging pixel circuit configuration> 21(A) is a circuit diagram illustrating an example of the circuit configuration of an imaging pixel 32. The imaging pixel 32 includes a photoelectric conversion device PHD (also referred to as a "photoelectric conversion element" or an "imaging element"), transistors Tr1, Tr2, Tr3, and Tr4, and a capacitance CA. Note that the capacitance CA may not be provided. Note that in this specification and elsewhere, a configuration excluding the photoelectric conversion device PHD from the above elements may be referred to as an "imaging pixel circuit."

[0404] One electrode (cathode) of the photoelectric conversion device PHD is electrically connected to either the source or the drain of transistor Tr1. The other of the source or the drain of transistor Tr1 is electrically connected to either the source or the drain of transistor Tr2. One of the source or the drain of transistor Tr2 is electrically connected to one electrode of capacitor CA. One electrode of capacitor CA is electrically connected to the gate of transistor Tr3. One of the source or the drain of transistor Tr3 is electrically connected to either the source or the drain of transistor Tr4.

[0405] Here, the electrical connection point between the other of the source or drain of the transistor Tr1, one electrode of the capacitor CA, and the gate of the transistor Tr3 is referred to as a node FD, which can function as a charge detection unit.

[0406] The other electrode (anode) of the photoelectric conversion device PHD is electrically connected to wiring POW1. The gate of transistor Tr1 is electrically connected to wiring SEL2. The other of the source or drain of transistor Tr2 is electrically connected to wiring POW2. The other of the source or drain of transistor Tr3 is electrically connected to wiring POW3. The gate of transistor Tr2 is electrically connected to wiring SEL1. The gate of transistor Tr4 is electrically connected to wiring SEL3. The other electrode of capacitor CA is electrically connected to a reference potential line, such as a GND wiring. The other of the source or drain of transistor Tr4 is electrically connected to wiring OPT.

[0407] The wirings SEL2, SEL1, and SEL3 function as signal lines that control the on / off states of the respective transistors. The wiring OPT functions as an output line.

[0408] The wiring POW1, wiring POW2, and wiring POW3 function as power supply lines. The imaging pixel 32 shown in Figure 21(A) has a configuration in which the cathode of the photoelectric conversion device PHD is electrically connected to the transistor Tr1, and imaging operation is possible by resetting the node FD to a high potential. Therefore, the wiring POW2 is set to a high potential (a higher potential than the wiring POW1).

[0409] 21A shows a configuration in which the cathode of the photoelectric conversion device PHD is electrically connected to the node FD, but a configuration in which the anode of the photoelectric conversion device PHD is electrically connected to either the source or the drain of the transistor Tr1 may be used. In this case, since the configuration is such that an imaging operation is possible by resetting the node FD to a low potential, the wiring POW2 may be set to a low potential (a potential lower than that of the wiring POW1).

[0410] Transistor Tr1 has the function of controlling the potential of node FD. Transistor Tr1 is also called a "transfer transistor." Transistor Tr2 has the function of resetting the potential of node FD. Transistor Tr2 is also called a "reset transistor." Transistor Tr3 functions as a source follower circuit and can output the potential of node FD to wiring OPT as imaging data. Transistor Tr4 has the function of selecting the pixel that outputs imaging data. Transistor Tr3 is also called an "amplification transistor." Transistor Tr4 is also called a "selection transistor."

[0411] 21(B), a plurality of pairs of a photoelectric conversion device PHD and a transistor Tr1 may be connected to the node FD. The circuit configuration shown in FIG. 21(B) can reduce the area occupied by each imaging pixel 32. This can increase the packaging density of the imaging pixels 32.

[0412] In FIG. 21B, the first pair of photoelectric conversion device PHD and transistor Tr1 is shown as photoelectric conversion device PHD_1 and transistor Tr1_1. The gate of transistor Tr1_1 is electrically connected to wiring SEL2_1. The second pair of photoelectric conversion device PHD and transistor Tr1 is shown as photoelectric conversion device PHD_2 and transistor Tr1_2. The gate of transistor Tr1_2 is electrically connected to wiring SEL2_2. The kth pair (k is an integer greater than or equal to 1) of photoelectric conversion device PHD and transistor Tr1 is shown as photoelectric conversion device PHD_k and transistor Tr1_k. The gate of transistor Tr1_k is electrically connected to wiring SEL2_k.

[0413] For example, all of the transistors included in the imaging device IM can be manufactured in the same process.

[0414] The functional circuits included in the imaging device IM do not need to have all of the components shown in the present embodiment or may have components other than these.

[0415] <Configuration example of display device and imaging device> Next, the configuration of the display device 10 in which the display device and the imaging device are integrated will be described.

[0416] Figure 22 shows the configuration of a display device 10 that combines a display device (hereinafter referred to as display device DS) that includes the pixel array PA, source driver circuit 11, and gate driver circuit 13 shown in Figure 19 with the imaging device IM shown in Figure 21.

[0417] In addition, in Figure 22, the multiple wirings 41 are described as wirings 41[1] to wirings 41[m], the multiple wirings 42 are described as wirings 42[1] to wirings 42[n], and the multiple wirings 43 are described as wirings 43[1] to wirings 43[n].

[0418] In FIG. 22, as an example, the second drive circuit section 34 and the source driver circuit 11 are electrically connected by wirings 44[1] to 44[n].

[0419] As an example, the imaging data read out by the readout circuit unit 35 is transmitted to the source driver circuit 11 via wiring 43[1] to wiring 43[n], the second drive circuit unit 34, and wiring 44[1] to wiring 44[n].

[0420] For this reason, the source driver circuit 11 may have functions such as voltage adjustment, polarity conversion, and power amplification of the imaging data supplied from the imaging device IM. In other words, the source driver circuit 11 may have a function of converting the imaging data into an image signal. This allows the source driver circuit 11 to output the image signal converted from the imaging data to the pixel array PA.

[0421] With this configuration, the imaging data acquired by the imaging unit 31 can be converted into an image signal more suitable for display on the pixel array PA by the source driver circuit 11. This makes it possible to realize, for example, a display device that is less susceptible to the effects of noise and has good display quality.

[0422] The display device 10 described above may also be configured such that the pixel array PA and the imaging unit 31 are arranged in the same array. For example, as shown in Fig. 23, the display device 10 may be configured such that the pixel circuit and the imaging circuit are arranged in the same array.

[0423] The display device 10 shown in Fig. 23 has a configuration in which circuits CE[1,1] to CE[m,n] are arranged in a matrix of m rows and n columns in a cell array AY. When i is an integer between 1 and m, and j is an integer between 1 and n, the circuit CE[i,j] includes, for example, a pixel circuit PX[i,j] and an imaging pixel 32[i,j]. Note that Fig. 23 only illustrates the circuit CE[1,1] and the circuit CE[m,n] in the cell array AY with reference symbols.

[0424] 23, the display device 10 may be configured such that the pixel circuits PX and the imaging pixels 32 are arranged in the same array, thereby enabling the entire display unit to serve as a sensor area. For example, the imaging pixels 32[1,1] to 32[m,n] capture images of a user's finger, thereby providing the display device 10 with a function for fingerprint authentication. Furthermore, the imaging pixels 32[1,1] to 32[m,n] continuously capture images of the user's finger, thereby enabling the display device 10 or an electronic device including the display device 10 to recognize the movement of the user's finger. Furthermore, the display device 10 or an electronic device including the display device 10 may be provided with a function for performing various operations (e.g., zooming in or out of an image, scrolling a displayed image, etc.) in response to the movement of the user's finger. In other words, the display device 10 may be provided with a function as a touch panel.

[0425] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0426] (Fourth embodiment) In this embodiment, a display device that can be included in an electronic device of one embodiment of the present invention will be described. Note that the display device described in this embodiment can be applied to the display unit DIS described in the above embodiment.

[0427] <Example of display device configuration> 24 is a cross-sectional view illustrating an example of a display device according to one embodiment of the present invention. As an example, a display device 1000 illustrated in FIG. 24 has a structure in which a pixel circuit and a driver circuit are provided over a substrate 310. Note that the display device DSP, the display device 10, and the like according to the above-described embodiments can have the same structure as the display device 1000 illustrated in FIG. 24.

[0428] Specifically, for example, the circuit layer SICL, wiring layer LINL, and pixel layer PXAL shown in the display device 10 can be configured as in the display device 1000 of Fig. 24. The circuit layer SICL has, as an example, a substrate 310, on which a transistor 300 is formed. In addition, a wiring layer LINL is provided above the transistor 300, and the wiring layer LINL is provided with wiring that electrically connects the transistor 300, a transistor 200 described later, a light-emitting device 150a, a light-emitting device 150b described later, and the like. In addition, a pixel layer PXAL is provided above the wiring layer LINL, and the pixel layer PXAL has, as an example, the transistor 200, a light-emitting device 150 (the light-emitting device 150a and the light-emitting device 150b in Fig. 24), and the like.

[0429] For example, a substrate that can be used for the substrate BS described above can be used as the substrate 310. Note that if a heat treatment is included in the manufacturing process of the display device 1000, it is preferable to select a material with high heat resistance for the substrate 310.

[0430] In this embodiment, the substrate 310 will be described as a semiconductor substrate made of silicon.

[0431] The transistor 300 is provided over a substrate 310 and includes an element isolation layer 312, a conductor 316, an insulator 315, an insulator 317, a semiconductor region 313 formed of part of the substrate 310, and low-resistance regions 314a and 314b functioning as source and drain regions. Therefore, the transistor 300 is a Si transistor. Note that although FIG. 24 illustrates a structure in which one of the source and drain of the transistor 300 is electrically connected to the conductor 330, the conductor 356, and the conductor 366, which will be described later, through the conductor 328, the electrical connection structure of the semiconductor device of one embodiment of the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention may have a structure in which the gate of the transistor 300 is electrically connected to the conductor 330, the conductor 356, and the conductor 366 through the conductor 328.

[0432] The transistor 300 can be made into a fin type by, for example, configuring the top surface and the side surfaces in the channel width direction of the semiconductor region 313 to be covered with a conductor 316 via an insulator 315 that functions as a gate insulating film. By configuring the transistor 300 as a fin type, the effective channel width can be increased, and the on-state characteristics of the transistor 300 can be improved. Furthermore, the contribution of the electric field of the gate electrode can be increased, and the off-state characteristics of the transistor 300 can be improved.

[0433] Note that the transistor 300 may be either a p-channel transistor or an n-channel transistor. Alternatively, a plurality of transistors 300 may be provided, and both p-channel and n-channel transistors may be used.

[0434] The region in the semiconductor region 313 where the channel is formed, the region nearby, and the low-resistance region 314a and low-resistance region 314b that serve as the source or drain region preferably contain a semiconductor such as a silicon-based semiconductor, preferably single-crystal silicon. Alternatively, they may be formed of a material containing germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), aluminum gallium arsenide (GaAlAs), or gallium nitride (GaN). The transistor 300 may also be configured using silicon in each of the above regions, with the effective mass controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 300 may be a high electron mobility transistor (HEMT) using gallium arsenide and aluminum gallium arsenide.

[0435] The conductor 316, which functions as a gate electrode, can be made of a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron. Alternatively, the conductor 316 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material.

[0436] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a stacked layer, and tungsten is particularly preferable in terms of heat resistance.

[0437] The element isolation layer 312 is provided to isolate a plurality of transistors formed on the substrate 310. The element isolation layer can be formed by using, for example, a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, a mesa isolation method, or the like.

[0438] 24 is just an example, and the structure of the transistor 300 is not limited to this example, and an appropriate transistor may be used depending on the circuit configuration, driving method, etc. For example, the transistor 300 may have a planar structure instead of a fin structure.

[0439] In the transistor 300 shown in FIG. 24, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order from the substrate 310 side.

[0440] The insulators 320, 322, 324, and 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride.

[0441] The insulator 322 may function as a planarizing film that flattens steps caused by the insulator 320 and the transistor 300 covered by the insulator 322. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the flatness.

[0442] Furthermore, the insulator 324 is preferably a barrier insulating film that prevents impurities such as water and hydrogen from diffusing from the substrate 310 or the transistor 300 to a region above the insulator 324 (e.g., a region where the transistor 200, the light-emitting device 150a, the light-emitting device 150b, etc. are provided). Therefore, the insulator 324 is preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (i.e., through which the impurities are less likely to permeate). Depending on the situation, the insulator 324 is preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, and NO), and copper atoms (i.e., through which the oxygen is less likely to permeate). Alternatively, the insulator 324 preferably has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules).

[0443] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method.

[0444] The amount of desorbed hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS) etc. For example, the amount of desorbed hydrogen from the insulator 324 is calculated by TDS analysis as follows: when the surface temperature of the film is in the range of 50°C to 500°C, the amount of desorbed hydrogen converted into hydrogen atoms is 10 x 10 per area of ​​the insulator 324. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0445] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0446] Furthermore, insulators 320, 322, 324, and 326 are embedded conductors 328 and 330, which connect to a light-emitting device or circuit element located above insulator 326. Conductors 328 and 330 function as plugs or wiring. Conductors functioning as plugs or wiring may be collectively designated by the same reference numeral. In this specification, the wiring and the plug connecting to the wiring may be integral. That is, there are cases where a portion of a conductor functions as a wiring, and cases where a portion of a conductor functions as a plug.

[0447] The materials for each plug and wiring (e.g., conductor 328 and conductor 330) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a laminated layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0448] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 24 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order over the insulator 326 and the conductor 330. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 300. Note that the conductor 356 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0449] Note that, for example, the insulator 350 is preferably an insulator that has barrier properties against hydrogen, oxygen, and water, similar to the insulator 324. Similarly to the insulator 326, the insulators 352 and 354 are preferably insulators with a relatively low dielectric constant in order to reduce parasitic capacitance between wirings. The insulators 362 and 364 function as an interlayer insulating film and a planarizing film. The conductor 356 preferably includes a conductor that has barrier properties against hydrogen, oxygen, and water.

[0450] Note that, for example, tantalum nitride is preferably used as the conductor having a barrier property against hydrogen. Furthermore, by stacking tantalum nitride and highly conductive tungsten, the diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0451] Furthermore, on the insulator 354 and the conductor 356, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order.

[0452] The insulator 360 is preferably an insulator having barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 360 can be made of, for example, a material that can be used for the insulator 324.

[0453] The insulators 362 and 364 function as an interlayer insulating film and a planarizing film. As the insulators 362 and 364, an insulator having a barrier property against impurities such as water and hydrogen is preferably used, similar to the insulator 324. Therefore, a material that can be used for the insulator 324 can be used for one or both of the insulators 362 and 364.

[0454] Openings are formed in the insulators 360, 362, and 364 in regions that overlap with part of the conductor 356, and the conductor 366 is provided to fill the openings. The conductor 366 is also formed over the insulator 362. For example, the conductor 366 functions as a plug or a wiring connected to the transistor 300. Note that the conductor 366 can be formed using a material similar to that of the conductors 328 and 330.

[0455] An insulator 370 and an insulator 372 are stacked in this order on the insulator 364 and the conductor 366 .

[0456] The insulator 370 is preferably an insulator having barrier properties against impurities such as water or hydrogen, similar to the insulator 324. Therefore, the insulator 370 can be made of, for example, a material that can be used for the insulator 324.

[0457] The insulator 372 functions as an interlayer insulating film and a planarizing film. Similarly to the insulator 324, the insulator 372 is preferably an insulator having a barrier property against impurities such as water and hydrogen. Therefore, the insulator 372 can be made of a material that can be used for the insulator 324.

[0458] Furthermore, openings are formed in the insulators 370 and 372 in regions that overlap with portions of the conductor 366, and the conductor 376 is provided to fill the openings. The conductor 376 is also formed on the insulator 372. Thereafter, the conductor 376 is patterned into the shape of wiring, terminals, pads, or the like by etching or the like.

[0459] For example, copper, aluminum, tin, zinc, tungsten, silver, platinum, or gold can be used for the conductor 376. Note that the conductor 376 is preferably made of the same material as the conductor 216 included in the pixel layer PXAL, which will be described later.

[0460] Next, an insulator 380 is formed to cover the insulator 372 and the conductor 376, and then a planarization process using a chemical mechanical polishing (CMP) method or the like is performed until the conductor 376 is exposed. This allows the conductor 376 to be formed on the substrate 310 as a wiring, a terminal, or a pad.

[0461] For example, similar to the insulator 324, the insulator 380 is preferably a film having barrier properties that prevent the diffusion of impurities such as water and hydrogen. That is, it is preferable to use a material that can be used for the insulator 324 for the insulator 380. Alternatively, similar to the insulator 326, for example, the insulator 380 may be an insulator with a relatively low dielectric constant in order to reduce parasitic capacitance that occurs between wirings. That is, the insulator 380 may be a material that can be used for the insulator 326.

[0462] The pixel layer PXAL, for example, includes a substrate 210, a transistor 200, a light-emitting device 150 (light-emitting device 150a and light-emitting device 150b in FIG. 24), and a substrate 102. The pixel layer PXAL also includes, for example, an insulator 220, an insulator 222, an insulator 226, an insulator 250, an insulator 111a, an insulator 111b, an insulator 112, an insulator 113, an insulator 162, and a resin layer 163. The pixel layer PXAL also includes, for example, a conductor 216, a conductor 228, a conductor 230, a conductor 121 (conductor 121a and conductor 121b in FIG. 24), a conductor 122 (conductor 122a and conductor 122b in FIG. 24), and a conductor 123.

[0463] 24, for example, the insulator 202 functions as a bonding layer together with the insulator 380. The insulator 202 is preferably made of the same material as the material used for the insulator 380, for example.

[0464] The substrate 210 is provided above the insulator 202. In other words, the insulator 202 is formed on the lower surface of the substrate 210. As the substrate 210, it is preferable to use, for example, a substrate that can be used as the substrate 310. Note that in the display device 1000 of FIG. 24, the substrate 310 will be described as a semiconductor substrate made of silicon.

[0465] For example, a transistor 200 is formed on the substrate 210. The transistor 200 functions as a Si transistor because it is formed on the substrate 210, which is a semiconductor substrate made of silicon. Note that the description of the transistor 300 is to be referred to for the configuration of the transistor 200.

[0466] An insulator 220 and an insulator 222 are provided above the transistor 200. The insulator 220 functions as an interlayer insulating film and a planarizing film, similar to the insulator 320. The insulator 222 functions as an interlayer insulating film and a planarizing film, similar to the insulator 322.

[0467] A plurality of openings are provided in the insulator 220 and the insulator 222. The plurality of openings are formed in regions overlapping with the source and drain of the transistor 200 and a region overlapping with the conductor 376. Of the plurality of openings, a conductor 228 is formed in the opening formed in the region overlapping with the source and drain of the transistor 200. Of the remaining openings, an insulator 214 is formed on the side surfaces of the opening formed in the region overlapping with the conductor 376, and a conductor 216 is formed in the remaining openings. In particular, the conductor 216 may be called a TSV (Through Silicon Via).

[0468] The conductor 216 or the conductor 228 may be made of, for example, a material that can be used for the conductor 328. In particular, the conductor 216 is preferably made of the same material as the conductor 376.

[0469] The insulator 214 has a function of insulating the substrate 210 from the conductor 216. Note that the insulator 214 is preferably made of a material that can be used for the insulator 320 or the insulator 324, for example.

[0470] The insulator 380 and the conductor 376 formed on the substrate 310 and the insulator 202 and the conductor 216 formed on the substrate 210 are joined together by, for example, a bonding process.

[0471] As a pre-process before the bonding process, for example, a planarization process is performed on the substrate 310 side to align the heights of the surfaces of the insulator 380 and the conductor 376. Similarly, a planarization process is performed on the substrate 210 side to align the heights of the surfaces of the insulator 202 and the conductor 216.

[0472] In the bonding process, when bonding insulator 380 and insulator 202, that is, bonding between insulators, a hydrophilic bonding method can be used in which high flatness is achieved by polishing or the like, then surfaces that have been hydrophilically treated with oxygen plasma or the like are brought into contact with each other to temporarily bond them, and then the final bonding is performed by dehydrating them through heat treatment.Hydrophilic bonding also produces bonds at the atomic level, so mechanically excellent bonding can be obtained.

[0473] Furthermore, when bonding conductor 376 and conductor 216, that is, bonding conductors together, a surface activated bonding method can be used, in which oxide films and impurity adsorption layers on the surfaces are removed by sputtering or other methods, and the cleaned and activated surfaces are brought into contact and bonded. Alternatively, a diffusion bonding method can be used, in which surfaces are bonded using a combination of temperature and pressure. Both methods involve bonding at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0474] By carrying out the above-described bonding process, the conductor 376 on the substrate 310 side can be electrically connected to the conductor 216 on the substrate 210 side. Also, a connection with sufficient mechanical strength can be obtained between the insulator 380 on the substrate 310 side and the insulator 202 on the substrate 210 side.

[0475] When bonding substrate 310 and substrate 210, since the bonding surfaces of each substrate contain a mixture of insulating and metal layers, a surface activated bonding method and a hydrophilic bonding method may be combined. For example, a bonding method may be used in which the surfaces are polished and then cleaned, and the surface of the metal layer is subjected to an anti-oxidation treatment, followed by a hydrophilic treatment. Alternatively, the surface of the metal layer may be made of a resistant metal such as gold and then subjected to a hydrophilic treatment.

[0476] Note that bonding methods other than those described above may be used to bond the substrates 310 and 210. For example, flip-chip bonding may be used to bond the substrates 310 and 210. Furthermore, when using flip-chip bonding, connection terminals such as bumps may be provided above the conductor 376 on the substrate 310 side or below the conductor 216 on the substrate 210 side. Examples of flip-chip bonding include a bonding method in which a resin containing anisotropic conductive particles is injected between the insulator 380 and the insulator 202 and between the conductor 376 and the conductor 216, and a bonding method using silver-tin solder. Alternatively, when the bumps and the conductors connected to the bumps are both made of gold, ultrasonic bonding may be used. Furthermore, in addition to the flip-chip bonding method described above, an underfill agent may be injected between the insulator 380 and the insulator 202 and between the conductor 376 and the conductor 216 to reduce physical stress such as impact and thermal stress. Furthermore, for example, the substrate 310 and the substrate 210 may be bonded together using a die bonding film.

[0477] An insulator 224 and an insulator 226 are stacked in this order on the insulator 222, the insulator 214, the conductor 216, and the conductor 228.

[0478] Like the insulator 324, the insulator 224 is preferably a barrier insulating film that prevents impurities such as water and hydrogen from diffusing into a region above the insulator 224. Therefore, it is preferable to use, for example, a material that can be used for the insulator 324 as the insulator 224.

[0479] The insulator 226 is preferably an interlayer film with a low dielectric constant, similar to the insulator 326. Therefore, the insulator 226 is preferably made of a material that can be used for the insulator 326, for example.

[0480] Furthermore, a conductor 230 and the like that are electrically connected to the transistor 200, the light-emitting device 150, and the like are embedded in the insulator 224 and the insulator 226. The conductor 230 functions as a plug or wiring. For example, the conductor 328 or a material that can be used for the conductor 330 can be used as the conductor 230.

[0481] On the insulators 224 and 226, the insulators 250, 111a, and 111b are stacked in this order.

[0482] The insulator 250 is preferably an insulator having barrier properties against impurities such as water or hydrogen, similar to the insulator 324. Therefore, the insulator 250 can be made of, for example, a material that can be used for the insulator 324.

[0483] The insulator 111a and the insulator 111b can be formed using various inorganic insulating films such as an insulating oxide film, an insulating nitride film, an insulating oxynitride film, and an insulating nitride oxide film. The insulator 111a is preferably formed using an insulating oxide film or an insulating oxynitride film such as a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film. The insulator 111b is preferably formed using a nitride insulating film or an insulating nitride oxide film such as a silicon nitride film or a silicon nitride oxide film. More specifically, the insulator 111a is preferably formed using a silicon oxide film, and the insulator 111b is preferably formed using a silicon nitride film. The insulator 111b preferably functions as an etching protective film. Alternatively, the insulator 111a may be formed using a nitride insulating film or a nitride oxide insulating film, and the insulator 111b may be formed using an insulating oxide film or an oxynitride insulating film. Although this embodiment illustrates an example in which a recess is provided in the insulator 111b, the insulator 111b does not necessarily have a recess.

[0484] Furthermore, openings are formed in the regions of the insulator 250, the insulator 111a, and the insulator 111b that overlap with part of the conductor 230, and the conductor 121 is provided to fill the openings. Note that in this specification and the like, the conductors 121a and 121b shown in FIG. 24 are collectively referred to as the conductor 121. Note that the conductor 121 can be provided using the same material as the conductor 328 and the conductor 330.

[0485] In addition, the pixel electrode described in this embodiment mode includes, for example, a material that reflects visible light, and the counter electrode includes a material that transmits visible light.

[0486] The display device 1000 is a top-emission type. Light emitted from the light-emitting device is emitted toward the substrate 102. The substrate 102 is preferably made of a material that is highly transparent to visible light.

[0487] Above the conductor 121, a light emitting device 150a and a light emitting device 150b are provided.

[0488] Here, the light emitting device 150a and the light emitting device 150b will be described.

[0489] The light-emitting device described in this embodiment refers to a self-luminous light-emitting device such as an organic EL element (also called an OLED (Organic Light Emitting Diode)). Note that the light-emitting device electrically connected to the pixel circuit can be a self-luminous light-emitting device such as an LED (Light Emitting Diode), a micro LED, a QLED (Quantum-dot Light Emitting Diode), or a semiconductor laser.

[0490] The conductor 122a and the conductor 122b can be formed, for example, by forming a conductive film over the insulator 111b, the conductor 121a, and the conductor 121b, and then performing a patterning process and an etching process on the conductive film.

[0491] The conductor 122a and the conductor 122b function as the anodes of the light emitting device 150a and the light emitting device 150b included in the display device 1000, respectively, as an example.

[0492] For example, indium tin oxide (sometimes called ITO) can be used as the conductor 122a and the conductor 122b.

[0493] Furthermore, each of the conductors 122a and 122b may have a laminated structure of two or more layers instead of a single layer. For example, a conductor with high reflectivity to visible light may be used as the first layer conductor, and a conductor with high light transmittance may be used as the top layer conductor. Examples of conductors with high reflectivity to visible light include silver, aluminum, and an alloy film of silver (Ag), palladium (Pd), and copper (Cu) (Ag-Pd-Cu (APC) film). Examples of conductors with high light transmittance include the aforementioned indium tin oxide. Furthermore, the conductors 122a and 122b may be, for example, a laminated film of aluminum sandwiched between a pair of titanium films (a laminated film of Ti, Al, and Ti in this order), or a laminated film of silver sandwiched between a pair of indium tin oxide films (a laminated film of ITO, Ag, and ITO in this order).

[0494] An EL layer 141a is provided on the conductor 122a, and an EL layer 141b is provided on the conductor 122b.

[0495] It is preferable that the EL layer 141a and the EL layer 141b each have a light-emitting layer that emits light of a different color. For example, the EL layer 141a may have a light-emitting layer that emits light of one of red (R), green (G), and blue (B), and the EL layer 141b may have a light-emitting layer that emits light of one of the remaining two. Although not shown in FIG. 24, when an EL layer other than the EL layer 141a and the EL layer 141b is provided, the EL layer may have a light-emitting layer that emits light of the remaining one. In this way, the display device 1000 may have a structure (SBS structure) in which different light-emitting layers for different colors are formed on multiple pixel electrodes (e.g., the conductors 121a and 121b).

[0496] The combination of colors emitted by the light-emitting layers included in the EL layer 141a and the EL layer 141b is not limited to the above, and may be, for example, cyan, magenta, or yellow. Although the above example shows three colors, the number of colors emitted by the light-emitting device 150 included in the display device 1000 may be two, four, or more.

[0497] The EL layer 141a and the EL layer 141b may each have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in addition to a layer containing a light-emitting organic compound (light-emitting layer).

[0498] In addition, the EL layer 141a and the EL layer 141b can be formed by a method such as a vapor deposition method (vacuum vapor deposition method, etc.), a coating method (dip coating method, die coating method, bar coating method, spin coating method, spray coating method, etc.), a printing method (inkjet method, screen (stencil printing) method, offset (lithographic printing) method, flexography (relief printing) method, gravure method, microcontact method, etc.).

[0499] When the coating method or printing method is used, a high molecular compound (e.g., an oligomer, a dendrimer, or a polymer), a medium molecular compound (a compound in the intermediate range between a low molecular weight and a high molecular weight: a molecular weight of 400 to 4000), or an inorganic compound (e.g., a quantum dot material) can be used. The quantum dot material can be a colloidal quantum dot material, an alloy quantum dot material, a core-shell quantum dot material, or a core quantum dot material.

[0500] For example, the light emitting device 150a and the light emitting device 150b in FIG. 24 can be configured with a plurality of layers such as a light emitting layer 4411 and a layer 4430, like the light emitting device 150 shown in FIG. 25(A).

[0501] The layer 4420 can have, for example, a layer containing a substance with a high electron-injecting property (electron-injecting layer) and a layer containing a substance with a high electron-transporting property (electron-transporting layer). The light-emitting layer 4411 contains, for example, a light-emitting compound. The layer 4430 can have, for example, a layer containing a substance with a high hole-injecting property (hole-injecting layer) and a layer containing a substance with a high hole-transporting property (hole-transporting layer).

[0502] A structure having a layer 4420, a light-emitting layer 4411, and a layer 4430 provided between a pair of electrodes (conductor 121 and conductor 122 described later) can function as a single light-emitting unit, and in this specification, the structure of Figure 25(A) is called a single structure.

[0503] 25(B) shows a modified example of the EL layer 141 of the light-emitting device 150 shown in Fig. 25(A). Specifically, the light-emitting device 150 shown in Fig. 25(B) has a layer 4430-1 on the conductor 121, a layer 4430-2 on the layer 4430-1, a light-emitting layer 4411 on the layer 4430-2, a layer 4420-1 on the light-emitting layer 4411, a layer 4420-2 on the layer 4420-1, and a conductor 122 on the layer 4420-2. For example, when the conductor 121 is the anode and the conductor 122 is the cathode, the layer 4430-1 functions as a hole injection layer, the layer 4430-2 functions as a hole transport layer, the layer 4420-1 functions as an electron transport layer, and the layer 4420-2 functions as an electron injection layer. Alternatively, when the conductor 121 is used as a cathode and the conductor 122 is used as an anode, the layer 4430-1 functions as an electron injection layer, the layer 4430-2 functions as an electron transport layer, the layer 4420-1 functions as a hole transport layer, and the layer 4420-2 functions as a hole injection layer. By using such a layer structure, it is possible to efficiently inject carriers into the light-emitting layer 4411 and increase the efficiency of carrier recombination in the light-emitting layer 4411.

[0504] Note that a structure in which a plurality of light-emitting layers (for example, a light-emitting layer 4411, a light-emitting layer 4412, and a light-emitting layer 4413) are provided between the layer 4420 and the layer 4430 as shown in FIG. 25C is also a variation of the single structure.

[0505] A stacked body having multiple layers such as the layer 4420, the light-emitting layer 4411, and the layer 4430 may be referred to as a light-emitting unit. Multiple light-emitting units may be connected in series via an intermediate layer (charge generation layer). Specifically, as shown in FIG. 25(D), multiple light-emitting units, such as a light-emitting unit 4400a and a light-emitting unit 4400b, may be connected in series via an intermediate layer (charge generation layer) 4440. In this specification, such a structure is referred to as a tandem structure. In this specification and the like, a tandem structure may also be referred to as a stack structure. By forming a light-emitting device into a tandem structure, a light-emitting device capable of emitting light with high brightness can be obtained. By forming a light-emitting device into a tandem structure, for example, improvement in the luminous efficiency and lifespan of the light-emitting device can be expected. When the light-emitting device 150 of the display device 1000 of Figure 24 has a tandem structure, the EL layer 141 can be configured to include, for example, layer 4420, light-emitting layer 4411, and layer 4430 of light-emitting unit 4400a, intermediate layer 4440, and layer 4420, light-emitting layer 4412, and layer 4430 of light-emitting unit 4400b.

[0506] Furthermore, when displaying white, the SBS structure described above can reduce power consumption compared to the single and tandem structures. Therefore, if you want to keep power consumption low, the SBS structure is preferable. On the other hand, the single and tandem structures are preferable because their manufacturing processes are easier than those of the SBS structure, allowing for lower manufacturing costs and higher manufacturing yields.

[0507] The light-emitting device 150 can emit light in red, green, blue, cyan, magenta, yellow, or white, depending on the material of the EL layer 141. Furthermore, the color purity can be further improved by providing the light-emitting device 150 with a microcavity structure.

[0508] A light-emitting device that emits white light preferably has a configuration in which the light-emitting layer contains two or more types of light-emitting materials. To obtain white light emission, it is sufficient to select two light-emitting materials such that the light emitted by each of the two light-emitting materials has a complementary color relationship. For example, by making the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer complementary to each other, it is possible to obtain a configuration in which the light-emitting device as a whole emits white light. Furthermore, when white light emission is obtained using three or more light-emitting layers, it is sufficient to configure the light-emitting device as a whole to emit white light by combining the respective light-emitting colors of the three or more light-emitting layers.

[0509] The light-emitting layer preferably contains two or more light-emitting materials that emit R (red), G (green), B (blue), Y (yellow), and O (orange). Alternatively, the light emitted by each of the light-emitting materials preferably contains spectral components of two or more colors selected from R, G, and B.

[0510] 24, a gap is provided between two EL layers between adjacent light-emitting devices. Specifically, in FIG. 24, a recess is formed between adjacent light-emitting devices, and an insulator 112 is provided to cover the side surfaces (side surfaces of the conductor 121a, the conductor 122a, and the EL layer 141a, and side surfaces of the conductor 121b, the conductor 122b, and the EL layer 141b) and the bottom surface (a portion of the insulator 111b) of the recess. An insulator 162 is also formed on the insulator 112 to fill the recess. In this manner, it is preferable that the EL layer 141a and the EL layer 141b are provided so as not to contact each other. This can suitably prevent unintended light emission (also known as crosstalk) caused by current (also known as lateral leakage current or side leakage current) flowing through the two adjacent EL layers. This can improve contrast and realize a display device with high display quality. Furthermore, for example, by adopting a configuration in which the lateral leakage current between light-emitting devices is extremely low, the black display performed by the display device can be a display with extremely little light leakage (also called true black display).

[0511] The EL layer 141a and the EL layer 141b can be formed, for example, by a method using photolithography. For example, an EL film to become the EL layer 141a and the EL layer 141b is formed on the conductor 122, and then the EL film is patterned by photolithography to form the EL layer 141a and the EL layer 141b. This also makes it possible to provide a gap between the two EL layers between adjacent light-emitting devices.

[0512] The insulator 112 can be an insulating layer containing an inorganic material. The insulator 112 can be, for example, an inorganic insulating film such as an insulating oxide film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film. The insulator 112 can have a single-layer structure or a stacked-layer structure. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film and an aluminum oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. In particular, an aluminum oxide film is preferable because it has a high etching selectivity with respect to the EL layer and protects the EL layer in the formation of the insulator 162, which will be described later. In particular, by using inorganic insulating films such as an aluminum oxide film, a hafnium oxide film, and a silicon oxide film formed by the ALD method as the insulator 112, it is possible to form an insulator 112 that has few pinholes and has excellent functionality for protecting the EL layer.

[0513] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0514] The insulator 112 can be formed by a film formation method such as a sputtering method, a CVD method, a PLD method, or an ALD method. In particular, the insulator 112 is preferably formed by an ALD method, which has good coverage.

[0515] The insulator 162 provided on the insulator 112 has the function of flattening recesses formed in the insulator 112 between adjacent light-emitting devices. In other words, the insulator 162 has the effect of improving the flatness of the surface on which the conductor 123 (described later) is formed. An insulating layer containing an organic material can be suitably used for the insulator 162. For example, the insulator 162 can be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, or precursors of these resins. Alternatively, the insulator 162 can be made of an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. Alternatively, the insulator 162 can be made of, for example, a photosensitive resin. The photosensitive resin can be a photoresist. The photosensitive resin may be, for example, a positive-type material or a negative-type material.

[0516] The difference in height between the top surface of the insulator 162 and the top surface of the EL layer 141a or 141b is, for example, preferably 0.5 times or less, more preferably 0.3 times or less, the thickness of the insulator 162. Alternatively, for example, the insulator 162 may be provided so that the top surface of the EL layer 141a or 141b is higher than the top surface of the insulator 162. Alternatively, for example, the insulator 162 may be provided so that the top surface of the insulator 162 is higher than the top surface of the light-emitting layer of the EL layer 141a or 141b.

[0517] A conductor 123 is provided on the EL layer 141a, the EL layer 141b, the insulator 112, and the insulator 162. An insulator 113 is provided on each of the light-emitting devices 150a and 150b.

[0518] The conductor 123 functions as, for example, a common electrode for the light-emitting device 150a and the light-emitting device 150b. In order to emit light from the light-emitting device 150 upward in the display device 1000, the conductor 123 preferably contains a light-transmitting conductive material.

[0519] The conductor 123 is preferably a highly conductive material that is also light-transmitting and light-reflective (sometimes called a semi-transparent / semi-reflective electrode). For example, an alloy of silver and magnesium or indium tin oxide can be used for the conductor 123.

[0520] The insulator 113 is sometimes referred to as a protective layer, and providing the insulator 113 above each of the light-emitting device 150a and the light-emitting device 150b can improve the reliability of the light-emitting devices. In other words, the insulator 113 functions as a passivation film that protects the light-emitting device 150a and the light-emitting device 150b. Therefore, the insulator 113 is preferably made of a material that prevents the intrusion of water and the like. For example, the insulator 113 can be made of a material that can be used for the insulator 111a or the insulator 111b. Specifically, aluminum oxide, silicon nitride, or silicon nitride oxide can be used.

[0521] A resin layer 163 is provided on the insulator 113. Furthermore, a substrate 102 is provided on the resin layer 163.

[0522] For example, a light-transmitting substrate is preferably used as the substrate 102. By using a light-transmitting substrate as the substrate 102, light emitted from the light-emitting device 150a and the light-emitting device 150b can be emitted upward from the substrate 102.

[0523] Note that the display device of one embodiment of the present invention is not limited to the configuration of the display device 1000 illustrated in Fig. 24. The configuration of the display device of one embodiment of the present invention may be changed as appropriate within the scope of solving the problem.

[0524] For example, the transistor 200 included in the pixel layer PXAL of the display device 1000 in Fig. 24 may be a transistor having a metal oxide in a channel formation region (hereinafter referred to as an OS transistor). The display device 1000 shown in Fig. 26 has a configuration in which a transistor 500 (OS transistor) replacing the transistor 200 and a light-emitting device 150 are provided above the circuit layer SICL and wiring layer LINL of the display device 1000 in Fig. 24.

[0525] 26, the transistor 500 is provided over an insulator 512. The insulator 512 is provided above the insulator 364 and the conductor 366, and is preferably formed using a substance that has a barrier property against oxygen and hydrogen. Specifically, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like can be used.

[0526] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0527] For example, the insulator 512 can be made of a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, the parasitic capacitance between wirings can be reduced. For example, the insulator 512 can be made of a silicon oxide film or a silicon oxynitride film.

[0528] An insulator 514 is provided over the insulator 512, and a transistor 500 is provided over the insulator 514. An insulator 576 is formed over the insulator 512 to cover the transistor 500. An insulator 581 is provided above the insulator 576 to cover the insulator 576.

[0529] The insulator 514 is preferably a film having a barrier property that prevents impurities such as hydrogen and water from diffusing from the substrate 310 or a region where circuit elements and the like below the insulator 512 are provided to the region where the transistor 500 is provided. Therefore, the insulator 514 can be made of silicon nitride formed by a CVD method, for example.

[0530] As described above, the transistor 500 illustrated in FIG. 26 is an OS transistor including a metal oxide in a channel formation region. Examples of the metal oxide include In-M-Zn oxide containing indium, an element M, and zinc (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium). Specifically, for example, an oxide containing indium, gallium, and zinc (sometimes referred to as IGZO) may be used. For example, an oxide containing indium, aluminum, and zinc (sometimes referred to as IAZO) may be used. For example, an oxide containing indium, aluminum, gallium, and zinc (sometimes referred to as IAGZO) may be used. In addition to the above, the metal oxide may also be In-Ga oxide, In-Zn oxide, or indium oxide.

[0531] In particular, it is preferable to use a metal oxide functioning as a semiconductor having a band gap of 2 eV or more, preferably 2.5 eV or more. By using such a metal oxide having a wide band gap, the off-state current (sometimes called leakage current) of a transistor can be reduced.

[0532] In particular, it is preferable to use a transistor, such as an OS transistor, whose off-state current is sufficiently small even when the source-drain voltage is large as the driving transistor included in the pixel circuit. By using an OS transistor as the driving transistor, the amount of off-state current flowing in the light-emitting device can be reduced when the driving transistor is in an off-state, thereby sufficiently reducing the luminance of light emitted from the light-emitting device through which the off-state current flows. Therefore, when comparing a driving transistor with a large off-state current with a driving transistor with a small off-state current, when black is displayed in the pixel circuit, the pixel circuit including the driving transistor with a small off-state current can have a lower luminance than the pixel circuit including the driving transistor with a large off-state current. In other words, by using an OS transistor, it is possible to suppress floating black when black is displayed by the pixel circuit.

[0533] The off-state current of the OS transistor per 1 μm of channel width at room temperature is 1 aA (1 × 10 -18 A) Below, 1zA(1×10 -21 A) or less, or 1yA (1 x 10 -24 A) or less. Note that the off-state current of a Si transistor per 1 μm of channel width at room temperature is 1 fA (1×10 -15 A) More than 1pA (1×10 -12 Therefore, it can be said that the off-state current of an OS transistor is about 10 orders of magnitude lower than that of a Si transistor.

[0534] Furthermore, to increase the emission luminance of a light-emitting device included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of the drive transistor included in the pixel circuit. OS transistors have a higher source-drain withstand voltage compared to Si transistors, so a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the drive transistor included in a pixel circuit, a high voltage can be applied between the source and drain of the OS transistor, thereby increasing the amount of current flowing through the light-emitting device and increasing the emission luminance of the light-emitting device.

[0535] Furthermore, when the transistor operates in the saturation region, OS transistors can reduce the change in source-drain current relative to a change in gate-source voltage compared to Si transistors. Therefore, by using OS transistors as the drive transistors in pixel circuits, the current flowing between the source and drain can be precisely determined by changing the gate-source voltage, allowing for precise control of the amount of current flowing through the light-emitting device. This allows for precise control of the light emission brightness of the light-emitting device (enhancing the gradation levels in the pixel circuit).

[0536] Furthermore, in terms of the saturation characteristics of the current that flows when a transistor operates in the saturation region, OS transistors can pass a more stable constant current (saturation current) than Si transistors, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a drive transistor, a stable constant current can be passed through a light-emitting device, for example, even when the current-voltage characteristics of a light-emitting device containing an EL material vary. In other words, when operating in the saturation region, OS transistors maintain almost no change in source-drain current even when the source-drain voltage increases, thereby stabilizing the light-emitting brightness of the light-emitting device.

[0537] As described above, by using an OS transistor as a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," and "suppression of luminance variations of light-emitting devices." Therefore, a display device including a pixel circuit can display clear and smooth images, resulting in image clarity (image sharpness) and / or a high contrast ratio. Note that image clarity (image sharpness) may refer to suppression of motion blur and / or suppression of black floating. Furthermore, by configuring the driving transistor included in the pixel circuit to have an extremely low off-state current, it is possible to achieve a black display (true black display) with minimal light leakage.

[0538] One or both of the insulator 576 and the insulator 581 preferably function as a barrier insulating film that prevents impurities such as water or hydrogen from diffusing into the transistor 500 from above the transistor 500. Therefore, for one or both of the insulator 576 and the insulator 581, an insulating material that has a function of preventing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, and NO), and copper atoms (i.e., through which the above impurities are less likely to permeate) is preferably used. Alternatively, an insulating material that has a function of preventing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules) (i.e., through which the above oxygen is less likely to permeate) is preferably used.

[0539] It is preferable to use an insulator that has the function of suppressing the diffusion of impurities such as water and hydrogen and oxygen for one or both of the insulators 576 and 581, and for example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium-gallium-zinc oxide, silicon nitride, or silicon nitride oxide can be used.

[0540] Openings for forming plugs or wirings are provided in the insulator 581, the insulator 576, and one of the source and drain electrodes of the transistor 500. A conductor 540 functioning as a plug or wiring is formed in the opening.

[0541] For example, the insulator 581 is preferably an insulator that functions as one or both of an interlayer film and a planarizing film.

[0542] An insulator 224 and an insulator 226 are formed above the insulator 581 and the conductor 540. Note that for descriptions of insulators, conductors, circuit elements, and the like located above the insulator 224, including the insulator 224, please refer to the description of the display device 1000 in FIG. 24.

[0543] 24 shows a display device formed by bonding a semiconductor substrate on which the light-emitting device 150, a pixel circuit, and the like are formed and a semiconductor substrate on which a driver circuit and the like are formed, and FIG. 26 shows a display device in which the light-emitting device 150, the pixel circuit, and the like are formed on a semiconductor substrate on which a driver circuit is formed, but the display device of one embodiment of the present invention is not limited to FIG. 24 or 26. The display device of one embodiment of the present invention may be, for example, a display device having a structure in which only one layer of transistors is formed, instead of a layer structure in which two or more transistors are stacked.

[0544] Specifically, for example, a display device of one embodiment of the present invention may have a structure including a circuit including a transistor 200 formed over a substrate 210 and a light-emitting device 150 provided above the transistor 200, as in the display device 1000 illustrated in Figure 27(A). Alternatively, for example, a display device 1000 may have a structure in which an insulator 512 is formed over a substrate 501, and the transistor 500 is provided over the insulator 512 and the light-emitting device 150 is provided above the transistor 500, as in the display device 1000 illustrated in Figure 27(B). Note that the substrate 501 can be, for example, a substrate that can be used for the substrate 310, and is preferably a glass substrate.

[0545] 27(A) and 27(B), the display device of one embodiment of the present invention may have a structure in which only one transistor layer is formed and a light-emitting device 150 is provided above the transistor. Although not shown, the display device of one embodiment of the present invention may have a layer structure in which three or more transistor layers are formed.

[0546] <Example of sealing structure for display device> Next, a sealing structure for the light emitting device 150 that can be applied to the display device 1000 of FIG. 24 will be described.

[0547] Fig. 28(A) is a cross-sectional view showing an example of a sealing structure applicable to the display device 1000 of Fig. 24. Specifically, Fig. 28(A) illustrates an edge of the display device 1000 of Fig. 24 and components provided around the edge. Fig. 28(A) also illustrates only a portion of the pixel layer PXAL of the display device 1000. Specifically, Fig. 28(A) illustrates the insulator 250, and the insulators, conductors, and light-emitting device 150a located above the insulator 250.

[0548] 28(A), for example, an opening is provided. Furthermore, as one example, a conductor 121CM is provided in the opening. The conductor 123 is electrically connected to wiring provided below the insulator 250 via the conductor 121CM. This allows a potential (for example, an anode potential and a cathode potential in the light-emitting device 150a) to be supplied to the conductor 123 functioning as a common electrode. Note that one or more selected from the conductors included in the region 123CM and the conductors around the region 123CM may be referred to as a connection electrode.

[0549] Furthermore, for the conductor 121CM, for example, a material that can be used for the conductor 121 can be used.

[0550] 28(A), an adhesive layer 164 is provided at or around the end of the resin layer 163. Specifically, the display device 1000 is configured so that the insulator 113 and the substrate 102 are connected via the adhesive layer 164.

[0551] The adhesive layer 164 is preferably made of a material that suppresses the permeation of impurities such as moisture. By using such a material for the adhesive layer 164, the reliability of the display device 1000 can be improved.

[0552] A structure in which the insulator 113 and the substrate 102 are bonded together via the resin layer 163 using the adhesive layer 164 is sometimes called a solid sealing structure. In addition, in the solid sealing structure, if the resin layer 163 has the function of bonding the insulator 113 and the substrate 102 together, similar to the adhesive layer 164, the adhesive layer 164 does not necessarily have to be provided.

[0553] On the other hand, a structure in which the insulator 113 and the substrate 102 are bonded together using the adhesive layer 164 and filled with an inert gas instead of the resin layer 163 is sometimes called a hollow sealing structure (not shown). Examples of the inert gas include nitrogen and argon.

[0554] 28(A), two or more adhesive layers may be stacked. For example, as shown in FIG. 28(B), an adhesive layer 165 may be further provided inside adhesive layer 164 (between adhesive layer 164 and resin layer 163). By stacking two or more adhesive layers, the permeation of impurities such as moisture can be further suppressed, thereby further improving the reliability of display device 1000.

[0555] Furthermore, a desiccant may be mixed into the adhesive layer 165. This allows the desiccant to adsorb moisture contained in the adhesive layer 164, the resin layer 163 formed inside the adhesive layer 165, the insulator, the conductor, the EL layer, and the like, thereby improving the reliability of the display device 1000.

[0556] Furthermore, although the display device 1000 in FIG. 28(B) has a solid sealing structure, it may have a hollow sealing structure.

[0557] 28(A) and 28(B), an inert liquid may be filled in place of the resin layer 163. Examples of the inert liquid include a fluorine-based inert liquid.

[0558] <Modifications of the display device> However, one embodiment of the present invention is not limited to the above-described structure, and the structure can be modified as appropriate depending on the situation. Modifications of the display device 1000 in FIG. 24 will be described below with reference to FIGS. 29A to 30B. Note that FIGS. 29A to 30B illustrate only a portion of the pixel layer PXAL of the display device 1000. Specifically, FIGS. 29A to 30B each illustrate the insulator 250, the insulator 111a, the insulators positioned above the insulator 111a, the conductors, the light-emitting device 150a, and the light-emitting device 150b. In particular, FIGS. 29A to 30B also illustrate the light-emitting device 150c, the conductor 121c, the conductor 122c, and the EL layer 141c.

[0559] For example, the color of light emitted by the EL layer 141c may be different from the colors of light emitted by the EL layer 141a and the EL layer 141b. Furthermore, for example, the display device 1000 may be configured so that the light-emitting devices 150a to 150c emit light of two colors. Furthermore, for example, the display device 1000 may be configured so that the number of light-emitting devices 150 is increased to four or more colors (not shown).

[0560] 29A, the display device 1000 may have an EL layer 142 formed on the EL layers 141a to 141c. Specifically, for example, in FIG. 25A, if the EL layers 141a to 141c include the layer 4430 and the light-emitting layer 4411, the EL layer 142 may include the layer 4420. In this case, the layer 4420 included in the EL layer 142 functions as a common layer for the light-emitting devices 150a to 150c. Similarly, for example, in Figure 25(C), when the EL layers 141a to 141c include the layer 4430, the light-emitting layer 4411, the light-emitting layer 4412, and the light-emitting layer 4413, the EL layer 142 includes the layer 4420, whereby the layer 4420 included in the EL layer 142 functions as a common layer in each of the light-emitting devices 150a to 150c. Furthermore, for example, in Figure 25 (D), when the EL layers 141a to 141c are configured to include the layer 4430, the light-emitting layer 4412, and the layer 4420 of the light-emitting unit 4400b, the intermediate layer 4440, and the layer 4430 and the light-emitting layer 4411 of the light-emitting unit 4400a, the EL layer 142 is configured to include the layer 4420 of the light-emitting unit 4400b, so that the layer 4420 of the light-emitting unit 4400a included in the EL layer 142 functions as a common layer in each of the light-emitting devices 150a to 150c.

[0561] Furthermore, for example, the display device 1000 may have a configuration in which the insulator 113 has a stacked structure of two or more layers instead of a single layer. For example, the insulator 113 may have a three-layer stacked structure in which an insulator made of an inorganic material is used as a first layer, an insulator made of an organic material is used as a second layer, and an insulator made of an inorganic material is used as a third layer. Figure 29(B) shows a cross-sectional view of a portion of the display device 1000 in which the insulator 113 has a multilayer structure including the insulators 113a, 113b, and 113c, where the insulator 113a is an insulator made of an inorganic material, the insulator 113b is an insulator made of an organic material, and the insulator 113c is an insulator made of an inorganic material.

[0562] 25A. Alternatively, for example, the display device 1000 may be configured such that each of the EL layers 141a to 141c has a microcavity structure (a microresonator structure). The microcavity structure refers to a structure in which, for example, a light-transmitting and light-reflective conductive material is used for the conductor 122 that is an upper electrode (common electrode) and a light-reflective conductive material is used for the conductor 121 that is a lower electrode (pixel electrode), and the distance between the bottom surface of the light-emitting layer and the top surface of the lower electrode, that is, the film thickness of the layer 4430 in FIG. 25A, is set to a thickness corresponding to the wavelength of the color of light emitted by the light-emitting layer included in the EL layer 141.

[0563] For example, light reflected by the lower electrode and returning (reflected light) significantly interferes with light directly incident on the upper electrode from the light-emitting layer (incident light). Therefore, it is preferable to adjust the optical distance between the lower electrode and the light-emitting layer to (2n-1)λ / 4 (where n is a natural number greater than or equal to 1, and λ is the wavelength of the emitted light to be amplified). By adjusting this optical distance, the phases of the reflected light and incident light, each of which has a wavelength λ, can be matched, thereby further amplifying the light emitted from the light-emitting layer. On the other hand, if the reflected light and incident light have a wavelength other than λ, they will no longer match in phase, resulting in attenuation without resonance.

[0564] In the above configuration, the EL layer may have a structure having multiple light-emitting layers or a structure having a single light-emitting layer. Furthermore, for example, in combination with the above-described tandem light-emitting device configuration, a single light-emitting device may be provided with multiple EL layers sandwiching a charge-generating layer, and each EL layer may have a single or multiple light-emitting layers.

[0565] The microcavity structure makes it possible to increase the light emission intensity of a specific wavelength in the front direction, thereby reducing power consumption. In particular, in the case of XR devices such as VR or AR, light from the light-emitting device is often incident on the eyes of the user wearing the device in the front direction, so it can be said that providing a microcavity structure in the display device of XR devices is preferable. In addition, in the case of a display device that displays images using four sub-pixels of red, yellow, green, and blue, in addition to the brightness improvement effect of yellow emission, the microcavity structure that can be applied to all sub-pixels is able to achieve a display device with good characteristics.

[0566] FIG. 30(A) shows a cross-sectional view of a portion of the display device 1000 having a microcavity structure, as an example. When the light-emitting device 150a has a light-emitting layer that emits blue (B) light, the light-emitting device 150b has a light-emitting layer that emits green (G), and the light-emitting device 150c has a light-emitting layer that emits red (R), it is preferable to increase the thickness of the EL layer 141a, the EL layer 141b, and the EL layer 141c in this order, as shown in FIG. 30(A). Specifically, the thickness of the layer 4430 included in each of the EL layers 141a, 141b, and 141c can be determined according to the color of the light emitted by each light-emitting layer. In this case, the layer 4430 included in the EL layer 141a is the thinnest, and the layer 4430 included in the EL layer 141c is the thickest.

[0567] 30B shows, as an example, a configuration in which colored layers 166a, 166b, and 166c are provided between the resin layer 163 and the substrate 102. The colored layers 166a to 166c can be formed on the substrate 102. In addition, when the light-emitting device 150a has a light-emitting layer that emits blue (B), the light-emitting device 150b has a light-emitting layer that emits green (G), and the light-emitting device 150c has a light-emitting layer that emits red (R), the colored layer 166a is blue, the colored layer 166b is green, and the colored layer 166c is red.

[0568] 30B can be constructed by bonding the substrate 102 provided with the coloring layers 166a to 166c to a substrate 310 on which the light-emitting devices 150a to 150c have been formed, via a resin layer 163. The bonding is preferably performed so that the light-emitting device 150a and the coloring layer 166a overlap, the light-emitting device 150b and the coloring layer 166b overlap, and the light-emitting device 150c and the coloring layer 166c overlap. By providing the coloring layers 166a to 166c in the display device 1000, for example, light emitted by the light-emitting device 150b is not emitted upward through the coloring layer 166a or the coloring layer 166c, but is emitted upward through the coloring layer 166b. In other words, since it is possible to block light from the light-emitting device 150 of the display device 1000 in an oblique direction (the direction of the elevation angle when the top surface of the substrate 102 is considered to be a horizontal plane), it is possible to reduce the dependency of the display device 1000 on the viewing angle, and it is possible to prevent a decrease in the display quality of the image displayed on the display device 1000 when viewed from an oblique angle.

[0569] The colored layers 166a to 166c formed on the substrate 102 may be covered with a resin called an overcoat layer. Specifically, the display device 1000 may be stacked in the order of the resin layer 163, the overcoat layer, the colored layers 166a to 166c, and the substrate 102 (not shown). Note that examples of resins used for the overcoat layer include thermosetting materials that are translucent and based on acrylic resin or epoxy resin.

[0570] Furthermore, for example, a black matrix (not shown) may be included in addition to the colored layers as part of the configuration of the display device 1000. By providing a black matrix between the colored layers 166a and 166b, between the colored layers 166b and 166c, and between the colored layers 166c and 166a, it is possible to more effectively block light from the light-emitting device 150 of the display device 1000 in an oblique direction (the direction of the elevation angle when the top surface of the substrate 102 is taken as a horizontal plane), thereby more effectively preventing a decrease in the display quality of an image displayed on the display device 1000 when the image is viewed obliquely.

[0571] 30(B), the light-emitting devices 150a to 150c included in the display device may all be light-emitting devices that emit white light (not shown). The light-emitting devices may have, for example, a single structure or a tandem structure.

[0572] Furthermore, in the above-described configuration of the display device 1000, the conductors 121a to 121c are used as anodes and the conductor 122 is used as a cathode, but the display device 1000 may be configured so that the conductors 121a to 121c are used as cathodes and the conductor 122 is used as an anode. That is, in the manufacturing process described above, the stacking order of the hole injection layer, hole transport layer, light-emitting layer, electron transport layer, and electron injection layer included in the EL layers 141a to 141c and the EL layer 142 may be reversed.

[0573] <Structural example of insulator 162> Next, the cross-sectional structure of the region including the insulator 162 and its periphery in the display device 1000 will be shown.

[0574] FIG. 31(A) shows an example in which the thicknesses of the EL layer 141a and the EL layer 141b are different from each other. The height of the top surface of the insulator 112 on the EL layer 141a side is the same as or approximately the same as the height of the top surface of the EL layer 141a, and on the EL layer 141b side is the same as or approximately the same as the height of the top surface of the EL layer 141b. The top surface of the insulator 112 has a gentle slope, with the EL layer 141a side being higher and the EL layer 141b side being lower. In this way, the heights of the insulators 112 and 162 are preferably the same as the height of the top surfaces of the adjacent EL layers. Alternatively, the top surface may have a flat portion that is the same as the height of the top surface of one of the adjacent EL layers.

[0575] 31B, the top surface of the insulator 112 has a region higher than the top surfaces of the EL layers 141a and 141b. The top surface of the insulator 112 has a shape that gently bulges out toward the center.

[0576] 31C, the display device 1000 has a region in which the top surface of the insulator 112 is higher than the top surfaces of the EL layers 141a and 141b. Specifically, in a region including the insulator 162 and its periphery, the display device 1000 has one or both of the sacrificial layers 118 and 119, and has a first region in which the top surface of the insulator 112 is higher than the top surfaces of the EL layers 141a and 141b and the insulator 112 is located outside the insulator 162, and the first region is located on one or both of the sacrificial layers 118 and 119. Furthermore, in the region including the insulator 162 and its surroundings, the display device 1000 has one or both of the sacrificial layer 118 and the sacrificial layer 119, and has a second region in which the insulator 162 is higher than the upper surface of the EL layer 141a and the upper surface of the EL layer 141b and is located outside the insulator 112, and the second region is located on one or both of the sacrificial layer 118 and the sacrificial layer 119.

[0577] 31(D), the top surface of the insulator 162 has a region that is lower than the top surfaces of the EL layers 141a and 141b. The top surface of the insulator 162 has a gently sloping shape that is concave toward the center.

[0578] 31(E), the upper surface of the insulator 112 has a region higher than the upper surface of the EL layer 141a and the upper surface of the EL layer 141b. That is, the insulator 112 protrudes from the surface on which the EL layer 141 is to be formed, forming a convex portion.

[0579] When forming the insulator 112, for example, if the insulator 112 is formed so that its height is aligned or approximately aligned with that of the sacrificial layer, the insulator 112 may be formed in a protruding shape, as shown in Figure 31(E).

[0580] 31(F), the upper surface of the insulator 112 has a region that is lower than the upper surfaces of the EL layers 141a and 141b. That is, the insulator 112 forms a recess on the surface on which the EL layer 141 is to be formed.

[0581] In this way, the insulators 112 and 162 can be applied in various shapes.

[0582] <Pixel circuit configuration example> Here, a configuration example of a pixel circuit that can be provided in the pixel layer PXAL will be described.

[0583] 32(A) and 32(B) show a configuration example of a pixel circuit that can be provided in the pixel layer PXAL and a light-emitting device 150 connected to the pixel circuit. Also, FIG. 32(A) is a diagram showing the connections of each circuit element included in a pixel circuit 400 provided in the pixel layer PXAL, and FIG. 32(B) is a diagram schematically showing the hierarchical relationship of a circuit layer SICL including a drive circuit 30 and the like, a layer OSL including multiple transistors of the pixel circuit, and a layer EML including a light-emitting device 150. The pixel layer PXAL of the display device 1000 shown in FIG. 32(B) includes, as an example, a layer OSL and a layer EML. Also, the transistors 500A, 500B, and 500C included in the layer OSL shown in FIG. 32(B) correspond to the transistor 200 in FIG. 24. Also, the light-emitting device 150 included in the layer EML shown in FIG. 32(B) corresponds to the light-emitting device 150a or 150b in FIG. 24.

[0584] 32A and 32B includes a pixel circuit 400 including a transistor 500A, a transistor 500B, a transistor 500C, and a capacitor 600. The transistors 500A, 500B, and 500C can be, for example, transistors applicable to the transistor 200 described above. That is, the transistors 500A, 500B, and 500C can be Si transistors. Alternatively, the transistors 500A, 500B, and 500C can be, for example, transistors applicable to the transistor 500 described above. That is, the transistors 500A, 500B, and 500C can be OS transistors. In particular, when the transistors 500A, 500B, and 500C are OS transistors, each of the transistors 500A, 500B, and 500C preferably includes a backgate electrode. In this case, the backgate electrode may receive the same signal as the gate electrode, or a different signal from the gate electrode. Although the transistors 500A, 500B, and 500C each include a backgate electrode in FIGS. 32A and 32B, the transistors 500A, 500B, and 500C may not include a backgate electrode.

[0585] The transistor 500B includes a gate electrode electrically connected to the transistor 500A, a first electrode electrically connected to the light-emitting device 150, and a second electrode electrically connected to the wiring ANO. The wiring ANO is a wiring for applying a potential for supplying a current to the light-emitting device 150.

[0586] Transistor 500A has a first terminal electrically connected to the gate electrode of transistor 500B, a second terminal electrically connected to a wiring SL that functions as a source line, and a gate electrode that has the function of controlling the conductive state or non-conductive state based on the potential of wiring GL1 that functions as a gate line.

[0587] The transistor 500C includes a first terminal electrically connected to the wiring V0, a ​​second terminal electrically connected to the light-emitting device 150, and a gate electrode that controls the conductive state or non-conductive state based on the potential of the wiring GL2 that functions as a gate line. The wiring V0 is a wiring for applying a reference potential and a wiring for outputting the current flowing through the pixel circuit 400 to the drive circuit 30.

[0588] The capacitor 600 includes a conductive film electrically connected to the gate electrode of the transistor 500B and a conductive film electrically connected to the second electrode of the transistor 500C.

[0589] The light emitting device 150 includes a first electrode electrically connected to the first electrode of the transistor 500B and a second electrode electrically connected to a wiring VCOM. The wiring VCOM is a wiring for applying a potential for supplying a current to the light emitting device 150.

[0590] This allows the intensity of light emitted by light-emitting device 150 to be controlled in accordance with an image signal applied to the gate electrode of transistor 500B. Also, the reference potential of wiring V0 applied via transistor 500C can suppress variations in the gate-source voltage of transistor 500B.

[0591] Furthermore, a current value that can be used to set pixel parameters can be output from the wiring V0. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 500B or the current flowing through the light-emitting device 150 to the outside. The current output to the wiring V0 is converted into a voltage by a current-voltage conversion circuit and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter and output to the AI ​​accelerator described in the above embodiment.

[0592] In the configuration shown in FIG. 32B as an example, the wiring electrically connecting the pixel circuit 400 and the driver circuit 30 can be shortened, thereby reducing the wiring resistance of the wiring. Therefore, data can be written at high speed, allowing the display device 1000 to be driven at high speed. This allows a sufficient frame period to be secured even if the display device 1000 includes a large number of pixel circuits 400, thereby increasing the pixel density of the display device 1000. Furthermore, increasing the pixel density of the display device 1000 can increase the resolution of an image displayed by the display device 1000. For example, the pixel density of the display device 1000 can be set to 1000 ppi or more, 5000 ppi or more, or 7000 ppi or more. Therefore, the display device 1000 can be used as a display device for AR or VR, for example, and can be suitably applied to a head-mounted display in which the display unit is close to the user.

[0593] 32A and 32B show an example of the pixel circuit 400 including three transistors in total, but one embodiment of the present invention is not limited to this. Below, a configuration example of a pixel circuit that can be used for the pixel circuit 400 will be described.

[0594] The pixel circuit 400A shown in Fig. 33(A) includes a transistor 500A, a transistor 500B, and a capacitor 600. Fig. 33(A) also illustrates a light-emitting device 150 connected to the pixel circuit 400A. The pixel circuit 400A is electrically connected to a wiring SL, a wiring GL, a wiring ANO, and a wiring VCOM.

[0595] The transistor 500A has a gate electrically connected to a wiring GL, one of its source and drain electrically connected to a wiring SL, and the other electrically connected to the gate of the transistor 500B and one electrode of the capacitor 600. The transistor 500B has one of its source and drain electrically connected to a wiring ANO, and the other electrically connected to the anode of the light-emitting device 150. The capacitor 600 has the other electrode electrically connected to the anode of the light-emitting device 150. The light-emitting device 150 has a cathode electrically connected to a wiring VCOM.

[0596] 33B has a configuration in which a transistor 500C is added to the pixel circuit 400A. A wiring V0 is electrically connected to the pixel circuit 400B.

[0597] A pixel circuit 400C shown in FIG. 33(C) is an example in which transistors whose gates and back gates are electrically connected are used as the transistors 500A and 500B of the pixel circuit 400A. A pixel circuit 400D shown in FIG. 33(D) is an example in which the same transistors are used as the pixel circuit 400B. This can increase the current that the transistors can pass. Note that, although all the transistors in this example have a pair of gates electrically connected, this is not a limitation. Alternatively, a transistor having a pair of gates electrically connected to different wirings may be used. For example, reliability can be improved by using a transistor in which one of the gates is electrically connected to a source.

[0598] 34A has a configuration in which a transistor 500D is added to the pixel circuit 400B described above. The pixel circuit 400E is electrically connected to three wirings (a wiring GL1, a wiring GL2, and a wiring GL3) that function as gate lines.

[0599] The gate of the transistor 500D is electrically connected to a wiring GL3, one of the source and drain of the transistor 500B is electrically connected to the gate of the transistor 500B, and the other is electrically connected to a wiring V0. The gate of the transistor 500A is electrically connected to a wiring GL1, and the gate of the transistor 500C is electrically connected to a wiring GL2.

[0600] By simultaneously turning on transistors 500C and 500D, the source and gate of transistor 500B have the same potential, making it possible to turn off transistor 500B. This forcibly cuts off the current flowing through light-emitting device 150. Such a pixel circuit is suitable for use in a display method in which display periods and off periods are alternately provided.

[0601] 34(B) is an example in which a capacitor 600A is added to the pixel circuit 400E. The capacitor 600A functions as a storage capacitor.

[0602] 34(C) and 34(D) are examples in which transistors whose gates and back gates are electrically connected are applied to the pixel circuit 400E or 400F, respectively. Transistors whose gates and back gates are electrically connected are applied to transistors 500A, 500C, and 500D, and a transistor whose gate is electrically connected to its source is applied to transistor 500B.

[0603] <Plane and cross-sectional schematic diagram of a light-emitting device> 35(A) is a schematic plan view showing a configuration example in which a light-emitting device and a light-receiving device are arranged within one pixel in a display device 1000 according to one embodiment of the present invention. The display device 1000 includes a plurality of light-emitting devices 150R that emit red light, a plurality of light-emitting devices 150G that emit green light, a plurality of light-emitting devices 150B that emit blue light, and a plurality of light-receiving devices 160. In FIG. 35(A), in order to easily distinguish between the light-emitting devices 150, the light-emitting regions of the light-emitting devices 150 are labeled with R, G, and B. Furthermore, the light-receiving regions of the light-receiving devices 160 are labeled with PD.

[0604] The light-emitting devices 150R, 150G, 150B, and the light-receiving devices 160 are arranged in a matrix. FIG. 35(A) shows an example in which the light-emitting devices 150R, 150G, and 150B are arranged in the X direction, and the light-receiving devices 160 are arranged below them. FIG. 35(A) also shows an example in which the light-emitting devices 150 emitting light of the same color are arranged in the Y direction intersecting the X direction. In the display device 1000 shown in FIG. 35(A), a pixel 80 can be configured by, for example, a sub-pixel having the light-emitting device 150R, a sub-pixel having the light-emitting device 150G, and a sub-pixel having the light-emitting device 150B arranged in the X direction, and a sub-pixel having the light-receiving device 160 provided below these sub-pixels.

[0605] Light-emitting device 150R, light-emitting device 150G, and light-emitting device 150B preferably use EL elements such as organic light-emitting diodes (OLEDs) or quantum-dot light-emitting diodes (QLEDs). Examples of light-emitting materials included in EL elements include fluorescent materials, phosphorescent materials, inorganic compounds (quantum dot materials, etc.), and thermally activated delayed fluorescence (TADF) materials. Note that TADF materials may be materials that are in thermal equilibrium between a singlet excited state and a triplet excited state. Such TADF materials have a short emission lifetime (excitation lifetime), which can suppress a decrease in efficiency in the high-brightness region of light-emitting devices.

[0606] For example, a pn-type or pin-type photodiode can be used as the light-receiving device 160. The light-receiving device 160 functions as a photoelectric conversion element that detects light incident on the light-receiving device 160 and generates electric charges. The amount of electric charges generated is determined based on the amount of incident light.

[0607] In particular, it is preferable to use an organic photodiode having a layer containing an organic compound as the light-receiving device 160. Organic photodiodes can be easily made thin, lightweight, and large in area, and have a high degree of freedom in shape and design, making them applicable to a variety of display devices.

[0608] In an electronic device according to one embodiment of the present invention, an organic EL element is used as the light-emitting device 150, and an organic photodiode is used as the light-receiving device 160. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be built into a display device using an organic EL element. Note that the organic EL elements and the organic photodiode are preferably separated by photolithography. This allows the distance between the light-emitting devices and the organic photodiodes to be narrowed, thereby realizing a display device with a higher aperture ratio than when a shadow mask such as a metal mask is used.

[0609] 35(A) shows a conductor 123 that functions as a common electrode and a conductor 121CM that functions as a connection electrode. Here, the conductor 121CM is electrically connected to the conductor 123. The conductor 121CM is provided outside the display section in which the light-emitting device 150 and the light-receiving device 160 are arranged. Also in FIG. 35(A), the conductor 123 having an area that overlaps with the light-emitting device 150, the light-receiving device 160, and the conductor 121CM is shown by a dashed line.

[0610] The conductor 121CM can be provided along the periphery of the display unit. For example, it may be provided along one side of the periphery of the display unit, or it may be provided over two or more sides of the periphery of the display unit. That is, if the top surface of the display unit has a rectangular shape, the top surface of the conductor 121CM can have, for example, a strip shape, an L-shape, a U-shape (square bracket shape), or a square shape.

[0611] Fig. 35(B) is a schematic plan view showing a configuration example of a display device 1000, which is a modification of the display device 1000 shown in Fig. 35(A). The display device 1000 shown in Fig. 35(B) differs from the display device 1000 shown in Fig. 35(A) in that it includes a light-emitting device 150IR that emits infrared light. The light-emitting device 150IR can emit, for example, near-infrared light (light with a wavelength of 750 nm or more and 1300 nm or less).

[0612] 35(B), in addition to light-emitting devices 150R, 150G, and 150B, light-emitting device 150IR is arranged in the X direction, and light-receiving device 160 is arranged below light-emitting device 150IR. Furthermore, light-receiving device 160 has a function of detecting infrared light.

[0613] Fig. 36(A) is a cross-sectional view corresponding to dashed-dotted line A1-A2 in Fig. 35(A), and Fig. 36(B) is a cross-sectional view corresponding to dashed-dotted line B1-B2 in Fig. 35(A). Fig. 36(C) is a cross-sectional view corresponding to dashed-dotted line C1-C2 in Fig. 35(A), and Fig. 36(D) is a cross-sectional view corresponding to dashed-dotted line D1-D2 in Fig. 35(A). The light-emitting device 150R, the light-emitting device 150G, the light-emitting device 150B, and the light-receiving device 160 are provided on an insulator 111. Furthermore, when the display device 1000 includes a light-emitting device 150IR, the light-emitting device 150IR is provided on the insulator 111.

[0614] In this specification and the like, for example, when it is said that "B is on A" or "B is below A," A and B do not necessarily have to have an area where they contact each other.

[0615] Fig. 36(A) shows an example of a cross-sectional configuration of the light-emitting device 150R, the light-emitting device 150G, and the light-emitting device 150B in Fig. 35(A), and Fig. 36(B) shows an example of a cross-sectional configuration of the light-receiving device 160 in Fig. 35(A).

[0616] The light-emitting device 150R has a conductor 121R functioning as a pixel electrode, a hole injection layer 85R, a hole transport layer 86R, a light-emitting layer 87R, an electron transport layer 88R, a common layer 89, and a conductor 123. The light-emitting device 150G has a conductor 121G functioning as a pixel electrode, a hole injection layer 85G, a hole transport layer 86G, a light-emitting layer 87G, an electron transport layer 88G, a common layer 89, and a conductor 123. The light-emitting device 150B has a conductor 121B functioning as a pixel electrode, a hole injection layer 85B, a hole transport layer 86B, a light-emitting layer 87B, an electron transport layer 88B, a common layer 89, and a conductor 123. The light-receiving device 160 has a conductor 121PD functioning as a pixel electrode, a hole transport layer 86PD, a light-receiving layer 90, an electron transport layer 88PD, a common layer 89, and a conductor 123.

[0617] The conductor 121R, the conductor 121G, and the conductor 121B can be, for example, the conductor 121a, the conductor 121b, and the conductor 121c shown in FIGS. 29A to 30B.

[0618] The common layer 89 functions as an electron injection layer in the light-emitting device 150. On the other hand, the common layer 89 functions as an electron transport layer in the light-receiving device 160. Therefore, the light-receiving device 160 does not need to have the electron transport layer 88PD.

[0619] The hole injection layer 85, the hole transport layer 86, the electron transport layer 88, and the common layer 89 can also be referred to as functional layers.

[0620] The conductor 121, the hole injection layer 85, the hole transport layer 86, the light-emitting layer 87, and the electron transport layer 88 can be provided separately for each element. The common layer 89 and the conductor 123 are provided in common to the light-emitting device 150R, the light-emitting device 150G, the light-emitting device 150B, and the light-receiving device 160.

[0621] 36(A), the light-emitting device 150 and the light-receiving device 160 may have a hole-blocking layer and an electron-blocking layer. The light-emitting device 150 and the light-receiving device 160 may have a layer containing a bipolar substance (a substance having high electron-transporting and hole-transporting properties) or the like.

[0622] Insulating layer 92 is provided to cover the end of conductor 121R, the end of conductor 121G, the end of conductor 121B, and the end of conductor 121PD. The end of insulating layer 92 is preferably tapered. Note that insulating layer 92 does not have to be provided if it is not necessary.

[0623] For example, the insulating layer 92 may be provided to prevent adjacent pixels (e.g., the light-emitting device 150R and the light-emitting device 150G, the light-emitting device 150G and the light-emitting device 150B, etc.) from accidentally short-circuiting and emitting light. When a light-emitting device is formed using a metal mask, the insulating layer 92 may be provided to cover the ends of the conductors 121R, 121G, 121B, and 121PD so that the metal mask does not come into contact with the conductors 121R, 121G, 121B, and 121PD. As a result, the surface of insulating layer 92 is higher than the surfaces of conductor 121R, conductor 121G, conductor 121B, and conductor 121PD, eliminating contact between the metal mask and conductor 121R, conductor 121G, conductor 121B, and conductor 121PD, and preventing damage to the surfaces of conductor 121R, conductor 121G, conductor 121B, and conductor 121PD.

[0624] For example, hole injection layer 85R, hole injection layer 85G, hole injection layer 85B, and hole transport layer 86PD each have a region in contact with the upper surface of conductor 121 and a region in contact with the surface of insulating layer 92. In addition, an end of hole injection layer 85R, an end of hole injection layer 85G, an end of hole injection layer 85B, and an end of hole transport layer 86PD are located on insulating layer 92.

[0625] Furthermore, a gap is provided between the common layer 89 and the insulating layer 92. This prevents the common layer 89 from coming into contact with the side surfaces of the light-emitting layer 87, the light-receiving layer 90, the hole-transporting layer 86, and the hole-injecting layer 85. This prevents short circuits in the light-emitting device 150 and the light-receiving device 160.

[0626] The voids are more easily formed, for example, as the distance between the light-emitting layers 87 becomes shorter. For example, the voids can be suitably formed when the distance is 1 μm or less, preferably 500 nm or less, and more preferably 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less.

[0627] In addition, a protective layer 91 is provided on the conductor 123. The protective layer 91 has a function of preventing impurities such as water from diffusing from above into each light-emitting device.

[0628] The protective layer 91 may have, for example, a single-layer structure or a multilayer structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, the protective layer 91 may be made of a semiconductor material such as indium gallium oxide or indium gallium zinc oxide.

[0629] Alternatively, a laminated film of an inorganic insulating film and an organic insulating film may be used as the protective layer 91. For example, a configuration in which an organic insulating film is sandwiched between a pair of inorganic insulating films is preferable. Furthermore, it is preferable that the organic insulating film functions as a planarizing film. This allows the upper surface of the organic insulating film to be flat, thereby improving the coverage of the inorganic insulating film thereon and enhancing the barrier properties. Furthermore, since the upper surface of the protective layer 91 is flat, when a structure (e.g., a color filter, a touch sensor electrode, or a lens array) is provided above the protective layer 91, the influence of uneven shapes caused by the structure below can be reduced, which is preferable.

[0630] 36A illustrates a configuration in which, from bottom to top, the light-emitting device 150 includes a conductor 121, a hole-injection layer 85, a hole-transport layer 86, a light-emitting layer 87, an electron-transport layer 88, a common layer 89 (electron injection layer), and a conductor 123, and the light-receiving device 160 includes, from bottom to top, a conductor 121PD, a hole-transport layer 86PD, a light-receiving layer 90, an electron-transport layer 88PD, the common layer 89, and a conductor 123. However, one embodiment of the present invention is not limited to this. For example, the light-emitting device 150 may include, from bottom to top, a conductor functioning as a pixel electrode, an electron-injection layer, an electron-transport layer, a light-emitting layer, a hole-transport layer, a hole-injection layer, and a conductor functioning as a common electrode, and the light-receiving device 160 may include, from bottom to top, a conductor functioning as a pixel electrode, an electron-transport layer, a light-receiving layer, a hole-transport layer, and a conductor functioning as a common electrode. In this case, the hole injection layer of the light-emitting device 150 can be a common layer, and the common layer can be provided between the hole transport layer and the common electrode of the light-receiving device 160. In the light-emitting device 150, the electron injection layer can be separated for each element.

[0631] <Pixel layout> Here, a pixel layout different from the pixel layout shown in Fig. 35 will be described. There are no particular limitations on the arrangement of sub-pixels, and various methods can be applied. Examples of sub-pixel arrangements include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0632] The top surface shape of the sub-pixel may be, for example, a polygon such as a triangle, a quadrangle (including a rectangle and a square), or a pentagon, or a polygon with rounded corners, an ellipse, or a circle. Here, the top surface shape of the sub-pixel corresponds to the top surface shape of the light-emitting region of the light-emitting device.

[0633] A stripe arrangement is applied to pixel 80 shown in Fig. 37(A). Pixel 80 shown in Fig. 37(A) is composed of three subpixels: subpixel 80a, subpixel 80b, and subpixel 80c. For example, as shown in Fig. 38(A), subpixel 80a may be a red subpixel R, subpixel 80b may be a green subpixel G, and subpixel 80c may be a blue subpixel B.

[0634] An S-stripe arrangement is applied to the pixel 80 shown in Fig. 37(B). The pixel 80 shown in Fig. 37(B) is composed of ...

Claims

1. a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a first capacitance, a second capacitance, a third capacitance, and a fourth capacitance; a first gate of the first transistor electrically connected to a first gate of the fourth transistor; one of a source or a drain of the first transistor is electrically connected to one of a source or a drain of the second transistor, one of a source or a drain of the fifth transistor, one of a source or a drain of the eighth transistor, and a first terminal of the fourth capacitor; the other of the source and the drain of the fifth transistor is electrically connected to a first gate of the sixth transistor and a first terminal of the second capacitor; the other of the source and the drain of the eighth transistor is electrically connected to a first gate of the ninth transistor and a first terminal of the third capacitor; a first gate of the second transistor is electrically connected to a first terminal of the first capacitance, one of a source or a drain of the third transistor, one of a source or a drain of the fourth transistor, a first gate of the seventh transistor, and a first gate of the tenth transistor; one of a source or a drain of the seventh transistor is electrically connected to one of a source or a drain of the sixth transistor and a second terminal of the second capacitor; one of a source or a drain of the tenth transistor is electrically connected to one of a source or a drain of the ninth transistor and a second terminal of the third capacitor. Semiconductor device.

2. In claim 1, a first gate of the fifth transistor electrically connected to a second gate of the fifth transistor; a first gate of the eighth transistor is electrically connected to a second gate of the eighth transistor; Semiconductor device.

3. In claim 1, a first gate of the first transistor electrically connected to a second gate of the first transistor; a first gate of the third transistor electrically connected to a second gate of the third transistor; a first gate of the sixth transistor electrically connected to a second gate of the sixth transistor; a first gate of the ninth transistor electrically connected to a second gate of the ninth transistor; Semiconductor device.

4. a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a first capacitance, a second capacitance, and a third capacitance; a first gate of the first transistor is electrically connected to one of a source or a drain of the eleventh transistor; the other of the source and the drain of the eleventh transistor is electrically connected to a first gate of the fourth transistor; one of a source or a drain of the first transistor is electrically connected to one of a source or a drain of the second transistor, one of a source or a drain of the fifth transistor, and one of a source or a drain of the eighth transistor; the other of the source and the drain of the fifth transistor is electrically connected to a first gate of the sixth transistor and a first terminal of the second capacitor; the other of the source and the drain of the eighth transistor is electrically connected to a first gate of the ninth transistor and a first terminal of the third capacitor; a first gate of the second transistor is electrically connected to a first terminal of the first capacitance, one of a source or a drain of the third transistor, one of a source or a drain of the fourth transistor, a first gate of the seventh transistor, and a first gate of the tenth transistor; one of a source or a drain of the seventh transistor is electrically connected to one of a source or a drain of the sixth transistor and a second terminal of the second capacitor; one of a source or a drain of the tenth transistor is electrically connected to one of a source or a drain of the ninth transistor and a second terminal of the third capacitor. Semiconductor device.

5. In claim 4, a first gate of the eleventh transistor is electrically connected to a second gate of the eleventh transistor; Semiconductor device.

6. In claim 4, A twelfth transistor is provided; a first gate of the first transistor is electrically connected to one of a source or a drain of the eleventh transistor and one of a source or a drain of the twelfth transistor; the other of the source and the drain of the eleventh transistor is electrically connected to a first gate of the eleventh transistor, a first gate of the fourth transistor, and the other of the source and the drain of the twelfth transistor; the other of the source and the drain of the sixth transistor is electrically connected to a first gate of the twelfth transistor; Semiconductor device.

7. a first transistor, a second transistor, a third transistor, a fourth transistor, a sixth transistor, a seventh transistor, a ninth transistor, a tenth transistor, a first capacitance, a second capacitance, and a third capacitance; a first gate of the first transistor electrically connected to a first gate of the fourth transistor; one of a source or a drain of the first transistor is electrically connected to one of a source or a drain of the second transistor, a first gate of the sixth transistor, a first terminal of the second capacitance, a first gate of the ninth transistor, and a first terminal of the third capacitance; a first gate of the second transistor is electrically connected to a first terminal of the first capacitance, one of a source or a drain of the third transistor, one of a source or a drain of the fourth transistor, a first gate of the seventh transistor, and a first gate of the tenth transistor; one of a source or a drain of the seventh transistor is electrically connected to one of a source or a drain of the sixth transistor and a second terminal of the second capacitor; one of a source or a drain of the tenth transistor is electrically connected to one of a source or a drain of the ninth transistor and a second terminal of the third capacitor. Semiconductor device.

8. A transistor comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a first capacitance, a second capacitance, and a third capacitance; a first gate of the first transistor electrically connected to a first gate of the fourth transistor; one of a source or a drain of the first transistor is electrically connected to one of a source or a drain of the second transistor, one of a source or a drain of the fifth transistor, and one of a source or a drain of the eighth transistor; the other of the source and the drain of the fifth transistor is electrically connected to a first gate of the sixth transistor and a first terminal of the second capacitor; the other of the source and the drain of the eighth transistor is electrically connected to a first gate of the ninth transistor and a first terminal of the third capacitor; a first gate of the second transistor is electrically connected to a first terminal of the first capacitance, one of a source or a drain of the third transistor, one of a source or a drain of the fourth transistor, a first gate of the seventh transistor, a second gate of the eighth transistor, and a first gate of the tenth transistor; one of a source or a drain of the seventh transistor is electrically connected to one of a source or a drain of the sixth transistor and a second terminal of the second capacitor; one of a source or a drain of the tenth transistor is electrically connected to one of a source or a drain of the ninth transistor and a second terminal of the third capacitor. Semiconductor device.

9. A semiconductor device comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a first capacitance, a second capacitance, and a third capacitance; a first gate of the first transistor electrically connected to a first gate of the fourth transistor; one of a source or a drain of the first transistor is electrically connected to one of a source or a drain of the second transistor, one of a source or a drain of the fifth transistor, and one of a source or a drain of the eighth transistor; the other of the source and the drain of the fifth transistor is electrically connected to a first gate of the sixth transistor and a first terminal of the second capacitor; the other of the source and the drain of the eighth transistor is electrically connected to a first gate of the ninth transistor and a first terminal of the third capacitor; a first gate of the second transistor is electrically connected to a first terminal of the first capacitance, one of a source or a drain of the third transistor, one of a source or a drain of the fourth transistor, a first gate of the seventh transistor, and a first gate of the tenth transistor; one of a source or a drain of the seventh transistor is electrically connected to one of a source or a drain of the sixth transistor, a second gate of the seventh transistor, and a second terminal of the second capacitor; one of a source or a drain of the tenth transistor is electrically connected to one of a source or a drain of the ninth transistor, a second gate of the tenth transistor, and a second terminal of the third capacitor. Semiconductor device.

10. In claim 9, each of the second transistor and the fourth transistor is a transistor having a multi-gate structure; Semiconductor device.

11. A semiconductor device comprising: a gate driver circuit having a shift register including the semiconductor device according to any one of claims 1 to 10; a source driver circuit; and a pixel array. Display device.

12. An electronic device comprising the display device according to claim 11 and a housing.

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