Display device and its control method

Abstract

To reduce a variation in luminance in a display area.SOLUTION: A display device includes multiple pixels, and a control circuit for controlling luminance of the multiple pixels. Each pixel of the multiple pixels includes a light emitting element, and a pixel circuit for controlling light emission of the light emitting element. The pixel circuit includes a drive transistor for supplying current to the light emitting element, and a holding capacitor for holding voltage for controlling current supplied to the light emitting element by the drive transistor. The control circuit determines a statistical value of luminance of a pixel shown by a video frame by a predetermined method, determines a threshold compensation period of a holding capacitor for the drive transistor on the basis of the statistical value, and controls the pixel circuit on the basis of the threshold compensation period.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present disclosure relates to a display device and a control method thereof.

Background Art

[0002] Since an OLED (Organic Light-Emitting Diode) element is a current-driven self-emitting element, it does not require a backlight and has advantages such as low power consumption, a wide viewing angle, and a high contrast ratio, and is expected in the development of flat panel displays.

[0003] An active matrix (AM) type OLED display device includes a transistor for selecting a pixel and a driving transistor for supplying current to the pixel. The transistor in an OLED display device is a TFT (Thin Film Transistor), and generally, an LTPS (Low Temperature Poly-silicon) TFT or an oxide semiconductor TFT is used.

[0004] TFTs have variations in threshold voltage and charge mobility. Since the driving transistor determines the light emission intensity of an OLED display device, such variations in electrical characteristics become a problem. Therefore, a correction circuit for compensating for variations and fluctuations in the threshold voltage of the driving transistor is implemented in the pixel circuit of a general OLED display device.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

[0006] Variations in in-plane brightness within the display area are due to the threshold voltage compensation characteristics of the drive transistor. Therefore, it is important to appropriately set the length of the threshold voltage compensation period of the drive transistor. According to the inventors' research, the threshold correction period that minimizes variations in pixel brightness within the display area differs depending on the current value flowing through the drive transistor (brightness of the light-emitting element). [Means for solving the problem]

[0007] A display device according to one aspect of the present disclosure includes a plurality of pixels and a control circuit for controlling the brightness of the plurality of pixels. Each of the plurality of pixels includes a light-emitting element and a pixel circuit for controlling the emission of light from the light-emitting element. The pixel circuit includes a drive transistor for supplying current to the light-emitting element and a holding capacitor for holding a voltage that controls the current supplied by the drive transistor to the light-emitting element. The control circuit determines statistical values ​​of the brightness of the pixels shown by the image frame by a predetermined method, determines a threshold compensation period for the holding capacitor for the drive transistor based on the statistical values, and controls the pixel circuit based on the threshold compensation period.

[0008] Another aspect of the present disclosure is a method for controlling a display device. The display device includes a plurality of pixels. Each of the plurality of pixels includes a light-emitting element and a pixel circuit for controlling the emission of light from the light-emitting element. The pixel circuit includes a drive transistor for supplying current to the light-emitting element and a holding capacitor for holding a voltage that controls the current supplied by the drive transistor to the light-emitting element. The control method determines statistical values ​​of the brightness of the pixels shown by the image frame by a predetermined method, determines a threshold compensation period for the holding capacitor for the drive transistor based on the statistical values, and controls the pixel circuit based on the threshold compensation period. [Effects of the Invention]

[0009] According to one aspect of this disclosure, variations in brightness within the display area can be reduced. [Brief explanation of the drawing]

[0010] [Figure 1] A schematic example of the configuration of an OLED display device is shown. [Figure 2] An example of the configuration of a pixel circuit according to one embodiment of this specification is shown. [Figure 3] An example of a timing chart for signals controlling a pixel circuit is shown. [Figure 4] The relationship between the threshold compensation period and the data writing period in four consecutive rows of pixel circuits is schematically shown. [Figure 5] This shows the relationship between the average brightness of a video frame and the optimal threshold compensation period in different pixel circuits. [Figure 6] This shows an example of a functional configuration for an OLED display device that dynamically changes the threshold compensation period. [Figure 7] The timing chart for the S1 selection signal and the control signal that generates the S1 selection signal is shown. [Figure 8] This document shows an example of the functional configuration of an OLED display device that dynamically changes the threshold compensation period according to one embodiment of this specification. [Figure 9] This diagram schematically illustrates the trimming of the STV1 start pulse signal by a trimming controller. [Figure 10] This document shows an example of the functional configuration of an OLED display device that dynamically changes the threshold compensation period according to one embodiment of this specification. [Figure 11] This is a schematic diagram showing the internal circuit configuration of the scanning driver. [Figure 12] An example of a latch circuit configuration is shown. [Figure 13] The truth table for the latch circuit is shown. [Figure 14] An example of a latch circuit configuration is shown. [Figure 15]An example of a timing chart of signals for controlling a pixel circuit, described with reference to FIGS. 10 to 14, is shown. [Figure 16] A configuration example of a trimming controller is shown. [Figure 17] A truth table of the trimming controller shown in FIG. 16 is shown. [Figure 18] A timing chart of input / output signals of the trimming controller shown in FIG. 16 is shown. [Figure 19] The relationship between the data voltage to the pixel circuit and the drive current (Ioled) of the OLED element in different threshold compensation periods is schematically shown. [Figure 20] A configuration example of a data voltage correction table is shown. [Figure 21] A functional configuration example of an OLED display device having a data voltage correction function according to a threshold compensation period is shown.

Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments will be described with reference to the drawings. The same reference numerals are assigned to common configurations in each figure. For ease of explanation, the dimensions and shapes of the illustrated objects may be exaggerated in some cases.

[0012] Hereinafter, in a light-emitting display device using a light-emitting element that emits light by a drive current, such as an OLED (Organic Light-Emitting Diode) display device, a configuration of a circuit that generates and outputs a control signal for a pixel circuit is disclosed. In an OLED display device, luminance variations may occur among pixels included in a display area.

[0013] This is due to the characteristics of threshold voltage compensation of the drive transistor by the pixel circuit. According to the inventors' research, it has been found that the length of the threshold compensation period that minimizes luminance variations in the display area varies depending on the current value flowing through the drive transistor (the luminance of the light-emitting element).

[0014] In one embodiment of this specification, a display device determines the threshold compensation period of a drive transistor in a pixel circuit based on the brightness of a plurality of pixels that comprise a display area shown by video data. This makes it possible to more effectively reduce brightness variations that change according to the brightness of the displayed image.

[0015] <Embodiment 1> Referring to Figure 1, the overall configuration of a display device according to one embodiment of this specification will be described. Note that, for the sake of clarity, the dimensions and shapes of the illustrated objects may be exaggerated in some cases. In the following, an OLED display device will be described as an example of a display device.

[0016] Figure 1 schematically shows an example of the configuration of an OLED display device 10. The OLED display device 10 is composed of a TFT (Thin Film Transistor) substrate 100 on which OLED elements (light-emitting elements) are formed, and a sealing structure 150 that encapsulates the OLED elements. A control circuit is arranged around the cathode electrode formation region 114 outside the display area 125 of the TFT substrate 100. Specifically, a scanning driver 131, an emission driver 132, an electrostatic discharge protection circuit 133, a driver IC 134, and a demultiplexer 136 are arranged.

[0017] The driver IC 134 is connected to external equipment via an FPC (Flexible Printed Circuit) 135. The scanning driver 131 drives the scan lines of the TFT substrate 100. The emission driver 132 drives the emission control lines to control the light emission of each pixel. The electrostatic discharge protection circuit 133 prevents electrostatic discharge damage to elements on the TFT substrate. The driver IC 134 is mounted, for example, using an anisotropic conductive film (ACF).

[0018] The driver IC 134 supplies power and control signals, including timing signals, to the scan driver 131 and the emission driver 132. Furthermore, the driver IC 134 supplies power and data signals to the demultiplexer 136. The demultiplexer 136 sequentially outputs the output of one pin of the driver IC 134 to d data lines (where d is an integer greater than or equal to 2). The demultiplexer 136 drives d times the number of output pins of the driver IC 134 by switching the data line to which the data signal from the driver IC 134 is output d times during the scan period.

[0019] Figure 2 shows an example configuration of a pixel circuit 107 according to one embodiment of this specification. The pixel circuit 107 is included in the Nth (N is an integer) row of pixel circuits. The pixel circuit 107 includes six transistors (TFTs) M11 to M16, each having a gate, source, and drain. In this example, all transistors M11 to M16 are P-type TFTs.

[0020] Transistor M11 is a driver transistor that controls the amount of current supplied to the OLED element E1. The driver transistor M11 controls the amount of current supplied to the OLED element E1 from the anode power supply providing the power supply potential PVDD, according to the voltage held by the retaining capacitor C10. The retaining capacitor C10 holds the written voltage throughout one frame period. The cathode of the OLED element E1 is connected to a power line 204 that transmits the power supply potential PVEE from the cathode power supply. The power supply potentials PVDD and PVEE are supplied, for example, from the driver IC 134.

[0021] In the configuration example shown in Figure 2, the retaining capacitor C10 is composed of capacitors C11 and C12 connected in series. One end of the retaining capacitor C10 is supplied with the anode power supply potential PVDD, and the other end is connected to the source / drain of switch transistors M13 and M14. The other end of the retaining capacitor C10 is connected to the gate of drive transistor M11. More specifically, one end of capacitor C12 is connected to power line 241. One end of capacitor C11 is connected to the source / drain of switch transistors M13 and M14. The intermediate node of capacitors C11 and C12 is connected to the gate of drive transistor M11.

[0022] The voltage across the retaining capacitor C10 is the voltage between the gate of the drive transistor M11 and the anode power supply line 241. The source of the drive transistor M11 is connected to the anode power supply line 241, and the source potential is the anode power supply potential PVDD. Therefore, the retaining capacitor C10 retains the gate-source voltage of the drive transistor M11. In the configuration example in Figure 2, capacitor C12 retains the gate-source voltage of the drive transistor M11.

[0023] Transistor M15 is a switch transistor that controls the ON / OFF state of the light emission of the OLED element E1. The source of transistor M15 is connected to the drain of the drive transistor M11. Transistor M15 switches the current supply to the OLED element E1 connected to its drain ON / OFF. The gate of transistor M15 is connected to the Em signal line (light emission control line) 133, and transistor M15 is controlled by the light emission control signal Em input to the gate from the emission driver 132.

[0024] Transistor M16 operates to supply a reset potential Vrst to the anode of the OLED element E1. One source / drain end of transistor M16 is connected to power line 242, which transmits the reset potential Vrst, and the other end is connected to the anode of the OLED element E1. The reset potential Vrst is supplied, for example, from driver IC 134.

[0025] The gate of transistor M16 is connected to the S1 selection signal line 231, and transistor M16 is controlled by the control signal S1. When transistor M16 is turned ON by the S1 control signal input to the gate from the scan driver 131, it supplies the reset potential Vrst transmitted by the power line 242 to the anode of the OLED element E1.

[0026] Furthermore, transistor M16 supplies a reset potential Vrst to the anode of OLED element E1, and at the same time, it bypasses the current flowing from power supply PVDD through M11 and M15 during the reset period, thereby preventing leakage light emission.

[0027] Transistor M12 is a switch transistor that writes the voltage for threshold compensation of the drive transistor M11 to the holding capacitor C10, and is a transistor that resets the gate potential of the drive transistor M11. The source and drain of transistor M12 connect to the gate and drain of the drive transistor M11. Therefore, when transistor M12 is ON, the drive transistor M11 is in a diode connection state.

[0028] Transistor M14 is a switch transistor that writes a voltage to the retaining capacitor C10 for threshold compensation of the drive transistor M11. Transistor M14 controls whether or not a reference potential Vref is supplied to the retaining capacitor C10. One source / drain end of transistor M14 is connected to the power line 202 that transmits the reference potential Vref, and the other end is connected to one end of capacitor C11. The gate of transistor M14 is connected to the S1 selection signal line 231, and transistor M14 is controlled by the control signal S1 input to the gate from the scan driver 131.

[0029] Transistors M12, M16, and M14 are controlled by the control signal S1. Therefore, these transistors M12, M16, and M14 are switched ON / OFF simultaneously. While they are ON, the light emission control transistor M15 is turned ON, resetting the gate potential of the drive transistor M11 and the potential of the retaining capacitor C10, after which the light emission control transistor M15 is turned OFF. When transistors M12 and M14 are ON, transistor M11 constitutes a diode-connected transistor. A threshold compensation voltage is written to the retaining capacitor C10 between the power supply potential PVDD and the reference potential Vref.

[0030] Transistor M13 is a switch transistor that selects the pixel circuit to supply the data signal and writes the data signal (data signal voltage) to the retaining capacitor C10. One end of the source / drain of transistor M13 is connected to the data line 237 that transmits the data signal Vdata, and the other end is connected to the retaining capacitor C10. More specifically, one end of the source / drain of transistor M13 is connected to one end of capacitor C11.

[0031] The gate of transistor M13 is connected to the S2 selection signal line 232, which transmits a control signal S2 for selecting the pixel circuit row on which to write the data signal. Transistor M13 is controlled by the control signal S2 supplied from the scanning driver 131. When transistor M13 is ON, it provides the data signal Vdata supplied from the driver IC 117 via the data line 237 to the holding capacitor C10.

[0032] Figure 3 shows an example of a timing chart for the signals that control the pixel circuit 107 shown in Figure 2. Figure 3 shows the timing chart for writing the threshold compensation voltage of the drive transistor M11 and the data signal Vdata to the pixel circuit of the Nth row of pixel circuit. Specifically, Figure 3 shows the time variation in one frame of the selection signals S1_N and S2_N of the Nth row of pixel circuit to which the data signal Vdata is written, the light emission control signal Em_N of the Nth row of pixel circuit, and the selection signal S2_N-6 of the (N-6) row of pixel circuit. Figure 3 shows the change in signal potential level. A selection signal is one of the control signals and is also called a scanning signal. Selection signal S1 is the first selection signal, and selection signal S2 is the second selection signal.

[0033] In the timing chart of Figure 3, the 1H period is the period during which the data signal Vdata is written to the pixel circuit, and the period during which the selection signal S2 is Low. The threshold compensation period is 1H or longer, and in the example of Figure 3, it is 5H.

[0034] At time T1, the selection signal S1_N changes from High to Low. Transistors M12, M14, and M16 turn ON in response to the change in selection signal S1_N. At time T1, the light emission control signal Em_N is Low, so transistor M15 is ON.

[0035] Since transistors M12, M14-M16 are ON, the reset potential Vrst is applied to the anode of the OLED element E1, and also to the gate of the drive transistor M11. At time T2, the light emission control signal Em_N changes from Low to High. The period from time T1 to T2 is the reset period for the gate voltage of the drive transistor M11 and the retaining capacitance C10.

[0036] From time T2 to time T3, the potential levels of signals S1_N, S2_N, and Em_N are maintained. Transistors M12, M14, and M16 are ON, while other transistors, including transistor M15, are OFF. During the period from time T2 to time T3, a threshold compensation voltage is written to the retaining capacitor C10. The period from time T2 to time T3 is the threshold compensation period, and its length is 5H.

[0037] At time T3, the selection signal S2_N changes from High to Low. The selection signal S1_N changes from Low to High. In response to the change in selection signal S1_N, transistors M12, M14, and M16 turn OFF. After time T3, the selection signal S1_N remains High.

[0038] Furthermore, in response to a change in the selection signal S2_N, transistor M13 turns from OFF to ON. This initiates the writing of the data signal Vdata to the holding capacitor C10. At time T4, the selection signal S2_N changes from High to Low. This causes transistor M13 to turn from ON to OFF, completing the data writing to the Nth pixel circuit row. The period from time T3 to T4 is the data writing period to the Nth pixel circuit row, and its length is 1H. After time T4, the selection signal S2_N is maintained at High.

[0039] At time T4, the light emission control signal Em_N changes from High to Low. This causes transistor M15 to change from OFF to ON. This provides a drive current to the OLED element E1, causing the OLED element to start emitting light.

[0040] Figure 4 schematically shows the relationship between the threshold compensation period and the data writing period in four consecutive rows of pixel circuitry. In each row of pixel circuitry, the data writing period follows the threshold compensation period. The lengths of the data writing period and the threshold compensation period are common to all rows of pixel circuitry. In the examples shown in Figures 3 and 4, the length of the data writing period is 1H, and the length of the threshold compensation period is (q-1)*H, where q is an integer greater than or equal to 2. To perform more appropriate threshold compensation, q should be set to an integer greater than or equal to 3. In the example explained with reference to Figure 3, q ​​is 6.

[0041] The length of the threshold compensation period changes according to the change in the length of the selection signal S1_N. As described above, the period during which the selection signal S1_N is Low is qH, and the threshold compensation period is (q-1)*H. The OLED display device 10 can dynamically change q to obtain an appropriate threshold compensation period. Note that, as will be described later, the length of the threshold compensation period does not have to be an integer multiple of the 1H period.

[0042] As shown in Figure 4, data signals are written sequentially to the pixel circuit rows. The data writing period for each pixel circuit row begins immediately after the end of the data writing period for the previous stage, and the data writing periods for different pixel circuit rows do not overlap. The threshold compensation period overlaps with part of the preceding threshold compensation period and the data writing period. The threshold compensation period may overlap with the data writing periods of several stages of pixel circuit rows from the preceding stage.

[0043] The following describes a method for dynamically changing the pixel threshold compensation period. The threshold compensation period that minimizes the variation in brightness within the display area 125 changes according to the brightness of the display area 125. Figure 5 shows the relationship between the average brightness of the video frame and the optimal threshold compensation period in different pixel circuits. Figure 5 shows the analysis results of a PCA (Principal Component Analysis) simulation.

[0044] In the graph in Figure 5, the horizontal axis represents the average brightness value of the pixels displayed in the video frame, and the vertical axis represents the optimal length of the threshold compensation period. More specifically, the horizontal axis represents the average brightness value expressed in grayscale levels, and the vertical axis represents the threshold compensation period as a multiple of the 1H period. The 1H period is 4.2 μs. A pixel can display a single color with different brightness values. Typically, each pixel displays a red, blue, or green dot and is sometimes called a subpixel.

[0045] Figure 5 shows the analysis results of three different pixel circuit examples. The 7T1C circuit consists of seven transistors and one capacitive element, while the 6T2C_D pixel circuit and the 6T2C_S pixel circuit both consist of six transistors and two capacitive elements, differing only in the connections of their components. The pixel circuit shown in Figure 2 is the 6T2C_D pixel circuit.

[0046] As shown in Figure 5, in any pixel circuit, the optimal length of the threshold compensation period can change depending on the brightness value of the display area 125. According to the inventors' research, the optimal threshold compensation period changes in response to changes in various statistical values ​​of the brightness of the display area 125, including the average brightness of the display area, the mode brightness value, and the average brightness of a specific color.

[0047] An OLED display device 10 according to one embodiment of this specification dynamically changes the threshold compensation period in the display area 125 during the period in which an image is being displayed. The period in which an image is being displayed is the period in which an image composed of consecutive image frames is being displayed.

[0048] For example, the OLED display device 10 updates the threshold compensation period for each video frame, or for every predetermined number of video frames. The OLED display device 10 calculates a predetermined statistical value of the brightness of the pixels shown in the video frame, and determines the threshold compensation period for that video frame or subsequent video frames based on that statistical value. This reduces variations in the brightness of the displayed video screen and improves the video quality.

[0049] Figure 6 shows an example of the functional configuration of an OLED display device 10 that dynamically changes the threshold compensation period according to one embodiment of this specification. The OLED display device 10 includes a brightness data calculation unit 410 and a pulse width control unit 400. The brightness data calculation unit 410 and the pulse width control unit 400 can be included, for example, in a driver IC 134 or an external circuit (not shown).

[0050] The luminance data calculation unit 410 receives video data from an external circuit. The luminance data calculation unit 410 includes a frame memory 411. The video data is a sequence of video frames, and the luminance data calculation unit 410 sequentially stores the received video frames in the frame memory 411. The luminance data calculation unit 410 calculates statistical values ​​of the luminance indicated by the video frames. The calculation of statistical values ​​may be performed, for example, for each frame, or intermittently for some of the video frames.

[0051] The statistical values ​​to be calculated may be, for example, average brightness, mode brightness, maximum brightness, or minimum brightness. Average brightness may be, for example, the average brightness of all or some pixels in the display area 120, or the average brightness of all or some pixels of a particular color. Mode brightness may be the brightness value with the highest number of pixels among the brightness values ​​of all pixels shown in the video frame, or it may be the mode brightness of a particular color or a particular sub-region within the display area 125. Maximum or minimum brightness may be the maximum or minimum brightness value of all pixels shown in the video frame, or it may be the maximum or minimum brightness of a particular color or a particular sub-region within the display area 125.

[0052] The pulse width control unit 400 includes a compensation period pulse width calculation unit 401, a volatile memory device SRAM 402, and a timing controller (TCON) 403. The compensation period pulse width calculation unit 401 receives luminance statistics of the video frame from the luminance data calculation unit 410. Based on the received luminance statistics, the compensation period pulse width calculation unit 401 determines a threshold compensation period.

[0053] More specifically, the pulse width of the start pulse signal of the S1 selection signal, which defines the threshold compensation period, is determined. The threshold compensation period is represented by this pulse width. The pulse width calculation unit 401 can determine the threshold compensation period, for example, by referring to a lookup table or by calculation using a pre-implemented function. The data indicating the start pulse width, that is, the data indicating the threshold compensation period, is stored in the SRAM 402.

[0054] The timing controller 403 controls the scan driver 131, the emission driver 132, and the data driver 421. The data driver 421 is included in the driver IC 134 and outputs a data signal corresponding to the video data (video frame) on each data line. In Figure 6, the multiplexer 136 and the protection circuit 133 are omitted.

[0055] The timing controller 403 acquires video data from the frame memory 411 and data indicating the threshold compensation period (start pulse width) from the SRAM 402. The timing controller 403 generates an internal clock signal and a start pulse signal to control the scan driver 131, the emission driver 132, and the data driver 421. The timing controller 403 also generates video data to be transmitted to the data driver 421 according to the video data from the outside.

[0056] The timing controller 403 transmits video data (video frames), a clock signal, and a start pulse signal (STH signal) to the data driver 421. The data driver 421 operates according to the clock signal. At timings and durations corresponding to the STH signal, the data driver 421 outputs data signals on the data lines that indicate the brightness of each pixel in each pixel row represented by the video data.

[0057] The timing controller 403 transmits a clock signal and two start pulse signals (STV1 signal and STV3 signal) to the scan driver 131. The scan driver 131 includes two shift register circuits 431 and 432. For example, the shift register circuit 431 outputs an S1 selection signal according to the received clock signal and STV1 signal. The shift register circuit 432 outputs an S2 selection signal according to the received clock signal and STV3 signal.

[0058] The STV1 signal and the STV2 signal define the length of the Low state of the S1 selection signal and the S2 selection signal, respectively. As will be described later, the pulse width control unit 400 can change the length of the threshold compensation period by changing the length of the Low state of the S1 selection signal.

[0059] The timing controller 403 transmits a clock signal and a start pulse signal (STV2 signal) to the emission driver 132. The emission driver 132 includes a shift register circuit and outputs an illumination control signal (Em signal) in response to the received clock signal and STV2 signal. The STV2 signal defines the length of the high state of the Em signal.

[0060] In one embodiment of this specification, the pulse width control unit 400 changes the length of the threshold compensation period by changing the length of the Low state of the S1 selection signal. The length of the light emission control signal Em is kept constant. Figure 7 shows timing charts of the S1 selection signal and the control signal that generates the S1 selection signal. Timing chart 601 shows the time evolution of the signal in video frame 1, and timing chart 602 shows the time evolution of the signal in video frame 2, which is different from video frame 1.

[0061] Figure 7 shows the time evolution of two clock signals (CK signal and CKB signal), a start pulse signal (STV1 signal), and an S1 selection signal. As an example, Figure 7 shows the time evolution of S1 selection signals S1_1, S1_2, S1_3, and S1_4 for four consecutive pixel rows.

[0062] The S1 selection signal is generated from two clock signals (CK signal and CKB signal) and the STV1 signal. The CK signal and CKB signal are generated by the scan driver 131 from the CKL signal from the timing controller 403. The pulse width (length of the low state) of the CK signal and CKB signal are common, but their phases are shifted by half a period.

[0063] As shown in Figure 7, the pulse width of the start pulse signal (STV1 signal) of the S1 selection signal, that is, the length of the Low state of the STV1 signal, determines the pulse width of the S1 selection signal, that is, the length of the Low state of the S1 selection signal. When the pulse width of the S1 selection signal becomes shorter, the threshold compensation period becomes shorter, and when the pulse width of the S1 selection signal becomes longer, the threshold compensation period becomes longer.

[0064] In the timing chart 601 of frame 1, during the period when the STV1 signal is Low, the width from the first falling edge to the last rising edge of the CKB signal is the pulse width of the S1 selection signal (Low period length). In frame 1, the pulse width of the S1 selection signal corresponds to one pulse of the CKB clock signal.

[0065] The pulse for the S1 selection signal S1_1 of the first pixel row begins on the first falling edge of the CKB signal when the STV1 signal is Low. The scan driver 131 starts outputting the S1 selection signals for the second and subsequent pixel rows in response to the falling edges of the CK clock signal and the CKB clock signal. The pulse width of the S1 selection signal is common for all pixel rows.

[0066] As in frame 1, in frame 2, during the period when the STV1 signal is Low, the pulse width of the S1 selection signal (Low period length) is the width from the first falling edge to the last rising edge of the CKB signal. In timing chart 602 of frame 2, the pulse width of the STV1 signal is longer than the pulse width of the STV1 signal in timing chart 601 of frame 1. Therefore, the pulse width of the S1 selection signal in frame 2 is longer than the pulse width of the S1 selection signal in frame 1. In the example in Figure 7, in frame 2, the pulse width of the S1 selection signal corresponds to 3 pulses of the CKB clock signal.

[0067] The pulse for the S1 selection signal S1_1 of the first pixel row begins on the first falling edge of the CKB signal when the STV1 signal is Low. The scan driver 131 starts outputting the S1 selection signals for the second and subsequent pixel rows in response to the falling edges of the CK clock signal and the CKB clock signal. The pulse width of the S1 selection signal is common for all pixel rows.

[0068] In the example shown in Figure 7, the falling edge of the STV1 signal is synchronized with the frame period. The pulse width control unit 400 changes the rising edge of the STV1 signal according to the brightness of the display area 125 indicated by the video frame. The start of the threshold compensation period is synchronized with the frame period, and the end of the threshold compensation period is shifted forward or backward.

[0069] In the configuration example described with reference to Figures 6 and 7, the scanning driver 131 determines the pulse width of the S1 selection signal, i.e., the threshold compensation period, according to the pulse width of the start pulse signal transmitted from the pulse width control unit 400. The pulse width control unit 400 determines the pulse width of the start pulse signal based on the statistical values ​​of the pixels in the display area 125 indicated by the video frame. This makes it possible to perform more appropriate threshold compensation according to the brightness of the pixels in the display area 125 and reduce variations in brightness within the display area 125.

[0070] In the above example, the rising edge of the S1 selection signal is maintained, and the falling edge is changed to alter the Low duration of the S1 selection signal. In another example, the rising edge of the S1 selection signal may be altered, while the falling edge is maintained. In this example, the rising edge of the light emission control signal Em is changed in accordance with the change in the rising edge of the S1 selection signal.

[0071] <Embodiment 2> Figure 8 shows an example of the functional configuration of an OLED display device 10 that dynamically changes the threshold compensation period according to one embodiment of this specification. The differences from the configuration example shown in Figure 6 will be mainly explained below. The OLED display device 10 includes a pulse width control unit 450 instead of the pulse width control unit 400 shown in Figure 6. The luminance data calculation unit 410 may operate in the same manner as in the configuration of Figure 6.

[0072] The pulse width control unit 450 includes a timing controller (TCON) 451, a trimming width calculation unit 452, and a trimming controller 453. Unlike the configuration example shown in Figure 6, the timing controller (TCON) 451 generates the STV1 start pulse signal without referring to the brightness statistics of the video frame from the brightness data calculation unit 410. The pulse width of the STV1 start pulse signal is constant. The generation of other control signals is the same as in the configuration example shown in Figure 6.

[0073] The trimming width calculation unit 452 obtains luminance statistics of the video frame from the luminance data calculation unit 410. Based on the luminance statistics, the trimming width calculation unit 452 determines the threshold compensation period. Specifically, the trimming width calculation unit 452 determines the trimming width that defines the threshold compensation period. The trimming width represents the threshold compensation period. The trimming width calculation unit 452 transmits a trimming signal indicating the trimming width to the trimming controller 453. The trimming width can be calculated, for example, using a lookup table or a predetermined function.

[0074] The trimming controller 453 acquires the STV1 start pulse signal from the timing controller and the trimming signal from the trimming width calculation unit 452. The trimming controller 453 trims the pulses of the STV1 start pulse signal according to the trimming signal. This shortens the pulse width of the STV1 start pulse signal.

[0075] Figure 9 schematically illustrates the trimming of the STV1 start pulse signal by the trimming controller 453. An STV1 start pulse signal having a pulse width W1 is input to the trimming controller 453. The trimming controller 453 shortens the pulse width of the STV1 start pulse signal by the trimming width indicated by the trimming signal. The output STV1 start pulse signal has a pulse width W2. The pulse width W2 is shorter than the pulse width W1 by the specified trimming width.

[0076] As described above, this configuration example adjusts the pulse width of the STV1 start pulse signal by trimming the STV1 start pulse signal from the trimming controller 453. This eliminates the need to implement a function to adjust the pulse width of the start pulse in the trimming controller 453, allowing the use of a conventional trimming controller. The pulse width control unit 450 may also include a function to extend the pulse width of the start pulse signal, either in addition to or instead of the function to trim the pulse width of the start pulse signal.

[0077] <Embodiment 3> Figure 10 shows an example of the functional configuration of an OLED display device 10 that dynamically changes the threshold compensation period according to one embodiment of this specification. The differences from the configuration example shown in Figure 6 will be mainly explained below. The OLED display device 10 includes a scanning driver 475 instead of the scanning driver 131 shown in Figure 6. The scanning driver 475 includes a shift register circuit 432, a selector circuit 476, and a latch circuit 478. Details of the scanning driver 475 will be described later with reference to Figure 11.

[0078] The OLED display device 10 includes a pulse width control unit 470 instead of the pulse width control unit 400 shown in Figure 6. The brightness data calculation unit 410 may operate in the same manner as in the configuration shown in Figure 6. The pulse width control unit 470 includes a timing controller (TCON) 471 and a pulse width calculation unit 472. The OLED display device 10 includes an emission driver 137 instead of the emission driver 132 shown in Figure 6.

[0079] As described above, the shift register circuit 431 is omitted from the scan driver 475 shown in Figure 6. Therefore, the STV1 start pulse signal is omitted from the control signals shown in Figure 6 that are generated and output by the timing controller (TCON) 471. The other control signals (CLK, STV2, STV3, STH) generated by the timing controller 471 are the same as in the example configuration shown in Figure 6.

[0080] The pulse width calculation unit 472 obtains luminance statistics for the display area 125 indicated by the video frame from the luminance data calculation unit 410. Based on the obtained luminance statistics, the pulse width calculation unit 472 determines the threshold compensation period. Specifically, the pulse width calculation unit 472 determines the pulse width of the STV1 start pulse signal that defines the threshold compensation period. As will be described later, the scanning driver 475 outputs a control signal to the selector circuit 476. This control signal is referred to as the selector signal in this specification.

[0081] As described later, the selector signal selects one of the control terminals of the selector circuit 476. The scanning driver 475 outputs an S1 selection signal with a pulse width corresponding to the selected control terminal. By selecting a different control terminal, S1 selection signals with different pulse widths are generated. The pulse width calculation unit 472 determines the control terminal to be selected from the selector circuit 476 based on the acquired luminance statistics, thereby determining the threshold compensation period according to the luminance statistics.

[0082] The scan driver 475 transmits the SET signal for each pixel circuit row, as described later, to the emission driver 137. The emission driver 137 generates an illumination control signal Em for each pixel circuit row based on the STV2 signal and the SET signal for each pixel circuit row.

[0083] Figure 11 is a schematic diagram showing the internal circuit configuration of the scan driver 475. The scan driver 475 includes a first-stage shift register circuit (SR circuit) 432, a subsequent selector circuit 476, and a final-stage latch circuit 478. The shift register circuit 432 includes multiple shift register units 481 connected in series. In Figure 11, only one shift register unit is indicated by the reference numeral 481.

[0084] Figure 11 shows the shift register units 481 from the (N-4)th stage to the (N+2)th stage, where N is an integer. These shift register units 481 correspond to the same row of pixel circuits. Each shift register unit 481 outputs an S2 selection signal to the S2 selection signal line 232 of the corresponding pixel row, and also outputs the same signal to the selector circuit 476 and a corresponding latch unit 300.

[0085] According to the CK clock signal and the CKB clock signal, data bits are moved from the previous shift register unit 481 to the next shift register unit 481. The shift register unit 481 that holds the data bits outputs a signal pulse.

[0086] The latch circuit 478 includes multiple latch units 300. In Figure 8, only one latch unit is indicated by the code 300. Figure 11 shows the latch units 300 from the (N-2)th stage to the (N+2)th stage. These latch units 300 correspond to the same row of pixel circuitry and output an S1 selection signal to the S1 selection signal line 231 of the corresponding row of pixel circuitry.

[0087] The selector circuit 476 switches the connection between the shift register unit 481 and the latch unit 300 between the shift register circuit 432 and the latch circuit 478. The selector circuit 476 has a switch matrix structure consisting of multiple switch transistors 483. In Figure 11, one switch transistor is indicated by the code 483, for example. In the example in Figure 11, the switch transistor is a P-type TFT, but the type of switch transistor is arbitrary.

[0088] In the configuration example shown in Figure 11, the selector circuit 476 includes three switch rows, each consisting of a group of switch transistors arranged vertically. The gate of one switch row is connected to control terminal A0, the gate of another switch row is connected to control terminal A1, and the gate of yet another switch row is connected to control terminal A2. All switch transistors in each switch row are simultaneously turned ON / OFF by the potential from their corresponding control terminal.

[0089] One source / drain of each switch transistor 483 connected to control terminal A0 is connected to the k-th stage latch unit 300, and the other is connected to the k-2 stage shift register unit 481, where k is an integer. One source / drain of each switch transistor 483 connected to control terminal A1 is connected to the k-th stage latch unit 300, and the other is connected to the k-3 stage shift register unit 481. One source / drain of each switch transistor 483 connected to control terminal A2 is connected to the k-th stage latch unit 300, and the other is connected to the k-4 stage shift register unit 481.

[0090] Each switch transistor 483 in each switch row is connected to a different latch unit 300 and a different shift register unit. Three switch transistors 483 are connected to each latch unit 300, each belonging to a different switch row.

[0091] Each shift register unit 481 is connected to three switch transistors 483, each belonging to a different switch row. Each shift register unit 481 is connected to a corresponding latch unit 300. The connected shift register units 481 and latch units 300 are assigned the same number of stages. Each shift register unit 481 is further connected to the S2 selection signal line 232 of the corresponding pixel row.

[0092] The shift register circuit 432 includes a shift register unit 481 corresponding to each pixel circuit row. The shift register unit 481 corresponding to a pixel circuit row outputs a signal pulse to that pixel circuit row and two latch units 300. The number of shift register units 481 is greater than the number of pixel circuit rows. Some shift register units 481 are not connected to a pixel circuit row and output signals only to the latch units 300.

[0093] Each latch unit 300 has two input terminals, to which the output signals from different stages of shift register units 481 are input. Specifically, the signal from the corresponding shift register unit 481 is input to the RST terminal. The signal from the shift register unit 481 prior to the one selected by the selector circuit 476 is input to the SET terminal. The RST terminal is the first terminal, and the SET terminal is the second terminal.

[0094] In the configuration example shown in Figure 11, the output of the Nth-stage shift register unit 481 is input to the RST terminal of the Nth-stage latch unit 300. The output of the (NL)-stage shift register unit 481 selected by the selector circuit 476 is input to the SET terminal of the Nth-stage latch unit 300. L is an integer greater than or equal to 2, and in the example in Figure 11, it is 2, 3, or 4.

[0095] Figure 12 shows an example configuration of the latch unit 300. The latch unit 300 outputs an S1 selection signal to the Nth row of pixel circuitry. The latch unit 300 includes a SET terminal 301 and an RST terminal 302 to which signals are input, and a Q terminal 303 to which signals are output.

[0096] The selection signal S2_N-L for the (NL)-th pixel circuit row from the shift register circuit 111 is input to the SET terminal 301. The selection signal S2_N for the N-th pixel circuit row is input to the RST terminal 302. The latch unit 300 outputs the selection signal S1_N from the Q terminal 303 to the S1 selection signal line 231 of the N-th pixel circuit row.

[0097] Figure 13 shows the truth table for the latch unit 300. In the truth table of Figure 13, L represents a logical Low level and H represents a logical High level. In the configuration described with reference to Figures 3 and 7, the High potential level of the S1 selection signal and the S2 selection signal corresponds to a logical Low, and the Low potential level corresponds to a logical High.

[0098] When the SET input is L and the RST input is L, the Q output is L. When the SET input is H and the RST input is L, the Q output is H, and even if the SET input changes afterward, the Q output remains H. When the SET input is L and the RST input is H, the Q output is L. The state where both the SET input and RST input are H is prohibited.

[0099] Figure 14 shows an example of the circuit configuration of the latch unit 300. In the configuration example in Figure 14, the latch unit 300 is composed of four transistors and one capacitive element. The four transistors M21 to M24 are P-type transistors. Transistor M21 is in a diode connection state, and its drain receives input from the SET terminal 301. Transistor M22 is connected between transistor M21 and the power supply that provides the power supply potential PVEE, and its gate receives input from the RST terminal 302.

[0100] Transistor M23 is connected between the power supply providing the power supply potential PVDD and terminal Q 303, and its gate is connected to the intermediate node between transistors M21 and M22. Transistor M24 is connected between transistor M23 and the power supply providing the power supply potential PVEE, and its gate receives the RST input. Capacitor element Cb is connected between the gate of transistor M23 and terminal Q 303. The intermediate node between transistors M23 and M24 is connected to terminal Q 303.

[0101] Returning to Figure 11, the Nth-stage shift register unit 481 simultaneously outputs signal pulses to the RST terminal of the Nth-stage latch unit 300, the SET terminal of the (N+L)th-stage latch unit 300 selected by the selector circuit 476, and the S2 selection signal line 232 of the Nth-stage pixel row.

[0102] The Nth stage latch unit 300 outputs an S1 selection signal to the Nth stage pixel circuit row. The Nth stage latch unit 300 starts the S1 selection signal pulse in response to the signal pulse from the (NL) stage shift register unit 481 and ends the pulse in response to the signal pulse from the Nth stage shift register unit 481.

[0103] When control terminals A0, A1, or A2 are selected for the Nth-stage S2 selection signal line 232 and latch unit 300, the corresponding (N-2), (N-3), or (N-4) stage shift register unit is selected.

[0104] More generally, the output of the Nth stage latch unit 300 is set by a pulse from the Kth stage shift register unit and reset by a signal pulse from the (K+p)th stage shift register unit, where K is an integer and p is an integer greater than or equal to 2. The threshold compensation period is (p-1)*H.

[0105] The output of the (N+q)-th stage latch unit is set by a signal pulse from the (K+q)-th stage shift register unit and reset by a signal pulse from the (K+q+p)-th stage shift register unit, where q is an integer greater than or equal to 1. The pulse from the latch unit 300 has a pulse width of p*H. The pulse from the (N+q)-th stage latch unit 300 has a time delay of q*H relative to the pulse from the N-th stage latch unit 300. The threshold compensation period is (p-1)*H.

[0106] In the above example, the selector signal selects one of the control terminals (A0, A1, A2), thereby selecting a value of p from (2,3,4). In other words, the shift register output corresponding to the selected p is selected. As described above, different S1 selection signals with different pulse widths, i.e., different threshold compensation periods, are generated for different p values. The combinations of selectable p values ​​are determined according to the design and do not have to consist of consecutive natural numbers.

[0107] Figure 15 shows an example of a timing chart for the signals that control the pixel circuit 107, as described with reference to Figures 10 to 14. Figure 15 shows a timing chart for writing the threshold compensation voltage of the drive transistor M11 and the data signal Vdata to the pixel circuit of the Nth row of pixel circuit.

[0108] Specifically, Figure 15 shows the time variation in one frame of the selection signals S1_N and S2_N for the Nth pixel circuit row to which the data signal Vdata is written, the light emission control signal Em_N for the Nth pixel circuit row, and the selection signal S2_N-6 for the (N-6)th pixel circuit row. The selection signal S2_N-6 is an example of the output of the shift register unit selected in the selector circuit 476.

[0109] The rising edge of the light emission control signal Em_N is synchronized (matches) with the rising edge of the SET signal of the Nth stage latch unit 300. As described above, the emission driver 137 generates the light emission control signal based on the input SET signal. In the example in Figure 15, the selection signal S2_N-6 is the SET signal of the Nth stage latch unit 300.

[0110] In the timing chart of Figure 15, the 1H period is the period during which the data signal Vdata is written to the pixel circuit, and the period during which the S2 selection signal is Low. The threshold compensation period is 1H or longer, and in the example of Figure 15, it is 5H.

[0111] At time T1, the selection signal S2_N-6 changes from High to Low. In response to the change in selection signal S2_N-6, the selection signal S1_N changes from High to Low. In response to the change in selection signal S1_N, transistors M12, M14, and M16 turn ON. At time T1, the light emission control signal Em_N is Low, so transistor M15 is ON.

[0112] Since transistors M12, M14 through M16 are ON, the reset potential Vrst is applied to the anode of the OLED element E1, and also to the gate of the drive transistor M11. At time T2, the light emission control signal Em_N changes from Low to High. The period from time T1 to T2 is the reset period for the gate voltage of the drive transistor M11. At time T2, the selection signal S2_N-6 also changes from Low to High. The period from time T1 to T2 is the period for writing the data signal to the (N-6)th pixel circuit row. The period from time T1 to T2 is 1H.

[0113] From time T2 to time T3, the potential levels of signals S1_N, S2_N, Em_N, and S2_N-6 are maintained. Transistors M12, M14, and M16 are ON, while other transistors, including transistor M15, are OFF. During the period from time T2 to time T3, a threshold compensation voltage is written to the retaining capacitor C10. The period from time T2 to time T3 is the threshold compensation period, and its length is 5H.

[0114] At time T3, the selection signal S2_N changes from High to Low. As described later, in response to the change in selection signal S2_N, the selection signal S1_N changes from Low to High. In response to the change in selection signal S1_N, transistors M12, M14, and M16 turn OFF. After time T3, the selection signal S1_N remains High.

[0115] In response to a change in the selection signal S2_N, transistor M13 turns from OFF to ON. This initiates the writing of the data signal Vdata to the holding capacitor C10. At time T4, the selection signal S2_N changes from High to Low. This causes transistor M13 to turn from ON to OFF, completing the data writing to the Nth pixel circuit row. The period from time T3 to T4 is the data writing period to the Nth pixel circuit row, and its length is 1H. After time T4, the selection signal S2_N remains High.

[0116] At time T4, the light emission control signal Em_N changes from High to Low. This causes transistor M15 to change from OFF to ON. This provides a drive current to the OLED element E1, causing the OLED element to start emitting light.

[0117] As can be understood from the explanation with reference to Figures 10 to 15, the shift register circuit 432 sequentially outputs pulses of the S2 selection signal to the corresponding pixel circuit row. The pulse width is 1H. Each latch unit 300 outputs the S1 selection signal to the corresponding pixel circuit row.

[0118] As described above, the Nth stage latch unit 300 receives a pulse at the Low potential level (High logic level) of the selected selection signal S2_N-q from the previous stage at the SET terminal 301, and changes the selection signal S1_N from the Q terminal 303 to a Low potential level. Subsequently, the selection signal S2_N-q changes to a High potential level (L logic level), but the input S2_N to the RST terminal 302 is at a High potential level, and the selection signal S1_N from the Q terminal 303 is maintained at a Low potential level.

[0119] Subsequently, the latch unit 300 receives a pulse at a low potential level (high logic level) of the selection signal S2_N of the Nth pixel circuit row at the RST terminal 302, and changes the selection signal S1_N from the Q terminal 303 to a high potential level (low logic level). The pulse width of the S1_N signal output from the latch unit 300 is qH.

[0120] As described above, by using a selector circuit and a latch circuit, the S1 selection signal and the S2 selection signal can be generated from a single shift register circuit. This reduces the area required for the circuitry that generates the S1 selection signal and the S2 selection signal.

[0121] In the above example, the emission driver 137 receives the SET signal generated in the scan driver 475 and generates the light emission control signal Em together with the STV2 signal. In other examples, the emission driver may include a selector circuit and a latch circuit, like the scan driver 475, and use these to generate the light emission control signal Em.

[0122] In the above example, the threshold compensation period is changed by varying the falling edge of the S1 selection signal and the rising edge of the light emission control signal Em. In other configuration examples, the threshold compensation period may be changed by fixing the light emission control signal Em and varying the rising edge of the S1 selection signal. The rising edge of the S1 selection signal is controlled by the RST signal to the Nth stage latch unit.

[0123] <Embodiment 4> Figure 16 shows an example configuration of the trimming controller 453. The trimming controller 453 can be implemented using the latch circuit shown in Figure 14. This reduces the circuit area of ​​the trimming controller 453. The circuit configuration of the latch 300 shown in Figure 16 is the same as the circuit configuration shown in Figure 14, but the input and output signals differ between them.

[0124] As shown in Figure 16, the STV1 signal is input to the SET terminal 301. The trimming signal (STRIM signal) is input to the RST terminal 302. The trimmed STV1 signal is output from the Q terminal 303.

[0125] Figure 17 shows the truth table for the trimming controller 453 shown in Figure 16. As described above, the SET terminal 301 and RST terminal 302 receive the STV1 signal and the STRIM signal, respectively, so Figure 17 shows them instead of the terminal names. In the truth table, L represents a logical Low level, and H represents a logical High level. The High potential level of the STV1 signal and STRIM signal corresponds to a logical Low, and the Low potential level corresponds to a logical High.

[0126] Figure 18 shows the timing chart of the input and output signals of the trimming controller 453. At time T11, the STRIM signal changes from a logical high level (potential low level) to a logical low level (potential high level). Then, at time T12, the STV1 signal and the trimmed STV1 signal change from a logical low level (potential high level) to a logical high level (potential low level).

[0127] Subsequently, at time T13, the STRIM signal changes from a logical low level (potential high level) to a logical high level (potential low level). Accordingly, the trimmed STV1 signal changes from a logical high level (potential low level) to a logical low level (potential high level). Then, at time T14, the STV1 signal changes from a logical high level (potential low level) to a logical low level (potential high level).

[0128] After the STV1 pulse has passed, i.e., from time T14 onwards, the STRIM signal can be either high or low (Don't Care). The STRIM signal should be set to a logical low level at any time before time T12, when the next frame's STV1 signal is input.

[0129] <Embodiment 5> The following describes a method for reducing brightness fluctuations caused by changes in the threshold compensation period (Vth compensation period). Figure 19 schematically shows the relationship between the data voltage to the pixel circuit and the drive current (Ioled) of the OLED element for different threshold compensation periods. In the graph of Figure 19, the horizontal axis represents the data voltage, and the vertical axis represents the log value of the drive current.

[0130] As shown in Figure 19, a general property of OLED pixel circuits with Vth compensation is that the brightness (drive current level) corresponding to the applied data voltage changes depending on the threshold compensation period. Specifically, brightness decreases as the threshold compensation period lengthens. This tendency is particularly pronounced at low brightness levels.

[0131] Therefore, when the threshold compensation period is changed, the change in the data voltage-luminance characteristics can be minimized by correcting the data voltage. In one embodiment of this specification, a data voltage correction table showing the gradation voltage is provided for each of the selectable threshold compensation periods.

[0132] Figure 20 shows an example configuration of a data voltage correction table. The data voltage correction table shows different threshold compensation periods and the corresponding grayscale voltages for each threshold compensation period. The grayscale voltages are the data voltages corresponding to each grayscale level. In the example configuration shown in Figure 20, grayscale levels from 1 to 255 are defined, and the data voltages are shown for each combination of grayscale level, threshold compensation period, and grayscale voltage.

[0133] The control circuit of the OLED display device 10 determines the output data voltage from the data driver 421 by referring to a data voltage correction table based on the gradation level and threshold compensation period indicated by the video data. This makes it possible to reduce the change in brightness due to changes in the threshold compensation period.

[0134] Figure 21 shows an example of the functional configuration of an OLED display device having a data voltage correction function according to the threshold compensation period. The following mainly explains the differences from the configuration example shown in Figure 8. The control flag signal for selecting the optimal threshold compensation period determined by the trimming width calculation unit 452 is transferred to the data driver 421 via the timing controller 451.

[0135] The data driver 421 holds a data voltage correction table, as described with reference to Figure 20. The data driver 421 selects a grayscale voltage curve for the threshold compensation period indicated by the control flag signal from among several grayscale voltage curves shown in the data voltage correction table. The data driver 421 determines the data voltage (grayscale voltage) corresponding to the grayscale level calculated from the video data, according to the selected grayscale voltage curve.

[0136] While embodiments of the present disclosure have been described above, the present disclosure is not limited to the embodiments described above. Those skilled in the art can easily modify, add to, and transform each element of the above embodiments within the scope of the present disclosure. It is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and to add the configuration of another embodiment to the configuration of one embodiment. [Explanation of Symbols]

[0137] 10 OLED display device 100 TFT substrates 125 Display area 131 Scanning Driver 132, 137 Emission Driver 134 Driver ICs 300 Latch Unit 400 Pulse width control unit 401 Compensation Period Pulse Width Calculation Unit 402 SRAM 403, 471 Timing Controller 410 Brightness Data Calculation Unit 411 frame memory 431, 432 Shift register circuit 450 Pulse width control unit 452 Trimming width calculation unit 453 Trimming Controller 470 Pulse width control unit 472 Pulse width calculation unit 475 Scanning Driver 476 Selector Circuit 478 Latch Circuit 481 Shift Register Unit 483 Switch Transistors

Claims

1. A display device, A plurality of pixels; a control circuit for controlling the luminance of the plurality of pixels; Including, Each pixel of the plurality of pixels is A light-emitting element; a pixel circuit for controlling the light emission of the light emitting element; Including, The pixel circuit a driving transistor for supplying a current to the light-emitting element; a storage capacitor that stores a voltage that controls a current that the driving transistor supplies to the light-emitting element; Including, The control circuit determining a luminance statistic of pixels represented by the video frame according to a predetermined method; determining a threshold compensation period of the storage capacitor for the drive transistor based on the statistical value; controlling the pixel circuit based on the threshold compensation period; Display device.

2. The display device according to claim 1 , The control circuit a shift register circuit that outputs a selection signal for sequentially selecting pixel rows from the plurality of pixels; a pulse width calculation unit; Memory and A timing controller, Including, a pulse width of the select signal defines a length of the threshold compensation period for a selected pixel row; the pulse width calculation unit determines a pulse width of the selection signal that defines the threshold compensation period based on the statistical value, and stores data indicating the pulse width in the memory; the timing controller reads out the data indicating the pulse width from the memory, and transmits a start pulse signal having a pulse width corresponding to the data indicating the pulse width to the shift register circuit; the shift register circuit outputs the selection signal having a pulse width corresponding to the pulse width of the start pulse signal. Display device.

3. The display device according to claim 1 , The control circuit a shift register circuit that outputs a selection signal for sequentially selecting pixel rows from the plurality of pixels; A timing controller, A trimming controller; a trimming width calculation unit; Including, a pulse width of the select signal defines a length of the threshold compensation period for a selected pixel row; the timing controller outputs a start pulse signal having a constant pulse width; the trimming width calculation unit determines a trimming width based on the statistical value; the trimming controller trims the pulse width of the start pulse signal output from the timing controller based on the trimming width; the shift register circuit outputs the selection signal having a pulse width corresponding to the trimmed pulse width. Display device.

4. The display device according to claim 1 , The control circuit a shift register circuit including connected shift register units that sequentially output second selection signals to a plurality of pixel rows each including the plurality of pixels; a latch circuit including a latch unit corresponding to each of the plurality of pixel rows; a selector circuit between the latch circuit and the shift register circuit; a pulse width calculation unit; Including, Each shift register unit outputs the second selection signal to one pixel row, a first terminal of a latch unit corresponding to the one pixel row, and the selector circuit; the pulse width calculation unit transmits a selector signal corresponding to the threshold compensation period to the selector circuit; the selector circuit outputs the output of the shift register unit selected in response to the selector signal to the second terminal of each latch unit; each latch unit outputs a first selection signal having a pulse width according to inputs to the first terminal and the second terminal to the corresponding pixel row; a pulse width of the first selection signal defining a length of the threshold compensation period in a selected pixel row; Display device.

5. The display device according to claim 1 , The statistical value is one of an average value, a mode value, a maximum value, and a minimum value. Display device.

6. The display device according to claim 1 , the control circuit determines a data voltage for each gray level in accordance with the threshold compensation period; Display device.

7. The display device according to claim 3, the trimming controller includes a second latch unit; the second latch unit includes a third terminal and a fourth terminal; the timing controller inputs the start pulse signal to the third terminal; the trimming width calculation unit inputs a trimming signal indicating a trimming width to the fourth terminal, the second latch unit outputs a start pulse signal whose pulse width is trimmed based on the trimming width; Display device.

8. A method for controlling a display device, comprising: the display device includes a plurality of pixels; Each pixel of the plurality of pixels includes a light emitting element and a pixel circuit that controls light emission of the light emitting element. Including, the pixel circuit includes a drive transistor that supplies a current to the light-emitting element, and a storage capacitor that holds a voltage that controls the current that the drive transistor supplies to the light-emitting element, The control method includes: determining a luminance statistic of pixels represented by the video frame according to a predetermined method; determining a threshold compensation period of the storage capacitor for the drive transistor based on the statistical value; controlling the pixel circuit based on the threshold compensation period; Control method.

9. 9. The control method according to claim 8, the display device includes a memory and a shift register circuit that outputs a selection signal for sequentially selecting pixel rows from the plurality of pixels; a pulse width of the select signal defines a length of the threshold compensation period for a selected pixel row; The control method includes: determining a pulse width of the selection signal based on the statistical value, and storing data indicating the pulse width in the memory; reading data indicating the pulse width from the memory, transmitting a start pulse signal having a pulse width corresponding to the data indicating the pulse width to the shift register circuit, and outputting the selection signal having a pulse width corresponding to the pulse width of the start pulse signal from the shift register circuit; Control method.

10. 9. The control method according to claim 8, the display device includes a shift register circuit that outputs a selection signal for sequentially selecting pixel rows from the plurality of pixels; a pulse width of the select signal defines a length of the threshold compensation period for a selected pixel row; The control method includes: outputting a start pulse signal having a constant pulse width; determining a trimming width based on the statistical value; trimming the pulse width of the start pulse signal based on the trimming width; a start pulse signal having the trimmed pulse width is input to the shift register circuit, and the selection signal having a pulse width corresponding to the trimmed pulse width is output from the shift register circuit; Control method.

11. 9. The control method according to claim 8, The display device includes: a shift register circuit including connected shift register units that sequentially output second selection signals to a plurality of pixel rows each including the plurality of pixels; a latch circuit including a latch unit corresponding to each of the plurality of pixel rows; a selector circuit between the latch circuit and the shift register circuit; a pulse width calculation unit; Including, The control method includes: each shift register unit outputs the second selection signal to one pixel row, a first terminal of a latch unit corresponding to the one pixel row, and the selector circuit; the pulse width calculation unit transmits a selector signal corresponding to the threshold compensation period to the selector circuit; the selector circuit outputs the output of the shift register unit selected in response to the selector signal to the second terminal of each latch unit; each latch unit outputs a first selection signal having a pulse width according to inputs to the first terminal and the second terminal to the corresponding pixel row, and the pulse width of the first selection signal defines the threshold compensation period; Control method.

12. 9. The control method according to claim 8, The statistical value is one of an average value, a mode value, a maximum value, and a minimum value. Control method.

13. 9. The control method according to claim 8, determining a data voltage for each gray level according to the threshold compensation period; Control method.

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