Game machine

Abstract

To provide a game machine capable of updating an appropriate random number value.SOLUTION: A first random number value and a second random number value are composed of the same two bytes, and the first random number value is used for determining whether control is performed to an advantageous state and is managed by increasing an update speed as compared with the second random number value. A performance control CPU 120 displays a first background display 004SG081 during a first customer-waiting period (first period) after completion of a game (stopping and displaying of a variable display) in a low-base state, and displays a demonstration movie during a second customer-waiting period (second period) after completion of the first customer-waiting period.SELECTED DRAWING: Figure 10-12

Description

Technical field

[0001] The present invention relates to a game machine capable of playing games. [Background technology]

[0002] As a game machine such as a pachinko game machine, there is a game machine that manages various random numbers using hard random numbers and soft random numbers (for example, Patent Document 1). As a pachinko game machine represented by a game machine, the normal background display is displayed during the first customer waiting period after the end of the variable display of symbols, and the second customer waiting period after the first customer waiting period is over. , there is one that executes control to display a demonstration display (see Patent Document 2, for example). [Prior art documents] [Patent document]

[0003] [Patent document 1] Patent No. 6124313 [Patent document 2] Japanese Patent Application Laid-Open No. 2016-22196 [Outline of the invention] [Problems to be solved by the invention]

[0004] There is room for improving the marketability of the game machine having the functions and configurations of both Patent Documents 1 and 2 above.

[0005] SUMMARY OF THE INVENTION The present invention has been made in view of such problems, and an object of the present invention is to provide a gaming machine with improved marketability. [Means for solving the problem]

[0006] In order to achieve the above object, a gaming machine according to the present invention is a gaming machine that can be played and can be controlled in an advantageous state that is advantageous to the player, updating means capable of updating the random value; display means; light emitting means; and a light emission control means, The random value includes a first random value used for processing regarding whether or not to control to the advantageous state, and a second random value different from the first random value, the first random value is composed of a specific number of bytes, and the total number of random values ​​included in the update range is a specific number; the second random number is composed of the specific number of bytes, and the total number of random numbers included in the update range is a predetermined number smaller than the specific number; updating of the first random value by the updating means is faster than updating of the second random value by the updating means; The display means is In the first period after the game ends, display the background display, Displaying a demonstration display in a second period after the first period ends, The light emission control means is controlling the light emitting means using a background display brightness data table corresponding to the background display when no specific error has occurred in the first period; in the second period, if the specific error has not occurred, controlling the light emitting means using a demonstration display luminance data table corresponding to the demonstration display; when the specific error occurs during a game, controlling the light emitting means using a specific error luminance data table corresponding to the specific error; Thereafter, if the specific error is not resolved during the first period, continuing to control the light emitting means using the specific error luminance data table, Thereafter, if the specific error is not eliminated during the second period, the control of the light emitting means using the specific error luminance data table is continued. A gaming machine characterized by: In such a configuration, it is possible to appropriately update the random number value so that intentional control of the advantageous state becomes difficult due to the high update speed of the first random number value regarding the advantageous state. In such a configuration, the notification of a specific error that occurs during a game by the lamp is inherited and executed during both the background display and the demonstration display, thereby stably reporting the specific error. As a result, suitable customer waiting control can be performed. [Brief description of the drawing]

[0007]

Figure 1

Figure 2

[0008] (basic explanation) First, the basic configuration and control of the pachinko game machine 1 will be described.

[0009] (Configuration of pachinko machine 1, etc.) FIG. 1 is a front view of the pachinko game machine 1, showing the arrangement layout of the main members. A pachinko game machine (game machine) 1 is roughly composed of a game board (gauge board) 2 that constitutes a game board surface and a game machine frame (underframe) 3 that supports and fixes the game board 2 . A game area is formed in the game board 2, and a game ball as a game medium is shot from a predetermined ball shooting device and hit into the game area.

[0010] At a predetermined position of the game board 2, a first special symbol display device 4A and a second special symbol display device 4B are provided. In the example shown in FIG. 1, it is provided on the right side of the game area. Each of the first special symbol display device 4A and the second special symbol display device 4B can variably display special symbols as a plurality of types of special identification information. A special design is also called a "special design." The variable display of special symbols is also called a "special symbol game". Both the first special symbol display device 4A and the second special symbol display device 4B are configured using a 7-segment LED or the like. The special symbols are represented by numbers indicating "0" to "9", symbols indicating "-", and other arbitrary lighting patterns. The special pattern may include a pattern in which all LEDs are turned off.

[0011] "Variable display" of special symbols means, for example, to display a plurality of types of special symbols in a variable manner. "Variable display" also means that a plurality of types of symbols are displayed in a variable manner with respect to other symbols such as effect symbols, small symbols, and normal symbols. The production design is also called a decoration design or a decoration design. Variable display is also referred to as variable display or simply variation. Variations include updating display of a plurality of patterns, scrolling display of a plurality of patterns, deformation, enlargement, and reduction of one or more patterns. Variation may include a mode of blinking a certain symbol. In the variable display of special symbols and normal symbols, a plurality of types of special symbols or normal symbols are displayed in an updatable manner. In the variable display of production patterns, a plurality of types of production patterns are scrolled or updated, or one or more production patterns are deformed, enlarged, or reduced. In the variable display of arbitrary patterns, a predetermined pattern is stopped and displayed at the end as a display result. A stop display is also referred to as a derivation display, or simply a derivation. The symbol that is finally stopped and displayed in the variable display is also called a final stop symbol or a fixed symbol. The final stop symbol in the special symbol game is also called a fixed special symbol. The display result of the variable display includes the display result of the special symbol, and is also referred to as the variable display result. The display result of a special design is also called a special figure display result. The execution time of the variable display includes the special symbol variation time, which is the variation time of the special symbol, and is also called variable display time. Different times can be set for the special figure variation time corresponding to the variation pattern of the special symbols in which a plurality of patterns are prepared in advance.

[0012] The special symbol variably displayed in the first special symbol display device 4A is also called "first special symbol". The special symbol variably displayed in the second special symbol display device 4B is also called "second special symbol". A special game using the first special game is also called a "first special game". A special game using the second special game is also called a "second special game". There may be one type of special symbol display device that performs variable display of special symbols.

[0013] At a predetermined position of the game board 2, a normal symbol display device 20 is provided. In the example shown in FIG. 1, it is provided on the left side of the game area. The normal symbol display device 20 can variably display normal symbols as a plurality of types of normal identification information different from special symbols. Ordinary design is also called 'Fu-zu'. The variable display of normal symbols is also called a “normal game”. The normal symbol display 20 is configured using a 7-segment LED or the like. The normal symbols are represented by numbers representing "0" to "9", symbols representing "-", and other arbitrary lighting patterns. The normal pattern may include a pattern in which some or all of the plurality of LEDs are turned on, or a pattern in which all of the plurality of LEDs are turned off. The final stop pattern in the general pattern game is also called a fixed normal pattern. The normal pattern display result is also called a normal pattern display result. The execution time during which the normal pattern is variably displayed in the general pattern game is also referred to as general pattern fluctuation time. The normal pattern fluctuation time can be set to different times corresponding to the normal pattern fluctuation patterns in which a plurality of patterns are prepared in advance.

[0014] An image display device 5 is provided near the center of the game area on the game board 2 . The image display device 5 may be, for example, an LCD (liquid crystal display device), an organic EL (Electro Luminescence), a dot matrix LED, a projector and a screen, a stereoscopic image projection device, or any other configuration using a mechanism capable of forming an arbitrary image. Just do it. The image display device 5 can display various effect images. Further, the image display device 5 is not limited to the effect image, and can display any control-related image such as an inspection image or a setting image.

[0015] For example, on the screen of the image display device 5, in synchronization with the first special game and the second special game, it is possible to execute the variable display of the effect symbols. The production pattern is a display pattern showing numbers and the like, and serves as a plurality of types of decoration identification information different from special patterns and normal patterns. The screen of the image display device 5 shown in FIG. In synchronism with the game, for example, the performance symbols are displayed by scrolling in the vertical direction or being updated, thereby performing variable display of the performance symbols. Synchronization of the variable display may be such that the timing at which pattern variation is started and the timing at which the pattern is finally stopped and displayed after the variation is completed are common timings for different types of symbols. . The final stop pattern in the variable display of the production pattern is also called a fixed production pattern, a fixed decorative pattern, or a fixed decorative pattern. Since the variable display of the production design is synchronized with the first special game and the second special game, the variable display time of the production design becomes the same as the special fluctuation time.

[0016] The screen of the image display device 5 may be provided with a display area capable of displaying effect images corresponding to the pending display and the active display. A pending display is a display corresponding to a variable display that has not yet been executed and is on hold. An active display is a display that corresponds to a running variable display. Suspended presentations and active presentations are also collectively referred to as variable presentation-enabled presentations that correspond to variable presentations. A display area for holding display is also called a holding display area. A display area for active display is also called an active display area. The number of variable representations that are reserved is also referred to as the number of reserved memories. The number of reserved memories corresponding to the first special game is also called the number of first reserved memories. The number of reserved memories corresponding to the second special game is also called the number of second reserved memories. The total value of the first reserved memory count and the second reserved memory count is also referred to as the total reserved memory count.

[0017] Above the first special symbol display device 4A and the second special symbol display device 4B shown in FIG. 1, a first suspension indicator 25A and a second suspension indicator 25B configured to include a plurality of LEDs are provided. . The first pending display 25A displays the number of first pending memories according to the number of lit LEDs. The second pending display 25B displays the number of second pending memories according to the number of lit LEDs. Above the normal design display 20 shown in FIG. 1, a normal design holding display 25C configured to include a plurality of LEDs is provided. The general pattern holding display 25C displays the number of general pattern holding storage according to the number of lit LEDs. The number of reserved memory for the normal pattern is the number of reserved memory corresponding to the normal pattern game.

[0018] Below the image display device 5, a winning ball device 6A and a variable winning ball device 6B are provided. Winning ball device 6A, for example, by a predetermined ball receiving member, forms a first starting winning opening that is always kept in a constant open state that allows game balls to enter. The variable winning ball device 6B forms a second starting prize opening that can be changed between a closed state and an open state by a normal electric accessory solenoid 81 shown in FIG. 2 as a normal electric accessory. The variable winning ball device 6B is provided with, for example, an electric tulip-shaped accessory having a pair of movable wing pieces, and when the normal electric accessory solenoid 81 is in an OFF state, the movable wing pieces are in a vertical position, thereby performing a second start. A closed state in which game balls do not enter the winning opening or a normal open state in which game balls hardly enter the second start winning opening. The variable winning ball device 6B is in an open state where the game ball can enter the second starting winning opening or the second starting winning opening by moving the movable wing to the tilting position when the normal electric accessory solenoid 81 is in the ON state. The mouth is in an enlarged open state in which game balls can easily enter. The open state where the game ball can enter the second start winning opening and the expanded open state where it is easy to enter are also called the first variable state. The closed state where the game ball does not enter the second start winning opening or the normal open state where it is difficult to enter is also called the second variable state. Note that the variable winning ball device 6B may be any device that can be changed between the first variable state and the second variable state, and is not limited to the one provided with the electric tulip-shaped accessory.

[0019] The entry of the game ball into the first starting winning opening formed by the winning ball device 6A is also called the first starting winning. The entry of the game ball into the second starting winning hole formed by the variable winning ball device 6B is also referred to as second starting winning. The game ball that has entered the first starting winning opening is detected by the first starting opening switch 22A shown in FIG. The game ball that has entered the second starting winning opening is detected by the second starting opening switch 22B shown in FIG. Based on the occurrence of the first start winning, a predetermined number of prize balls, such as three, are paid out, and the first reserved storage number can be updated so that one is added. However, when the first reserved memory number has reached the upper limit number, the first reserved memory number is not updated even if the first start winning is generated. Corresponding to the case where 1 is added to the first reserved memory number, the first starting condition is established, and the first special symbol game that variably displays the special symbol by the first special symbol display device 4A can be executed. Based on the occurrence of the second start winning, a predetermined number of prize balls, such as three, are paid out, and the second reserved storage number can be updated so that one is added. However, when the second reserved memory number has reached the upper limit number, the second reserved memory number is not updated even if the second start winning is generated. Corresponding to the case where 1 is added to the second reserved memory number, the second starting condition is satisfied, and the second special symbol game that variably displays the special symbol by the second special symbol display device 4B can be executed.

[0020] At a predetermined position of the game board 2, a general prize winning opening 10 is provided which is always kept in a constant open state by a predetermined ball receiving member. In the example shown in FIG. 1, the general prize winning openings 10 are provided at two locations on the lower left side of the game area. When a game ball enters one of the general winning holes 10, a predetermined number of prize balls, such as 10, are paid out.

[0021] In the game area formed by the game board 2, a first path and a second path are provided as flow paths along which game balls flow. The first path is mainly provided in an area on the left side of the image display device 5 when viewed from the front. The second path is mainly provided in a region on the right side of the image display device 5 when viewed from the front. The left area of ​​the image display device 5 is also called a left game area or a left game area. The right area of ​​the image display device 5 is also called a right game area or a right game area. The left game area and the right game area may be separated by, for example, the end face of the image display device 5 in the game area, the arrangement of the game nails, or the like. Shooting a game ball toward the left game area in order to make the game ball flow down the first path is also called left hitting. Shooting a game ball toward the right game area in order to make the game ball flow down the second path is also called right hitting. The first path is also called a left-handed path. The second path is also called a right-handed path. The first route and the second route may be composed of separate routes, or may be a partially shared route.

[0022] A game ball is shot from the ball shooting device and struck into the game area in response to the operation of a ball operating handle provided on the ball shooting device. When the game ball hit into the game area is guided to the left game area and flows down the first path, for example, by being guided along the arrangement of the game nails, it is guided to the second path in the right game area It becomes impossible or difficult to induce. When the game ball hit into the game area is guided to the right game area and flows down the second path, for example, by being guided along the arrangement of the game nails, the game ball is guided to the first path in the left game area It becomes impossible or difficult to induce.

[0023] The winning ball device 6A is provided on the first path in the left game area, and the game balls flowing down the first path can enter. The variable winning ball device 6B is provided on the second path in the right game area, and game balls flowing down the second path can enter. In addition, the variable winning ball device 6B may be able to enter the game ball that flows down the first path in the left game area. The variable winning ball device 6B may be arranged so that a game ball flowing down the second path in the right side gaming area is easier to enter than a game ball flowing down the first path in the left side gaming area.

[0024] A passage gate 41 and a special variable winning ball device 50 are provided on the second path in the right game area. The passage gate 41 forms a passage area through which game balls can pass. A game ball that has passed through the passage gate 41 is detected by the gate switch 21 shown in FIG. Based on the game ball passing through the passage gate 41, the number of normal reserved memories can be added and updated, and the variable display of normal patterns by the normal pattern display 20 can be executed as a normal pattern game. The passage gate 41 can be configured as a normal symbol operation opening into which game balls can enter. In this case, the gate switch 21 can be configured as a normal symbol operation port switch capable of detecting a game ball that has entered the normal symbol operation port.

[0025] The special variable winning ball device 50 forms a large winning opening that can be changed between a closed state and an open state by a large winning opening solenoid 82 as a special electric accessory. The upper portion of the special variable winning ball device 50 is formed with a guide passage having a passage width in the front-rear direction to the extent that game balls can pass therethrough. This guide path slopes down from the right side to the left side, and walls are provided on both sides of the extended passage, the front side and the back side. At the center of the guide path, there is formed an accessory entrance that serves as a big winning entrance. In the special variable winning ball device 50, a movable member 52 that can move in the front-rear direction is provided as a large winning opening opening / closing member at a position where the large winning opening can be opened and closed. In the special variable prize winning ball device 50, a fixing member 53 forming a fixed passage is provided in a portion of the guide passage where the large winning opening is not formed.

[0026] The movable member 52 is driven by a large winning prize opening solenoid 82, and is capable of advancing and retreating to open and close the accessory entrance serving as a large winning prize opening. In the special variable winning ball device 50, the game ball entering the inside from the big winning opening is detected by the count switch 23. Inside the special variable winning ball device 50, there is provided a V winning area 51, which is a specific area, as a winning area through which game balls can pass. Also, inside the special variable winning ball device 50, a normal area different from the V winning area 51 is provided. Above the V winning area 51, a plate-shaped distribution member is provided as a V winning opening opening / closing member that can switch the V winning area 51 between an open state and a closed state. The distribution member is driven by a specific area solenoid 83 and can advance and retreat to open and close the V winning area 51 . A game ball can pass through the V winning area 51 when it is in an open state, and a game ball cannot pass through when it is in a closed state. A gaming ball that has passed through the V winning area 51 is detected by the specific area switch 24 . Game balls that do not pass through the V winning area 51 pass through the normal area. The game balls that have passed through the V winning area 51 and the game balls that have passed through the normal area without passing through the V winning area 51 are is discharged to

[0027] On the surface of the game board 2, in addition to the above configuration, windmills for changing the flowing direction and speed of the game ball and a large number of obstacle nails are provided. At the bottom of the game area, an out port is provided for taking in game balls that have not entered any of the winning ports. Speakers 8L and 8R for reproducing and outputting sound effects are provided at the left and right upper positions of the game machine frame 3, and game effect lamps 9 for lighting effects are provided at the periphery of the game area. there is The game effect lamp 9 includes an LED. At a predetermined position on the game board 2, a movable body 32 that operates according to the effect is provided.

[0028] At the lower right position of the game machine frame 3, there is provided a ball-hitting operation handle operated by a player or the like to shoot a game ball toward the game area by the ball-hitting device. The hitting operation handle is also called an operation knob. At a predetermined position of the game machine frame 3 below the game area, a game ball paid out as a prize ball or a game ball lent by a predetermined ball lending machine is held so as to be supplied to the ball launching device. A serving tray is provided. The hitting ball supply plate is also called an upper plate. Below the upper plate, there is provided a prize ball storage plate in which the awarded balls flow down and are stored when the upper plate is full. The prize ball storage plate is also called a lower plate.

[0029] A stick controller 31A and a push button 31B are provided at predetermined positions of the gaming machine frame 3 below the game area. The stick controller 31A can be gripped and tilted by the player, and is provided with a trigger button that can be pushed and pulled by the player. An operation on the stick controller 31A is detected by the controller sensor unit 35A shown in FIG. The push button 31B can be pressed by the player. An operation on push button 31B is detected by push sensor 35B shown in FIG. In the pachinko game machine 1, the stick controller 31A and the push button 31B are used as detection means for detecting actions such as operations of the player, but detection means other than these may be used.

[0030] (Overview of game progress) A game ball is shot toward a game area by a player's rotation operation of the ball-hitting operation handle provided in the pachinko game machine 1.例文帳に追加 When the game ball passes through the passage gate 41, the normal pattern display device 20 starts the normal pattern game. In addition, when the previous normal game is being executed, even if the game ball passes through the passage gate 41, the normal game based on the passage cannot be executed immediately, so the normal game based on the passage cannot be performed. , is withheld up to a predetermined upper limit number, for example, "4". In the general pattern game, when a specific normal pattern such as a general pattern winning pattern is stopped and displayed as a fixed normal pattern, the display result of the normal pattern becomes "normal pattern winning". On the other hand, when a normal pattern other than the normal per pattern, such as a normal pattern losing pattern, is stop-displayed as the fixed normal pattern, the display result of the normal pattern becomes "normal pattern losing". In the case of "per normal", the variable winning ball device 6B is open control to open state or enlarged open state in a predetermined period. At this time, the second start winning opening becomes an open state or an enlarged open state.

[0031] When the game ball enters through the first starting winning port formed in the winning ball device 6A, the first special symbol game by the first special symbol display device 4A can be started. When the game ball passes through the second starting winning port formed in the variable winning ball device 6B and enters, the second special symbol game by the second special symbol display device 4B can be started. In addition, during the period during which the special game is being executed, or during the period when it is controlled to the big win game state or the small win game state, even if the game ball enters the start prize opening and the start prize is generated, Since the special game based on the starting prize cannot be executed immediately, the special game based on the starting prize is suspended up to a predetermined upper limit number such as "4". In the special symbol game, when a specific special symbol such as a big hit symbol is stopped and displayed as a fixed special symbol, the display result of the special symbol becomes a "big hit". On the other hand, when a predetermined special symbol different from the big-hit symbol such as a small-hit symbol is stop-displayed as the fixed special symbol, the display result of the special symbol becomes "small-hit". Further, when a special symbol different from the big winning symbol or the small winning symbol, such as a lost symbol, is stop-displayed as the fixed special symbol, the display result of the special symbol becomes "losing". Furthermore, when a special pattern different from a big hit pattern, a small hit pattern, and a losing pattern, such as a time saving pattern, is stopped and displayed as a fixed special pattern, the display result of the special pattern may be "time saving". . The special pattern may not include the time saving pattern. That is, the display result of the special symbol may not include "time saving".

[0032] In the special symbol game, after the display result of the special symbol becomes "big win", the game is controlled to a big win game state as an advantageous state for the player. In the jackpot game state, the jackpot opening formed in the special variable winning ball device 50 can be opened in a predetermined manner. At this time, the open state continues until a predetermined period of time, such as 29 seconds or 1.8 seconds, or the timing when the number of game balls entering the big winning opening reaches a predetermined number, whichever is earlier. be. The predetermined period during which the large winning opening can be controlled to be open is an upper limit period during which the large winning opening can be opened in one round, and is also referred to as an upper opening period. One cycle in which the big winning hole is open in the jackpot game state is called a round or a round game. In the jackpot game state, such rounds can be repeatedly executed until a predetermined upper limit number of times, such as 15 times or 2 times, is reached. In the jackpot game state, the player can get a prize ball by entering the game ball into the big winning hole. Therefore, the jackpot game state is an advantageous state for the player. The larger the number of rounds in the jackpot game state and the longer the upper limit period of opening, the more advantageous the player is.

[0033] When the display result of the special symbol becomes "big win", it includes a plurality of big win types. For example, the game state after the end of the big win game state such as the opening mode of the big winning mouth such as the number of rounds and the upper limit of the opening period, the normal state, the time saving state, and the probability variable state is set to a plurality of different settings, and the big win is set according to each setting. A type is specified. A plurality of jackpot types may include a part or all of a jackpot type with which many prize balls can be obtained, a jackpot type with few prize balls, or a jackpot type with which few prize balls can be obtained. Alternatively, the prize balls that can be obtained may include the same level of jackpot types. The control to the big win game state based on the display result of the special pattern being a "big win" is also called a big win in the pattern, a big win by the special pattern, a big win in the variable display, or a direct hit.

[0034] In the special symbol game, after the display result of the special symbols becomes "small hit", the game is controlled to the small win game state. In the small winning game state, the big winning opening formed in the special variable winning ball device 50 can be opened in a predetermined opening mode. For example, in the small winning game state, the big winning opening may be opened in the same opening mode as the big winning game state at the time of some jackpot types. It is sufficient that the big winning openings can be opened in a similar manner by sharing the number of times of opening and the opening period. Alternatively, in the small winning game state, the big winning opening may be opened in an opening mode different from the big winning game state. Similar to the big hit type, even when the display result of the special symbol is "small hit", a plurality of small hit types may be included. The big hit type and the small hit type are also collectively referred to as the hit type. The operation of opening and closing the big winning opening in the small winning game state is also called starting operation. When in the small winning game state, when the special variable winning ball device 50 is opened as a large winning opening, and the game ball passes through the V winning area 51 and is detected by the specific area switch 24, A condition for generating a big win is established, and control to a big win game state becomes possible. Controlling to the big hit game state based on the occurrence of the V prize by the game ball passing through the V winning area 51 in the small hit game state is also called the big hit via the small hit.

[0035] After the jackpot game state is finished, the game state can be controlled to a time-saving state or a variable probability state corresponding to the jackpot type. Further, in the special symbol game, after the display result of the special symbols becomes "time saving", the game state is controlled to the time saving state without being controlled to the jackpot game state. The time saving state is a gaming state in which the second special symbol game by the second special symbol display device 4B is more likely to be executed than the normal state. The gaming state in which the second special figure game is more likely to be executed than the normal state is a gaming state in which the game ball is more likely to enter through the second start winning opening than in the normal state. The control of whether or not the game ball is likely to pass through the second starting winning opening is also referred to as base control. Base control in the normal state is also called normal base control or low base control. Base control in the time saving state includes high base control. In addition to high-based control, the time-saving state may include mid-based control. Middle base control is base control in which the game ball is more likely to pass through the second start winning opening than the low base control, while the game ball is less likely to pass through the second starting winning opening than the high base control. The game state in which the middle base control is performed is also called a middle base state. A game state in which high base control is performed is also referred to as a high base state. High base control is also called high opening control.

[0036] In the case of the normal state, the medium base state, and the high base state, the time-saving design can be stopped and displayed as a display result of the special design. However, in the medium base state and the high base state, even if the time saving pattern is stopped and displayed as a result of the display of the special pattern, the base control based on the time saving pattern is not performed, and the medium base state or the high base state is not performed. A new control transition to the high base state is not initiated. In the time-saving state, time-saving control that shortens the average variable display time compared to the normal state is possible. Accordingly, the time saving state is also referred to as a time shortening state.

[0037] Since the time-saving state is a state in which the variation efficiency of the special symbols, especially the second special symbol, is improved, it is included in the special state advantageous to the player, which is different from the jackpot game state. When the game state is the variable probability state, in addition to the time-saving control, variable probability control is possible in which the probability that the display result of the special symbol is a "jackpot" is higher than in the normal state. Accordingly, the probability variable state is also referred to as the probability variable state. The probability variable state is included in the special state advantageous to the player, which is different from the jackpot game state, because the variable probability state is a state in which the special symbol variation efficiency is improved and the "big win" is likely to occur. The time-saving state and the variable probability state continue until any one of the predetermined termination conditions, such as execution of a predetermined number of special game games and control to the next jackpot game state, is established first. The end condition that the special figure game has been executed a predetermined number of times is also called a number cut. The time-saving state of cutting the number of times is also called the time-saving state of cutting the number of times. The probability-variable state of the number-of-times cutting is also called a number-of-times-cutting probability variation.

[0038] The normal game state is an advantageous state such as a big win game state that is advantageous to the player, a predetermined state such as a small win game state, and a game state that is not included in special states such as a time saving state and a variable probability state. In the normal state, the probability that the display result in the normal game is "normal game", the probability that the display result in the special game is "big hit", etc. are controlled to be the same as the initial setting state of the pachinko gaming machine 1. It is in play state. The initial setting state of the pachinko gaming machine 1 is a control state after executing the initial setting process without executing a predetermined recovery process after power-on, such as when the system is reset.

[0039] The state in which probability variable control is executed is also called a high probability state, and the state in which probability variable control is not executed is also called a low probability state. A state in which time-saving control is performed is also referred to as a high-based state, and a state in which time-saving control is not performed is also referred to as a low-based state. Combining these, the short-time state is also called a low-probability-high base state, the probability-variable state is a high-probability-high base state, and the normal state is a low-probability-low base state. The high probability state and the low base state are also referred to as the high probability low base state. In addition, the pachinko gaming machine 1 may not include the variable probability state as the game state.

[0040] After the end of the small winning game state, there are two cases: one is controlled to the big winning game state based on the occurrence of the V winning, and the other is the case where the game state before entering the small winning game state is not changed without the occurrence of the V winning. be. However, when the display result of the special game is "small hit" and the special game is executed a predetermined number of times in the cut, the control of the time saving state and the variable probability state ends and the normal state may occur. . In addition, the pachinko gaming machine 1 may not include the small winning game state as the game state. That is, the display result of the special symbols may not include the "minor hit".

[0041] It may be possible to control the game state to the time saving state when the time saving condition based on the number of execution times of the variable display is satisfied. Such a time-saving state is also called relief time-saving. The time saving condition is that after turning on the power to the pachinko machine 1, after the occurrence of a big hit, or after the display result of the special game becomes "time saving", even if the variable display is executed for a specific number of times, a new big hit game state or When control to a time saving state is not performed, what is necessary is just to be the conditions which can be established.

[0042] (Progress of production, etc.) In the pachinko game machine 1, various effects can be executed according to the progress of the game. This effect includes an effect for notifying the progress of the game and an effect for exciting the game. These effects include displaying various effects images on the image display device 5, outputting sound effects from the speakers 8L and 8R, turning on the game effect lamp 9, operating the movable body 32, and operating the stick controller. Vibration of 31A or push button 31B, or a combination of some or all of these, as long as it can be executed using any production device.

[0043] The effects that can be executed in accordance with the progress of the game include variable display of the effect symbols. Corresponding to the start of the first special game or the second special game, the "left", "middle", and "right" production pattern display areas 5L provided on the screen of the image display device 5, In 5C and 5R, the variable display of the production pattern is started. When the finalized special symbols, which are the display results in the first special game and the second special game, are stopped and displayed, the finalized production symbols, which are the display results in the variable display of the production symbols, are stopped and displayed. The fixed effect pattern is composed of a combination of three effect patterns corresponding to the "left", "middle" and "right" effect pattern display areas 5L, 5C and 5R. During the period from the start of the variable display of the performance symbols to the end thereof, the display mode in the variable display of the performance symbols may be the ready-to-win mode. The ready-to-win mode is a mode in which, when the stopped performance symbols on the screen of the image display device 5 constitute a part of the jackpot combination, the performance symbols that have not yet stopped continue to fluctuate. . The fact that the display mode in the variable display of the production pattern is the ready-to-win mode is also said to be the ready-to-win.

[0044] The ready-to-win effect can be executed in response to the variable display of the effect pattern becoming the ready-to-win mode. The pachinko gaming machine 1 can execute a plurality of types of ready-to-win effects so that the ratio of the display result of the variable display to be a "jackpot" differs when the effect modes are different. The ratio of "big win" corresponding to the effect mode is also called "big win reliability" and "big win expectation". The ready-to-win performance includes, for example, normal ready-to-win and super ready-to-win with higher reliability of big win than normal ready-to-win. In addition, a short reach and a long reach whose execution time is longer than the short reach may be included in correspondence with the execution time of the reach effect.

[0045] When the display result of the special symbols is a "big hit", the finalized performance symbols that are a predetermined big hit combination are stopped and displayed on the screen of the image display device 5 as the display result of the performance symbols. As an example, in the "left", "middle", and "right" production pattern display areas 5L, 5C, 5R, for example, the same production pattern, such as a production pattern showing the number "7", is aligned and on a predetermined effective line displayed to stop. In the case of a ``variable probability big hit'' controlled to a variable probability state after the end of the big winning game state, odd-numbered performance symbols such as a performance symbol showing the number ``7'', for example, may be stop-displayed together. In the case of a ``non-probability variable big win'' that is not controlled to a probability variable state after the end of the big win game state, even-numbered performance symbols such as a performance symbol showing the number ``6'', for example, may be stop-displayed together. The "non-probable variable jackpot" is also referred to as the "normal jackpot". In this case, the odd production design is also referred to as a probability variable design. The even-numbered production pattern is also called a non-variable pattern or a normal pattern. After becoming a ready-to-win mode with non-probability variation symbols, a promotion performance may be executed to finally become a "probability variation big hit".

[0046] When the display result of the special symbols is "small hit", the finalized performance symbols that are a predetermined small winning combination are stopped and displayed on the screen of the image display device 5 as the display result of the performance symbols. As an example, in the "left", "middle", and "right" production pattern display areas 5L, 5C, 5R, the same production pattern, such as a production pattern showing a number other than "7", is aligned and a predetermined effective line is displayed. May be paused on top. A common fixed performance symbol may be stop-displayed depending on whether the display result of the special symbol is a "big hit" or a "small hit".

[0047] When the display result of the special design becomes "losing", there is a case where the display result is not displayed in the ready-to-win state in the variable display of the production design, and the display result is stopped. In this case, as a result of displaying the performance symbols, the fixed performance symbols of the non-reach combination are stopped and displayed. The display result in which the fixed effect symbol of the non-reach combination is stopped and displayed without being in the reach mode is also called non-reach loss. When the display result of the special symbol becomes "losing", the variable display of the effect symbol becomes a ready-to-win mode, and the display result may be stopped after the ready-to-win effect is executed. In this case, as a result of the display of the performance symbols, the determined performance symbols of the ready-to-win combinations other than the big winning combination and the small winning combination are stopped and displayed. The display result in which the fixed effect pattern of the ready-to-win combination is stopped and displayed after the ready-to-win state is reached is also called a ready-to-win failure.

[0048] The effects that can be executed by the pachinko gaming machine 1 include display corresponding to variable display such as pending display and active display. In addition, for example, it is possible to execute a notice effect for notifying the reliability of the big hit during the variable display of the effect symbols. The notice effect includes the variable notice effect for notifying the reliability of the big hit corresponding to the variable display during execution, and the pre-reading notice effect for notifying the reliability of the big hit corresponding to the variable display before the execution of which the execution is suspended. may contain. The pre-reading advance notice effect may be capable of executing a change effect that changes the display mode of variable display compatible display such as suspended display and active display to a mode different from usual.

[0049] On the screen of the image display device 5, by temporarily stopping the effect pattern during the variable display of the effect pattern and then restarting the variable display, one variable display is simulated as a plurality of variable displays. It may be possible to execute a pseudo-continuous effect that makes it look like. The pseudo-continuous performance may be set so that the reliability of the big win is higher when the number of times of re-fluctuation for resuming the variable display after temporarily stopping the performance pattern is larger than when the number of times of re-fluctuation is small. . The variable display of the performance symbols may include a case where the pseudo-continuous performance is executed before the ready-to-win state is established and a case where the pseudo-continuous performance is executed after the ready-to-win state is established. In addition, in the variable display of the performance symbols, the pseudo-continuous performance may be executed at a plurality of timings.

[0050] During the control of the big-hit game state, it is possible to execute the performance during the big-hit game for notifying the big-hit game state. The effect during the big win may include the effect of notifying the number of rounds and the promotion effect of suggesting or notifying that the advantage of the big win game state is improved. During the control of the small-hit game state, it is possible to execute a performance during the small-hit game for notifying the small-hit game state. By executing a common performance during the control of the big win game state and during the control of the small win game state, the player can determine whether the current game state is the big win game state or the small win game state. It may be made unrecognizable or difficult to recognize.

[0051] In a non-game state in which no special game or the like is executed and the game is not progressing, an effect image for demonstration can be displayed on the screen of the image display device 5. FIG. The effect image for demonstration is also called a demo image. The display of the demonstration image is also called demonstration display. The production by the demonstration display is also called a customer waiting demonstration production.

[0052] (board configuration) The pachinko game machine 1 is equipped with, for example, a main board 11, an effect control board 12, a sound control board 13, a lamp control board 14, a relay board 15, a power supply board 17, etc. as shown in FIG. In addition, on the back of the pachinko gaming machine 1, various boards such as a payout control board, an information terminal board, and a launch control board are arranged.

[0053] The main board 11 is a control board on the main side, and has a function capable of controlling the progress of the game in the pachinko gaming machine 1 . The progress of the game is the execution of various games and game states such as execution of special game with management of suspension, execution of general game with management of suspension, big hit game state, small hit game state, time saving state, probability variable state, etc. including the migration of The main board 11 includes a game control microcomputer 100, a switch circuit 110, and a solenoid circuit 111.

[0054] The game control microcomputer 100 provided on the main board 11 is, for example, a one-chip microcomputer, and includes a ROM (Read Only Memory) 101, a RAM (Random Access Memory) 102, a CPU (Central Processing Unit) 103, and a random number It can be configured with a circuit 104 and an I / O (Input / Output port) 105 . ROM101, RAM102, part or all of the random number circuit 104 may be externally attached to the game control microcomputer 100, or may be built in the game control microcomputer 100 good. The switch circuit 110 takes in detection signals from various switches for game ball detection and transmits them to the game control microcomputer 100 . Various switches for game ball detection include, for example, gate switch 21, starter switches such as first starter switch 22A and second starter switch 22B, count switch 23, specific area switch 24, and outlet switch 26. The detection signal indicates that a game ball has passed or entered and the switch has been turned on. The transmission of the detection signal means that the passage or entry of the game ball has been detected. The solenoid circuit 111 can supply the solenoid drive signal from the game control microcomputer 100 to the normal electric accessory solenoid 81, the big winning opening solenoid 82, and the specific area solenoid 83. The solenoid drive signal may be any signal that turns on each solenoid.

[0055] The ROM 101 provided in the game control microcomputer 100 is a non-volatile storage device that stores computer programs and data used for game control. The data stored by the ROM 101 includes table data that constitutes a table used for variation patterns, effect control commands, other various settings, determinations, and decisions. The RAM 102 provided in the game control microcomputer 100 is a temporary storage device that provides a work area used for game control and a stack for saving data. RAM102, even when the power supply to the pachinko game machine 1 is stopped, if it is within a predetermined period of time, it may be a backup RAM that saves the storage content in part or all of the storage area so that it can be restored. The RAM 102 is also called RWM (Read / Write Memory). The work area of ​​the RAM 102 includes storage areas capable of storing various data used for game control, such as counters, timers, buffers, and storage areas for various codes and numerical values. The CPU 103 provided in the game control microcomputer 100 can control the progress of the game in the pachinko gaming machine 1 by executing the process corresponding to the program stored in the ROM 101 .

[0056] A random number circuit 104 provided in the game control microcomputer 100 counts updatably numerical data indicating various random numbers used when controlling the progress of the game. A random number used to control the progress of a game is also called a game random number. Part or all of the game random numbers may be updated by hardware using a dedicated circuit, or may be updated by software such as a computer program executed by the CPU 103.

[0057] FIG. 3 shows an example of game random numbers. The random numbers for the game are the random number MR1-1 for special design determination, the random number MR1-2 for the winning design, the initial value for the winning design MR1-3, and the random number MR2-1 for the normal design per design. , Random number MR2-2, which is the initial value for the pattern per normal pattern, random number MR3-1 for the normal pattern variation pattern, random number MR3-2 for selecting the loss effect, and random number MR3-3 for selecting the variation pattern type , and random numbers MR3-4 for variation patterns.

[0058] The random number MR1-1 for special design determination determines the display result of the special design, such as whether the display result of the special design is a "big hit" or whether the display result of the special design is a "small hit". Used for judgment. The random number MR1-2 for the winning design is a fixed special design, such as a big hit design when the display result of the special design is set to "big hit", and a small hit design when the display result of the special design is set to "small hit". Used to select from multiple special symbols. The random number MR1-3, which is the initial value for the winning symbol, is used to set the initial value of the random number MR1-2. The random number MR2-1 for the normal symbol per pattern is used to select a fixed normal symbol to be displayed when the display result is "normal per pattern" in the variable display of normal symbols from a plurality of normal symbols. The random number MR2-2, which is the initial value for the normal per symbol pattern, is used to set the initial value of the random number MR2-1. The random number MR3-1 for the normal symbol variation pattern is used to determine the normal symbol variation pattern to one of a plurality of patterns prepared in advance. The random number MR3-2 for selecting the loss effect is used to select whether or not the ready-to-win state is set in the variable display of the effect symbols when the display result of the special symbol is "loss". The random number MR3-3 for selecting the variation pattern type is used to select the variation pattern type of the special symbol. Variation pattern type of special design is, for example, a group in which the variation pattern of special design is classified in advance based on the production mode during variable display of production design, and it is configured to include one or more variation patterns. Just do it. The random number MR3-4 for the variation pattern is used to select a special symbol variation pattern.

[0059] The CPU 103 reads out various tables from the ROM 101 and refers to them when performing various determinations and decisions based on random numbers such as numerical data indicating values ​​of game random numbers. Even when random numbers are not used, a necessary table may be read out from the ROM 101 and referenced to perform various determinations, decisions, settings, and the like.

[0060] The I / O 105 provided in the game control microcomputer 100 includes an input port to which various signals are input and an output port to which various signals are output. Various signals input to the input port of the I / O 105 may include detection signals from various switches transmitted via the switch circuit 110 . Various signals output from the output port of I / O 105 are the first special symbol display device 4A, the second special symbol display device 4B, the normal symbol display device 20, the first reservation display device 25A, the second reservation display device 25B, A signal for controlling the normal figure holding display 25C, etc., and a solenoid drive signal for driving the normal electric accessory solenoid 81, the big winning opening solenoid 82, the specific area solenoid 83, etc., may be included.

[0061] The main board 11 outputs a performance control command corresponding to the progress of the game to the performance control board 12 as a part of the operation of controlling the progress of the game by the game control microcomputer 100 . The effect control command is a command that designates or notifies the progress of the game or the like. The effect control command output from the main board 11 is relayed by the relay board 15 and supplied to the effect control board 12. The effect control commands include commands for specifying various determination results on the main board 11, such as the display result of the special game, the winning type, and the variation pattern; , the number of pending memories, the game state, and a command specifying the occurrence of an error.

[0062] The effect control board 12 is a sub-side control board independent of the main board 11, and has a function capable of receiving the effect control command and controlling the effect based on the received effect control command. Effects that can be controlled by the effect control board 12 are various effects according to the progress of the game, such as driving the movable body 32, and also include various reports such as an error report and a power failure recovery report. Effect control board 12 includes effect control CPU 120, ROM 121, RAM 122, display control unit 123, random number circuit 124, and I / O 125.

[0063] The effect control CPU 120 executes a program stored in the ROM 121 to perform processing for controlling the execution of the effect together with the display control unit 123 . This process is a process for realizing various functions of the effect control board 12, and includes determination of the effect to be executed. Production control CPU120, such as data of various tables, while using the various data ROM121 is stored, uses the RAM122 as a main memory. Effect control CPU120, based on the detection signal from the controller sensor unit 35A and the push sensor 35B, may also instruct the display control unit 123 to execute the effect. The detection signal here is a signal that is output when an operation by a player is detected, and may be a signal that appropriately indicates the content of the operation.

[0064] The display control unit 123 includes a VDP (Video Display Processor), a CGROM (Character Generator ROM), a VRAM (Video RAM), etc., and mainly executes effects related to display based on the effect execution instruction from the effect control CPU 120. control possible. The display control unit 123 displays the effect image on the screen of the image display device 5 by supplying the image display device 5 with a video signal corresponding to the effect to be executed. The display control unit 123 further supplies a sound designation signal to the audio control board 13 and supplies a lamp signal to the lamp control board 14 . The sound designation signal designates sounds to be output from the speakers 8L and 8R. The lamp signal designates a lighting mode or an extinguishing mode of the game effect lamp 9 . By supplying the sound designation signal and the lamp signal, it becomes possible to output sounds from the speakers 8L and 8R and turn on / off the game effect lamp 9 in synchronization with the display of the effect image. The display control unit 123 may be capable of supplying a signal for operating the movable body 32 to the motor or solenoid of the movable body 32 or to a driver circuit that drives the movable body 32 . A driver board for driving the movable body 32 may be provided separately from the effect control board 12 .

[0065] The random number circuit 124 counts updatably numerical data indicating various random numbers used when controlling the execution of various effects. A random number used to control the execution of an effect is also called a random number for effect. The effect random number may be updated by software such as a computer program executed by the effect control CPU120. Effect control CPU120, such as numerical data indicating the value of the random number for effect, when performing various determinations and decisions based on the random number, read from the ROM121 and refer to various tables. Even if the random number value is not used, the effect control CPU 120 may read and refer to the necessary table from the ROM 121 to perform various determinations, determinations, settings, and the like.

[0066] The I / O 125 includes an input port for taking in production control commands and the like transmitted from the main board 11, for example, and an output port for transmitting various signals. The input port of the I / O 125 may include an input terminal for the detection signal supplied from the controller sensor unit 35A and an input terminal for the detection signal supplied from the push sensor 35B. The output port of the I / O 125 is an output terminal for a video signal supplied to the image display device 5, an output terminal for an audio designation signal supplied to the audio control board 13, and an output terminal for a lamp signal supplied to the lamp control board 14. and an output terminal.

[0067] The audio control board 13 is equipped with various circuits for driving the speakers 8L and 8R, drives the speakers 8L and 8R based on the sound designation signal from the display control unit 123, and outputs the sound designated by the sound designation signal to the speaker. Output from 8L and 8R. The lamp control board 14 is equipped with various circuits for driving the game effect lamp 9, drives the game effect lamp 9 based on the lamp signal from the display control unit 123, and displays the game effect lamp in a manner specified by the lamp signal. Turn on or off 9. In this way, the sound output from the speakers 8L and 8R and the lighting and extinguishing of the game effect lamp 9 can be controlled based on the signal from the display control section 123. FIG. It should be noted that the control of the movable body 32, such as the supply of the sound designation signal and the lamp signal, the control of the sound output and the lighting and extinguishing of the lamp, and the supply of the signal to operate the movable body 32, is partly performed by the production control CPU 120. Or you may make it run all. Boards other than the main board 11, such as the effect control board 12, the sound control board 13, and the lamp control board 14, are also called sub-boards. As in the configuration example shown in FIG. 2, a plurality of sub-boards may be provided for each function, or unlike the configuration example shown in FIG. 2, one sub-board may be configured to have a plurality of functions. good.

[0068] The power supply board 17 can supply power from an AC power supply such as AC100V in an external power supply such as a commercial power supply to electrical components including various control boards such as the main board 11 and the production control board 12. The power supply board 17 includes, for example, a rectifier circuit for converting alternating current (AC) into direct current (DC), a power circuit for converting a predetermined DC voltage into a specific DC voltage (for example, 12 V DC or 5 V DC), and the like. I have. The pachinko game machine 1 can switch between starting and ending power-on by operating the power switch 91 . The switch circuit 110 of the main board 11, the reset signal from the power supply board 17, the power off signal, the clear signal is captured and transmitted to the microcomputer 100 for game control. The reset signal is an operation stop signal for making the control circuit such as the game control microcomputer 100 in the operation stop state, and can be output using either the power supply monitoring circuit, the IC with built-in watchdog timer, or the system reset IC. I wish I had. The power-off signal turns off when the predetermined power supply voltage used in the pachinko game machine 1 exceeds a predetermined value, and turns on when the period in which the predetermined power supply voltage is equal to or less than the predetermined value continues for the power-off reference time or longer. Become. The clear signal is turned on, for example, when a clear switch 92 provided on the power supply board 17 is pressed.

[0069] (motion) Next, the operation (action) of the pachinko gaming machine 1 will be described.

[0070] (Major operations of the main board 11) First, main operations in the main board 11 will be described. When power supply to the pachinko game machine 1 is started, the game control microcomputer 100 is activated, and the CPU 103 executes the main process for game control.

[0071] FIG. 4 is a flowchart showing the main processing P_MAIN for game control executed by the CPU 103 on the main board 11. As shown in FIG. When the main process P_MAIN for game control shown in FIG. 4 is started, the CPU 103 executes the power supply start corresponding process P_POWER_ON (step S1), and then executes the RWM check process P_RWM_CHK (step S2). The power supply start corresponding process P_POWER_ON of step S1 corresponds to the start of power supply in the pachinko game machine 1, and initial setting of the game control microcomputer 100 can be executed. The initial setting of the game control microcomputer 100 may include output port initialization, interrupt vector setting, built-in device register setting, and specific register setting. The RWM check processing P_RWM_CHK in step S2 includes checksum calculation processing, and compares the checksum data obtained as a processing result with the data stored in the checksum buffer. Judge that the content is normal.

[0072] Subsequently, it is determined whether or not a predetermined restoration condition is satisfied (step S3). The recovery condition can be established when the clear signal corresponding to the operation of the clear switch 92 is in the off state, the checksum buffer has normal stored data, and the stored contents in the RAM 102 as backup RAM are normal. . When the power of the pachinko game machine 1 is turned on, for example, if the clear switch 92 provided on the power supply board 17 is pressed down, a clear signal in the ON state is input to the game control microcomputer 100. If such an on-state clear signal is input, it may be determined in step S3 that the restoration condition is not established. The checksum buffer stores the checksum data calculated by the checksum calculation process when the backup judgment time is measured by the backup monitoring timer at the time of the previous power failure. If the counted value of the backup monitoring timer does not match the specific value corresponding to the backup determination time, it may be determined in step S3 that the recovery condition is not satisfied. The backup data may be data stored in the game work area in the RAM 102, which serves as a backup RAM for game control. In step S3, whether or not the recovery condition can be satisfied may be determined based on the result of confirming or inspecting the presence or absence of backup data and the presence or absence of data errors by the RWM check process P_RWM_CHK of step S2.

[0073] If the recovery condition is satisfied (step S3; Yes), the backup setting process P_BACKUP_SET is executed (step S4). The backup time setting process P_BACKUP_SET uses the backup time command transmission table to enable transmission of the effect control command corresponding to the time of backup from the main board 11 to the effect control board 12 . The backup setting process P_BACKUP_SET enables initialization by clearing the process code, timer, counter, and flag specified by the backup setting table.

[0074] If the recovery condition is not satisfied (step S3; No), the initialization setting process P_INIT_SET is executed (step S5). The initialization setting process P_INIT_SET enables clear data to be transferred to the game work area, which is the work area in the RAM 102 . Thereby, the game work area in the RAM 102 is initialized. Then, the initialization setting process P_INIT_SET uses the command transmission table at the time of initialization to enable transmission of the effect control command corresponding to the time of initialization from the main board 11 to the effect control board 12. The initialization setting process P_INIT_SET enables initialization by clearing the buffers, timers, pointers, and counters specified by the initialization setting table.

[0075] After that, the control start setting process P_STACON is executed (step S6). The control start setting processing P_STACON may include wait processing. In the wait process, the sub-board such as the effect control board 12 can be reliably activated by executing the loop process and waiting until the set waiting time elapses. Also, the control start setting process P_STACON may include a specific number of times command transmission process or a chip individual number information command transmission process. The specified number of times command transmission process makes it possible to transmit an effect control command designating the count value of the specified number of times counter from the main board 11 to the effect control board 12 when the power is turned on. The specific number counter is provided at a predetermined address in the RAM 102, and may be capable of counting the remaining number of times until the number of executions of the variable display reaches the specific number corresponding to the time saving condition. The command transmission processing for chip individual number information makes it possible to transmit from the main board 11 to the effect control board 12 an effect control command designating the stored value of the chip individual number register. The individual chip number register is included in the built-in register of the game control microcomputer 100, and a different value assigned to each chip may be stored as an individual chip number.

[0076] The control start setting process P_STACON may include an out-of-area process at startup. Start-up outside processing is a process executed by reading a program stored in the non-game program area of ​​the ROM 101 corresponding to start-up due to the start of power supply in the pachinko gaming machine 1 . The start-up outside area processing may be, for example, performance display RWM initial value setting processing. The performance display RWM initial value setting process enables setting of initial values ​​for initial display by the 7-segment LEDs that constitute the performance display monitor. The performance display monitor may be mounted on the main board 11, for example, and can display the contents of the set values ​​and the contents of the base. The set value can be changed in any of a plurality of stages, such as 6 stages, when the pachinko gaming machine 1 is in a setting change state in which the settings can be changed, and the probability that the display result of the special symbol will be a "big hit". be configurable. The base is divided by the number of game balls launched into the game area by the number of prize balls paid out when the game balls pass through each of the winning openings, such as the start winning opening, the general winning opening, and the big winning opening. Calculated.

[0077] After the control start setting process P_STACON in step S6, timer interrupt counter setting is performed (step S7). In step S7, the PTC counter output value is set such that a periodic timer interrupt occurs at predetermined time intervals, such as 4 [ms (milliseconds)]. After that, the main process P_MAIN for game control enters a loop process. In this loop processing, interrupts are disabled (step S8), random number update processing P_TFINIT for initial value determination is executed (step S9), processing outside the loop area P_REGOUT is executed (step S10), and interrupts are enabled. is set (step S11), and the process returns to step S8. Then, each time an interrupt request signal is input to the CPU 103 from the PTC when the interrupt is enabled, the CPU 103 can execute timer interrupt processing. As a result, the CPU 103 can execute timer interrupt processing every time a predetermined period of time, such as 4 [ms], elapses.

[0078] Figure 5 is the flowchart which shows one example of timer interrupt processing P_PCT for game control. In the timer interrupt process P_PCT shown in FIG. 5, a power-off process P_POWER_OFF is executed (step S51). Subsequently, it is determined whether or not the fraudulent activity monitoring flag is "0" (step S52). The fraud monitoring flag is set to "1" corresponding to the on state when magnetism is detected by the magnet sensor or radio waves are detected by the frame radio wave sensor. Otherwise, the fraud monitor flag is set to '0', which corresponds to an off state.

[0079] When the fraudulent activity monitoring flag is "1" (step S52; No), game stop processing P_GAME_STOP is executed (step S53). The game stop processing P_GAME_STOP may be processing that initializes the output port and turns off the output of the connection confirmation signal. The connection confirmation signal is transmitted from the main board 11 to the payout control board, and when it is in the OFF state, execution of the payout process in the payout control board is stopped.

[0080] If the illegal activity monitoring flag is "0" (step S52; Yes), switch processing P_SW is executed (step S54), switch error notification processing P_CON_CHK is executed (step S55), and random number update processing P_RANDOM is executed. (Step S56), the initial value determination random number update process P_TFINIT is executed (Step S57). In addition, the special symbol process processing P_TPROC is executed (step S58), the normal symbol process processing P_FPROC is executed (step S59), the information output processing P_JYOUHOU is executed (step S60), and the prize ball processing P_PAY is executed (step S61 ), and the display process P_HYOUZI is executed (step S62). Further, other timer interrupt handling processing is executed (step S63). After that, after the interrupt permission is set (step S64), the timer interrupt process P_PCT ends.

[0081] In the power-off process P_POWER_OFF in step S51, the power confirmation signal transmitted from the power supply board 17 is judged, and the checksum calculation process and the like at the time of power-off can be executed. The switch processing P_SW in step S54 determines the state of the input port and enables update of the switch-on buffer and the like. The switch error notification process P_CON_CHK in step S55 can update the count value of the sensor ON counter specified by the switch error notification determination table, for example, and when the count value reaches the sensor abnormality error determination value, the error notification display to be executable. The random number update process P_RANDOM in step S56 allows software random numbers among game random numbers to be updated by software. The random number update process P_TFINIT for initial value determination in step S57 makes it possible to update the random number used as the random number initial value among the game random numbers by software.

[0082] The special symbol process processing P_TPROC in step S58 includes processing related to the variable display of special symbols and the game state, such as management of execution and suspension of the special symbol game, control of the big win game state and small win game state, and control of the game state. be The normal symbol process processing P_FPROC in step S59 includes normal symbol processing, such as managing the execution and suspension of the general pattern game based on the detection signal from the gate switch 21, and opening and closing control of the variable winning ball device 6B based on the "normal pattern hit". It includes processing related to variable display and state control of the second start winning opening. Information output processing P_JYOUHOU in step S60 sets an information output signal. The information output signal is a signal corresponding to information supplied to a hall management computer installed outside the pachinko gaming machine 1, such as jackpot information, starting information, probability fluctuation information, and the like. The jackpot information indicates the number of occurrences of jackpots and the like. The starting information indicates the number of starting winnings and the like. The probability variation information indicates, for example, the number of times the probability variation state has occurred. The prize ball processing P_PAY in step S61 includes a prize ball command output counter addition process and a prize ball control process. In the prize ball command output counter addition process, a prize ball number table is used to determine whether the switch is turned on, and when the switch is detected to be on, the prize ball command output counter and the winning information output counter are updated. The prize ball control process selects the process corresponding to the prize ball process code, and controls the payout of the prize balls based on the detection of the game balls. The display process P_HYOUZI of step S62 sets the display related to the first holding indicator 25A, the second holding indicator 25B, the normal figure holding indicator 25C, and various other status indicator lights.

[0083] FIG. 6 is a flowchart showing an example of a process that can be executed in step S58 shown in FIG. 5 as the special symbol process process P_TPROC. CPU103, in special design process processing P_TPROC, does 1st start winning a prize correspondence flag setting (step S101). The first start winning corresponding flag setting reflects the state of the first start opening switch 22A included in the switch-on buffer in the flag register of the CPU 103 by executing a logic operation instruction or the like. At this time, the fact that the zero flag in the flag register is ON indicates that the first start winning corresponding flag is OFF. On the other hand, the fact that the zero flag is in the off state indicates that the first start winning corresponding flag is in the on state. Then, by the transfer command for setting the table pointer, set the first start winning table (step S102). After that, it is determined whether or not the first start winning corresponding flag is ON (step S103). When the first starting winning correspondence flag is ON (step S103; Yes), the starting opening switch passing process P_TZU_ON is executed (step S104).

[0084] When the first start winning corresponding flag is off corresponding to step S103 (step S103; No), after the starting opening switch passage processing P_TZU_ON in step S104, the second starting winning corresponding flag is set (step S105) . The second start winning corresponding flag setting reflects the state of the second start opening switch 22B included in the switch-on buffer in the flag register of the CPU 103 by executing a logic operation instruction or the like. At this time, the fact that the zero flag in the flag register is ON indicates that the second start winning corresponding flag is OFF. On the other hand, the fact that the zero flag is off indicates that the second start winning corresponding flag is on. Then, by the transfer command for setting the table pointer, set the second starting opening winning table (step S106). After that, it is determined whether or not the second start winning corresponding flag is ON (step S107). When the second starting winning corresponding flag is ON (step S107; Yes), the starting opening switch passing process P_TZU_ON is executed (step S108).

[0085] The starting opening switch passing process P_TZU_ON of step 104 uses the first starting opening winning table set in step S102, and when the number of first reserved memories is less than the upper limit number, the number of first reserved memories and the total reserved Update to add 1 to the number of memories, random number MR1-1 for special pattern judgment, random number MR3-2 for selection of loss effect, random number MR3-3 for selection of variation pattern type, random number MR3 for variation pattern After extracting -4 and storing them in each random number buffer, transfer them to the first special symbol holding buffer. In addition, using the first reservation storage information designation command transmission table, the first reservation storage information designation command in which the number of first reservation storage is designated can be transmitted from the main board 11 to the effect control board 12. Then, the value indicating "1" as the specified value of starting winning prize is stored in the starting winning prize buffer.

[0086] The starting opening switch passage process P_TZU_ON in step S108 uses the second starting opening winning table set in step S106, and if the second holding memory number is less than the upper limit number, the second holding memory number and the total holding Update to add 1 to the number of memories, random number MR1-1 for special pattern judgment, random number MR3-2 for selection of loss effect, random number MR3-3 for selection of variation pattern type, random number MR3 for variation pattern After extracting -4 and storing them in each random number buffer, transfer them to the second special symbol holding buffer. In addition, using the second reservation storage information designation command transmission table, the second reservation storage information designation command in which the number of second reservation storage is designated can be transmitted from the main board 11 to the effect control board 12. Then, the value indicating "2" as the specified start winning prize value is stored in the starting winning prize buffer.

[0087] In step S104 and step S108, a common starting port switch passage process P_TZU_ON can be executed. On the other hand, the starting opening switch passage processing P_TZU_ON in step S104 uses the first starting opening winning table set in step S102, whereas the starting opening switch passage processing P_TZU_ON in step S108 uses the first opening opening winning table set in step S106. 2 Use the start-up prize table. In this way, the common starting opening switch passing process P_TZU_ON is executed using different starting opening winning tables. Therefore, when the game ball enters the first starting winning opening and when entering the second starting winning opening, different data setting and control are possible by common processing. In addition, the starting opening switch passage process P_TZU_ON may include a winning effect process using the extracted game random number.

[0088] If the second start winning flag corresponding to step S107 is off (step S107; No), after the start opening switch passage processing P_TZU_ON in step S108, the transfer instruction to set the pointer, special symbol process processing jump A table is set (step S109). The special symbol process processing jump table is an address management table that enables selection and execution of processing corresponding to the read value of the special symbol process code. Special symbol process code, corresponding to the progress of the game control in the pachinko gaming machine 1, it is possible to update setting to either 00 [H] ~ 0B [H], also referred to as a special pattern process code. where [H] indicates hexadecimal. Binary numbers are sometimes indicated by [B].

[0089] Following step S109, a special symbol process code is loaded by a transfer command for reading out stored data (step S110). Then, by executing the 2-byte data selection process P_ABXEXEC (step S111), to obtain the address of the process selected corresponding to the special symbol process code. The address acquired at this time is set in the pointer. After that, by executing the process pointed by the pointer according to the subroutine call command (step S112), the process selected corresponding to the special symbol process code can be executed. When the selected process ends and returns to the special symbol process process P_TPROC by the return command, this special symbol process process P_TPROC also ends and returns to the timer interrupt process P_PCT for game control by the return command.

[0090] FIG. 7 shows a configuration example TT01 of a special symbol process processing jump table used in the special symbol process processing P_TPROC. The special symbol process processing jump table includes table data that can be set to the internal register of the CPU 103 used as a pointer for the address of the process selected in correspondence with the special symbol process code. The special symbol process processing jump table of the configuration example TT01 includes special symbol normal processing P_TNORMAL when the special symbol process code is 00 [H] and special symbol variation processing P_TSTART when the special symbol process code is 01 [H]. And, special symbol stop processing P_TSTOP when the special symbol process code is 02 [H], small hit open pre-processing P_TLFAN when the special symbol process code is 03 [H], and special symbol process code is 04 [ Small hit open processing P_TLOPEN when it is H], small hit post-processing P_TLCLSF when special symbol process code is 05 [H], and small hit when special symbol process code is 06 [H] Eject ball standby process P_TLOUT, small hit end process P_TLEND when special symbol process code is 07 [H], large winning opening pre-process P_TINT when special symbol process code is 08 [H], special Large winning opening open processing P_TOPEN when the symbol process code is 09 [H], large winning opening post-processing P_TCLSF when the special symbol process code is 0A [H], and special symbol process code is 0B [ H], table data that can set the address value corresponding to the jackpot end process P_TEND in the pointer is included.

[0091] The special symbol normal process P_TNORMAL determines whether or not to start the special symbol game based on the presence or absence of stored reservation information, determines the special symbol display result using the random number MR1-1 for special symbol determination, To determine fixed special symbols to be stopped and displayed in variable display of special symbols, and to determine variation patterns of special symbols. The special figure display result includes ``big win'', ``small win'', ``losing'', etc., and when it is determined to be ``big win'', control is made to a big win game state as an advantageous state for the player. is determined. Further, when the display result of the special pattern is "big win", any one of a plurality of types of jackpot game states with different degrees of advantage for the player can be selected in correspondence with the jackpot pattern to be a confirmed special pattern. It is determined whether the state is controlled. Therefore, by executing the special symbol normal processing P_TNORMAL, the CPU 103 can determine whether or not to control to an advantageous state that is advantageous to the player. It is possible to decide which one to control. Furthermore, CPU103, by executing the special symbol normal process P_TNORMAL, can be determined to any one of a plurality of types of variation patterns.

[0092] Special symbol variation processing P_TSTART measures the elapsed time from the start of the special symbol variation in the first special symbol display device 4A and the second special symbol display device 4B, and the special symbol variation time corresponding to the variation pattern has passed. It is possible to determine whether or not The special symbol stop processing P_TSTOP measures the elapsed time after the special symbol stops changing in the first special symbol display device 4A or the second special symbol display device 4B, and determines whether or not the symbol stop time has passed. enable The symbol stop time may be set as the time to stop and display the special symbol when it is determined that the special symbol variation time has elapsed in the special symbol variation process P_TSTART. When the symbol stop time has elapsed, the special symbol process code is updated and various settings are performed in accordance with the special symbol display result. For example, if the special figure display result is "big hit", the special symbol process code can be updated to 08 [H], and if the special figure display result is "small hit", the special symbol process code can be changed to 03 [H]. It is possible to update the special symbol process code to 00 [H] when the special symbol display result is "loss".

[0093] Small hit opening pre-processing P_TLFAN, small hit opening middle processing P_TLOPEN, small hit opening post-processing P_TLCLSF, small hit discharge ball standby processing P_TLOUT, small hit end processing P_TLEND are processes for controlling the progress of the game in the small hit game state is. The big winning mouth opening pre-processing P_TINT, the big winning mouth opening process P_TOPEN, the big winning mouth opening post-processing P_TCLSF, and the big winning ending process P_TEND are processes for controlling the progress of the game in the big winning game state.

[0094] (Major operations of production control board 12) Next, main operations in the effect control board 12 will be described. In the effect control board 12, when the power supply voltage is supplied from the power supply board 17 or the like, the effect control CPU 120 is activated to execute the effect control main process.

[0095] FIG. 8 is a flowchart showing the main processing S_MAIN for effect control executed by the effect control CPU 120 in the effect control board 12. As shown in FIG. When the main process S_MAIN for the effect control shown in FIG. 8 is started, the effect control CPU 120 executes the effect control initialization process S_INIT (step S71). Effect control initialization process S_INIT includes clearing of RAM122, setting of various initial values, register setting for a timer circuit mounted on effect control board 12, and the like. Subsequently, an initial operation control process S_SYOKI is executed (step S72). The initial motion control process S_SYOKI makes it possible to control the initial motion of the movable body 32, such as control of driving the movable body 32 to return it to the initial position, control of confirming a predetermined motion, and the like. After that, it is determined whether or not the timer interrupt flag is on (step S73). The timer interrupt flag is set to ON every time a predetermined period of time, for example 2 [ms (milliseconds)], elapses based on the register setting for the timer circuit. When the timer interrupt flag is turned off (step S73; No), step S73 is repeated to wait.

[0096] The timer interrupt flag corresponds to ON (step S73; Yes), the timer interrupt flag is cleared and turned off (step S74), the command analysis process S_COMMAND is executed (step S75), and the effect control process process S_CPROC is executed (step S76), the effect random number update process S_RANDOM is executed (step S77), and the effect output process S_OUT is executed (step S78). Then, after executing other timer interrupt handling processing (step S79), the process returns to step S73.

[0097] Command analysis processing S_COMMAND of step S75 enables reading of the production control command stored in the production control command reception buffer, and setting and control corresponding to the read production control command. Effect control CPU120, by executing the command analysis process S_COMMAND, corresponding to the effect control command transmitted from the main board 11, the storage data indicating the state of the flag, the storage data of the register, other, the work area of ​​the RAM122 Any stored data in , etc., can be updated. The effect control process processing S_CPROC in step S76 includes, for example, the display of the effect image on the screen of the image display device 5, the sound output from the speakers 8L and 8R, and the lighting or It is possible to control the execution of performance using various performance devices including turning off the light and driving control of the movable body 32. - 特許庁 Control contents of the production using various production devices, based on the production control command sent from the main board 11, the execution result of the processing by the production control CPU 120, etc. If it becomes possible good. The effect random number update process S_RANDOM of step S77 enables at least part of the effect random numbers used on the side of the effect control board 12 to be updated by executing a program as software.

[0098] FIG. 9(A) is a flow chart showing an example of a process executable in step S76 shown in FIG. 8 as the effect control process S_CPROC. Effect control CPU120 executes the look-ahead effect setting process S_SAKI_SET in the effect control process (step S151). The look-ahead effect setting process S_SAKI_SET enables determination, determination, setting, etc. regarding the execution of the look-ahead preview effect based on the effect control command at the time of start winning, for example, transmitted from the main board 11. Also, the look-ahead effect setting process S_SAKI_SET makes it possible to update the pending display based on the number of pending memories specified from the effect control command.

[0099] After the look-ahead effect setting process S_SAKI_SET in step S151, the effect control process process jump table is set by the transfer command for setting the pointer (step S152). The performance control process processing jump table is an address management table that enables selection and execution of processing corresponding to the read value of the performance control process code. The effect control process code can be updated to any one of 00[H] to 0A[H] corresponding to the progress of effect control in the pachinko game machine 1, and is also called the effect process code. The effect control process code is loaded by a transfer command for reading out stored data (step S153). Corresponding to the production control process code thus acquired, the address of the selected process is set to the production control pointer (step S154). Therefore, by executing the process pointed to by the effect control pointer (step S115), the process selected corresponding to the effect control process code can be executed.

[0100] FIG. 9(B) shows a configuration example TT02 of the effect control process processing jump table used in the effect control process processing S_CPROC. The performance control process processing jump table includes table data capable of setting the address of the process selected in correspondence with the performance control process code to a register used as a performance control pointer. The effect control process processing jump table of the configuration example TT02 is the variation pattern command waiting process when the effect control process code is 00 [H], and the effect symbol variation start process when the effect control process code is 01 [H] And, the production pattern fluctuation process when the production control process code is 02 [H], the production design fluctuation stop processing when the production control process code is 03 [H], and the production control process code is 04 [H ], a small hit display process when the production control process code is 05 [H], a small hit open process when the production control process code is 06 [H], and a small hit end production process when the production control process code is 06 [H] , The jackpot display processing when the production control process code is 07 [H], the round processing when the production control process code is 08 [H], and the production control process code when it is 09 [H] Round post-processing, jackpot end effect processing when the effect control process code is 0A[H], table data that can set the address value corresponding to the effect control pointer is included.

[0101] Variation pattern command reception wait processing makes it possible to determine whether or not the variation pattern designation command transmitted from the game control microcomputer 100 of the main board 11 is received. If it is determined that the variation pattern designation command is received, the production control process code is updated to 01 [H] corresponding to the production pattern variation start process, and if it is determined that the variation pattern designation command is not received, the demo Make the display controllable. The performance symbol variation start processing enables the start of the performance at the time of variation corresponding to the special symbol game. For example, corresponding to the variation pattern command transmitted from the main board 11, it is possible to select an effect pattern used for controlling the effect at the time of change and to start updating the effect process timer for measuring the effect execution time. The performance symbol change process makes it possible to control the switching timing of each performance element constituting the performance pattern, and to determine whether or not the performance execution time has elapsed based on the measured value of the performance process timer. When it is determined that the effect execution time has passed, the effect control process code is updated to 03[H] corresponding to the effect symbol variation stop process. The production design fluctuation stop processing is based on the fact that the production execution time has elapsed or the production design confirmation command has been received, and the end condition of the production at the time of fluctuation is satisfied. To enable display control of a performance result corresponding to a pattern. At this time, the production control process code is updated and various settings are performed in accordance with the display result of the variable display. For example, if the display result of the variable display is "big hit", the production control process code can be updated to 07[H], and if the display result of the variable display is "small hit", the production control process code can be changed to 04[H]. ], and the effect control process code can be updated to 00 [H] when the display result of the variable display is "losing".

[0102] The small-hit display process, the small-hit opening process, and the small-hit end production process are processes for controlling the progress of the production corresponding to the small-hit game state. The big hit display process, the mid-round process, the post-round process, and the big hit end effect process are processes for controlling the progress of the effect corresponding to the big win game state.

[0103] (Modified example of basic explanation, etc.) The pachinko game machine 1 is not limited to the configuration, functions, processing, and operations in the basic explanation and other explanations, and various modifications and applications are possible. For example, the pachinko machine 1 does not have to have all the technical features shown in the embodiment, and some of the technical features explained in the embodiment can solve at least one problem in the prior art. It may be provided with the configuration of. In the embodiment, when a matter that is a more specific concept is described, an invention of a generic concept using a matter of the same family or a similar kind, or an invention of a generic concept using a common property is regarded as the claimed invention. It may have some of the structures and characteristics described in the embodiments so as to be included and solve at least one problem in the prior art.

[0104] The pachinko game machine 1 may be a payout type game machine that pays out a predetermined number of game media as prizes based on the occurrence of winning, or an enclosed type game that encloses game media and gives points when winning occurs. machine.

[0105] What is displayed during the variable display of the special pattern is, for example, only one type of pattern such as a symbol indicating "-", and the variable display is performed by repeating the display and extinguishing of this pattern. One type of pattern may be displayed during the variable display, and this pattern may not be displayed when the variable display is stopped. For example, as a display result, the sign indicating "-" may not be displayed, and a non-display state may be set in which no special symbol is displayed.

[0106] The pachinko gaming machine 1 may have a configuration in which the probability of winning a jackpot or the rate of winning a ball is changed according to a plurality of set values. For example, in the special symbol normal processing of the special symbol process processing, by using a different jackpot determination value for each set value that is set, it may be possible to change the probability of winning the jackpot and the ball output rate. As a specific example, the setting value consists of 6 levels from 1 to 6, with 6 having the highest probability of winning the jackpot, and the smaller the value in the order of 6, 5, 4, 3, 2, 1, the higher the probability of winning the jackpot. lower. In this case, if 6 is set as the set value, the advantage for the player is the highest, and the lower the value is in the order of 6, 5, 4, 3, 2, and 1, the lower the advantage is. If the winning probability of the big win changes according to the set value, the ball payout rate may also change according to the set value. While the winning probability of the big win is constant regardless of the set value, the number of rounds in the big win game state may change according to the set value. The pachinko gaming machine 1 may be configured so as to be able to set one of a plurality of set values ​​with different degrees of advantage for the player. The set value set in the pachinko game machine 1 may be notified by transmitting a set value designation command from the main board 11 side to the effect control board 12 side. During execution of the variable display, it may be possible to execute a setting suggestion effect that suggests the setting value in the pachinko gaming machine 1 at a predetermined rate. The suggestion regarding the setting value of the pachinko gaming machine 1 is not limited to suggesting the setting value of the pachinko gaming machine 1, and may be, for example, suggesting whether or not the setting value of the pachinko gaming machine 1 has been changed. . The setting suggestion effect may suggest the degree of expectation for a big hit by an arbitrary effect, and may also be capable of suggesting a setting value of the pachinko gaming machine 1. - 特許庁

[0107] In place of part or all of the suggestion about the control of the big win game state, or together with part or all of the suggestion about the control of the big win game state, a suggestion about control of a state advantageous to the player different from the big win game state is provided. can be anything. For example, it may suggest a variable probability state to be controlled after the end of the jackpot gaming state. In addition, as the advantageous state, a suggestion may be made according to whether or not control is to be performed regarding a state in which an arbitrary game value that is advantageous to the player is awarded.

[0108] The invention relating to gaming machines is not limited to the pachinko gaming machine 1, and can be applied to slot machines as appropriate. In the slot machine, medals are inserted and a predetermined number of bets is set, a plurality of types of symbols are rotated according to the operation of the operation lever by the player, and the symbols are stopped according to the operation of the stop button by the player. It is possible to execute a game in which a predetermined number of medals are paid out to the player when the combination of stop symbols becomes a combination of specific symbols. In a slot machine, an advantageous state advantageous to a player may include one or more so-called bonuses such as big bonus, regular bonus, RT, AT, ART, and CZ.

[0109] Programs and data for realizing various controls including the progress of games and the execution of effects can be distributed and provided to computer devices included in gaming machines such as the pachinko gaming machine 1 via detachable recording media. It may be possible, or it may be possible to distribute and provide it by installing it in a storage device such as a computer device in advance. Further, it may be provided with a communication processing unit connectable to an external device on a network via a communication line or the like, and may be distributed or provided by downloading the program or data from the external device. The mode of execution of games and presentations may be executable by installing a detachable recording medium, or programs and data downloaded via a communication line etc. may be temporarily stored in an internal memory or the like. or can be directly executed using hardware resources in an external device on a network connected via a communication line, or another computer device A game or performance may be executed by exchanging data via a network.

[0110] Expressions such as "high", "low", and "different" when comparing various ratios such as the ratio of processing and data decisions, the execution ratio of effects, etc. are the ratio of "0%" or "100%" may include being For example, one decision result or execution content may include a case where there is no decision or execution at a rate of "0%", or a case where there is always a decision or execution at a rate of "100%".

[0111] (Description on feature part 01AK) FIG. 10-1 shows a configuration example of the game control microcomputer 100 with respect to the characteristic portion 01AK. Characteristic part 01AK game control microcomputer 100 includes ROM 101, RAM 102, CPU 103, external bus interface 131, clock circuit 132, unique information storage circuit 133, reset controller 134, interrupt controller 135, timer circuit 136, address decoding It comprises a circuit 137 , a free-running counter 138 and a serial communication circuit 139 . Random number circuit 104 shown in FIG. 2 includes 16-bit random number circuit 104A and 8-bit random number circuit 104B. The I / O 105 shown in FIG. 2 includes a PIP (Parallel Input Port) 105A and a POP (Parallel Output Port) 105B.

[0112] The external bus interface 131 is a bus interface that has an interface function between the external bus and the internal bus of the chip that constitutes the game control microcomputer 100, an address bus, a data bus, a direction control function for each control signal, and the like. For example, the external bus interface 131 is connected to an external memory or an external input / output device externally attached to the game control microcomputer 100, and an address signal, a data signal, or various control signals between these external devices. can be sent and received. The external bus interface 131 may include an internal resource access control circuit that controls access to internal data of the game control microcomputer 100 from an external device.

[0113] The clock circuit 132 can generate an internal system clock SCLK using an oscillation signal input to the control external clock terminal EXC. Control external clock terminal EXC, the control clock generated by the control clock generation circuit provided in the game control microcomputer 100 may be input. The internal system clock SCLK generated by the clock circuit 132 can be supplied to various circuits in the game control microcomputer 100, such as the CPU 103, 16-bit random number circuit 104A, and 8-bit random number circuit 104B. In addition, the internal system clock SCLK can be output to the outside of the game control microcomputer 100 from the system clock output terminal CLKO. Alternatively, the internal system clock SCLK is restricted so as not to be output to the outside of the game control microcomputer 100, making it difficult to identify the operating state of the game control microcomputer 100 from the outside. good.

[0114] Unique information storage circuit 133, for example, can store a plurality of types of unique information to be the internal information of the game control microcomputer 100. For example, the unique information storage circuit 133 can store the ROM code, chip individual number, and ID number as unique information different for each chip of the game control microcomputer 100. A ROM code is numerical data that can be generated from data stored in a predetermined area of ​​the ROM 101 . The individual chip number and the ID number are numbers given when the game control microcomputer 100 is manufactured, and show different numerical values ​​for each chip. It is sufficient if the individual chip number can be set so that it can be read by a user program such as a game program, while the ID number cannot be read by the user program. The unique information storage circuit 133 may be included in a predetermined area of ​​the ROM 101, or may be included in the built-in register of the game control microcomputer 100.

[0115] The reset controller 134 can control various resets that occur inside or outside the game control microcomputer 100. Resets controllable by reset controller 134 include system resets and user resets. A system reset occurs when the input signal of the external system reset terminal XSRST is at low level for a certain period of time. A user reset is caused by a predetermined factor such as occurrence of a timeout signal of the watchdog timer 134A or occurrence of travel prohibition outside the designated area (IAT). Reset controller 134 includes watchdog timer 134A. The watchdog timer 134A can set a timer value corresponding to the monitoring time, and enables a countdown that periodically updates the timer value by subtracting 1. When the timer value becomes "0" and a timeout occurs, , It is possible to output a timeout signal for resetting the game control microcomputer 100 and restarting it. Thereby, the watchdog timer 134A can reset the game control microcomputer 100 when measuring the monitoring time and measuring that the monitoring time has passed. The watchdog timer 134A can be set to enable or disable operation according to, for example, a game program.

[0116] The interrupt controller 135 can control various interrupt requests generated inside or outside the game control microcomputer 100. Interrupts controllable by interrupt controller 135 include non-maskable interrupt NMI and maskable interrupt INT. The non-maskable interrupt NMI is an interrupt that is unconditionally accepted even when the CPU 103 is in an interrupt disabled state, and is generated when the input signal of the external non-maskable interrupt terminal XNMI (also used as the input port PI6) is at low level for a certain period of time. The maskable interrupt INT is an interrupt that can permit or prohibit acceptance of an interrupt request by a setting command of the CPU 103, and multiple interrupts can be executed by priority setting. The factors of the maskable interrupt INT are that the input signal of the external maskable interrupt terminal XINT (also used as the input port PI5) is low level for a certain period of time, timeout occurs in the timer circuit 136, and the 16-bit random number circuit 104A. It is only required that some or all of the multiple types of interrupt factors can be set, including the fact that the 8-bit random number circuit 104B has stored the numerical data indicating the random number in the random number register.

[0117] The timer circuit 136 includes PTCs (Programmable Timer Counters) as timer counters corresponding to three channels PTC0 to PTC2, and enables real-time interrupt generation and time measurement. Each channel PTC0 to PTC2 of the timer circuit 136 uses a count clock generated based on the internal system clock SCLK, and detects signal changes in the count clock such as falling timing when the clock signal changes from high level to low level. It suffices if the timer value can be updated corresponding to .

[0118] The address decoding circuit 137 can decode various signals acquired from each functional block inside the game control microcomputer 100, and can output chip select signals, which are decoding signals for external devices. The chip select signal selectively activates the internal circuit of the game control microcomputer 100 or the external device serving as a peripheral device, allowing access from the CPU103. The output terminals that can be used by the address decoding circuit 137 are the parallel output signal from the POP105B, the serial transmission signal from the serial communication circuit 139, the clock output signal from the clock circuit 132, and the chip select signal generated by the address decoding circuit 137. , can be used as long as it is a function-shared terminal capable of selectively outputting .

[0119] The free-running counter 138 includes counter circuits corresponding to four channels FRC0 to FRC3, and can update the count value independently of the operation of the CPU 103. FIG. Each channel FRC0-FRC3 of the free-running counter 138 can be activated by an independent update clock, and can be set to stop or change the operation according to the game program, for example. The count value by the free-running counter 138 can be stored in a hard latch register corresponding to the latch signal transmitted from the input terminal serving as the latch signal input terminal in the PIP 105A. The count value stored in the hard latch register can be read by the CPU 103 and used when executing a game program.

[0120] The serial communication circuit 139 includes serial communication units corresponding to three channels SCU0, SCU1, and STU2, and enables communication with external devices by a serial communication method. Each channel SCU0, SCU1, STU2 of serial communication circuit 139 is capable of processing communication data, for example, in full-duplex, asynchronous, standard NRZ (Non Return to Zero) format. Channels SCU0 and SCU1 of serial communication circuit 139 are included in a first channel transmission / reception circuit capable of bidirectionally transmitting / receiving serial data to / from an external circuit. Channel STU2 of serial communication circuit 139 is included in a second channel transmission circuit capable of only transmitting serial data unidirectionally to an external circuit. For example, the channel SCU0 of the serial communication circuit 139 is used for data communication with the payout control board. In addition, the channel SCU1 of the serial communication circuit 139 is used for data communication with the effect control board 12. Instead of the channel SCU1 of the serial communication circuit 139, the channel STU2 of the serial communication circuit 139 may be used for data communication with the effect control board 12.

[0121] The 16-bit random number circuit 104A includes random number generation units corresponding to four channels RL0 to RL3. ” can be generated. The maximum value of random numbers generated by channels RL0 to RL3 in 16-bit random number circuit 104A can be set to any value within the range from "256" to "65535." By setting such a maximum value, it is possible to perform an initial setting for selecting a random number activation method so that updating of numerical data indicating random numbers is started. Alternatively, each channel RL0 ~ RL3 in the 16-bit random number circuit 104A, so that the operation mode of the game control microcomputer 100 is automatically started by shifting from the security mode to the user mode, to select the random number starting method Initial setting is possible. The 16-bit random number circuit 104A can update the random number MR1-1 for special symbol determination through the channel RL0, and can update the random number MR3-2 for selecting the losing effect through the channel RL2.

[0122] The 8-bit random number circuit 104B includes random number generation units corresponding to four channels RS0 to RS3, each of which operates independently to generate 8-bit pseudo-random number values ​​from "0" to "255". ” can be generated. The maximum value of random numbers generated by each channel RS0 to RS3 in 8-bit random number circuit 104B can be set to any value within the range from "16" to "255". By setting such a maximum value, it is possible to perform an initial setting for selecting a random number activation method so that updating of numerical data indicating random numbers is started. Alternatively, each channel RS0 ~ RS3 in the 8-bit random number circuit 104B, so that the operation mode of the game control microcomputer 100 is automatically started by shifting from the security mode to the user mode, to select the random number starting method Initialization may be possible. The 8-bit random number circuit 104B can update the random number MR3-3 for selecting the variation pattern type by the channel RS1, can update the random number MR3-4 for the variation pattern by the channel RS2, and the normal pattern variation by the channel RS3 It is possible to update the random number MR3-1 for the pattern.

[0123] PIP105A, for example, incorporates an 8-bit width input-only port, enabling various signals to be input from the outside of the game control microcomputer 100. The PIP 105A can use input terminals corresponding to input ports PI0 to PI7. Input port PI5 uses a function-shared pin that can also be used as external maskable interrupt pin XINT. Input port PI6 uses a function-shared pin that can also be used as an external non-maskable interrupt pin XNMI. The input port PI7 uses a function-shared terminal that can also be used as the receiving terminal of the channel SCU0 in the serial communication circuit 139. FIG. POP105B, for example, incorporates an 11-bit width output-only port, and enables various signals to be output to the outside of the microcomputer 100 for game control. The POP 105B can supply the address decode circuit 137 with parallel output signals corresponding to the output ports PO0-PO7 and PO10-PO12.

[0124] FIG. 10-2 shows an example of an address map in the game control microcomputer 100. FIG. In the example shown in FIG. 10-2, the area from address 0000[H] to 3FFF[H] is allocated to the ROM 101, and includes a game program area, game data area, non-game program area, non-game data area, ROM comment area, Includes program management area and other unused areas. The area of ​​addresses F000[H] to F3FF[H] is allocated to the RAM 102 and includes a game work area, a game stack area, a non-game work area, a non-game stack area, and other unused areas. The area of ​​address FE00 [H] ~ FEBF [H] is a function setting register area assigned to the built-in register of the microcomputer 100 for game control. The area of ​​address FF00 [H] ~ FFFF [H] is a function control register area assigned to the built-in register of the microcomputer 100 for game control.

[0125] In the ROM 101, a game program area can store a game program, which is a computer program relating to game progress. The game data area can store game data used by the game program. The non-game program area can store a non-game program, which is a computer program related to control and processing different from progress of the game. The non-game data area can store non-game data used by the non-game program. These programs and data stored in the ROM 101 are designed and created in advance by the manufacturer of the pachinko gaming machine 1 who is the user of the game control microcomputer 100. Therefore, the game program and the non-game program are included in the user program. Game data and non-game data are included in user data.

[0126] In the storage area of ​​the ROM 101, a game program area that can store a game program related to the progress of the game and a non-game program area related to control and processing different from the progress of the game are separately provided. Among the game program areas, the area before the non-game program area to which the rear address is assigned becomes an unused area of ​​a storage area with a number of bytes equal to or larger than the boundary byte, such as 16 bytes. As a result, it is possible to easily specify a game program area capable of storing a game program relating to the progress of a game and a non-game program area capable of storing a non-game program relating to control and processing different from the progress of the game. The design and management of programs and data stored in the ROM 101 are facilitated.

[0127] In the storage area of ​​the ROM 101, a game program area capable of storing a game program relating to progress of a game and a game data area capable of storing game data used by the game program are separately provided. Of the areas, the area before the game data area to which the rear address is assigned becomes an unused area of ​​a storage area equal to or larger than the boundary byte number, such as 16 bytes. As a result, it is possible to easily specify a game program area capable of storing a game program relating to the progress of a game and a game data area capable of storing game data used by the game program. Easier data design and management.

[0128] In the storage area of ​​the ROM 101, a non-game program area that can store non-game programs related to control and processing different from the progress of the game, and a non-game data area that can listen to non-game data used by the non-game program. Of the non-game program area and the non-game data area provided adjacently, the area behind the non-game program area to which the front address is assigned becomes the non-game data area, and the non-game data to which the rear address is assigned. The area before the area is a non-game program area. As a result, a non-game program area capable of storing a non-game program relating to control and processing different from the progress of a game and a non-game data area capable of storing non-game data used by the non-game program are provided at consecutive addresses. It can be provided in the assigned storage area to improve integration, and the design and management of the programs and data stored in the ROM 101 can be facilitated. By providing an unused area with a storage area equal to or larger than the boundary byte number between the non-game program area and the non-game data area, the non-game program area and the non-game data area can be easily identified. You may do so.

[0129] In the storage area of ​​the ROM 101, data indicating a value of "0" may be stored in all of the unused storage areas. This makes it possible to easily distinguish between the game program area and game data area, the non-game program area and non-game data area, and the unused area. Also, if unauthorized data is stored in the unused area, the data can be easily found. It should be noted that data indicating a value of "1" may be stored in all of the unused storage areas. In other words, data indicating the same value may be stored in all the unused storage areas. As a result, it is possible to easily distinguish between multiple types of storage areas, and to easily find illegal stored data.

[0130] A game work area in the RAM 102 can be used as a work area when the CPU 103 executes a game program. The game stack area can be used as a stack area when the CPU 103 executes the game program. The non-game work area can be used as a work area when the CPU 103 executes a non-game program. The non-gaming stack area can be used as a stack area when the CPU 103 executes a non-gaming program.

[0131] A game program area and a game data area provided in the storage area of ​​the ROM 101, and a game work area and a game stack area provided in the storage area of ​​the RAM 102 are included in the storage area for game control. A non-game program and non-game data area provided in the storage area of ​​the ROM 101, and a non-game work area and a non-game stack area provided in the storage area of ​​the RAM 102 are included in the storage area for non-game control.

[0132] The ROM comment area provided in the storage area of ​​the ROM 101 stores data indicating arbitrary program specific information such as program title and version. Program management area provided in the storage area of ​​ROM101, in order for CPU103 to execute the game program and non-game program, it is possible to store the setting information necessary for the internal setting of the game control microcomputer 100.

[0133] FIG. 10-3 shows a main setting example AKA01 of the address included in the function setting register area among the addresses assigned to the built-in register of the game control microcomputer 100. FIG. Function setting register area, for example, watchdog timer 134A of reset controller 134, interrupt controller 135, timer circuit 136, serial communication circuit 139, etc., for function setting using various circuits included in game control microcomputer 100 1 region.

[0134] In setting example AKA01, the set values ​​of the WDT start register at address FE1A[H] and the WDT clear registers at addresses FE1B[H] to FE1C[H] are invalid values ​​corresponding to unused. As a result, the monitoring time measurement function using the watchdog timer 134A of the reset controller 134 is set to an unused state. Since the set value of the interrupt mask register at address FE00[H] is 7E[H], the interrupt control function using the interrupt controller 135 is set to enable the maskable interrupt IR0. Since the set values ​​of the registers related to channel PTC0 of timer circuit 136 at addresses FE01[H] to FE03[H] are valid, the timer function using channel PTC0 of timer circuit 136 is enabled. be. At addresses FE04[H] to FE09[H], the set values ​​of the registers related to channels PTC1 and PTC2 of timer circuit 136 are invalid values ​​corresponding to unused, so that timer circuit 136 channels PTC1 and PTC2 are used for time measurement. Features are set to an unused state.

[0135] Since the register settings for channels SCU0 and SCU1 of serial communication circuit 139 are valid at addresses FE0A[H] to FE11[H], the serial communication function using channels SCU0 and SCU1 of serial communication circuit 139 is disabled. , is set to the enabled state. At addresses FE12[H] to FE14[H], the set value of the register related to channel STU2 of serial communication circuit 139 is an invalid value corresponding to unused, so that the serial communication function using channel STU2 of serial communication circuit 139 is disabled. are set to the unused state.

[0136] Since the set values ​​of the registers related to the input ports of PIP 105A at addresses FE2C[H] to FE2E[H] are valid values, the signal input function using each input port is set to a usable state. Since the set values ​​of the registers related to the random number circuit 104 at addresses FE36[H] to FE4A[H] include valid values ​​and invalid values, the random number generation function using the random number circuit 104 has channels corresponding to valid values. Channels that are set to the enabled state and that correspond to invalid values ​​are set to the unused state. For example, among the four channels RL0 to RL3 in the 16-bit random number circuit 104A, the channels RL0 and RL2 for which the set values ​​of the corresponding maximum value setting registers are valid are enabled for the random number generation function. , and channels RL1 and RL3 for which the set values ​​of the corresponding maximum value setting registers are invalid values, the random number generation function is set to an unused state. In addition, of the four channels RS0 to RS3 in the 8-bit random number circuit 104B, the channels RS1 to RS3 for which the set values ​​of the corresponding maximum value setting registers are valid are enabled for the random number generation function. The random number generation function of the channel RS0 for which the set value of the maximum value setting register is an invalid value is set to an unused state.

[0137] In this way, the various circuits included in the game control microcomputer 100 correspond to the set values ​​in the function setting register area, and the various functions using each circuit are set to either a usable state or an unused state. If possible. The function setting register area is not limited to various circuits included in the game control microcomputer 100, and may be the first area for any function setting.

[0138] Figure 10-4, among the addresses assigned to the built-in register of the game control microcomputer 100, shows a main setting example AKA02 of the address included in the function control register area. Function control register area, for example RAM102, random number circuit 104, PIP105A, serial communication circuit 139, etc., the second area for function control using various circuits included in the game control microcomputer 100.

[0139] In the setting example AKA02, the RWM access protect register at address FF00[H] enables function control to prohibit or permit access to RAM102, which is RWM, corresponding to the setting value 00[H] or 01[H]. to The internal information register at address FF01[H] is set to an invalid value corresponding to unused state, and function control using the corresponding circuit is in an unused state. The internal information register can store data indicating internal information such as random number update status abnormality, random number update clock frequency abnormality, system reset occurrence, WDT timeout occurrence, IAT occurrence, etc. However, in this embodiment, it is unused. not used as

[0140] Each register of addresses FF25[H] to FF28[H] is used to control the serial communication function using channel SCU0 of the serial communication circuit 139 in response to the availability of the serial communication function. It is possible to store set values ​​that are Each register of addresses FF29[H] to FF2C[H] is used to control the serial communication function using channel SCU1 of the serial communication circuit 139 in response to the availability of the serial communication function. It is possible to store the configured delay.

[0141] Each register of addresses FF60[H] to FF67[H] can store a random value that can be obtained using the soft latch random value obtaining function of the 16-bit random number circuit 104A. Of these, the RL0 soft-latch random number registers at addresses FF60[H] to FF61[H] soft-latch numeric data indicating the value of random numbers that can be generated by the channel RL0 provided in the 16-bit random number circuit 104A. can be stored when obtained by The RL1 soft-latch random number registers at addresses FF62[H] to FF63[H] acquire numeric data indicating the value of random numbers that can be generated by the channel RL1 provided in the 16-bit random number circuit 104A. can be stored if The RL2 soft-latch random number register at addresses FF64[H] to FF65[H] acquires numeric data indicating the value of a random number that can be generated by the channel RL2 provided in the 16-bit random number circuit 104A. can be stored if The RL3 soft-latch random number register at addresses FF66[H] to FF67[H] acquires numeric data indicating the value of a random number that can be generated by the channel RL3 provided in the 16-bit random number circuit 104A. can be stored if

[0142] Each register of addresses FF68[H] to FF6B[H] can store a random value that can be obtained using the soft latch random value obtaining function of the 8-bit random number circuit 104B. Of these, the RS0 soft-latch random value register at address FF68[H] is used when numeric data indicating the value of a random number that can be generated by the channel RS0 provided in the 8-bit random number circuit 104B is acquired by soft latching. can be stored in The RS1 soft-latch random value register at address FF69[H] can store a random number that can be generated by the channel RS1 provided in the 8-bit random number circuit 104B when the numeric data indicating the value is acquired by the soft latch. is. The RS2 soft-latch random value register at address FF6A[H] can store a random number that can be generated by the channel RS2 provided in the 8-bit random number circuit 104B when the numeric data indicating the value is acquired by the soft latch. is. The RS3 soft-latch random value register at address FF6B[H] can store a random number that can be generated by the channel RS3 provided in the 8-bit random number circuit 104B when the numeric data indicating the value is acquired by the soft latch. is.

[0143] The RL0 hard latch random value register number "0" at addresses FF88[H] to FF89[H] and the RL0 hard latch random value register number "1" at addresses FF98[H] to FF99[H] are 16-bit random number circuits. A random number that can be generated by channel RL0 provided in 104A can be stored when numerical data indicating the value is acquired by a hard latch. Here, the RL0 hard latch random value register includes a plurality of storage areas corresponding to a plurality of register numbers, and different hard latch conditions can be set corresponding to the storage areas of different register numbers. For example, the RL0 hard latch random value register number "0", which is the RL0 hard latch random value register corresponding to the register number "0", is in the ON state when the game ball detection signal by the first start port switch 22A is in the ON state. A hard latch condition can be met. On the other hand, the RL0 hard latch random value register number "1", which is the RL0 hard latch random value register corresponding to the register number "1", is when the game ball detection signal by the second start port switch 22B is in the ON state. , a hard latch condition can be satisfied. As a result, the RL0 hard latch random number register number "0" acquires numeric data indicating the value of the random number MR1-1 for special symbol judgment acquired in response to the occurrence of the first start winning by hard latching. can be stored if RL0 hard latch random number register number "1" is for the random number MR1-1 for special symbol judgment acquired in response to the occurrence of the second start winning, when the numerical data indicating the value is acquired by hard latch can be stored in

[0144] Each register of addresses FFF0[H] to FFF2[H], FF35[H] corresponds to the signal input function using the input port of PIP105A is in the usable state, and is input at each input port. Can store signal values. Among them, the input port number "0" register of address FFF0[H] can store the signal value input to the input port of port number "0" provided in PIP 105A. The input port number "1" register at address FFF1[H] can store the input signal value for the input port with port number "1" provided in PIP 105A. The input port number "2" register at address FFF2[H] can store the input signal value for the input port with port number "2" provided in PIP 105A. The input port number "3" register at address FF35[H] can store the input signal value for the input port with port number "3" provided in PIP 105A.

[0145] In this way, various circuits included in the game control microcomputer 100 need only be able to control their operating states in correspondence with the values ​​stored in the function control register area. In addition, various circuits included in the game control microcomputer 100 may be able to update the stored value in the function control register area corresponding to their respective operating states. The function control register area is not limited to various circuits included in the game control microcomputer 100, and may be a second area for arbitrary function control.

[0146] FIG. 10-5 is a diagram for explaining a setting example of the game random numbers shown in FIG. 3 in this embodiment. The random numbers for the game shown in FIG. 3 correspond to each application, and the random number used for determining the display result in the variable display of the special symbol and the random number used for determining the display result in the variable display of the normal symbol. , and a random number used to determine the display mode in the variable display of special symbols and normal symbols.

[0147] FIG. 10-5(A) shows a setting example AKA11 of game random numbers used for determining the display result in variable display of special symbols. The game random numbers in the setting example AKA11 include a random number MR1-1 for special symbol determination, a random number MR1-2 for winning symbols, and a random number MR1-3 as an initial value for winning symbols. For example, the random number MR1-1 for special symbol determination can be used to determine whether or not the special symbol display result is a "big hit" or a "small hit". Random numbers MR1-2 for the winning design can be used to determine the designated value of the big winning design or the designated value of the small winning design corresponding to the confirmed special design when the special design result is "big hit" or "small hit". be. The random number MR1-3, which is the initial value for the winning design, can be used when setting the initial value of the random number MR1-2.

[0148] The range of the random number MR1-1 is the range of numerical values ​​that can update the random number MR1-1, and is "0" to "65535". The magnitude of the random number MR1-1 is the total number of random numbers included in the update range of the random number MR1-1, and is "65536" corresponding to the range of "0" to "65535" of the random number MR1-1. Since the random number MR1-1 has a magnitude of "65536", the total number of random numbers included in the update range is not a prime number. The random number MR1-1 has "2" as the number of bytes of numeric data used to update its value. The method of setting the maximum value of the random number MR1-1 is based on initial setting of a register provided corresponding to the 16-bit random number circuit 104A. The random number MR1-1 is updated by hardware update using a 16-bit random number circuit 104A. The update condition for random number MR1-1 is the system clock input in 16-bit random number circuit 104A. Acquisition conditions for the random number MR1-1 include a hard latch corresponding to the starting winning and reading to the random number buffer by software corresponding to the starting winning. The cycle of random number MR1-1 is 4.369 [ms].

[0149] The range of the random numbers MR1-2 is the range of numerical values ​​in which the random numbers MR1-2 can be updated, and is "0" to "199". The magnitude of the random numbers MR1-2 is the total number of random numbers included in the update range of the random numbers MR1-2, and is "200" corresponding to the range of the random numbers MR1-2 from "0" to "199". Since the random numbers MR1-2 have a magnitude of "200", the total number of random numbers included in the update range is not a prime number. The random number MR1-2 has "1" as the number of bytes of numeric data used to update its value. The method of setting the maximum value of the random numbers MR1-2 is based on the immediate value setting of the program code. The update method for random numbers MR1-2 is software update SA1. A condition for updating the random numbers MR1-2 is a timer interrupt due to the elapse of a predetermined time. The acquisition condition of the random number MR1-2 is reading by the software corresponding to the starting prize. The cycle of random numbers MR1-2 is 800 [ms].

[0150] The range of the random numbers MR1-3 is the range of numerical values ​​in which the random numbers MR1-3 can be updated, and is the same "0" to "199" as the random numbers MR1-2. The magnitude of random numbers MR1-3 is the total number of random numbers included in the update range of random numbers MR1-3. It is the same "200" as Since the random numbers MR1-3 have a magnitude of "200", the total number of random numbers included in the update range is not a prime number. The random numbers MR1-3 have "1" as the number of bytes of numerical data used to update their values. The method of setting the maximum value of the random numbers MR1-3 is based on the immediate value setting of the program code. The update method for random numbers MR1-3 is software update SA2. The update condition of the random number MR1-3 includes a timer interrupt due to the lapse of a predetermined time, and loop processing that is standby processing in the main processing P_MAIN for game control. The condition for obtaining the random numbers MR1-3 is that the random numbers MR1-2 have completed one cycle. The period of the random numbers MR1-3 is indefinite due to the update conditions.

[0151] FIG. 10-5(B) shows a setting example AKA12 of the game random number used for determining the display result in the variable display of normal symbols. The game random numbers in the setting example AKA12 include the random number MR2-1 for the normal per symbol pattern and the random number MR2-2 as the initial value for the normal per symbol pattern. For example, the random number MR2-1 for the normal symbol per symbol can be used for determining the normal symbol designation value corresponding to the determined normal symbol as the normal symbol display result. The random number MR2-2, which is the initial value for the normal per symbol pattern, can be used when setting the initial value of the random number MR1-2.

[0152] The range of the random number MR2-1 is the range of numerical values ​​that can update the random number MR2-1, and is "0" to "198". The magnitude of the random number MR2-1 is the total number of random numbers included in the update range of the random number MR2-1, and is "199" corresponding to the range of the random number MR2-1 from "0" to "198". Since the random number MR2-1 has a magnitude of "199", the total number of random numbers included in the update range is a prime number. The random number MR2-1 has "1" as the number of bytes of numeric data used to update its value. The method of setting the maximum value of the random number MR2-1 is based on the immediate value setting of the program code. The update method for random number MR2-1 is software update SA1. A condition for updating the random number MR2-1 is a timer interrupt due to the elapse of a predetermined time. Acquisition condition of random number MR2-1 is read-out by the software corresponding to the fact that the game ball has passed through passage gate 41 which can be configured as a normal symbol operation opening. The cycle of random number MR2-1 is 796 [ms].

[0153] The range of the random number MR2-2 is the range of numerical values ​​that can update the random number MR2-2, and is the same as the random number MR2-1, from "0" to "198". The size of random number MR2-2 is the total number of random numbers included in the update range of random number MR2-2. It is the same "199" as Since the random number MR2-2 has a magnitude of "199", the total number of random numbers included in the update range is a prime number. The random number MR2-2 has "1" as the number of bytes of numeric data used to update its value. The method of setting the maximum value of the random number MR2-2 is based on the immediate value setting of the program code. The update method for random number MR2-2 is software update SA2. The update condition of the random number MR2-2 includes a timer interrupt due to the lapse of a predetermined time, and loop processing that is standby processing in the main processing P_MAIN for game control. The condition for obtaining the random number MR2-2 is that the random number MR2-1 has completed one cycle. The period of the random number MR2-2 is indefinite due to the update conditions.

[0154] FIG. 10-5(C) shows a setting example AKA13 of game random numbers used for determining the display mode in the variable display of special symbols and normal symbols. The random numbers for the game in the setting example AKA13 are the random number MR3-1 for the normal pattern variation pattern, the random number MR3-2 for selecting the losing effect, the random number MR3-3 for selecting the variation pattern type, and the random number MR3 for the variation pattern. -4 and, including. For example, the random number MR3-1 for the normal design variation pattern can be used to determine the normal design variation pattern corresponding to the variable display of the normal design. The random number MR3-2 for selecting the loss effect can be used to determine the variable display mode corresponding to the variable display of the special symbol whose special symbol display result is "loss". The random number MR3-3 for selecting the variation pattern type can be used for selecting the variation pattern type corresponding to the variable display of the special symbols. Random numbers MR3-4 for the variation pattern can be used to determine the variation pattern corresponding to the variable display of special symbols.

[0155] The range of the random number MR3-1 is the range of numerical values ​​that can update the random number MR3-1, and is "0" to "232". The magnitude of the random number MR3-1 is the total number of random numbers included in the update range of the random number MR3-1, and is "233" corresponding to the range of the random number MR3-1 from "0" to "232". Since the random number MR3-1 has a magnitude of "233", the total number of random numbers included in the update range is a prime number. For the random number MR3-1, the number of bytes of numerical data used to update its value is "1". The method of setting the maximum value of the random number MR3-1 is based on initial setting of a register provided corresponding to the 8-bit random number circuit 104B. The random number MR3-1 is updated by hardware update using the 8-bit random number circuit 104B. The update condition for random number MR3-1 is the system clock input in 8-bit random number circuit 104B. The acquisition condition of the random number MR3-1 is the start of fluctuation in the variable display of normal symbols. The cycle of random number MR3-1 is 0.249 [ms].

[0156] The range of the random number MR3-2 is the range of numerical values ​​that can update the random number MR3-2, and is "0" to "65518". The magnitude of the random number MR3-2 is the total number of random numbers included in the update range of the random number MR3-2, and is "65519" corresponding to the range of the random number MR3-2 from "0" to "65518". Since the random number MR3-2 has a magnitude of "65519", the total number of random numbers included in the update range is a prime number. The random number MR3-2 has "2" as the number of bytes of numeric data used to update its value. The method of setting the maximum value of the random number MR3-2 is based on initial setting of a register provided corresponding to the 16-bit random number circuit 104A. The random number MR3-2 is updated by hardware update using a 16-bit random number circuit 104A. The update condition for random number MR3-2 is the system clock input in 16-bit random number circuit 104A. The acquisition condition of the random number MR3-2 is, for example, readout to the random number buffer by the software corresponding to the start winning. The cycle of random number MR3-2 is 139.774 [ms].

[0157] The range of the random number MR3-3 is the range of numerical values ​​that can update the random number MR3-3, and is "0" to "240". The magnitude of the random number MR3-3 is the total number of random numbers included in the update range of the random number MR3-3, and is "241" corresponding to the range of the random number MR3-3 from "0" to "240". Since the random number MR3-3 has a magnitude of "241", the total number of random numbers included in the update range is a prime number. The random number MR3-3 has "1" as the number of bytes of numeric data used to update its value. The method of setting the maximum value of the random number MR3-3 is based on initial setting of a register provided corresponding to the 8-bit random number circuit 104B. The random number MR3-3 is updated by hardware update using the 8-bit random number circuit 104B. The update condition for random number MR3-3 is the system clock input in 8-bit random number circuit 104B. The acquisition condition of the random number MR3-3 is, for example, readout to the random number buffer by the software corresponding to the start winning. The period of random number MR3-3 is 0.257 [ms].

[0158] The range of the random numbers MR3-4 is the range of numerical values ​​in which the random numbers MR3-4 can be updated, and is "0" to "250". The magnitude of the random numbers MR3-4 is the total number of random numbers included in the update range of the random numbers MR3-4, and is "251" corresponding to the range of the random numbers MR3-4 from "0" to "250". Since the random numbers MR3-4 have a magnitude of "251", the total number of random numbers included in the update range is a prime number. The random number MR3-4 has "1" as the number of bytes of numeric data used to update its value. The method of setting the maximum value of the random numbers MR3-4 is based on initial setting of a register provided corresponding to the 8-bit random number circuit 104B. The random numbers MR3-4 are updated by hardware update using the 8-bit random number circuit 104B. The update condition for the random numbers MR3-4 is the system clock input in the 8-bit random number circuit 104B. The acquisition condition of the random number MR3-4 is, for example, readout to the random number buffer by the software corresponding to the start winning. The cycle of random numbers MR3-4 is 0.268 [ms].

[0159] The software update SA1, which is a method for updating the random numbers MR1-2 and MR2-1, can be updated so that the previous value is incremented by 1 each time the software update process is executed. At this time, if the updated value exceeds the maximum random number, it is changed to "0" as the minimum random number. If the updated value matches the initial random number value, the current random number value is set using the corresponding random number as the initial value and stored as a new initial random number value. For example, for the random number MR1-2, if the updated value matches the initial value of the random number, use the random number MR1-3, which is the initial value for the winning design, to set the current random value and set the random value to a new value. Store as the initial value of the random number. For the random number MR2-1, if the updated value matches the initial value of the random number, use the random number MR2-2, which is the initial value for the pattern per normal pattern, to set the current random value and set the random value to a new value. Store as the initial value of the random number.

[0160] The software update SA2, which is a method for updating the random numbers MR1-3 and MR2-2, can be updated so that the previous value is incremented by 1 each time the software update process is executed. At this time, if the updated value exceeds the maximum random number, it is changed to "0" as the minimum random number. In this case, unlike the software update SA1, the random number initial value is not used, so the value after the update is either the previous value plus 1 or the minimum random number "0". .

[0161] FIG. 10-6 is a diagram for explaining the random number update cycle when updating the random number using the 16-bit random number circuit 104A and the 8-bit random number circuit 104B included in the random number circuit 104. FIG. Here, the random number that can be generated by channels RL0 to RL4 provided in 16-bit random number circuit 104A is assumed to be 16-bit random number RLn. A random number that can be generated by the channels RS0 to RS4 provided in the 8-bit random number circuit 104B is assumed to be an 8-bit random number RSn. The period in which the 16-bit random number RLn that can be updated by the 16-bit random number circuit 104A makes one cycle corresponds to whether or not the maximum value of the 16-bit random number RLn is a specific maximum value expressed using a power of 2. are determined by different relations. The cycle in which the 8-bit random number RSn that can be updated by the 8-bit random number circuit 104B makes one cycle corresponds to whether or not the maximum value of the 8-bit random number RSn is a specific maximum value expressed using a power of 2. are determined by different relations.

[0162] FIG. 10-6(A) shows a 16-bit random number period setting example AKA21 in the 16-bit random number circuit 104A. The 16-bit random number period is a period in which the 16-bit random number RLn that can be updated by the 16-bit random number circuit 104A makes one cycle. In the 16-bit random number cycle setting example AKA21, if the maximum value of the 16-bit random number RLn corresponds to 2m-1 when m=9 to 16, the cycle of the 16-bit random number sequence is , the reciprocal of the count clock frequency, ie proportional to the count clock period. Then, it becomes a linear function when the value obtained by adding 1 to the maximum value, that is, the size of the 16-bit random number RLn is used as a variable. On the other hand, if the maximum value of the 16-bit random number RLn does not correspond to 2m-1 where m is any of 9 to 16, the cycle of the 16-bit random number sequence is equal to the count clock frequency. Proportional to the reciprocal, ie, 32 times the count clock period. Then, it becomes a linear function when the value obtained by adding 1 to the maximum value, that is, the size of the 16-bit random number RLn is used as a variable. In this way, the 16-bit random number RLn that can be updated by the 16-bit random number circuit 104A has a shorter random number update cycle when its maximum value is the specific maximum value than when it is other than the specific maximum value. , the speed of updating the random value increases.

[0163] FIG. 10-6(B) shows an 8-bit random number period setting example AK22 in the 8-bit random number circuit 104B. The 8-bit random number cycle is a cycle of the 8-bit random number RSn that can be updated by the 8-bit random number circuit 104B. In the 8-bit random number cycle setting example AKA22, when the maximum value of the 8-bit random number RSn corresponds to 2m-1 when m=5 to 8, the cycle of the 8-bit random number sequence is , the reciprocal of the count clock frequency, ie proportional to the count clock period. Then, it becomes a linear function when the value obtained by adding 1 to the maximum value, that is, the size of the 8-bit random number RSn is used as a variable. On the other hand, if the maximum value of the 8-bit random number RSn does not correspond to 2m-1 when m=5 to 8, the cycle of the 8-bit random number sequence is the count clock frequency. Proportional to the reciprocal, ie, 16 times the count clock period. Then, it becomes a linear function when the value obtained by adding 1 to the maximum value, that is, the size of the 8-bit random number RSn is used as a variable. In this way, when the maximum value of the 8-bit random number RSn that can be updated by the 8-bit random number circuit 104B is the specific maximum value, the random number update period is shorter than when the maximum value is other than the specific maximum value. , the speed of updating the random value increases.

[0164] FIG. 10-6(C) shows a random value comparison example AKA23 in which random values ​​that can be updated by the 16-bit random number circuit 104A and the 8-bit random number circuit 104B are compared. The 16-bit random number circuit 104A can update the random numbers corresponding to the random number MR1-1 for special symbol determination and the random number MR3-2 for selecting the losing effect. The 8-bit random number circuit 104B can update random numbers corresponding to the random number MR3-3 for selecting the variation pattern type and the random number MR3-4 for the variation pattern.

[0165] The random number MR1-1 has a maximum value of "65535" and corresponds to 2m-1 when m=16. As a result, the period of the random number MR1-1 is 4.369 [ms], and the update speed at this time is 15000 [times / ms]. The random number MR3-2 has a maximum value of "65518" and does not correspond to 2m-1 when m=9 to 16. As a result, the period of the random number MR3-2 is 139.774 [ms], and the update speed at this time is 469 [times / ms]. The random number MR3-3 has a maximum value of "240" and does not correspond to 2m-1 when m=5 to 8. As a result, the period of the random number MR3-3 is 0.257 [ms], and the update speed at this time is 938 [times / ms]. The random numbers MR3-4 have a maximum value of "250" and do not correspond to 2m-1 when m=5 to 8. As a result, the period of the random numbers MR3-4 is 0.268 [ms], and the update speed at this time is 938 [times / ms].

[0166] Thus, the game random numbers that can be updated by the 16-bit random number circuit 104A include a random number MR1-1 for special symbol determination and a random number MR3-2 for selecting a losing effect. These random number MR1-1 and random number MR3-2 each have a number of bytes of numerical data of "2", and consist of two bytes as the specific number of bytes. Since the size of random number MR1-1 is "65536" and the size of random number MR3-2 is "65519", it is assumed that the total number of random numbers included in the update range of random number MR1-1 is a specific number. , the total number of random numbers included in the update range of random numbers MR3-2 is a predetermined number smaller than the specific number. The update speed of random number MR1-1 is 15000 [times / ms], and the update speed of random number MR3-2 is 469 [times / ms], so the update speed of random number MR1-1 is faster than that of random number MR3-2. becomes faster. As a result, synchronous generation of random numbers can be suppressed, and random numbers can be appropriately updated.

[0167] In addition, the game random numbers that can be updated by the 16-bit random number circuit 104A include random numbers MR3-2 for selecting a losing effect. The game random numbers that can be updated by the 8-bit random number circuit 104B include random numbers MR3-3 for selecting the type of variation pattern and random numbers MR3-4 for variation patterns. All of these random numbers MR3-2 to MR3-4 are prime numbers in total in the update range. The update speed of the random number MR3-2 is 469 [times / ms], while the update speed of the random numbers MR3-3 and MR3-4 is 938 [times / ms]. That is, the update speeds of the random numbers MR3-3 and MR3-4 are two times, which is an integer multiple of the update speed of the random numbers MR3-2. Therefore, if the random number MR3-2 is the first random value and the random numbers MR3-3 and MR3-4 are the second random values, the update speed of the first random value is the first speed, and the second random value is This is the second rate where the update rate is an integral multiple of the first rate. The update range of the random number MR3-2 is "0" to "65518", the update range of the random number MR3-3 is "0" to "240", and the update range of the random number MR3-3 is "0" to Since it is "250", the total number of random numbers included in each update range is different between the first random number value and the second random number value, and the total number of random numbers included in both update ranges is a prime number. As a result, synchronous generation of random numbers can be suppressed, and random numbers can be appropriately updated.

[0168] A plurality of registers such as a program counter, an interrupt register, a stack pointer, an index register, a flag register, an address register, and a general-purpose register including an accumulator are provided inside the CPU 103 . Index registers, flag registers, and general-purpose registers may be provided with main registers and sub-registers. The registers included in the main register and sub-registers and the stack pointer may be provided so as to configure a plurality of register banks. The plurality of register banks may include a first register bank for inside the area that can be used when executing the game program, and a second register bank for outside the area that can be used when executing the non-gaming program. . As a result, for example, when switching between a game program and a non-game program, there is no need to save the values ​​stored in general-purpose registers to the stack area and restore them from the stack area, increasing the amount of programs and the processing load. can be prevented.

[0169] The program counter is for holding the address value of the instruction to be executed next by the CPU 103, and is also called a PC register. The stored value of the program counter is sequentially counted up each time each instruction is executed, or the address value of the branch destination by the branch instruction is set. The interrupt register can hold the upper address value of the interrupt vector table, and is also called an I register. The value stored in the I register is set corresponding to the start of power supply to the pachinko gaming machine 1.

[0170] A stack pointer can hold an address value corresponding to a game stack area or a non-game stack area, and is also called an SP register. The value stored in the stack pointer is specified by a predetermined register or instruction, including the program counter, in response to the occurrence of an interrupt, the execution of a PUSH instruction, or the execution of a subroutine call instruction such as the CALL, CALLF, or RST instruction. It is possible to specify a save destination address for saving and holding the stored value or immediate value in the registered register. Also, for the stored value of the stack pointer, it is possible to specify the read address for restoring the stored value of the saved register corresponding to the end of interrupt processing, the execution of the POP instruction, the end of subroutine processing, etc. Along with this return, the stored value is updated to a value indicating the corresponding address after reading. In addition, the value stored in the stack pointer can be set to a value stored in a register specified by a load instruction such as an LD instruction or an immediate value.

[0171] The index register includes an IX register and an IY register each having a 2-byte storage capacity capable of storing 16-bit data. The accumulator is also called the A register. Other general-purpose registers include a plurality of registers having a storage capacity of 1 byte that can store 8-bit data, such as B, C, D, E, H, and L registers. The B and C registers can be used as a paired BC register capable of storing 16-bit data. The D and E registers can be used as paired DE registers that can store 16-bit data. The H register and L register can be used as the HL register of pair registers that can store 16-bit data.

[0172] The internal register of the CPU103 can update the stored value corresponding to the operation instruction and transfer instruction executed by the CPU103, and the program address and data address or the built-in register address provided in the game control microcomputer 100 Specification, operation data and to hold transfer data.

[0173] In the game control microcomputer 100, the instruction set for causing the CPU 103 to execute the program includes transfer instructions such as load instructions, subroutine call instructions, jump instructions, arithmetic instructions including arithmetic operation instructions and logical operation instructions, input It includes output instructions and the like. Computer programs such as game programs and non-game programs executable by the CPU 103 are prepared in advance as program codes describing these various instructions and stored in the ROM 101 .

[0174] The load instruction is used to store and set data read from the memory area of ​​ROM101 or RAM102 or the internal device area in the internal register of CPU103, or to load the stored value in the internal register of CPU103 into the memory area of ​​RAM102 or the internal device area. It is a transfer instruction that can be used when writing to and storing data in and storing it in the internal register of CPU 103, the memory area of ​​RAM 102, or the built-in device area as an immediate value specified by the operand. The object to which data is transferred by the load instruction can be specified corresponding to the instruction code and the operand, and generally includes the transfer source and transfer destination of the data. However, when an immediate value is specified by an operand, the source of the data is not included.

[0175] Load instructions include regular LD instructions, special LDQ instructions, special LDF instructions, and special ICPLD instructions. A normal LD ​​instruction is also called a normal transfer instruction. A special LDQ instruction is also called a first special transfer instruction. A special LDF instruction is also called a second special transfer instruction. The special ICPLD instruction is also called a third special transfer instruction.

[0176] The LD instruction, which is a normal transfer instruction, is a normal transfer instruction that can transfer data by specifying both the upper address and the lower address when transferring data targeting the storage area of ​​ROM 101 or RAM 102 or the internal device area. . In addition, the LD instruction, which is a normal transfer instruction, uses a pair register such as the HL register as a pointer when transferring data to the storage area of ​​ROM101 or RAM102 or the internal device area. Data can be transferred by specifying an address with a pointer.

[0177] The LDQ instruction, which is the first special transfer instruction, can use the Q register, which is a special register included in the internal registers of the CPU 103, to transfer data by specifying only a lower address. A stored value indicating the upper address is set in advance in the Q register, and by combining it with the lower address specified by the LDQ instruction, it is possible to specify the transfer destination or transfer source address and transfer data.

[0178] The LDQ instruction, which is the first special transfer instruction, can transfer data with a smaller amount of program code than the LD instruction, which is the normal transfer instruction. However, in a program that frequently changes the value stored in the Q register, the amount of program code may actually increase compared to a normal LD ​​instruction. Therefore, in the game work area of ​​addresses F000[H] to F0D7[H], the function setting register area of ​​addresses FE00[H] to FEBF[H], and the function control register area of ​​addresses FF00[H] to FFFF[H] , it is only necessary to be able to transfer data using the LDQ instruction, which is the first special transfer instruction, in correspondence with processing that requires multiple transfers of various data.

[0179] The LDF instruction, which is the second special transfer instruction, can transfer data by specifying only a lower address for stored data in a specific address range. The specific address range is, for example, the range of addresses 1200[H] to 1DFF[H]. Therefore, the game data area of ​​the ROM 101 is set in advance so that it is included in this specific address range, and by combining it with the lower address specified by the LDF instruction, the transfer source address is specified and the data is transferred. can be done. Since the game data area of ​​the ROM 101 is read-only and not writable, the address of the game data area is never specified as the transfer destination address.

[0180] The LDF instruction, which is the second special transfer instruction, can transfer data with a smaller amount of program code than the LD instruction, which is the normal transfer instruction. However, since the specific address range is fixed by the specification, for example, the game data area of ​​ROM 101, such as the game data area of ​​​​highly used data is set to be included in the specific address range, and the second special transfer instruction It is sufficient if the transfer of data using the LDF instruction can be executed.

[0181] The ICPLD instruction, which is the third special transfer instruction, compares the update target value and the comparison judgment value, and if the update target value is less than the comparison judgment value, updates the update target value by adding 1. If the update target value is greater than or equal to the comparison determination value, the update target value is changed to the minimum value of "0". The value to be updated may be the value indicated by the stored data at the address pointed to by the pointer, or may be the value stored in the register. The comparison determination value may be a value stored in a register or a value indicated by an operand of the ICPLD instruction.

[0182] In this way, the ICPLD instruction, which is the third special transfer instruction, compares the update target value with the comparison judgment value, adds 1 to the update target value if the comparison result is less than the comparison judgment value, and is greater than or equal to the comparison judgment value, the update target value is changed to the minimum value.

[0183] Note that setting a stored value in an internal register of the CPU 103 using an immediate value or the like by an operand of a transfer instruction is also called a set. Reading the stored data in the game data area of ​​the ROM 101 or the game work area of ​​the RAM 102 and storing it in the internal register of the CPU 103 is also called loading. Storing the stored value in the internal register of the CPU 103 in a buffer, counter, timer, or any other storage area provided in the game work area of ​​the RAM 102 is also called store.

[0184] FIG. 10-7 is a flowchart illustrating an example of power supply start response processing P_POWER_ON. The power supply start corresponding process P_POWER_ON is included in the process that can be called from the main process P_MAIN for game control shown in FIG. is. When the CPU 103 executes the power supply start handling process P_POWER_ON, the CPU 103 disables interrupts (step AKS1), and then sets the stack pointer initial value within the area to the stack pointer (step AKS2). The initial value of the stack pointer in the area may be the address F200[H] obtained by adding 1 to the final address of the game stack area corresponding to the initial state where the save data is not stored in the game stack area.

[0185] Following step AKS2, a transfer instruction for setting an internal register of CPU 103 is used to set a connection confirmation signal ON output value (step AKS3). The connection confirmation signal ON output value is a value indicating that the connection confirmation signal is in the ON state, and may be 00[H], for example. At this time, a transfer instruction for setting the Q register contained in the internal register of CPU 103 sets the upper address of the function control register to the Q register (step AKS4). The function control register upper address is a value FF[H] indicating the upper address of the function control register area in the setting example AKA02 shown in FIG. 10-4. When the function control register upper address is set in this way, the connection confirmation signal ON output value is stored by the transfer instruction using the upper address indicated by the stored value of the Q register (step AKS5). In this case, the lower address of the transfer destination can be specified by the operand of the transfer instruction. The value stored in the Q register is set at the upper address of the function control register area by step AKS4. Therefore, by a transfer instruction for writing to the storage area of ​​the specified address, such as a special 2-byte LDQ instruction that specifies the lower address, the connection confirmation set in step AKS3 is transferred to the function control register of the specified address in the function control register area. A signal on output value can be stored. At step AKS5, the connection confirmation signal ON output value is stored in the output port number "1" register provided in the function control register area. Thereby, the connection confirmation signal transmitted from the main board 11 to the payout control board is set to the ON state.

[0186] When the connection confirmation signal is set to ON state by step AKS5, the SCU0 command register clear output value is stored by the transfer instruction using the upper address indicated by the stored value of the Q register (step AKS6). In this case, the lower address of the transfer destination can be specified by the operand of the transfer instruction. The value stored in the Q register is set at the upper address of the function control register area by step AKS4. The SCU0 command register clear output value can be specified by the transfer instruction operand. Therefore, a transfer instruction to write to the storage area at the specified address, such as a 3-byte special LDQ instruction that specifies the lower address and the SCU0 command register clear output value, will cause the SCU0 Command register clear output value can be stored. At step AKS6, the SCU0 command register clear output value is stored in the SCU0 command register provided at address FF28[H] of the function control register area in setting example AKA02 shown in FIG. 10-4. As a result, the serial communication function using channel SCU0 of serial communication circuit 139 is controlled to the initial state.

[0187] After step AKS6, the SCU1 command register clear output value is stored by a transfer instruction using the upper address indicated by the stored value of the Q register (step AKS7). In this case, the lower address of the transfer destination can be specified by the operand of the transfer instruction. The value stored in the Q register is set at the upper address of the function control register area by step AKS4. The SCU1 command register clear output value can be specified by the transfer instruction operand. Therefore, a transfer instruction to write to the storage area at the specified address, such as a 3-byte special LDQ instruction that specifies the lower address and the SCU0 command register clear output value, will cause the SCU1 Command register clear output value can be stored. In step AKS7, the SCU1 command register clear output value is stored in the SCU1 command register provided at address FF2C[H] of the function control register area in setting example AKA02 shown in FIG. 10-4. As a result, the serial communication function using channel SCU1 of serial communication circuit 139 is controlled to the initial state.

[0188] When these serial communication functions are controlled to the initial state, the upper address of the interrupt vector table is set by the transfer instruction for setting the internal register of CPU 103 (step AKS8). The interrupt vector table upper address is the upper address of the interrupt vector table provided in the game program area of ​​the ROM 101 . Interrupt vector table, for example timer interrupt processing P_PCT for game control executed corresponding to the occurrence of timer interrupt, the leading address is stored in the table position corresponding to the interrupt order. Such an interrupt vector table upper address is set in the I register by a transfer instruction for setting the internal register of CPU 103 (step AKS9).

[0189] After step AKS9, the value stored in the Q register is updated by subtracting 1 (step AKS10). The value stored in the Q register was set to the upper address of the function control register area by step AKS4. When this stored value is subtracted by 1, the upper address of the function setting register area in the setting example AKA01 shown in FIG. 10-3 is stored in the Q register. In this way, after the function control registers provided in the function control register area are set, the function setting registers provided in the function setting register area can be set. At this time, the function setting register storage value table address is set by a transfer instruction for setting the pointer (step AKS11). The function setting register storage value table address is the address of the function setting register storage value table stored in the game data area of ​​the ROM 101 . Then, the number of processes is loaded by a transfer instruction for reading the stored data at the address pointed by the pointer (step AKS12). Further, setting using the function setting register storage value table is performed by the function setting register store instruction (step AKS13). The function setting register store instruction specifies the function setting register by the stored data at the address when the address pointed by the pointer is incremented by 1, and sets the function setting register indicated by the stored data at the address when the address pointed by the pointer is incremented by 2. Any instruction may be used as long as it repeats the steps of storing a value in a specified function setting register, adding 2 to the stored value of the pointer, and subtracting 1 from the number of processes until the number of processes reaches zero. Thus, initial setting of the function setting register is enabled.

[0190] When the initial setting of the function setting register is completed in step AKS13, the access permission output value is stored in the RWM access protect register (step AKS14). The access permission output value of the RWM access protect register is set to 01[H], for example, by a transfer instruction for setting the internal register of the CPU 103 . Such an access permission output value is stored in the RWM access protect register by a transfer instruction for writing to the storage area of ​​the top address in the function setting register area. The RWM access protect register enables function control to permit access to the RWM RAM 102 in response to the setting of 01[H], which is the access permission output value. Therefore, by storing the access permission output value in the RWM access protection register by step AKS14, access to the RAM 102 is permitted in response to the start of power supply in the pachinko game machine 1.

[0191] After step AKS14, after setting the upper address of the game work area, which is the work area of ​​RAM 102, to the Q register (step AKS15), the power supply start corresponding process P_POWER_ON ends. Thus, after step AKS14 permits access to the RAM 102, the value F0[H] indicating the upper address of the game work area in the RAM 102 is set in the Q register. After step AKS15, when the LDQ instruction, which is the first special transfer instruction, is executed, the value stored in the Q register, F0[H], can be used as the high-order address of the transfer destination or transfer source without being specified by an operand. can. As a result, it is possible to reduce the program capacity of the process using the game work area in the RAM 102, thereby enhancing the marketability of the game machine.

[0192] FIG. 10-8 shows a configuration example AKT01 of the function setting register storage value table used in the power supply start handling process P_POWER_ON. In the power supply start corresponding process P_POWER_ON, for example, by using the function setting register storage table whose address is set by step AKS11, the number of processes is loaded by step AKS12, and each function setting register is stored by the function setting register store instruction of step AKS13. Value is stored. In the function setting register storage value table of the configuration example AKT01, a value 18[H] indicating the number of processes is stored at the start address 1200[H]. At step AKS12, this table data is read and loaded into the internal register of CPU103. Thereafter, the function setting register store instruction in step AKS13 sequentially reads the table data combining the lower addresses of the function setting registers and the stored values, and makes it possible to store the stored values ​​in the function setting registers corresponding to the respective lower addresses. .

[0193] In the function setting register storage value table of configuration example AKT01, the value stored in the function setting register with the smaller value indicating the lower address can be set first, and the value stored in the function setting register with the larger value indicating the lower address can be set later. The table data is structured so that As a result, in the function setting register area, the value stored in the function setting register closest to the start address is set first, and the value stored in the function setting register closest to the final address is set later. Value is set. This facilitates the design and management of the data indicating the values ​​stored in the function setting registers, and enhances the marketability of the gaming machine.

[0194] The 16-bit random number circuit 104A can start updating from the channel in which the stored value indicating the maximum random number value is set in the maximum value setting register, corresponding to the four channels RL0 to RL3. The 8-bit random number circuit 104B can start updating from the channel in which the stored value indicating the maximum random number value is set in the maximum value setting register, corresponding to the four channels RS0 to RS3. The function setting register area of ​​the setting example AKA01 shown in Figure 10-3 consists of the RL0 maximum value setting registers at addresses FE3F[H] to FE40[H] and the RL1 maximum value at addresses FE41[H] to FE42[H]. A setting register, an RL2 maximum value setting register at addresses FE43[H] to FE44[H], and an RL3 maximum value setting register at addresses FE45[H] to FE46[H] are four random number circuits in the 16-bit random number circuit 104A. They are provided corresponding to channels RL0 to RL3. This function setting register area consists of the RS0 maximum value setting register at address FE47[H], the RS1 maximum value setting register at address FE48[H], the RS2 maximum value setting register at address FE49[H], and the RS2 maximum value setting register at address FE4A. [H] RS3 maximum value setting registers are provided corresponding to the four channels RS0 to RS4 in the 8-bit random number circuit 104B. In the function setting register storage value table of the configuration example AKT01, among these maximum value setting registers, the value stored in the RL0 maximum value setting register is set first, and the value stored in the RL2 maximum value setting register is set next. The table data is configured so that the value stored in the RS1 maximum value setting register is set next, the value stored in the RS2 maximum value setting register is set next, and the RS3 maximum value setting register is set last. Therefore, the update of channel RL0 in 16-bit random number circuit 104A is initiated first, the update of channel RL2 in 16-bit random number circuit 104A is initiated next, and the update of channel RS1 in 8-bit random number circuit 104B is initiated next. The update of channel RS2 in the 8-bit random number circuit 104B is started next, and the update of channel RS3 in the 8-bit random number circuit 104B is started last. In this way, updating of random values ​​is started in order from the random value set to the maximum random value. Therefore, the uncertainty of the random values ​​increases depending on the timing of starting updating the random values, the processing load is reduced, and appropriate random values ​​are generated. Numerical updates are possible.

[0195] The power supply start corresponding process P_POWER_ON is included in the process that can be called from the main process P_MAIN for game control, which is the start-up process that is executed based on the start of the power supply in the pachinko gaming machine 1, and the function setting of the configuration example AKT01. Using the register storage value table, it is possible to set a storage value in a function setting register area as a storage area related to functions. At this time, since the random number maximum value of the random numbers updated by the 16-bit random number circuit 104A and the 8-bit random number circuit 104B can be set, the power supply start corresponding process P_POWER_ON can be executed as the maximum value setting process. The 16-bit random number circuit 104A can update the first random number value composed of 16 bits corresponding to 2 bytes as the specific number of bytes. The 8-bit random number circuit 104B can update a second random number composed of 8 bits corresponding to 1 byte as a predetermined number of bytes smaller than the specific number of bytes. Then, when executing the power supply start handling process P_POWER_ON, after setting the random number maximum value of the first random number that can be updated by the 16-bit random number circuit 104A using the function setting register storage value table of the configuration example AKT01, The maximum random number value of the second random number value that can be updated by the 8-bit random number circuit 104B is set. In this way, by setting the second random value of the predetermined number of bytes after setting the first random value of the specific number of bytes, the first random value and the second random value are stably updated and an appropriate random value is set. Numerical updates are possible.

[0196] FIG. 10-9 shows a configuration example of the RWM access protect register. The RWM access protect register is provided at address FF00[H] in the configuration example AKA02 of the function control register area shown in FIG. 10-4. The stored value of the RWM access protect register becomes a different value corresponding to access prohibition or access permission of the RAM 102 serving as RWM.

[0197] FIG. 10-9(A) shows a bit configuration example of the RWM access protect register. The RWM access protect register can store 8-bit data RAP with bit numbers from "0" to "7", and set bit data RAP0 of bit number "0" to 0[B] or 1[B]. It is possible. On the other hand, bit data from bit number "1" to bit number "7" are always set to 0[B] and indicate fixed values ​​that are never set to "1".

[0198] FIG. 10-9(B) is a diagram for explaining a usage example of the bit data RAP of the RWM access protect register. In bit data RAP, bit data RAP0 with bit number "0" is an RWM access control bit, and setting 0[B] disables access to RWM, and setting 1[B] allows access to RWM. Corresponding to the start of power supply in the pachinko gaming machine 1, the bit data RAP0 of bit number "0" is set to 0[B], which is the initial value. Thereby, corresponding to the start of the power supply in the pachinko gaming machine 1, it is possible to prohibit the access to the RAM102 to be the RWM.

[0199] FIG. 10-10 is a flowchart illustrating an example of power-off processing P_POWER_OFF. The power-off process P_POWER_OFF is included in the process that can be called from the timer interrupt process P_PCT for game control shown in FIG. 5, and can be executed in step S51 each time a timer interrupt occurs. When the power-off process P_POWER_OFF is executed, the CPU 103 sets a backup monitoring timer address by a transfer instruction for setting a pointer (step AKS31). The backup watchdog timer address is the address of the backup watchdog timer provided in the game work area of ​​the RAM 102 .

[0200] Enter the input port number "3" (step AKS32). The input port number "3" is an input port to which "3" is assigned as the port number and includes a power confirmation signal input bit. Therefore, a logical AND operation is executed using the input data of the input port number "3" and the check data corresponding to the bit position of the power supply confirmation signal input bit. At this time, it is determined whether or not the power confirmation signal input bit is "0" depending on whether or not the zero flag is ON (step AKS33). The power check signal input bit indicates that the power check signal is off when the bit value is 0[B] corresponding to "0", and the bit value is 1[B] corresponding to "1". ] indicates that the power confirmation signal is on.

[0201] If the power supply confirmation signal input bit is not "0" but "1" (step AKS33; No), the backup monitoring timer clear data is stored (step AKS34). In step AKS34, by storing clear data in the backup monitor timer, the backup monitor timer can be cleared when the power confirmation signal is in the ON state, corresponding to the fact that the power failure is not determined.

[0202] When the power supply confirmation signal input bit is "0" in response to step AKS33 (step AKS33; Yes), the time counted by the backup monitoring timer is updated by adding 1 (step AKS35). Also, the backup monitor timer is loaded by a transfer command for reading the stored data at the address pointed by the pointer (step AKS36). Then, by an operation return instruction capable of comparing the time value measured by the backup monitoring timer and the determination value corresponding to the backup determination time (step AKS37), it is confirmed that the backup monitoring timer does not indicate the backup determination time (step AKS38). This operation return instruction, when the timing value by the backup monitoring timer and the judgment value corresponding to the backup judgment time are different, corresponds to the zero flag which becomes OFF state, ends the power off processing and goes to the special symbol process processing allow the return of In this way, when the backup monitoring timer does not indicate the backup determination time (step AKS38; Yes), the power-off process ends.

[0203] When the backup monitoring timer indicates the backup determination time corresponding to step AKS38 (step AKS38; No), checksum calculation processing P_SUM_CALC is executed (step AKS39). The checksum calculation process P_SUM_CALC of step AKS39 may be the same process as the checksum calculation process included in the RWM check process P_RWM_CHK of step S2 in the main process P_MAIN for game control shown in FIG. In this way, by executing a common checksum calculation process corresponding to the start and stop of the power supply in the pachinko gaming machine 1, it is possible to determine whether or not the stored contents in the game work area of ​​the RAM 102 are held unchanged. Thus, it becomes possible to determine whether or not restoration is possible using backup data. The checksum data created by the checksum calculation process P_SUM_CALC in step AKS39 is stored in the checksum buffer by a transfer instruction for writing to the storage area of ​​the address pointed by the pointer (step AKS40).

[0204] After step AKS40, the clear data is set to the output value data by an exclusive OR operation instruction (step AKS41). This exclusive OR operation instruction performs an exclusive OR operation of the stored values ​​of a single register, so that all bit values ​​are exclusive ORed with the same value. It can be initialized to clear data of 00[H]. Such clear data is stored in the RWM access protect register by a transfer instruction for writing to the storage area of ​​the top address in the function setting register area (step AKS42). The RWM access protect register enables function control to prohibit access to the RAM 102, which is RWM, in response to the setting of 00[H], which is clear data. Therefore, by storing the clear data in the RWM access protect register by step AKS42, corresponding to the stop of the power supply in the pachinko game machine 1, access to the RAM102 is prohibited.

[0205] After step AKS42, the output port numbers "0" to "10" are cleared (step AKS43). The output port numbers from "0" to "10" are the output ports from "0" to "10", and are all the output ports in the game control microcomputer 100. Therefore, according to step AKS43, all the output ports in the game control microcomputer 100 are set to the clear state in response to the stop of the power supply in the pachinko game machine 1. At this time, a transfer instruction for setting an internal register of CPU 103 is used to set a connection confirmation signal OFF output value (step AKS44). The connection confirmation signal OFF output value is a value indicating that the connection confirmation signal is OFF, and may be 01[H], for example. Such a connection confirmation signal OFF output value is stored in the output port number "1" register by a transfer instruction for writing to the storage area of ​​the specified address in the function control register area (step AKS45). Thereby, the connection confirmation signal transmitted from the main board 11 to the payout control board is set to the OFF state.

[0206] Following step AKS45, the PTC0 interrupt disable output value is set by a transfer instruction for setting the internal register of CPU 103 (step AKS46). The PTC0 interrupt disable output value is an output value for setting the generation of a timer interrupt using the channel PTC0 of the timer circuit 136 to a disabled state. This PTC0 interrupt disabled output value is stored in the PTC0 control register by a transfer instruction for writing to the function setting register at the specified address in the function setting register area (step AKS47). The PTC0 control register can set the use state of the timer function using the channel PTC0 of the timer circuit 136 . In step AKS47, the PTC0 interrupt prohibition output value set by step AKS46 is stored in the PTC0 control register, so that the timer interrupt for game control is prohibited in response to the stoppage of the power supply in the pachinko game machine 1. set.

[0207] When the setting corresponding to the elapse of the backup determination time is performed, the system shifts to a standby state by execution of loop processing. In this standby state, the input port number "3" is input (step AKS48), and it is determined whether or not the power confirmation signal input bit is "0" (step AKS49). When the power confirmation signal input bit is "0" corresponding to the power confirmation signal being off (step AKS49; Yes), the loop processing returning to step AKS48 is continued. As a result, by maintaining the standby state until the operation is stopped due to the power failure in response to the power supply stop in the pachinko game machine 1, it is possible to prevent inconvenient changes in stored data and runaway processing by the CPU 103.

[0208] In response to step AKS49, if the power check signal input bit is "1" and not "0" (step AKS49; No), set the vector table address to the stack pointer when power is restored (step AKS50) , the interrupt return instruction terminates the power-off process P_POWER_OFF. The vector table address at the time of power failure recovery is the address of the vector table at the time of power failure recovery provided in the game program area of ​​the ROM 101 . The interrupt return instruction can use the stack pointer as a pointer to set the stored data in the storage area indicated by the address specified by the stored value of the stack pointer to the program counter. For example, the storage data in the storage area indicated by the address specified by the stack pointer storage value is set to the lower byte of the program counter, and the storage area specified by the value obtained by adding 1 to the storage value of the stack pointer Store data in the upper byte of the program counter.

[0209] FIG. 10-11 is a diagram for explaining a usage example of a data configuration related to power-off processing P_POWER_OFF. In the power-off process P_POWER_OFF, for example, step AKS38 executes branch processing using the time value of the backup monitoring timer, and step AKS40 saves the checksum data using the checksum buffer. In addition, by setting the vector table address at the time of power failure recovery at step AKS50, the operation is not stopped after the stop of the power supply in the pachinko game machine 1 is detected, and when the normal power supply is resumed, the game control Make the program for .exe executable from the beginning. Thus, the power-off process P_POWER_OFF enables control when the power supply to the pachinko gaming machine 1 is stopped using the backup monitoring timer, checksum buffer, and power-off restoration vector table.

[0210] FIG. 10-11(A) shows a configuration example AKB01 of a storage area that serves as a backup data area. The backup data area of ​​the configuration example AKB01 can store backup setting data used when backing up data stored in the game work area of ​​the RAM 102 . This backup data area includes a backup watchdog timer at address F000[H] and a checksum buffer at address F0DE[H]. Address F000[H] is the top address of the game work area, and address F0DE[H] is the last address of the game work area. By providing the backup data area at the top address and the last address of the game work area in this way, it is possible to appropriately back up the data stored in the game work area of ​​the RAM 102 .

[0211] FIG. 10-11(B) shows a configuration example AKT11 of the vector table at power failure recovery. The power-off recovery time vector table of the configuration example AKT11 can specify a return destination address from power-off processing in response to an interrupt return instruction when normal power supply is resumed. The power failure recovery vector table consists of the lower address specification data 00[H] stored at address 0016[H] in the game program area of ​​ROM 101 and the upper address stored at address 0017[H] in the game program area of ​​ROM 101. Designated data 00[H] and are included as table data. In step AKS50 of the power-off process P_POWER_OFF, data indicating address 0016[H] is set in the stack pointer as the vector table address for power-off recovery. After that, by the interrupt return instruction, the stored value of the program counter is set to 0000 [H] and the process is returned, thereby making it possible to execute the main process P_MAIN for game control from the beginning.

[0212] FIG. 10-12 is a flowchart showing an example of random number update processing P_RANDOM. Random number update process P_RANDOM is included in the process that can be called from timer interrupt process P_PCT for game control shown in FIG. It can be executed in step S56. On the other hand, the random number update process P_RANDOM is not included in the process that can be called from the main process P_MAIN for game control shown in FIG. never Therefore, the random number update process P_RANDOM is included in the first process that can be executed in response to a timer interrupt caused by the elapse of a predetermined time, but is not included in the second process that can be repeatedly executed until the first process is executed. do not have. In addition, the random number update process P_RANDOM can be called and executed in the timer interrupt process P_PCT for game control that controls the progress of the game, but the game control is executed based on the start of power supply in the pachinko game machine 1. In the main process P_MAIN for , after the start-up process such as the power supply start corresponding process P_POWER_ON in step S1, the standby process as a repeated loop process is not called and cannot be executed.

[0213] Random number update process P_RANDOM uses the internal registers of CPU 103 such as B register, DE register, and HL register to indicate the values ​​of random number MR1-2 for the winning design and random number MR2-1 for the normal design per design. Allow numeric data to be updated. The random number MR1-2 for the winning design corresponds to the special design game which is the variable display of the special design in the first special design display device 4A or the second special design display device 4B, and the final special design that results in the display of the special design. Used to determine the design. The normal symbol-per-symbol random number MR2-1 corresponds to the normal symbol game, which is a variable display of the normal symbol on the normal symbol display device 20, and is used to determine the determined normal symbol, which is the display result of the normal symbol. The random number update process P_RANDOM is common to the case of updating the random number MR1-2 for the winning symbol and the case of updating the random number MR2-1 for the normal symbol per symbol. A register can be used to update each random value.

[0214] When the CPU 103 executes the random number update process P_RANDOM, the transfer instruction for setting the HL register used as the random number pointer sets the random number counter address for the winning symbol (step AKS61). The winning symbol random number counter address is the address of the winning symbol random number counter provided in the game work area of ​​the RAM 102 . The random number pointer can store the address of the random number counter corresponding to the random number value to be updated, and the random number value to be updated can be specified by setting the stored value. In step AKS61, by storing the address of the random number counter for the winning design in the random number pointer by the LDQ instruction, the random number MR1-2 for the winning design can be set as the random number value to be updated.

[0215] Following step AKS61, the transfer instruction for setting the B register used as the random number maximum value register sets the random number maximum value corresponding to the winning design random number maximum determination value (step AKS62). The random number maximum value register can store the maximum value that the random number value to be updated can take, and the maximum random number value can be specified by setting the stored value. In step AKS62, for the random number MR1-2 for the winning design, the maximum value included in the update range of the random number MR1-2, such as C7[H] corresponding to "199", is stored in the random number maximum value register by the LD instruction. . As a result, it is possible to set the maximum random number value of the random number MR1-2 set as the random value to be updated in step AKS61.

[0216] Next to step AKS62, the transfer instruction for setting the DE register used as the initial value pointer sets the random number initial value data buffer address for the winning design (step AKS63). The winning design random number initial value data buffer address is the address of the winning design random number initial value data buffer provided in the game work area of ​​the RAM 102 . The initial value pointer can store the address of the random number initial value data buffer corresponding to the random number value to be updated, and enables acquisition and modification of the random number initial value by setting the stored value. In step AKS63, by storing the address of the random number initial value data buffer for winning symbols in the initial value pointer by the LDQ instruction, it is possible to acquire the random number initial value corresponding to the random number MR1-2, which is the random number to be updated in step AKS61. and set mutable. Subsequently, an initial value change random number update process P_RANCP is executed by a subroutine call instruction (step AKS64). The initial value change random number update process P_RANCP in step AKS64 can update random numbers MR1-2 for winning symbols, which are random numbers to be updated, and change the initial value of random numbers, based on the settings in steps AKS61 to AKS63. to

[0217] After the initial value change random number update process P_RANCP in step AKS64, by the transfer instruction for setting the HL register used as a random number pointer, normally set the random number counter address per symbol (step AKS65). The normal per-symbol random number counter address is the address of the normal per-symbol random number counter provided in the game work area of ​​the RAM 102 . In step AKS65, by storing the address of the random number counter per symbol in the random number pointer by the LDQ instruction, the random number MR2-1 for normal per symbol can be set as the random number value to be updated.

[0218] Following step AKS65, the transfer instruction for setting the B register used as the random number maximum value register sets the random number maximum value corresponding to the normal symbol per symbol random number maximum judgment value (step AKS66). In step AKS66, for the random number MR2-1 for normal per symbol, the maximum value included in the update range of the random number MR2-1, such as C6[H] corresponding to the maximum value "198", is set to the maximum random number by the LD command. Store in a register. As a result, it is possible to set the maximum random number value of the random number MR2-1 set as the random value to be updated in step AKS65.

[0219] Next to step AKS66, the transfer instruction for setting the DE register used as the initial value pointer sets the random number initial value data buffer address for the normal design per design (step AKS67). The normal per-symbol random number initial value data buffer address is the address of the normal per-symbol random number initial value data buffer provided in the game work area of ​​the RAM 102 . In step AKS67, by storing the address of the random number initial value data buffer for normal symbols per symbol in the initial value pointer by the LDQ instruction, it is possible to obtain the random number initial value for the random number MR2-1, which is the random value to be updated in step AKS65. and set mutable. Subsequently, an initial value change random number update process P_RANCP is executed by a subroutine call instruction common to step AKS64 (step AKS68). The initial value change random number update process P_RANCP of step AKS68 updates the random number MR2-1 for the normal symbol per symbol, which is the random number to be updated, and changes the initial value of the random number, based on the settings of steps AKS65 to AKS67. Make it executable.

[0220] FIG. 10-13 is a diagram for explaining a usage example of a data structure related to random number update processing P_RANDOM. In the random number update process P_RANDOM, step AKS64 of step AKS64 is performed using a winning symbol random number counter whose address is set in the random number pointer in step AKS61 and a winning symbol initial value data buffer whose address is set in the initial value pointer in step AKS63. An initial value change random number update process P_RANCP is executed. In addition, in the random number update process P_RANDOM, the random number counter for normal design with the address set to the random number pointer at step AKS65, the random number initial value data buffer for normal design per design with the address set to the initial value pointer at step AKS67, is used to execute the initial value change random number update process P_RANCP of step AKS68. The winning symbol random number counter is provided in the special symbol random number buffer area, and can store numerical data corresponding to the winning symbol random numbers MR1-2. The winning symbol random number initial value data buffer is provided in the winning symbol random number data area, and can store numerical data corresponding to the random number initial values ​​of the random numbers MR1-2. The normal per-symbol random number counter is provided in the per-symbol random number data area, and can store numerical data corresponding to the normal per-symbol random number MR2-1. The normal per symbol random number initial value data buffer is provided in the per symbol random number data area, and can store numerical data corresponding to the random number initial value of the random number MR2-1. In this way, the random number update process P_RANDOM consists of a winning symbol random number initial value data buffer provided in a winning symbol random number data area, a normal symbol per symbol random number counter, and a normal symbol per symbol random number initial value data buffer. , and the winning symbol random number counter provided in the special symbol random number buffer area, the random number MR1-2 and the random number MR2-1 can be updated by software.

[0221] FIG. 10-13(A) shows a configuration example AKB11 of the winning symbol random number data area. The winning design random number data area of ​​the configuration example AKB11 consists of the winning design random number initial value data buffer at address F050 [H], the winning design initial value random number counter at address F051 [H], and the normal design at address F052 [H]. It includes a winning symbol random number counter, a normal symbol per symbol random number initial value data buffer at address F053 [H], and a normal symbol per symbol initial value random number counter at address F054 [H]. Of these, the address F050 [H] of the random number initial value data buffer for the winning design is set to the initial value pointer by step AKS63 of the random number update process P_RANDOM, and the address F052 [H] of the random number counter for the normal design is the random number update process. It is set to the random number pointer by step AKS65 of P_RANDOM, and the address F053[H] of the random number initial value data buffer for the normal design is set to the initial value pointer by step AKS67 of the random number update process P_RANDOM. The winning symbol initial value random number counter can store numerical data corresponding to the random numbers MR1-3 that are the winning symbol initial values. The normal per-symbol initial value random number counter can store numerical data corresponding to the random number MR2-2 which is the normal per-symbol initial value for the symbol.

[0222] FIG. 10-13(B) shows a configuration example AKB12 of the random number buffer area for special symbols. The random number buffer area for special symbols of configuration example AKB12 is a random number buffer for special symbol judgment of address F07F [H], a random number counter for winning symbols of address F081 [H], and a variation pattern type selection of address F082 [H] It includes a random number buffer, a random number buffer for variation pattern at address F083[H], and a random number buffer for selection of loss effect at address F084[H]. Among them, the address F081[H] of the winning symbol random number counter is set to the random number pointer by step AKS61 of the random number update process P_RANDOM. The special symbol determination random number buffer can store numerical data corresponding to the special symbol determination random number MR1-1 obtained from the 16-bit random number circuit 104A. The variation pattern type selection random number buffer can store numerical data corresponding to the variation pattern type selection random number MR3-3 obtained from the 8-bit random number circuit 104B. The fluctuation pattern random number buffer can store numerical data corresponding to the fluctuation pattern random numbers MR3-4 obtained from the 8-bit random number circuit 104B. The random number buffer for selecting the losing effect can store numerical data corresponding to the random number MR3-2 for selecting the losing effect obtained from the 16-bit random number circuit 104A.

[0223] FIG. 10-14 is a flowchart showing an example of the initial value change random number update process P_RANCP. The initial value change random number update process P_RANCP is included in the process that can be called from the random number update process P_RANDOM shown in FIG. 10-12. It can be executed in step AKS65 to AKS67 after setting the random number MR2-1 for the normal per symbol pattern, and can be executed in step AKS68. Such an initial value change random number update process P_RANCP makes it possible to update the value of the random number MR1-2 using the numerical data corresponding to the random number MR1-2 for the winning symbol in step AKS64. In addition, the initial value change random number update process P_RANCP makes it possible to update the value of the random number MR2-1 using numerical data corresponding to the random number MR2-1 for normal per symbol in step AKS68.

[0224] When executing the initial value change random number update process P_RANCP, the CPU 103 first executes a comparison addition instruction (step AKS101). This comparison addition instruction uses the storage data at the address indicated by the value stored in the HL register, which is a random number pointer, as the update target value, and the value stored in the B register, which is the maximum random number value register, as the comparison determination value. It can be executed by a single ICPLD instruction. The value stored in the HL register, which is a random number pointer, indicates the address of the random number counter in which numerical data corresponding to the random number value to be updated is stored. The value stored in the B register, which is the maximum random number value register, indicates the maximum random number value set corresponding to the random number value to be updated. Then, if the count value of the random number counter that indicates the random value to be updated is less than the value stored in the random number maximum value register, by updating the count value of the random number counter by adding 1, the random value to be updated is incremented by 1. be done. On the other hand, if the count value of the random number counter that indicates the random value to be updated is greater than or equal to the value stored in the random number maximum value register, the random number counter is cleared and the count value is initialized to "0". The random value is changed to the minimum random value. Therefore, the comparison addition instruction in step AKS101 compares the random number value to be updated with the maximum random number value, adds 1 to the random number value to be updated if the comparison result is less than the maximum random number value, It is a single instruction including changing the random value to be updated to the minimum random value if it is greater than or equal to the value. In this way, when updating the random number value to be updated by the initial value change random number update process P_RANCP, a single comparison addition instruction is first executed. By executing such a single compare-add instruction first, it is possible to suppress the occurrence of malfunctions and appropriately update the random value.

[0225] When the comparison addition instruction is executed in step AKS101, the random number pointed to by the random number pointer is loaded by the transfer instruction for reading the stored data (step AKS102). Also, the random number pointer and the initial value pointer are exchanged (step AKS103). Then, the random number loaded in step AKS102 is compared with the random number initial value data buffer pointed to by the initial value pointer (step AKS104). It is determined whether or not the random number value compared at this time is different from the value stored in the random number initial value data buffer pointed to by the initial value pointer (step AKS105). The value stored in the DE register, which is the initial value pointer, indicates the address of the random number initial value data buffer corresponding to the random value to be updated. Therefore, in step AKS104, after executing the comparison-addition instruction of step AKS101, the random number to be updated after being updated by the comparison-addition instruction is compared with the random number initial value.

[0226] If the random value differs from the value stored in the random number initial value data buffer pointed to by the initial value pointer in response to step AKS105 (step AKS105; Yes), the initial value change random number update process P_RANCP ends. When the comparison addition instruction of step AKS101 is executed, the count value of the random number counter indicating the random number value to be updated indicates the random number value to be updated after updating. Then, when the initial value change random number update process P_RANCP ends according to the determination result of step AKS105, the value stored in the random number counter indicating the updated random number value after update is stored as it is as the current random number value. Therefore, in step AKS105, if the updated random number value after update does not match the random number initial value, the initial value change random number update process P_RANCP is terminated, and the updated random number value after update is stored as the current random number value. be able to.

[0227] If the random value is the same as the value stored in the random number initial value data buffer pointed to by the initial value pointer corresponding to step AKS105 (step AKS105; No), the initial value indicated by adding 1 to the value stored in the initial value pointer Load the random number counter (step AKS106). In the configuration example AKB11 of the random number data area for the winning design shown in FIG. H] is provided with a winning symbol initial value random number counter. In addition, in the next address F054 [H] when 1 is added to the address F053 [H] provided with the random number initial value data buffer for normal per design, the initial value random number counter for normal per design is provided. . Therefore, in step AKS106, when the stored value of the initial value pointer indicates the address of the winning symbol random number initial value data buffer, the count value of the winning symbol initial value random number counter is read. Further, in step AKS106, when the stored value of the initial value pointer indicates the address of the normal per-symbol random number initial value data buffer, the count value of the normal per-symbol initial value random number counter is read. Thus, in step AKS106, the count value of the initial value random number counter can be read as the initial value random number value.

[0228] When the initial value random number counter is loaded in step AKS106, the read count value of the initial value random number counter is stored in the random number counter indicated by the random number pointer (step AKS107). Since the stored value of the random number pointer indicates the address of the random number counter corresponding to the random number value to be updated, step AKS107 can store the count value of the initial value random number counter as the current random number value to be updated. Therefore, if the random number to be updated after the update matches the random number initial value according to the determination result of step AKS105, then in step AKS107 the initial value random number read out in step AKS106 is stored as the current random number. can be done.

[0229] Following step AKS107, after the count value of the initial value random number counter read out in step AKS106 is stored in the random number initial value data buffer pointed to by the initial value pointer (step AKS108), the initial value change random number update process P_RANCP is executed. finish. Since the stored value of the initial value pointer indicates the address of the random number initial value data buffer corresponding to the random number value to be updated, step AKS108 can store the count value of the initial value random number counter as a new random number initial value. Therefore, if the random number value to be updated after the update matches the initial random number value according to the determination result of step AKS105, the random number value for the initial value is stored as the current random number value in step AKS107, and in step AKS108, the random number read by step AKS106 is stored. The generated initial value random number can be stored as a new random number initial value. In this way, by setting a new random number initial value, the uncertainty of the random number is increased, and by storing it as the current random number, an increase in the data capacity is prevented, and the random number can be appropriately updated.

[0230] In the random number update process P_RANDOM shown in FIG. 10-12, steps AKS61 to AKS63 are performed for the random numbers MR1-2 for winning symbols, and after setting the random number to be updated, the maximum random number, and the initial random number, step AKS64 Initial value change random number update process P_RANCP is executed. The initial value change random number update process P_RANCP makes it possible to update the random number value to be updated and change the initial random number value based on the settings of the random number value to be updated, the maximum random number value, and the initial value of the random number. The initial value change random number update process P_RANCP of step AKS64 uses the random number maximum value set by step AKS62 and the random number initial value set by step AKS63 for the random number MR1-2 for the winning symbol that is the random value to be updated by step AKS61. update. In addition, the initial value change random number update process P_RANCP of step AKS64 is for the random number MR1-2 for the winning design that is the random value to be updated by step AKS61. Allows you to change the initial random number value. In this way, by updating the set random number to be updated, it is possible to appropriately update the random number.

[0231] Random number update process P_RANDOM is step AKS65~AKS67, for the random number MR2-1 for normal per symbol pattern, after setting the random number value to be updated, the maximum random number value, and the initial value of the random number, the initial value change random number update of step AKS68 Execute process P_RANCP. The initial value change random number update process P_RANCP of step AKS68 is the random number initial value set by step AKS66 or the random number initial value set by step AKS67 for the random number MR2-1 for the normal symbol per symbol set as the random value to be updated by step AKS65. Allows updates using In addition, the initial value change random number update process P_RANCP of step AKS68 is for the random number MR2-1 for the normal symbol per symbol, which is the random value to be updated by step AKS65, when the value matches the random number initial value set by step AKS67 In addition, it is possible to change the random number initial value. In this way, by updating the set random number to be updated, it is possible to appropriately update the random number. Also, by updating the set random number value to be updated or changing the initial value of the random number, it is possible to update the random number value appropriately.

[0232] The random number update process P_RANDOM can update the random number MR1-2 for the winning symbol used when determining the display result of the special symbol by the first update process consisting of steps AKS61 to AKS64, and can update the display result of the normal symbol. It is possible to update the random number MR2-1 for the normal symbol per symbol used for determination by the second update process consisting of steps AKS65 to AKS68. Then, step AKS61~AKS64 updates the random number MR1-2 for the winning design as the first random value, and then updates the random number MR2-1 for the normal design per design as the second random value by steps AKS65-AKS68. . A fixed special symbol, which is a display result of the special symbol, corresponds to the maximum value of the number of openings of the big winning opening in the jackpot game state. In addition, the fixed special symbol, which is the display result of the special symbol, is whether or not it is controlled to the probability variable state after the end of the big win game state, and the maximum value of the variable display times that can be executed in the time saving state after the end of the big win game state. may also correspond to On the other hand, the finalized normal symbol, which is the display result of the normal symbol, corresponds to the opening time and the number of openings of the second big winning opening. Therefore, the display result of the special symbol attracts a higher degree of player's attention than the display result of the normal symbol. The random number update process P_RANDOM, which is a specific update process, updates the random number MR1-2 as the first random value, and then updates the random number MR2-1 as the second random value, so that the display result attracts the player's attention. By updating the first random value used for determination before the second random value, it is possible to suppress the occurrence of defects and appropriately update the random value.

[0233] In the random number update process P_RANDOM, steps AKS61-AKS64 can update the random number MR1-2 as the first random value, and steps AKS65-AKS68 can update the random number MR2-1 as the second random value. Then, the initial value change random number update process P_RANCP of step AKS64 can be called and executed in correspondence with the random number MR1-2 as the first random value, and step AKS68 can be executed in correspondence with the random number MR2-1 as the second random value. can be executed by calling the initial value change random number update process P_RANCP. In this way, the random number update process P_RANDOM, which is a specific update process, calls the initial value change random number update process P_RANCP, which is a common update process, in correspondence with the first random value and the second random value. The random number MR1-2 as a numerical value and the random number MR2-1 as a second random value are updated, and their initial values ​​can be changed. This initial value change random number update process P_RANCP, which is a common update process, prevents an increase in program capacity, stably updates the first random number and second random number, and makes it possible to update the appropriate random number. become.

[0234] In the random number update process P_RANDOM, steps AKS61 to AKS64 for enabling update of the random numbers MR1-2 as the first random value are the first update process, and steps AKS65 to AKS65 for enabling update of the random number MR2-1 as the second random value. AKS68 is the second update process. The first update process can be executed by calling the initial value change random number update process P_RANCP in step AKS64, and the second update process can be executed by calling the initial value change random number update process P_RANCP in step AKS68. In this way, the random number update process P_RANDOM calls the initial value change random number update process P_RANCP as a common update process in the first update process and the second update process, thereby generating the random numbers MR1-2 and MR1-2 as the first random values. Update the random number MR2-1 as the second random value and make their initial values ​​changeable. This initial value change random number update process P_RANCP, which is a common update process, prevents an increase in program capacity, stably updates the first random number and second random number, and makes it possible to update the appropriate random number. become.

[0235] In the random number update process P_RANDOM, steps AKS61 to AKS64 for enabling update of the random numbers MR1-2 as the first random value are the first update process, and steps AKS65 to AKS65 for enabling update of the random number MR2-1 as the second random value. AKS68 is the second update process. Random numbers MR1-2 as the first random number and the second random Make the random number MR2-1 as a number updatable. In this way, the first random number value and the second random number value can be stably updated using the common internal storage means, and the appropriate random number value can be updated.

[0236] In the random number update process P_RANDOM, before executing the initial value change random number update process P_RANCP by step AKS64, by steps AKS61 to AKS63, the winning symbol random number counter address, the winning symbol random number maximum judgment value, the winning symbol random number initial value data Reference destination information such as a buffer address is stored in the HL register, B register, and DE register of the CPU 103, which are internal storage means. Also, in the random number update process P_RANDOM, before executing the initial value change random number update process P_RANDCP at step AKS68, at steps AKS65 to AKS67, the random number counter address for normal design per design, the random number maximum judgment value for normal design per design, normal HL register, B register, and DE register of CPU 103, which are internal storage means, are stored with reference destination information such as the random number initial value data buffer address for the design per design. The instruction used to update the random numbers MR1-2, which are the first random values ​​in step AKS61, and the instruction used to update the random numbers MR2-1, which are the second random values ​​in step AKS65, are said to set the HL register of the CPU 103. It is a common instruction in that it sets the random number counter address for the winning symbol by step AKS61, but the random number counter address for the normal symbol is set by step AKS65, so different reference destination information can be set. The instruction used to update the random numbers MR1-2, which become the first random value in step AKS62, and the instruction used to update the random numbers MR2-1, which become the second random value in step AKS66, are said to set the B register of the CPU 103. Step AKS62 sets the maximum random number value corresponding to the maximum random number judgment value for winning symbols, but step AKS66 sets the maximum random number value corresponding to the maximum judgment value for random numbers per normal symbol. Different reference destination information can be set. The instruction used to update the random numbers MR1-2, which become the first random value in step AKS63, and the instruction used to update the random numbers MR2-1, which become the second random value in step AKS67, are said to set the DE register of the CPU 103. Random number initial value data buffer address for winning design is set by step AKS63, but random number initial value data buffer address for normal design is set by step AKS67, so different reference destination information can be set. be. These steps AKS61 to AKS63 and steps AKS65 to AKS67 can set different reference destination information using common instructions such as LD and LDQ instructions, which are transfer instructions for setting the internal registers of the CPU 103. do. Then, in steps AKS64 and AKS68, an initial value change random number update process P_RANCP is called and executed by a common subroutine call instruction. In this way, in the random number update process P_RANDOM, which is the specific update process, an instruction used to update the random numbers MR1-2 as the first random value and an instruction used to update the random number MR2-1 as the second random value are , are common. Stable update of the first and second random numbers by making it possible to update the random numbers MR1-2 as the first random numbers and the random numbers MR2-1 as the second random numbers using common instructions. to update the appropriate random value.

[0237] The random number update process P_RANDOM makes it possible to update the random numbers MR1-2, which are the first random values, by steps AKS61 to AKS64, which are the first update processes, and update the random numbers MR1-2, which are the first random numbers, by steps AKS65 to AKS68, which are the second update processes. , the random number MR2-1 can be updated. Then, the initial value change random number update process P_RANCP can be called and executed in steps AKS64 and AKS68. The initial value change random number update process P_RANCP shown in Fig. 10-14 first executes a single compare-add instruction, so when updating the random numbers MR1-2 as the first random number and as the second random number In both the case of updating the random number MR2-1 of , and the case of updating, the compare-add instruction is made executable first. By executing such a comparison-addition instruction first, it is possible to suppress the occurrence of defects in the first random number value and the second random number value, and to appropriately update the random number value.

[0238] When the initial value change random number update process P_RANCP is executed in step AKS64 of the random number update process P_RANDOM, the random numbers MR1-2 for the winning design can be updated, and the random numbers MR1-3 as the initial values ​​for the winning design can be changed. Using, it is possible to change the random number initial value corresponding to the random number MR1-2 for the winning design. In addition, when the initial value change random number update process P_RANCP is executed in step AKS68 of the random number update process P_RANDOM, it is possible to update the random number MR2-1 for the normal per symbol pattern, and the initial value for the normal per symbol pattern. It is possible to change the random number initial value corresponding to the random number MR2-1 for normal per symbol using the random number MR2-2. Therefore, the random number MR1-3, which is the initial value for the winning symbol, is the random number to be updated by executing the initial value change random number update process P_RANCP at step AKS64 of the random number update process P_RANDOM. Corresponding to the random number MR1-2 for the symbol, it is the first initial value random number used when changing the random number initial value. The random number MR2-2, which is the initial value for the pattern per normal pattern, is executed by executing the initial value change random number update process P_RANCP in step AKS68 of the random number update process P_RANDOM, so that the random number to be updated becomes the second random number. Corresponding to the random number MR2-1 for the symbol per symbol, it is the random number for the second initial value used when changing the random number initial value.

[0239] FIG. 10-15 is a flowchart showing an example of the initial value determination random number update process P_TFINIT. The random number update process P_TFINIT for initial value determination is included in the process that can be called from the main process P_MAIN for game control shown in FIG. is executable. In addition, the random number update process P_TFINIT for initial value determination is included in the process that can be called from the timer interrupt process P_PCT for game control shown in FIG. It can be executed in step AKS57 upon occurrence. Therefore, the initial value determination random number update process P_TFINIT consists of a first process that can be executed in response to a timer interrupt caused by the elapse of a predetermined time, and a second process that can be repeatedly executed until the first process is executed. included. In addition, the initial value determination random number update process P_TFINIT can be called and executed in the timer interrupt process P_PCT for game control that controls the progress of the game, and is executed based on the start of power supply in the pachinko game machine 1. In the main process P_MAIN for the game control to be performed, after the start-up process such as the power supply start corresponding process P_POWER_ON of step S1, it is called by step S9 included in the standby time process as a repeated loop process and can be executed . In this way, the random number update process P_IFINIT for initial value determination is included in processes that can be executed in response to periodic timer interrupts as random number update processes for initial values, and is also included in processes that can be executed irregularly and repeatedly. Since the update cycle and update speed of the random number for initial value become indeterminate by being included, the uncertainty of the random number for initial value is increased, and it is possible to update the random number appropriately.

[0240] When the CPU 103 executes the initial value determination random number update process P_TINIT, the transfer instruction for setting the pointer sets the initial value random number counter address for the winning symbol (step AKS81). The winning design initial value random number counter address is the address F051[H] assigned to the winning design initial value random number counter in the configuration example AKB11 of the winning design random number data area shown in Fig. 10-13(A). be. When the pointer is set in this way, the count value of the winning design initial value random number counter can be updated within the update range of "0" to "199" by the comparison addition command (step AKS82). This compare-add instruction uses the stored data at the address pointed by the pointer as the update target value and the immediate value specified by the operand as the comparison determination value, and can be executed by a single ICPLD instruction, which is the third special transfer instruction. The stored value of the pointer indicates the address of the random number counter in which the numerical data corresponding to the update target initial value random number is stored. The immediate value specified by the operand indicates the maximum random number for initial value set corresponding to the random number for initial value to be updated. Then, when the count value of the random number counter indicating the random value for the update target initial value is less than the maximum value of the random number for the initial value, by updating the count value of the random number counter by adding 1, the update target initial value 1 is added to the random number. On the other hand, if the count value of the random number counter that indicates the random value for the initial value to be updated is greater than or equal to the value stored in the maximum random value register for the initial value, the random number counter is cleared and the count value is initialized to "0". By doing so, the random number for the initial value to be updated is changed to the minimum random number. Therefore, in the comparison addition instruction of step AKS82, the random number MR1-3, which is the initial value for the winning symbol, is set as the random number for the initial value to be updated, and the random number for the initial value to be updated is compared with the maximum random number for the initial value. If the comparison result is less than the maximum random number for initial value, 1 is added to the random number for initial value to be updated. If the result of comparison is greater than or equal to the maximum random number for initial value, A single instruction containing changing the number to a random minimum value. Note that the comparison-addition instruction is not limited to the ICPLD instruction, in which the address of the stored data indicating the value to be updated is specified by a pointer. Even an ICPLDQ instruction where the low address is set using the immediate value specified. In this case, the immediate value specified by the second operand of the comparison-addition instruction should be set as the comparison determination value. By updating the random number for the initial value to be updated using such a comparison addition instruction, it is possible to suppress the occurrence of defects and to appropriately update the random number.

[0241] After step AKS82, the initial value random number counter address for normal design per design is set by the transfer instruction for setting the pointer (step AKS83). The normal per-symbol initial value random number counter address is the address F054 assigned to the normal per-symbol initial value random number counter in the configuration example AKB11 of the per-symbol random number data area shown in Fig. 10-13 (A). [H]. When the pointer is set in this way, the count value of the initial value random number counter for normal symbols per symbol can be updated within the update range of "1" to "198" (step AKS84), and the initial value The determination random number update process P_TFINIT ends. The comparison-addition instruction in step AKS84 may be the same comparison-addition instruction as in step AKS82. However, since the random number MR2-2, which is the initial value for the normal symbol per symbol, is set to the random number for the initial value for the update target, the comparison addition command of step AKS84 is specified by the operand that indicates the maximum value of the random number for the initial value. The immediate value is set to a different value than the compare-add instruction of step AKS82. Therefore, in the comparison addition command of step AKS84, the random number MR2-2, which is the initial value for the normal symbol per symbol, is set as the random number for the initial value to be updated, and the random number for the initial value to be updated is the maximum random number for the initial value. If the comparison result is less than the maximum random number for initial value, 1 is added to the random number for initial value to be updated. If the result of comparison is greater than or equal to the maximum random number for initial value, the initial value to be updated It is a single instruction that includes changing the random value to the minimum random value. By updating the random number for the initial value to be updated using such a comparison-addition instruction, it is possible to suppress the occurrence of defects and appropriately update the random number.

[0242] The initial value determination random number update process P_TFINIT updates the random number MR1-3 that is the initial value for the winning symbol by steps AKS81 and AKS82 as the update of the first initial value random number. Along with this, the random number update process P_TFINIT for initial value determination updates the random number MR2-2, which is the initial value for normal per symbol pattern by steps AKS83 and AKS84, as the update of the random number value for the second initial value. The random number MR1-3, which is the initial value for the winning design, is the first random number used when changing the initial value of the random number when the random number to be updated is the random number MR1-2 for the winning design, which is the first random value. Random value for initial value. The random number MR2-2, which is the initial value for the normal per-symbol pattern, is used when changing the initial value of the random number when the random number to be updated is the random number MR2-1 for the normal per-symbol pattern, which is the second random value. is the random value for the second initial value to be set. Steps AKS81 and AKS82 of the initial value determination random number update process P_TFINIT are the first initial value update process capable of updating the first initial value random number value. Steps AKS83 and AKS84 of the initial value determination random number update process P_TFINIT are second initial value update processes capable of updating the second initial value random number value. By updating the random number for the first initial value and the random number for the second initial value, it is possible to update the random number appropriately so that the uncertainty of the first random number and the second random number can be reliably increased. Become.

[0243] In addition, the initial value determination random number update process P_TFINIT updates the random number MR1-3 that is the initial value for the winning symbol as the first random value for the initial value by steps AKS81 and AKS82, and then the second by steps AKS83 and AKS84. The random number MR2-2, which is the initial value for normal per design, is updated as the random number for initial value. Therefore, the initial value determination random number update process P_TFINIT is the first initial value update process steps AKS81, AKS82 after updating the random number MR1-3 to be the winning symbol initial value, which is the first initial value random value, Steps AKS83 and AKS84, which are the second initial value update processing, update the random number MR2-1 which is the initial value for the normal per symbol pattern, which is the random number value for the second initial value.

[0244] FIG. 10-16 is a flow chart showing an example of the starting port switch passage process P_TZU_ON. Starting port switch passage processing P_TZU_ON is included in the processing that can be called from the special symbol process processing P_TPROC shown in FIG. Yes, it can be executed in step S108 when the second start winning correspondence flag is ON in step S107. CPU103, when executing the starting opening switch passing process P_TZU_ON, by the transfer instruction for setting the pointer, sets the starting opening winning storage counter address (step AKS201). The start opening winning memory counter address is the address of the first starting opening winning memory counter or the second starting opening winning memory counter provided in the game work area of ​​RAM102. In step AKS201, different addresses in the game work area can be specified corresponding to the first starting opening winning table or the second starting opening winning table set by the special symbol process P_TPROC. For example, the upper address F0 [H] of the game work area, which is the work area, is set to the upper byte of the pointer by the transfer instruction, and is stored in the first starting winning table or the second starting winning table pointed to by the table pointer. The lower address of the starting opening winning storage counter is set to the lower byte of the pointer by a transfer command. Thereby, the value indicating the address of the first start opening winning memory counter or the second starting opening winning memory counter is stored in the internal register of the CPU 103 as a pointer. Then, by the transfer instruction for reading the storage data of the address pointed to by the pointer, load the start opening winning storage counter (step AKS202).

[0245] After step AKS202, it is determined whether or not the count value of the start opening winning memory counter is equal to or greater than the counter maximum value (step AKS203). For example, if the value loaded by step AKS202 and the counter maximum value such as "4" can be compared with a comparison return instruction, if the counter maximum value or more (step AKS203; Yes), the start switch passage processing P_TZU_ON is completed and returns to the special symbol process processing P_TPROC. On the other hand, when less than the maximum value of the counter (step AKS203; No), the count value of the start opening winning prize storage counter is updated so as to add 1 (step AKS204). In this case, the arithmetic logic operation instruction to increment the stored data of the address pointed to by the pointer, it is possible to update the count value of the first start winning prize storage counter or the second start winning prize storage counter by adding 1.

[0246] After step AKS204, the buffer address for special symbol determination is set to the transfer destination (step AKS205). The special symbol determination buffer address is the first special symbol determination buffer included in the first special symbol reservation buffer provided in the game work area of ​​RAM 102 or the second special symbol determination buffer included in the second special symbol reservation buffer. is the address of In step AKS205, the 1st starting entrance winning table or the 2nd starting entrance winning table set by the special symbol process P_TPROC, and the count value of the 1st starting entrance winning counter or the 2nd starting entrance winning counter loaded by step AKS202 , a different address in the game work area can be specified.

[0247] The 1st special symbol reservation buffer includes a 1st special symbol determination buffer, a 1st winning symbol buffer, a 1st variation pattern type selection buffer, a 1st variation pattern buffer, and a 1st loss effect selection buffer. For example, the buffer number from "0" to "4 ” are secured as multiple storage areas, such as 5 storage areas corresponding to The second special symbol reservation buffer includes a second special symbol determination buffer, a second winning symbol buffer, a second variation pattern type selection buffer, a second variation pattern buffer, and a second loss effect selection buffer. For example, the buffer number is from "0" to "4 ” are secured as multiple storage areas, such as 5 storage areas corresponding to

[0248] In step AKS205, the value corresponding to the buffer size of the first pending storage buffer or the second pending storage buffer and the count value of the starting entrance winning counter are multiplied, and the first pending storage buffer of the buffer number "1" Alternatively, the multiplied value is added to the lower address of the second reserved storage buffer. By setting such an addition value to the transfer destination pointer, it is sufficient that the special symbol determination buffer address can be set to the transfer destination.

[0249] Following step AKS205, the RL0 hard latch random value register address is set (step AKS206). The RL0 hard latch random value register address is the address of the RL0 hard latch random value register provided in the function control register area. For example, the upper address FF[H] of the function control register area is set to the upper byte of the pointer by the transfer instruction, and the RL0 hardware stored in the first start winning table or the second starting winning table pointed to by the table pointer The lower address of the latch random value register is set to the lower byte of the pointer by a transfer instruction. The first starting entry winning table stores the lower address of the RL0 hard latch random number register with buffer number "0". The second starting entry winning table stores the lower address of the RL0 hard latch random number register with buffer number "1". As a result, as the address of the RL0 hard latch random value register, different addresses are stored in the internal register of the CPU 103 as a pointer for the first start winning and the second starting winning.

[0250] After step AKS206, the RL0 hard latch random value register is loaded by a transfer instruction for reading the stored data at the address pointed by the pointer (step AK207). The stored value of the RL0 hard latch random number register acquired in this way is stored in the special symbol determination random number buffer by a transfer command for writing to the storage area of ​​the specified address in the game work area of ​​RAM 102 (step AKS208). In this way, by storing the numerical data obtained from the RL0 hard latch random number register in the random number buffer for special symbol determination, the numerical data indicating the value of the random number MR1-1 for special symbol determination is extracted. The value of the random number MR1-1 can be stored in the special symbol determination random number buffer.

[0251] After step AKS208, the RL2 soft-latch random value register is loaded by a transfer instruction for reading stored data from the storage area of ​​the specified address in the function control register area (step AKS209). The stored value of the RL2 soft latch random value register obtained at this time is stored in the random number buffer for selecting the losing effect by the transfer instruction for writing to the storage area of ​​the specified address in the game work area of ​​RAM 102 (step AKS210). In this way, by storing the numerical data obtained from the RL2 soft latch random number register in the random number buffer for selecting the losing effect, the numerical data indicating the value of the random number MR3-2 for selecting the losing effect is extracted. The value of the random number MR3-2 can be stored in the random number buffer for selecting a failure effect.

[0252] After step AKS210, the RS1 soft-latch random value register is loaded by a transfer instruction for reading stored data from the storage area of ​​the specified address in the function control register area (step AKS211). The stored value of the RS1 soft latch random value register obtained at this time is stored in the random number buffer for selecting the variation pattern type by a transfer command for writing to the storage area of ​​the specified address in the game work area of ​​RAM 102 (step AKS212). In this way, by storing the numerical data obtained from the RS1 soft-latch random number register in the random number buffer for selecting the variation pattern type, the numerical data indicating the value of the random number MR3-3 for selecting the variation pattern type is extracted. and the value of the random number MR3-3 can be stored in the random number buffer for selecting the variation pattern type.

[0253] After step AKS212, the RS2 soft-latch random value register is loaded by a transfer instruction for reading stored data from the storage area of ​​the specified address in the function control register area (step AKS213). The stored value of the RS2 soft latch random number register acquired at this time is stored in the random number buffer for variation pattern by a transfer command for writing to the storage area of ​​the specified address in the game work area of ​​RAM 102 (step AKS214). In this way, by storing the numerical data obtained from the RS2 soft-latch random number register in the random number buffer for the fluctuation pattern, the numerical data indicating the value of the random number MR3-4 for the fluctuation pattern is extracted, and the random number MR3 A value of -4 can be stored in the fluctuation pattern random number buffer.

[0254] Following step AKS214, block transfer from the random number buffer to the special symbol determination buffer is performed (step AKS215). The random number buffer is a random number buffer for special symbol judgment in which the value of random number MR1-1 is stored in step AKS208, a random number buffer for selecting a losing effect in which the value of random number MR3-2 is stored in step AKS210, and a random number MR3- ​​by step AKS212. It includes a fluctuation pattern type selection random number buffer in which the value of 3 is stored, and a fluctuation pattern random number buffer in which the values ​​of the random numbers MR3-4 are stored in step AKS214. In step AKS215, the address of the random number buffer for special symbol determination is set as the transfer source, and the value corresponding to the buffer size of the random number buffer is set as the number of transfers. It should be noted that the buffer address for special design determination to be the transfer destination is set by step AKS205. By executing a block transfer instruction based on these settings, each random number value temporarily stored in the random number buffer is stored as new pending information in the first pending storage buffer or second pending storage buffer. can be made

[0255] When the new storage information is stored in step AKS215, it is determined whether or not the winning effect condition is established (step AKS216). The prize-winning effect condition may be set in advance as a condition for enabling execution of the look-ahead effect. For example, when the specified value for start-up winning is "2", it is determined that the conditions for the winning effect are satisfied. In addition, when the starting mouth winning specified value is "1", the time saving function flag is "0" in response to not being in the time saving state, and it corresponds to not being in the small hit game state or the big hit game state. When the special symbol process code is less than 03 [H], it is determined that the winning effect condition is satisfied. When it is determined that the winning effect condition is satisfied (step AKS216; Yes), the winning effect process P_GAME_CHK is executed (step AKS217). Winning effect processing P_GAME_CHK includes a hit determination of a special symbol, selects a specified value for effect corresponding to the determination result, and enables transmission of a winning effect command.

[0256] When it is determined that the winning effect condition is not established in response to step AKS216 (step AKS216; No), or after executing the winning effect process in step AKS217, the transfer command for setting the pointer is used to execute the effect. A storage information designation command transmission table address is set (step AKS218). The performance memory information designation command transmission table address is the address of the performance memory information designation command transmission table stored in the game data area of ​​the ROM 101 . Then, by executing the command set process P_COM_SET (step AKS219), it is possible to transmit the first effect storage information designation command or the second effect storage information designation command as the start winning command. The first effect storage information designation command is a effect control command that designates the number of first pending storage indicated by the count value of the first start opening winning memory counter. The second effect storage information specification command is a effect control command that specifies the second pending storage number indicated by the count value of the second start opening winning storage counter. Thus, by the command set processing P_COM_SET of step AKS219, it is possible to transmit from the main board 11 to the effect control board 12 the effect control command to be the start winning command.

[0257] Next to step AKS219, a start opening winning buffer storage counter address is set by a transfer instruction for setting a pointer (step AKS220). The starting entry winning buffer storage counter address is the address of the starting entry winning buffer storage counter provided in the game work area of ​​the RAM 102 . In this way, the count value of the starting entrance winning buffer storage counter to which the address is set is updated so as to add 1 (step AKS221). In addition, the pointer is updated corresponding to the start opening winning buffer storage counter by the composite transfer instruction for setting the register and pointer (step AKS222). For example, by loading the count value of the starting entry winning buffer storage counter after updating by step AKS221 into the internal register of the CPU 103 and updating the stored value of the pointer by adding 1, the starting address of the starting entry winning buffer A value indicating is stored in the pointer. Furthermore, by adding the loaded count value of the starting entry winning buffer storage counter to the stored value of the pointer, it is possible to specify the storage area of ​​the buffer number to be updated in the starting entry winning prize buffer.

[0258] When the pointer is updated by step AKS222, the start opening winning designation value is loaded (step AKS223). Start entry winning specified value, corresponding to the first starting entry winning table or the second starting entry winning table set by the special symbol process P_TPROC, indicates the first starting entry winning or "1" indicating the second starting entry winning "2" can be set. In step AKS223, the transfer instruction for reading the table data from the first starting opening winning table or the second starting opening winning table makes it possible to acquire the starting opening winning designation value. The starting opening winning designation value thus acquired is stored in the starting opening winning buffer by a transfer command for writing to the storage area of ​​the address pointed by the pointer (step AKS224), and the starting opening switch passing process P_TZU_ON ends.

[0259] FIG. 10-17 is a diagram for explaining a usage example of a data configuration relating to the starting switch passage processing P_TZU_ON. In the starting opening switch passage processing P_TZU_ON, various Settings and controls are performed. And, for example, the first starting opening winning memory counter and the second starting opening winning memory counter that can update the count value by step AKS204 are provided in the special symbol control data area, and the first reserved memory number and the second reserved memory number Corresponding data can be stored. A starting winning buffer storage counter that can update the count value by AKS221 and a starting winning winning buffer that stores the specified starting winning winning value by AKS224 are provided in the starting winning winning buffer area, the first starting winning and the second starting The total number of wins and the order of occurrence can be stored. Also, in the command set process P_COM_SET of step AKS219, the first effect storage information designation command transmission table or the second effect storage information designation command transmission table whose address is set by step AKS218 is used.

[0260] Thus, the starting opening switch passage processing P_TZU_ON is the first starting opening winning table or the second starting opening winning table, the first starting opening winning storage counter provided in the special symbol control data area or the second starting opening winning storage counter , Using the starting mouth winning buffer storage counter provided in the starting mouth winning buffer area, the starting mouth winning buffer, the first performance storage information specification command transmission table or the second performance storage information specification command transmission table, variable display of special symbols Enables control over a special game that is.

[0261] FIG. 10-17 (A1) shows a configuration example AKT21 of the first starting entry winning table. The first start winning prize table of the configuration example AKT21 is the lower address of the first starting win winning storage counter, the lower address of the RL0 hard latch random number register number "0", and the first special symbol judgment buffer number "1" , the address of the first effect storage information specification command transmission table, and the start opening winning prize specification value "1".

[0262] The first starting opening winning memory counter is provided in the game work area of ​​the RAM 102, and can store data corresponding to the number of first reserved memories. RL0 hard latch random value register number "0" is the RL0 hard latch random value register with register number "0" provided in the function control register area, and channel RL0 provided in the 16-bit random number circuit 104A can be generated. For the random number MR1-1 for special symbol determination, numerical data indicating the value can be acquired by a hard latch and stored. The first special symbol determination buffer number "1" is the first special symbol determination buffer included in the first reserved storage buffer of the buffer number "1" in the first special symbol reserved buffer. The first effect memory information designation command transmission table is stored in the game data area of ​​the ROM 101 and used when transmitting the first effect memory information designation command designating the first reserved memory number. The start entry winning specified value "1" is a specified value that indicates that the first starting winning has occurred.

[0263] FIG. 10-17 (A2) shows a configuration example AKT22 of the second starting entry winning table. The second starting entry winning table of the configuration example AKT22 is the lower address of the second starting entry winning storage counter, the lower address of the RL0 hard latch random number register number "1", and the second special symbol judgment buffer number "1" , the address of the second effect storage information specification command transmission table, and the start entry winning prize specification value "2".

[0264] The second start opening winning storage counter is provided in the game work area of ​​the RAM 102, and can store data corresponding to the second reserved storage number. RL0 hard latch random value register number "1" is the RL0 hard latch random value register with register number "1" provided in the function control register area, and channel RL0 provided in the 16-bit random number circuit 104A can be generated. For the random number MR1-1 for special symbol determination, numerical data indicating the value can be acquired by a hard latch and stored. The second special symbol determination buffer number "1" is the second special symbol determination buffer included in the second reserved storage buffer of the buffer number "1" in the second special symbol reserved buffer. The second effect storage information specification command transmission table is stored in the game data area of ​​the ROM 101 and used when transmitting the second effect storage information specification command specifying the second reserved storage number. The start entry winning designation value “2” is a designated value that indicates that the second starting winning prize has occurred.

[0265] FIG. 10-17 (B1) shows a configuration example AKB21 of the special symbol control data area. The special symbol control data area of ​​the configuration example AKB21 is related to control by special symbol process processing P_TPROC, such as a special symbol game that is a variable display of special symbols, a small winning game state and a big winning game state that can be controlled based on the display result Various data can be stored. This special symbol control data area includes a special symbol process timer at address F030 [H], a hit flag at address F032 [H], a special symbol process code at address F033 [H], and the first at address F034 [H]. Starting opening winning prize storage counter, address F035 [H] jackpot pattern judgment buffer, address F036 [H] small hitting pattern judgment buffer, address F037 [H] big winning prize number counter, address F038 [H ], a large winning opening opening number counter, a large winning opening opening pattern timer at address F039 [H], a large winning opening opening pattern table pointer at address F03B [H], a demonstration display flag at address F03D [H], Address F099 [H] 2nd start entrance winning memory counter and, is included.

[0266] The special symbol process timer can store a clock value corresponding to the control time by the special symbol process P_TPROC. The special symbol process code can specify the process selected in the special symbol process P_TPROC. The first start opening winning memory counter can store a count value corresponding to the first reserved memory number. The big-hit design determination buffer can store data corresponding to the big-hit design designation value. The jackpot design designation value is a designation value corresponding to the determined special design displayed when the display result is "big hit" in the variable display of the special design, and enables the setting of the type of the jackpot game state. The small-hit design determination buffer can store data corresponding to the small-hit design designation value. The small winning symbol specified value is a specified value corresponding to the fixed special symbol displayed when the display result is "small winning" in the variable display of the special symbols, and the liquor in the small winning game state can be set. The big winning hole winning number counter can store a count value corresponding to the number of game balls that have passed through the big winning hole formed by the special variable winning ball device 50 . The large winning opening opening number counter can store a count value corresponding to the number of openings of the large winning opening in the small winning game state or the big winning game state. The large winning opening opening pattern timer can store a time value corresponding to the remaining time for controlling the large winning opening to be opened in the small winning game state or the big winning game state. The large winning opening opening pattern table pointer can specify the storage address of the large winning opening opening pattern table in which the opening time of the large winning opening is set. The demonstration display flag can store a flag value corresponding to an ON state or an OFF state corresponding to whether or not the demonstration display is being executed. The second start opening winning memory counter can store a count value corresponding to the second reserved memory number.

[0267] FIG. 10-17 (B2) shows a configuration example AKB22 of the starting entry winning buffer area. The starting opening winning buffer area of ​​the configuration example AKB22 can store various data related to the first starting winning and second starting winning that occurs when the game ball enters the first starting winning opening and the second starting winning opening. This starting entry winning buffer area includes a starting entry winning buffer storage counter of address F0BA[H] and starting entry winning buffer numbers "0" to "8" of addresses F0BB [H] to F0C3 [H]. there is

[0268] The starting entry winning buffer storage counter can store a count value corresponding to the number of effective starting entry winning designation values ​​stored in the starting entry winning buffer area. Therefore, the count value of the starting opening winning buffer storage counter indicates the total number of times of the first starting winning and the second starting winning. The starting winning buffer numbers "0" to "8" are starting winning buffers to which the buffer numbers "0" to "8" are assigned, and the starting winning buffers in the order in which the first starting winning and the second starting winning have occurred. Winning designation values ​​can be stored. As a result, the information stored in the start winning buffer indicates the order in which the first start winning and the second starting winning are generated.

[0269] FIG. 10-17(C1) shows a configuration example AKT23 of the first effect storage information designation command transmission table. The first effect storage information designation command transmission table of the configuration example AKT23 is configured to include table data indicating the first effect storage information designation command upper byte and the first start winning prize memory counter reference designation value. there is The command set process P_COM_SET of step AKS219 enables transmission of the first effect storage information designation command when using the first effect storage information designation command transmission table. The first effect storage information specification command can set the lower byte corresponding to the count value of the first start opening winning storage counter. By transmitting such a first effect storage information specifying command, it is possible to notify the effect control board 12 of the first reserved storage number.

[0270] FIG. 10-17 (C2) shows a configuration example AKT24 of the second effect storage information designation command transmission table. The second effect storage information specification command transmission table of the configuration example AKT24 is configured to include table data indicating the second effect storage information specification command upper byte and the second start winning prize storage counter reference specification value. there is The command set process P_COM_SET of step AKS219 enables transmission of the second effect storage information designation command when the second effect storage information designation command transmission table is used. The second effect storage information specification command can set the lower byte corresponding to the count value of the second start opening winning storage counter. By transmitting such a second effect storage information designation command, it is possible to notify the effect control board 12 of the second reserved storage number.

[0271] The start switch passage processing P_TZU_ON shown in Fig. 10-16 stores the value stored in the RL2 soft latch random number register loaded in step AKS209 in the random number buffer for selecting a failure effect in step AKS210. It becomes possible to extract numerical data indicating the value of the random number MR3-2 of . In addition, the starting port switch passage processing P_TZU_ON stores the value stored in the RS1 soft latch random number register loaded in step AKS211 in the fluctuation pattern type selection random number buffer in step AKS212. For 3, numerical data indicating its value can be extracted. Furthermore, in the starting gate switch passing process P_TZU_ON, t...

Claims

[Claim 1] A gaming machine that can be controlled to a favorable state for a player by variably displaying special identification information based on the establishment of a starting condition, A display means; A light emitting means; A light emission control means, The display means includes: In a first period after the game ends, a background display is displayed; displaying a demonstration display during a second post-game period after the first post-game period has ended; displaying the background display during a first period after a power outage occurs and the power is turned on; displaying the demonstration display during a second period after power-on after the first period after power-on has ended; A variable display of a performance identification information corresponding to the variable display of the special identification information can be displayed, When the start condition is satisfied, a variable display of the effect identification information is displayed so that a transparency of the effect identification information changes from a first value to a second value higher than the first value; when the start condition is satisfied while the demonstration display is being displayed, before the transparency of the effect identification information becomes the second value, a display is switched from the demonstration display to a variable display of the effect identification information, The light emission control means during a first period after the end of the game, controlling the light emitting means using a background display luminance data table corresponding to the background display; during a second period after the end of the game, controlling the light emitting means using a demonstration display luminance data table corresponding to the demonstration display; during a first period after power-on, the light-emitting means is controlled using the background display luminance data table; during a second period after the power is turned on, the front light emitting means is controlled using the demonstration display luminance data table; when the start condition is established when the first period after the end of the game is changed to a second period after the end of the game and the demonstration display is being displayed by the display means, before the display means switches the display from the demonstration display to a display corresponding to the variable display of the performance identification information, the display means switches from the demonstration display luminance data table to a luminance data table corresponding to the variable display of the performance identification information, and controls the light emitting means; before the first period after power-on changes to the second period after power-on and the display means switches from the background display to the demonstration display, switching from the background display luminance data table to the demonstration display luminance data table to control the light emitting means; the demonstration display includes a company name display scene, a title name display scene, and a warning display scene; the company name display scene is a scene in which a character display of a company name related to the gaming machine is displayed as an animation, the title name display scene is a scene in which the title name of the gaming machine is displayed in characters as an animation, The warning display scene is a scene in which a character display for warning a player when playing the gaming machine is displayed in the form of an animation, the animated display of the text display of the company name related to the gaming machine is more emphasized than the animated display of the text display of the caution when playing the gaming machine, The animation display of the character display of the title name of the gaming machine is emphasized more than the animation display of the character display of the attention calling for playing the gaming machine. A gaming machine characterized by:

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