Electro-optical device and electronic apparatus

Abstract

To provide electro-optical device and an electronic apparatus that can increase the quality of display.SOLUTION: A liquid crystal device 100 includes: a capacitive element 26; a first insulation film 221 covering the capacitive element 26, the first insulation film having a recessed part 221r as a recessed part on which the shape of the capacitive element 26 is reflected; and a scan line 24 serving as a light shielding film provided along the recessed part 221r. The recessed part 221r has a curved bottom surface.SELECTED DRAWING: Figure 7

Description

Technical Field

[0006] , ,

[0001] The present invention relates to an electro-optical device and an electronic device.

Background Art

[0002] In electronic devices such as projectors, electro-optical devices such as liquid crystal display devices capable of changing optical characteristics for each pixel are used.

[0003] The electro-optical device described in Patent Document 1 includes an element substrate, a counter substrate, and a liquid crystal layer sandwiched between these substrates. The element substrate includes a base material, various wirings having light-shielding properties such as scanning lines and data lines, a capacitor element, a transistor, and a pixel electrode.

[0004] In Patent Document 1, the capacitor element is provided so as to cover the upper surface and the side surface of a convex portion protruding from the surface of the base material. By providing the capacitor element so as to cover the upper surface and the side surface of the convex portion, an increase in the capacitance of the capacitor element can be achieved. Further, the capacitor element, the scanning line, the transistor, and the data line are arranged on the base material in this order from the base material side. Light traveling from the base material to the transistor is blocked by the scanning line provided between the base material and the transistor.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] The scanning lines are provided on an interlayer insulating layer that fills the recesses between the protrusions on which the capacitive elements are located. The interlayer insulating layer has depressions that reflect the depressions between the protrusions on which the capacitive elements are located. These depressions in the interlayer insulating layer cause problems such as seams, cracks, or uneven film formation in the scanning lines provided on these depressions, which can lead to scanning line defects such as disconnection, increased resistance, or reduced light shielding performance. [Means for solving the problem]

[0007] An electro-optical apparatus according to one aspect of the present invention comprises a capacitive element, an insulating film covering the capacitive element and having a recess that reflects the shape of the capacitive element, and a light-shielding film provided along the recess, wherein the recess has a curved bottom surface.

[0008] An electronic device according to one aspect of the present invention comprises the aforementioned electro-optical device and a control unit that controls the operation of the electro-optical device. [Brief explanation of the drawing]

[0009] [Figure 1] A plan view of a liquid crystal device according to an embodiment. [Figure 2] A cross-sectional view of the liquid crystal device shown in Figure 1 along line II-II. [Figure 3] Equivalent circuit diagram showing the electrical configuration of the element substrate in Figure 1. [Figure 4] A plan view showing a portion of the element substrate in Figure 2. [Figure 5] Figure 4 shows a cross-sectional view of the element substrate along the VV line. [Figure 6] Figure 4 shows a cross-sectional view of the element substrate along the VI-VI line. [Figure 7] An enlarged cross-sectional view corresponding to area VII enclosed by the dashed line in Figure 5. [Figure 8] Plan view corresponding to line VIII-VIII in Figures 5 and 6. [Figure 9] Plan view corresponding to the IX-IX line in Figures 5 and 6. [Figure 10] An enlarged plan view corresponding to area X in Figure 9. [Figure 11] Plan view corresponding to line XI-XI in FIGS. 5 and 6. [Figure 12] Plan view corresponding to line XII-XII in FIGS. 5 and 6. [Figure 13] Plan view corresponding to line XIII-XIII in FIGS. 5 and 6. [Figure 14] Flowchart showing the process flow of manufacturing a part of an element substrate. [Figure 15] Diagram for explaining the recess forming process. [Figure 16] Diagram for explaining the capacitor element forming process. [Figure 17] Diagram for explaining the first insulating film forming process. [Figure 18] Diagram for explaining the first insulating film forming process. [Figure 19] Diagram for explaining the scanning line forming process. [Figure 20] Diagram for explaining the scanning line forming process according to a comparative example. [Figure 21] Diagram for explaining the second insulating film forming process and the semiconductor film forming process. [Figure 22] Schematic diagram showing a projector which is an example of an electronic device.

Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing, for the purpose of making each member recognizable, the scale of each member is made different from the actual one. For the sake of convenience in explanation, the X-axis, Y-axis, and Z-axis that are perpendicular to each other will be used for explanation as appropriate. Also, one direction along the X-axis is denoted as the X1 direction, and the direction opposite to the X1 direction is denoted as the X2 direction. Similarly, one direction along the Y-axis is denoted as the Y1 direction, and the direction opposite to the Y1 direction is denoted as the Y2 direction. One direction along the Z-axis is denoted as the Z1 direction, and the direction opposite to the Z1 direction is denoted as the Z2 direction. In the following explanation, the X direction as the second direction is either the X1 direction or the X2 direction. The Y direction as the first direction is either the Y1 direction or the Y2 direction. The Z direction is either the Z1 direction or the Z2 direction.

[0011] Also, when the plane including the X-axis and the Y-axis is defined as the XY plane, looking at the XY plane in the Z1 direction or the Z2 direction is referred to as a plan view or planar, and looking at a cross-section including the Z-axis from a direction perpendicular to the cross-section is referred to as a cross-sectional view or cross-sectional. Furthermore, in the following explanation, descriptions such as "on the substrate" for example, when referring to the substrate, mean any of the cases where it is disposed in contact with the substrate, where it is disposed on the substrate via other structural elements or the like, or where a part is disposed in contact with the substrate and a part is disposed via other elements.

[0012] 1. Liquid Crystal Device 1A. Basic Configuration FIG. 1 is a plan view of a liquid crystal device according to an embodiment. FIG. 2 is a diagram schematically showing a cross-section taken along line II-II of the liquid crystal device shown in FIG. 1. In FIG. 1, the illustration of the counter substrate 3 is omitted.

[0013] The liquid crystal device 100 as an electro-optical device shown in FIGS. 1 and 2 is a transmissive liquid crystal device of an active matrix driving method. As shown in FIG. 2, the liquid crystal device 100 includes a device substrate 2, a counter substrate 3, a seal member 4, and a liquid crystal layer 5 as an electro-optical layer. The device substrate 2, the liquid crystal layer 5, and the counter substrate 3 are arranged in the Z1 direction in this order. Also, as shown in FIG. 1, the shape of the liquid crystal device 100 in plan view is a rectangle, but it may also be circular.

[0014] As shown in Figure 1, the liquid crystal display device 100 has a display area A10 for displaying an image and a peripheral area A20 located outside the display area A10 in a plan view. The display area A10 is provided with a plurality of pixels P arranged in a matrix. The peripheral area A20 is the area that surrounds the display area A10 in a plan view.

[0015] The peripheral region A20 of the element substrate 2 contains a scan line drive circuit 11, a data line drive circuit 12, and a plurality of external terminals 13. Some of the plurality of external terminals 13 are connected to the scan line drive circuit 11 or the data line drive circuit 12 via wiring. In addition, the plurality of external terminals 13 include terminals to which a common potential is applied.

[0016] The element substrate 2 is provided with a TFT (Thin Film Transistor) which will be described later as a transistor. As shown in Figure 2, the element substrate 2 has a first substrate 21 as a light-transmitting insulating material, a light-transmitting laminate 22, a light-transmitting pixel electrode 25, and a light-transmitting first alignment film 29. Light-transmitting means transmittance to visible light, and preferably the transmittance of visible light is 50% or more.

[0017] The first substrate 21, the laminate 22, the pixel electrode 25, and the first alignment film 29 are stacked in this order in the Z1 direction. The first substrate 21 is a flat plate that is translucent and insulating. The first substrate 21 is, for example, a glass substrate or a quartz substrate. The laminate 22 comprises a plurality of light-transmitting insulating films and various wirings arranged between the plurality of insulating films. The first substrate 21 and the laminate 22 will be described later.

[0018] The pixel electrode 25 is transparent and conductive. The pixel electrode 25 is used to apply an electric field to the liquid crystal layer 5. The material of the pixel electrode 25 is a transparent conductive material such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and FTO (Fluorine-doped tin oxide). The first alignment film 29 is transparent and insulating. The first alignment film 29 aligns the liquid crystal molecules in the liquid crystal layer 5. The first alignment film 29 is arranged to cover a plurality of pixel electrodes 25. The material of the first alignment film 29 is, for example, polyimide and silicon dioxide.

[0019] The opposing substrate 3 is positioned opposite the element substrate 2. The opposing substrate 3 has a light-transmitting second base material 31, a light-transmitting inorganic insulating film 32, a light-transmitting common electrode 33, and a light-transmitting second orientation film 34. Although not shown in the figures, the opposing substrate 3 also has a light-shielding border that surrounds the display area A10 in a plan view. Light-shielding refers to light-shielding properties with respect to visible light, preferably with a visible light transmittance of less than 50%, and more preferably 10% or less.

[0020] The second substrate 31, the inorganic insulating film 32, the common electrode 33, and the second orientation film 34 are stacked in this order in the Z2 direction. The second substrate 31 is a flat plate that is translucent and insulating. The second substrate 31 is, for example, a glass substrate or a quartz substrate. The inorganic insulating film 32 is transparent and insulating. The inorganic insulating film 32 is formed from an inorganic material containing silicon, such as silicon oxide.

[0021] The common electrode 33 is positioned opposite to the multiple pixel electrodes 25 via the liquid crystal layer 5. The common electrode 33 is transparent and conductive. A common potential is applied to the common electrode 33. The material of the common electrode 33 is, for example, a transparent conductive material such as ITO, IZO, and FTO. The second alignment film 34 is transparent and insulating. The second alignment film 34 aligns the liquid crystal molecules in the liquid crystal layer 5. The material of the second alignment film 34 is, for example, polyimide and silicon dioxide.

[0022] The sealing member 4 is placed between the element substrate 2 and the opposing substrate 3. The sealing member 4 is formed using an adhesive containing various curable resins, such as epoxy resin. The sealing member 4 may also include a gap material made of an inorganic material such as glass.

[0023] The liquid crystal layer 5 is located within a region enclosed by the element substrate 2, the opposing substrate 3, and the sealing member 4. The liquid crystal layer 5 contains liquid crystal molecules having positive or negative dielectric anisotropy. The orientation of the liquid crystal molecules changes in response to the voltage applied to the liquid crystal layer 5, and the optical properties of the liquid crystal layer 5 change accordingly.

[0024] The light LL is incident on the liquid crystal device 100 from the opposing substrate 3 and is modulated according to the image signal as it is emitted from the element substrate 2. As a result, the liquid crystal device 100 displays an image. Alternatively, the liquid crystal device 100 may be configured to display an image by having the light LL incident from the element substrate 2 side and emitting the modulated light from the opposing substrate 3.

[0025] The liquid crystal device 100 is applied, for example, to a projection-type projector, as described later. In this case, the liquid crystal device 100 functions as a light bulb.

[0026] 1B. Electrical configuration of the element substrate 2 Figure 3 is an equivalent circuit diagram showing the electrical configuration of the element substrate shown in Figure 1. The laminated structure 22 of the element substrate 2 shown in Figure 2 is provided with multiple transistors 23, n scan lines 241, m data lines 242, and n constant potential lines 243, as shown in Figure 3. n and m are integers of 2 or more.

[0027] Transistors 23 are arranged to correspond to each intersection of n scan lines 241 and m data lines 242. Each transistor 23 is, for example, a TFT (thin film transistor) that functions as a switching element. Each transistor 23 includes a gate, source, and drain.

[0028] The scan lines 241 extend in the X direction, and the n scan lines 241 are arranged at equal intervals in the Y direction. The scan lines 241 are electrically connected to the gates of the corresponding transistors 23. The scan lines 241 are electrically connected to the scan line drive circuit 11 shown in Figure 1, and the corresponding scan signals G1, G2, ..., or Gn are supplied from the scan line drive circuit 11.

[0029] The data lines 242 extend in the Y direction, and m data lines 242 are arranged at equal intervals in the X direction. The data lines 242 are electrically connected to the sources of the corresponding transistors 23. The data lines 242 are electrically connected to the data line drive circuit 12 shown in Figure 1. The data lines 242 are supplied with corresponding image signals S1, S2, ..., or Sm from the data line drive circuit 12.

[0030] The n scan lines 241 and m data lines 242 are electrically isolated from each other and arranged in a grid pattern in a planar view. The region enclosed by two adjacent scan lines 241 and two adjacent data lines 242 corresponds to a pixel P. Each pixel electrode 25 is electrically connected to the drain of the corresponding transistor 23.

[0031] The constant potential lines 243 extend in the Y direction, and the n constant potential lines 243 are arranged at equal intervals in the X direction. Furthermore, the constant potential lines 243 are electrically insulated from the data lines 242 and the scan lines 241. A fixed potential, such as ground potential, is applied to the constant potential lines 243. A common potential may also be applied to the constant potential lines 243. The potential of the constant potential lines 243 is supplied to one electrode of the capacitive element 26. The capacitive element 26 is a holding capacitor for maintaining the potential of the pixel electrode 25, and the other electrode of the capacitive element 26 is electrically connected to the pixel electrode 25 and the drain of the transistor 23.

[0032] When a corresponding scan line 241 is selected by the scan signals G1, G2, ..., and Gn, the transistor 23 connected to the selected scan line 241 turns ON. Then, image signals S1, S2, ..., and Sm corresponding to the grayscale to be displayed are applied via the data line 242 to the pixel electrode 25 of the pixel P corresponding to the selected scan line 241. As a result, a voltage corresponding to the grayscale to be displayed is applied to the liquid crystal layer 5, and the orientation of the liquid crystal molecules changes according to the applied voltage. This change in the orientation of the liquid crystal molecules modulates the light LL, making it possible to display the grayscale.

[0033] 1C. Structure of element substrate 2 Figure 4 is a plan view showing a portion of the element substrate in Figure 2. Figure 4 corresponds to the IV-IV line in Figure 2 and shows a portion of the element substrate 2 in display area A10. As shown in Figure 4, the multiple pixel electrodes 25 on the element substrate 2 are spaced apart from each other and arranged in a matrix. The rectangular area shown by the dashed line is the aperture A11 through which light is transmitted, and the frame-shaped area between two adjacent apertures A11 is the light-blocking area A12 through which light is blocked. A pixel electrode 25 is provided in the opening A11. The outer edge of the pixel electrode 25 is positioned to overlap with the light-shielding region A12.

[0034] In the light-shielding region A12, the transistor 23, capacitive element 26, and scan lines 241, data lines 242, constant potential lines 243, etc., as shown in Figure 3, are arranged. The pixel electrode 25 is connected to the transistor 23 and the capacitive element 26 via the contact hole C25.

[0035] Figure 5 is a schematic cross-sectional view of the element substrate in Figure 4 along the VV line, and Figure 6 is a schematic cross-sectional view of the element substrate in Figure 4 along the VI-VI line. The first substrate 21 shown in Figures 5 and 6 has a first groove 211, a second groove 212, and a third groove 213 as second recesses.

[0036] The first groove 211, the second groove 212, and the third groove 213 are grooves provided in the first base material 21. As shown in Figure 6, the first groove 211 has a groove that is long in the Y direction. As shown in Figure 5, the second groove 212 and the third groove 213 are arranged to be spaced apart from the first groove 211 in the X1 and X2 directions, respectively.

[0037] Capacitive elements 26 are provided in the first groove 211, the second groove 212, and the third groove 213. A capacitive element 26 is provided for each pixel P. The capacitive element 26 has a first capacitive electrode 261, a dielectric film 263, and a second capacitive electrode 262. The capacitive element 26 has a first trench capacitive section 265, a second trench capacitive section 266, and a third trench capacitive section 267. The first trench capacity section 265 is located in the first groove section 211 and has a recessed shape that reflects the shape of the first groove section 211. The second trench capacity section 266 is located in the second groove section 212. The third trench capacity section 267 is located in the third groove section 213.

[0038] A laminate 22, a pixel electrode 25, and a first alignment film 29 are provided covering the first substrate 21 and the capacitive element 26. The laminate 22 includes a first insulating film 221, a second insulating film 222, a third insulating film 223, a fourth insulating film 224, a fifth insulating film 225, a sixth insulating film 226, a seventh insulating film 227, a scan line 241, a semiconductor film 231, a gate electrode 232, a data line 242, a constant potential line 243, and relay electrodes 271, 272, 273, 274, 275, 276, 277, and 279.

[0039] The first capacitance electrode 261 is electrically connected to the transistor 23 and the pixel electrode 25. As shown in Figure 6, the first capacitance electrode 261 is electrically connected to the drain region 231b of the semiconductor film 231 of the transistor 23 via relay electrodes 271 and 273. Also, as shown in Figure 5, the relay electrode 273 is electrically connected to the pixel electrode 25 via relay electrodes 277 and 279.

[0040] As shown in Figure 6, the relay electrode 271 is provided on the third insulating film 223, and also on the inner wall of the contact hole C271 that penetrates the third insulating film 223, the second insulating film 222, and the first insulating film 221 to expose the connection portion 261e of the first capacitive electrode 261, and is electrically connected to the first capacitive electrode 261 via the contact hole C271.

[0041] The relay electrode 273 is provided on the fourth insulating film 224 and also on the inner wall of a contact hole C273 that penetrates the fourth insulating film 224 and the fifth insulating film 225 to expose the drain region 231b of the semiconductor film 231, and is electrically connected to the drain region 231b via the contact hole C273.

[0042] As shown in Figure 5, the relay electrode 277 is provided on the fifth insulating film 225 and also on the inner wall of the contact hole C277 that penetrates the fifth insulating film 225 and exposes the relay electrode 273, and is electrically connected to the relay electrode 273 via the contact hole C277. The relay electrode 279 is provided on the sixth insulating film 226 and also on the inner wall of the contact hole C279 that penetrates the sixth insulating film 226 and exposes the relay electrode 277, and is electrically connected to the relay electrode 277 via the contact hole C279. The pixel electrode 25 is provided on the seventh insulating film 227 and also on the inner wall of the contact hole C25 that penetrates the seventh insulating film 227 and exposes the relay electrode 279, and is electrically connected to the relay electrode 279 via the contact hole C25.

[0043] The second capacitive electrode 262 is electrically connected to the constant potential line 243. The second capacitive electrode 262 is electrically connected to the constant potential line 243 via relay electrodes 272, 275, and 276.

[0044] As shown in Figure 5, the relay electrode 272 is provided on the third insulating film 223 and also on the inner wall of the contact hole C272 that penetrates the third insulating film 223, the second insulating film 222, and the first insulating film 221 to expose the connection portion 262e of the second capacitive electrode 262, and is electrically connected to the second capacitive electrode 262 via the contact hole C272. The relay electrode 275 is provided on the fourth insulating film 224 and also on the inner wall of the contact hole C275 that penetrates the fourth insulating film 224 to expose the relay electrode 272, and is electrically connected to the relay electrode 272 via the contact hole C275. The relay electrode 276 is provided on the fifth insulating film 225 and also on the inner wall of the contact hole C276 that penetrates the fifth insulating film 225 to expose the relay electrode 275, and is electrically connected to the relay electrode 275 via the contact hole C276. The constant potential wire 243 is provided on the sixth insulating film 226 and also penetrates the sixth insulating film 226 and is provided on the inner wall of the contact hole C243 that exposes the relay electrode 276. The constant potential wire 243 has a projection 243p that protrudes in the X1 direction, and is electrically connected to the relay electrode 276 at the position of the projection 243p via the contact hole C243.

[0045] The gate electrode 232 is electrically connected to the scan line 241. The gate electrode 232 is provided on the third insulating film 223 and also on the inner wall of a contact hole C232 that penetrates the third insulating film 223 and the second insulating film 222 to expose the scan line 241, and is electrically connected to the scan line 241 via the contact hole C232. As shown in Figure 6, the region of the third insulating film 223 corresponding to the gate electrode 232 corresponds to the gate insulating film 233.

[0046] Data line 242 is electrically connected to the source region 231c of the semiconductor film 231. As shown in Figure 6, the data line 242 is provided on the fifth insulating film 225 and also on the inner wall of the contact hole C242 that penetrates the fifth insulating film 225 and exposes the relay electrode 274, and is electrically connected to the relay electrode 274 via the contact hole C242. The relay electrode 274 is provided on the fourth insulating film 224 and is also formed on the inner wall of the contact hole C274 that penetrates the fourth insulating film 224 and exposes the source region 231c of the semiconductor film 231, and is electrically connected to the source region 231c.

[0047] Figure 7 is an enlarged cross-sectional view corresponding to region VII enclosed by the dashed line in Figure 5. The first groove 211 comprises an opening 211a on the surface of the first base material 21, a bottom surface 211b located in the Z2 direction of the opening 211a, and a wall surface 211c between the opening 211a and the bottom surface 211b. The first trench capacity section 265 provided inside the first groove 211 has a concave shape that reflects the shape of the first groove 211.

[0048] Here, the width W1, which is the length in the X direction of the bottom surface 211b of the first groove 211, is, for example, 0.3 μm or more and 0.8 μm or less. The width W2, which is the length in the X direction of the opening 211a, is, for example, 0.4 μm or more and 0.9 μm or less. Also, the width W3, which is the length in the X direction of the opening 26a of the first trench capacity portion 265, is, for example, 0.2 μm or more and 0.7 μm or less. The width W4, which is the length in the X direction of the bottom surface 26b of the first trench capacity portion 265, is, for example, 0.1 μm or more and 0.5 μm or less. Also, the depth D1 of the first groove 211 is, for example, 0.5 μm or more and 2.0 μm or less.

[0049] A first insulating film 221 is laminated on the capacitive element 26 as an insulating film. In the first insulating film 221, a recessed portion 221r ​​is formed in the portion that overlaps with the opening 26a of the first trench capacitive portion 265, as a recess that reflects the concave shape of the first trench capacitive portion 265.

[0050] The recessed portion 221r ​​has a curved bottom surface. In this embodiment, the angle θ1 formed by the tangent t1 tangent to the curved bottom surface and the normal n of the first base material 21 is 52°. Note that angle θ1 is the smallest angle formed by the tangent t1 tangent to the curved bottom surface and the normal n of the first base material 21.

[0051] The angle θ1 is preferably 40° or more and less than 90°. The inventors of the present invention have obtained the following findings through experiments: When the angle θ1 is 40° or more and less than 90°, defects such as seams, cracks, or uneven film formation in the scanning lines 241 provided on the first insulating film 221 are suppressed. When the angle θ1 is 40° or more and less than 90°, display defects and a decrease in display quality caused by disconnection of the scanning lines 241, increased resistance of the wiring of the scanning lines 241, or a decrease in the light-shielding performance of the scanning lines 241 are suppressed.

[0052] A scan line 241 is provided on the first insulating film 221. At the position where the scan line 241 overlaps with a recessed portion 221r ​​of the first insulating film 221, a recessed portion 241r is formed that reflects the shape of the recessed portion 221r. The recessed portion 241r has a curved bottom surface, similar to the recessed portion 221r.

[0053] Figure 8 is a plan view corresponding to the line VIII-VIII in Figures 5 and 6. A laminated film including a first capacitive electrode 261, a dielectric film 263, and a second capacitive electrode 262 is provided on the surface of the first substrate 21, including the first groove 211, the second groove 212, and the third groove 213.

[0054] The first groove 211 is a rectangle that is elongated in the Y direction when viewed from above. The second groove 212 and the third groove 213 are rectangles that are elongated in the X direction. The first groove 211 is located between the second groove 212 and the third groove 213 when viewed from above.

[0055] The capacitive element 26 has a portion extending in the Y direction, a portion extending in the X direction, and an intersection of these portions. Furthermore, in a plan view, the capacitive element 26 is provided so as to cover the first groove 211, the second groove 212, and the third groove 213, and also has a portion that extends outward from the first groove 211, the second groove 212, and the third groove 213. A connection portion 261e is provided at one end of the first capacitive electrode 261 in the Y2 direction. The connection portion 261e and the first groove 211 do not overlap in a plan view. As shown in Figure 6, the connection portion 261e is a portion where the dielectric film 263 and the second capacitive electrode 262 overlapping the first capacitive electrode 261 are cut out, and the first capacitive electrode 261 and the intermediate electrode 271 are electrically connected at the connection portion 261e.

[0056] Furthermore, as shown in Figure 8, a connection portion 262e is provided at one end of the second capacitive electrode 262 in the X1 direction. The connection portion 262e does not overlap with the second groove portion 212 and the third groove portion 213 in a plan view. As shown in Figure 5, the second capacitive electrode 262 and the constant potential wire 243 are electrically connected at the connection portion 262e.

[0057] Figure 9 is a plan view corresponding to the IX-IX line in Figures 5 and 6. The first insulating film 221, scan line 241, second insulating film 222, semiconductor film 231, third insulating film 223, gate electrode 232, and relay electrodes 271, 272 are stacked on the first substrate 21 and capacitive element 26 shown in Figure 8.

[0058] In a plan view, the semiconductor film 231 is arranged in the following order along the Y1 direction: drain region 231b, low-concentration drain region 231d, channel region 231a, low-concentration source region 231e, and source region 231c. The width of the semiconductor film 231 in the X direction is, for example, 0.3 μm. In a plan view, the semiconductor film 231 has a shape that is elongated in the Y direction. Note that the drain region 231b and source region 231c are formed to be wider than the channel region 231a.

[0059] The scan line 241 has, for example, a width of 0.5 μm to 1 μm and extends in the X direction in a plan view. The scan line 241 has a wider portion 241w than the main body portion that extends in the X direction. The wider portion 241w has protrusions 243p extending in the Y1 and Y2 directions and covers the semiconductor film 231 from the first substrate 21 side. A contact hole C232 is provided on the wider portion 241w, and the scan line 241 is electrically connected to the gate electrode 232 in the wider portion 241w. The gate electrode 232 overlaps the channel region 231a of the semiconductor film 231 in a plan view.

[0060] Figure 10 is an enlarged plan view corresponding to the region X enclosed by the dashed line in Figure 9. Figure 10 shows the planar positional relationship between the first groove 211, the first trench capacitance 265, the scan line 241, the semiconductor film 231, and the gate electrode 232.

[0061] The first groove 211 is positioned along the extending direction of the semiconductor film 231 in a plan view and overlaps with the semiconductor film 231 in a plan view. Similarly, the first trench capacitance portion 265 of the capacitance element 26 provided in the first groove 211 is positioned along the semiconductor film 231 in a plan view and overlaps with the semiconductor film 231. Furthermore, in the scan line 241, a recessed portion 241r of the scan line 241 is formed along the first trench capacitance portion 265 at a position that overlaps with the first trench capacitance portion 265 in a plan view.

[0062] Furthermore, in the example shown in Figure 10, the width W1 of the bottom surface 211b of the first groove 211 is less than or equal to the width W0 of the source region 231c of the semiconductor film 231, and is smaller than the width of the channel region 231a. Although not shown, the width W2 of the opening 211a of the first groove 211 is larger than the width of the channel region 231a. Note that the width W1 of the bottom surface 211b of the first groove 211 may be greater than or equal to the width of the channel region 231a.

[0063] Figure 11 is a plan view corresponding to the line XI-XI in Figures 5 and 6. Relay electrodes 273, 274, and 275 are provided on the fourth insulating film 224. The relay electrode 273 overlaps with a portion of the semiconductor film 231 in a plan view. The relay electrode 274 overlaps a portion of the semiconductor film 231 in a plan view and is positioned at a distance from the relay electrode 273 in the Y1 direction. The relay electrode 275 is positioned at a distance from the relay electrode 273 in the X1 direction when viewed from above.

[0064] Figure 12 is a plan view corresponding to the line XII-XII in Figures 5 and 6. Data lines 242 and relay electrodes 276 and 277 are provided on the fifth insulating film 225. The relay electrode 276 is positioned in a plan view, spaced apart from the corresponding data line 242 in the X1 direction. The relay electrode 277 is positioned in a plan view, spaced apart from the corresponding data line 242 in the X2 direction. The data line 242 extends in the Y direction and, in a plan view, overlaps the semiconductor film 231. The width of the data line 242 is, for example, 0.5 μm to 1 μm.

[0065] Figure 13 is a plan view corresponding to the line XIII-XIII in Figures 5 and 6. A constant potential line 243 and a relay electrode 279 are arranged on the sixth insulating film 226. The constant potential line 243 has a projection 243p that protrudes in the X1 direction from the constant potential line 243 in a plan view. The constant potential line 243 extends in the Y direction and overlaps the data line 242 and the semiconductor film 231 in a plan view. The width of the constant potential line 243 is, for example, 0.5 μm to 1 μm. The relay electrode 279 is positioned in the X2 direction with respect to the corresponding constant potential line 243 in a plan view.

[0066] The configuration of the various wirings and other elements of the element substrate 2 described above is merely an example and is not limited to the configurations shown in Figures 5 and 6. For example, the scan line 241 may be formed on a layer above the transistor 23. In this case, a light-shielding film having light-shielding properties other than the scan line 241 is placed between the capacitive element 26 and the transistor 23. This light-shielding film may be other wiring, other relay electrodes, or electrically insulated island-shaped light-shielding films.

[0067] 1D. Manufacturing method of element substrate 2 Figure 14 is a flowchart showing the flow of a part of the manufacturing method of the element substrate. In this embodiment, the manufacturing methods of the first groove 211, the capacitive element 26, the scan line 241, and the semiconductor film 231, which are part of the manufacturing method of the element substrate 2 of the liquid crystal device 100, will be described. The device substrate 2 can be manufactured using methods used in known semiconductor processes, such as reduced-pressure CVD (Chemical Vapor Deposition), atmospheric pressure CVD, plasma CVD, photolithography, sputtering, etching, and CMP (Chemical Mechanical Planarization), or by combining these methods.

[0068] The method for manufacturing the element substrate 2 includes a recess formation step, a capacitive element formation step, a first insulating film formation step, a scanning line formation step, a second insulating film formation step, and a semiconductor film formation step.

[0069] Figure 15 is a diagram illustrating the recess formation process. In Figure 14, in step S11, a first groove 211 is formed in the first substrate 21. In step S11, a second groove 212 and a third groove 213 are also formed. As shown in Figure 15, the first groove 211 is formed, for example, by forming a mask (not shown) on a quartz substrate and performing anisotropic etching through the mask.

[0070] The width W2 of the opening 211a of the first groove 211 in the X direction is wider than the width W1 of the bottom surface 211b, and the depth D1 of the first groove 211 is formed such that the aspect ratio (D1 / W1) of the depth D1 with respect to the width W1 is greater than 1. The first groove 211 may also be provided by laminating an interlayer insulating film on the first substrate 21, and providing the first groove 211 in the interlayer insulating film or in the interlayer insulating film and the first substrate 21. In this case, the interlayer insulating film with the first groove 211 or the interlayer insulating film and the first substrate 21 correspond to an insulating member.

[0071] Figure 16 is a diagram illustrating the capacitive element formation process. In Figure 14, step S12 involves forming a capacitive element 26. As shown in Figure 16, the capacitive element 26 is formed to cover the opening 211a, bottom surface 211b, and wall surface 211c of the first groove 211, and a portion of the XY plane of the first substrate 21. In this step, first, the first capacitive electrode 261 of the capacitive element 26 is deposited on the first substrate 21 including the first groove 211. Next, a dielectric film 263 is deposited to cover the first capacitive electrode 261. Finally, the first capacitive electrode 261 is deposited on the dielectric film 263. The patterning of the first capacitive electrode 261, the dielectric film 263, and the second capacitive electrode 262 may be performed all at once, or it may be divided into two steps: one after the formation of the first capacitive electrode 261 and another after the formation of the second capacitive electrode 262.

[0072] The materials for the first capacitance electrode 261 and the second capacitance electrode 262 are preferably polysilicon films containing conductive impurities such as phosphorus (P), but may also be metals such as titanium, metal oxides, or metal nitrides. Furthermore, while a silicon nitride film with a high dielectric constant is preferred for the dielectric film 263, metal oxide films such as aluminum oxide, hafnium oxide, or silicon oxide, metal nitride films such as silicon nitride, or multilayer films in which these metal oxide films and metal nitride films are laminated may also be used.

[0073] The film thicknesses of the first capacitive electrode 261 and the second capacitive electrode 262 are, for example, 0.03 μm to 0.2 μm. The film thickness of the dielectric film 263 is, for example, 0.01 μm to 0.03 μm. The thickness of the multilayer film is, for example, 0.07 μm to 0.26 μm.

[0074] Figures 17 and 18 are diagrams illustrating the first insulating film formation process. In Figure 14, in step S13, a first insulating film 221 is formed on the capacitive element 26. As shown in Figure 17, in this step, the first insulating film 221 is deposited to a thickness of approximately 600 nm by a reduced-pressure CVD method.

[0075] The first insulating film 221 is formed to fill the first groove 211 of the first substrate 21, and a V-shaped groove 221t is formed on the surface of the first insulating film 221 at a position corresponding to the first groove 211. The groove 221t has a V-shape with the bottom of the groove sharply pointed.

[0076] Next, as shown in Figure 18, the surface of the first insulating film 221 is etched back by about 150 nm. As a result, the thickness of the first insulating film 221 becomes about 450 nm, and the V-shaped groove 221t is transformed into a recessed portion 221r ​​with a curved bottom surface.

[0077] The etch-back of the first insulating film 221 is performed until the minimum angle θ1 between the tangent line t1 touching the curved bottom surface of the recessed portion 221r ​​and the normal line n of the first substrate 21 is 40° or more and less than 90°. Planarization treatments such as CMP may be performed to make the angle θ1 40° or more and less than 90°. Furthermore, the first insulating film 221 may be deposited with a thickness greater than 600 nm to make the angle θ1 40° or more and less than 90°.

[0078] Figure 19 is a diagram illustrating the scan line formation process. In Figure 14, in step S14, a scan line 241 is formed on the first insulating film 221. As shown in Figure 19, the scan line 241 is formed by first depositing a metal film by sputtering or vapor deposition, and then etching the metal film using a resist mask. At this time, a recessed portion 241r is formed on the scan line 241, which has a curved bottom surface that reflects the shape of the recessed portion 221r ​​of the first insulating film 221. The scanning line 241 is made of a light-shielding metallic material. For example, it is preferable to use a metallic material containing tungsten or tungsten silicide. This allows the scanning line 241 to shield the semiconductor film 231 from light, even when polysilicon films with low light-shielding properties are used for the first capacitance electrode 261 and the second capacitance electrode 262.

[0079] Figure 20 is a diagram illustrating the scanning line formation process related to a comparative example. In the comparative example, the first insulating film 221 was deposited to a thickness of approximately 600 nm, and scan lines 241 were formed without etch-back. V-shaped grooves 241t were formed on the scan lines 241, reflecting the shape of the V-shaped grooves 221t of the first insulating film 221.

[0080] At the bottom of groove 221t, the angle θ2 between the tangent line t2 that contacts the inclined surface of groove 221t and the normal line n of the first substrate 21 is approximately 28°. Angle θ2 is the smallest angle between the tangent line t2 that contacts the inclined surface of groove 221t and the normal line n of the first substrate 21 at the bottom of groove 221t. Experiments by the inventors of the present invention have shown that when the angle θ2 is less than 40°, defects such as seams, cracks, or uneven film formation occur in the groove 241t portion of the scan line 241.

[0081] Figure 21 is a diagram illustrating the second insulating film formation process and the semiconductor film formation process. In Figure 14, in step S15, a second insulating film 222 is formed on the scan line 241. As shown in Figure 21, the second insulating film 222 is formed, for example, by a reduced-pressure CVD method. The Z1 direction surface of the second insulating film 222 that overlaps the first groove 211 is a flat surface. By stacking the second insulating film 222 on the recessed portion 241r of the scan line 241, the Z1 direction surface of the second insulating film 222 becomes a flat surface.

[0082] In Figure 14, in step S16, a semiconductor film 231 is formed on the second insulating film 222. As shown in Figure 21, in this step, first, an amorphous silicon film is formed on the second insulating film 222, and a crystallized polysilicon film is formed by heat treatment of the film. Next, the semiconductor film 231 is formed by selectively implanting impurities into the polysilicon film. Here, since the Z1 direction surface of the second insulating film 222 that overlaps the first groove 211, the recessed portion 221r, and the recessed portion 241r is a flat surface, the risk of unevenness occurring in the semiconductor film 231 formed on the second insulating film 222 due to the influence of the first groove 211 is reduced.

[0083] As described above, the liquid crystal device 100 as an electro-optical device of this embodiment provides the following advantages. The liquid crystal apparatus 100 of this embodiment includes a capacitive element 26, a first insulating film 221 which covers the capacitive element 26 and has a recessed portion 221r ​​which is a recess that reflects the shape of the capacitive element 26, and a scanning line 241 which is a light-shielding film provided along the recessed portion 221r, the recessed portion 221r ​​having a curved bottom surface.

[0084] As described above, in the liquid crystal device 100 of this embodiment, the first insulating film 221 has a recessed portion 221r ​​on the opposite side of the capacitive element 26, which is a recess that reflects the shape of the capacitive element 26, and the recessed portion 221r ​​of the first insulating film 221 has a curved bottom surface. Furthermore, since the scanning lines 241 that are laminated on the first insulating film 221 are formed along the curved bottom surface of the recessed portion 221r ​​of the first insulating film 221, it is possible to suppress the occurrence of problems such as breakage due to cracking, increased wiring resistance, or reduced light shielding performance in the scanning lines 241. Therefore, the liquid crystal device 100 of this embodiment can improve the display quality.

[0085] In this embodiment, the liquid crystal apparatus 100 further comprises tungsten or tungsten silicide as the scanning line 241, which serves as the light-shielding film. Thus, in this embodiment, the liquid crystal apparatus 100 uses a metallic material containing tungsten or tungsten silicide for the scanning lines 241, allowing the scanning lines 241 to function as a light-shielding film.

[0086] The liquid crystal apparatus 100 of this embodiment further includes a first substrate 21 as an insulating member on which capacitive elements 26 are provided, and the minimum angle θ1 between the tangent line t1 that contacts the curved bottom surface of the recessed portion 221r ​​of the first insulating film 221 as a recess and the normal line n of the first substrate 21 is 40° or more and less than 90°. In this way, the liquid crystal apparatus 100 of this embodiment can suppress defects such as seams, cracks, and uneven film formation in the scanning lines 241 provided on the first insulating film 221 by setting the angle θ1 to 40° or more and less than 90°.

[0087] The liquid crystal apparatus 100 of this embodiment further comprises a first substrate 21 as an insulating member on which capacitive elements 26 are provided. The first substrate 21 has a first groove 211 as a second recess that overlaps with the first trench capacitance portion 265. The first groove 211 and the first trench capacitance portion 265 are provided along the Y direction as a first direction, and the scanning lines 241 as a light-shielding film are provided along the X direction as a second direction that intersects the Y direction.

[0088] Thus, even when the extending direction of the first groove 211 and the extending direction of the scan line 241 intersect, the liquid crystal device 100 of this embodiment can suppress the occurrence of defects such as seams, cracks, or uneven film formation in the scan line 241 that intersects with the first groove 211. Therefore, display defects and a decrease in display quality caused by disconnection of the scan line 241, increased wiring resistance of the scan line 241, or a decrease in the light-shielding performance of the scan line 241 can be suppressed.

[0089] The liquid crystal apparatus 100 of this embodiment further comprises a transistor 23 and a data line 242 extending along the Y direction as a first direction, wherein the transistor 23 has a semiconductor film 231 provided along the Y direction, and the first trench capacitance portion 265, the first groove portion 211 as a second recess, and the semiconductor film 231 are provided in a position that overlaps with the data line 242 in a plan view. As described above, in this embodiment, the liquid crystal device 100 has the first trench capacitance section 265 and the data line 242 arranged in the same direction as the semiconductor film 231 of the transistor 23, thereby improving the light shielding performance for the transistor 23.

[0090] 2. Variations In the embodiments described above, an active-matrix liquid crystal display 100 is exemplified as the liquid crystal display 100, but a passive-matrix display may also be used. Furthermore, the driving method of the liquid crystal display device 100 may be either a vertical electric field method or a horizontal electric field method. Examples of horizontal electric field methods include the IPS (In Plane Switching) mode. Examples of vertical electric field methods include the TN (Twisted Nematic) mode, VA (Vertical Alignment), PVA mode, and OCB (Optically Compensated Bend) mode. Furthermore, although the liquid crystal device 100 is transmissive, a reflective or LCOS (Liquid crystal on silicon) type liquid crystal device may be used. Furthermore, the electro-optical device of this embodiment may be used in an organic EL (electro-luminescence) device or a DMD (Digital Micromirror Device).

[0091] 3.Electronic equipment The liquid crystal device 100, as an electro-optical device, can be used in various electronic devices.

[0092] Figure 22 is a schematic diagram showing a projector, which is an example of an electronic device. The projection display device 4000 is, for example, a three-panel projector equipped with three liquid crystal displays 100. Liquid crystal device 1r is a liquid crystal device 100 corresponding to the red display color, liquid crystal device 1g is a liquid crystal device 100 corresponding to the green display color, and liquid crystal device 1b is a liquid crystal device 100 corresponding to the blue display color. The control unit 4005 includes, for example, a processor and memory, and controls the operation of the liquid crystal devices 1r, 1g, and 1b.

[0093] The illumination optical system 4001 supplies monochromatic light of the red component r from the light source illumination device 4002 to the liquid crystal device 1r, monochromatic light of the green component g to the liquid crystal device 1g, and monochromatic light of the blue component b to the liquid crystal device 1b. The liquid crystal devices 1r, 1g, and 1b function as light modulators, such as light bulbs, that modulate the monochromatic light supplied from the illumination optical system 4001 according to the displayed image. The projection optical system 4003 combines the light emitted from each liquid crystal device 1r, 1g, and 1b and projects it onto a projection surface 4004 such as a screen.

[0094] As described above, the projection display device 4000 of this embodiment provides the following effects in addition to the effects of each of the embodiments described above. The projection display device 4000 as an electronic device preferably comprises a liquid crystal device 100 as an electro-optical device according to each of the above embodiments, and a control unit 4005 that controls the operation of the liquid crystal device 100.

[0095] With this configuration, the projection display device 4000 can improve the display quality of the projection display device 4000 by including the aforementioned liquid crystal device 100.

[0096] The electronic devices to which the liquid crystal display device 100 of the present invention is applied are not limited to the examples given. Examples include personal computers, smartphones, PDAs (Personal Digital Assistants), digital still cameras, televisions, video cameras, car navigation systems, in-car displays, electronic organizers, electronic paper, calculators, word processors, workstations, video phones, POS (Point of Sale) systems, printers, scanners, copiers, video players, and devices equipped with touch panels.

[0097] Although the present invention has been described above based on preferred embodiments, the present invention is not limited to the embodiments described above. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that performs a similar function to the embodiments described above, and any configuration can be added. [Explanation of symbols]

[0098] 1b, 1g, 1r, 100…Liquid crystal device, 2…Element substrate, 3…Opposite substrate, 4…Sealing member, 5…Liquid crystal layer, 11…Scan line driving circuit, 12…Data line driving circuit, 13…External terminal, 21…First substrate, 22…Laminate, 23…Transistor, 25…Pixel electrode, 26…Capacitor element, 29…First alignment film, 31…Second substrate, 33…Common electrode, 211…First groove, 211b…Bottom surface, 211a…Opening, 21 2...Second groove, 213...Third groove, 221...First insulating film, 222...Second insulating film, 223...Third insulating film, 224...Fourth insulating film, 225...Fifth insulating film, 226...Sixth insulating film, 227...Seventh insulating film, 231...Semiconductor film, 231a...Channel region, 231b...Drain region, 231c...Source region, 232...Gate electrode, 233...Gate insulating film, 241...Scan line, 241r...Recessed portion, 22 1r... recessed portion, 242... data line, 243... constant potential line, 26a... opening, 261... first capacitance electrode, 262... second capacitance electrode, 263... dielectric film, 265... first trench capacitance section, 266... ​​second trench capacitance section, 267... third trench capacitance section, 271, 272, 273, 274, 275, 276, 277, 279... intermediate electrodes, C232, C242, C243, C25, C271, C27 2, C273, C274, C275, C276, C277, C279... Contact holes, 4000... Projection type display device, 4001... Illumination optical system, 4002... Illumination device, 4003... Projection optical system, 4004... Projection surface, 4005... Control unit, A10... Display area, A11... Aperture, A12... Light-shielding area, A20... Peripheral area, LL... Light, P... Pixel, W1, W2, W3, W4, W0... Width, D1... Depth.

Claims

1. A capacitive element; an insulating film covering the capacitive element and having a first recess that reflects a shape of the capacitive element; a light-shielding film provided along the first recess, The first recess has a curved bottom surface. Electro-optical device.

2. The light-shielding film contains tungsten or tungsten silicide.

2. The electro-optical device according to claim 1.

3. an insulating member provided with the capacitance element; the minimum angle between a tangent line contacting the curved bottom surface of the first recess and a normal line of the insulating member is equal to or greater than 40° and less than 90°; 2. The electro-optical device according to claim 1.

4. an insulating member provided with the capacitance element; the insulating member has a second recess overlapping the first recess, The second recess and the first recess are provided along a first direction, The light-shielding film is provided along a second direction intersecting the first direction.

2. The electro-optical device according to claim 1.

5. A transistor and a data line extending along the first direction; The transistor has a semiconductor film provided along the first direction, the first recess, the second recess, and the semiconductor film are provided at positions overlapping with the data line in a plan view; 5. The electro-optical device according to claim 4.

6. The electro-optical device according to claim 1 , A control unit for controlling the operation of the electro-optical device. electronic equipment.

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