Image sensor

Abstract

To provide an image sensor with sensitivity improved.SOLUTION: An image sensor includes a first substrate including pixel regions, each pixel region including a photoelectric conversion region, a color filter provided on each of the pixel regions and provided on a first surface of the first substrate, a microlens provided on each color filter, and a lens coating layer on the microlens. The lens coating layer includes a first coating layer and a second coating layer on the first coating layer. The first and second coating layers contain a same material, and density of the second coating layer is larger than that of the first coating layer.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present invention relates to an image sensor, and more particularly to an image sensor having improved sensitivity and a method for manufacturing the same. [Background technology]

[0002] An image sensor is a device that converts an optical image into an electrical signal. Image sensors are classified into CCD (Charge Coupled Device) type and CMOS (Complementary Metal Oxide Semiconductor) type. CMOS type image sensors are called CIS (CMOS image sensor). CIS has a number of pixels arranged two-dimensionally. Each pixel includes a photodiode (PD). The photodiode converts incident light into an electrical signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Pat. No. 1,118,9654 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the above-mentioned conventional techniques, and an object of the present invention is to provide an image sensor having improved sensitivity, and to provide a method for manufacturing an image sensor having improved sensitivity. [Means for solving the problem]

[0005] In order to achieve the above object, an image sensor according to one aspect of the present invention includes a first substrate including pixel regions, each of the pixel regions including a photoelectric conversion region, color filters each provided on the pixel regions, the color filters provided on a first surface of the first substrate, microlenses each provided on the color filters, and a lens coating layer on the microlenses, the lens coating layer including a first coating layer and a second coating layer on the first coating layer, the first and second coating layers including the same material, and the density of the second coating layer being greater than the density of the first coating layer.

[0006] According to another aspect of the present invention, an image sensor may include a first substrate including pixel regions, each of the pixel regions including a photoelectric conversion region, color filters provided on the pixel regions, the color filters provided on a first surface of the first substrate, a fence pattern partitioning the color filters, a protective film between the color filters and the fence pattern, microlenses provided on the color filters, and a lens coating layer on the microlenses. The protective film may include a first protective film and a second protective film sequentially stacked, and it is preferable that the first protective film includes aluminum oxide or hafnium oxide, and the second protective film includes silicon oxide.

[0007] According to another aspect of the present invention, an image sensor includes a circuit chip and an image sensor chip stacked on the circuit chip. The image sensor chip may include a first substrate having a first surface and a second surface facing each other and including a photoelectric conversion region therein, an isolation pattern defining the photoelectric conversion region in the first substrate, an insulating layer covering the first surface, a color filter on the insulating layer, a fence pattern partitioning the color filter, a protective film between the fence pattern and the color filter, microlenses provided on the color filters, a lens coating layer on the microlenses, an isolation pattern adjacent to the second surface and defining an active region, a buried gate pattern on the second surface, and a first wiring layer on the buried gate pattern. The circuit chip may include a second substrate on which an integrated circuit is provided, and a second wiring layer on the second substrate. The first wiring layer and the second wiring layer face each other and are electrically connected to each other, and the lens coating layer may include a first coating layer and a second coating layer on the first coating layer, and the first and second coating layers may include the same material, and the density of the second coating layer may be greater than the density of the first coating layer. Effect of the Invention

[0008] The image sensor according to the present invention can prevent defects caused by pigment residues being adsorbed on the color filter by using a second protective layer between the color filter and the fence pattern, and the second protective layer can prevent crosstalk between adjacent pixels.

[0009] The image sensor according to the present invention can prevent defects such as voids from occurring in the microlens layer by providing not only the first coating layer but also the dense and conformal second coating layer on the microlens layer. As a result, the present invention can improve the reliability and sensitivity of the image sensor. [Brief description of the drawings]

[0010] [Figure 1] 2 is a circuit diagram of a pixel of an image sensor according to an embodiment of the present invention; [Diagram 2] 1 is a plan view illustrating an image sensor according to an embodiment of the present invention; [Diagram 3] 3 is a cross-sectional view taken along line II' in FIG. 2. [Figure 4] 2. FIG. 4 is a cross-sectional view illustrating an image sensor according to another embodiment of the present invention, taken along line II' of FIG. [Diagram 5] 2. FIG. 4 is a cross-sectional view illustrating an image sensor according to another embodiment of the present invention, taken along line II-II' of FIG. [Figure 6] FIG. 3 is a plan view illustrating a color filter and a microlens according to an embodiment of the present invention, showing an M region in FIG. 2. [Figure 7] 7 is a cross-sectional view taken along line II' in FIG. 6. [Figure 8] FIG. 7 is a cross-sectional view taken along line II' of FIG. 6 for explaining an image sensor according to a comparative example of the present invention. [Figure 9] 7 is a cross-sectional view corresponding to line II' of FIG. 6, illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 10] 7 is a cross-sectional view corresponding to line II' of FIG. 6, illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 11] 7 is a cross-sectional view corresponding to line II' of FIG. 6, illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 12] 7 is a cross-sectional view corresponding to line II' of FIG. 6, illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 13] 7 is a cross-sectional view corresponding to line II' of FIG. 6, illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 14] 7 is a cross-sectional view corresponding to line II' of FIG. 6, illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 15] 7 is a cross-sectional view corresponding to line II' of FIG. 6, illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 16] 3 is a plan view illustrating a color filter and a microlens according to another embodiment of the present invention, showing an M region in FIG. 2. FIG. [Figure 17] 17 is a cross-sectional view taken along line II' in FIG. 16. [Figure 18] 17 is a cross-sectional view illustrating a method of manufacturing an image sensor according to another embodiment of the present invention, the cross-sectional view corresponding to line II' in FIG. 16. [Figure 19] 17 is a cross-sectional view illustrating a method of manufacturing an image sensor according to another embodiment of the present invention, the cross-sectional view corresponding to line II' in FIG. 16. [Figure 20] 17 is a cross-sectional view illustrating a method of manufacturing an image sensor according to another embodiment of the present invention, the cross-sectional view corresponding to line II' in FIG. 16. [Figure 21] 17 is a cross-sectional view illustrating a method of manufacturing an image sensor according to another embodiment of the present invention, the cross-sectional view corresponding to line II' in FIG. 16. [Figure 22] 17 is a cross-sectional view corresponding to line II' in FIG. 16 for explaining a method for manufacturing an image sensor according to a comparative example of the present invention. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] FIG. 1 is a circuit diagram of a pixel of an image sensor according to an embodiment of the present invention.

[0012] 1, the image sensor includes first to fourth pixels PX1 to PX4. Each of the first to fourth pixels PX1 to PX4 includes a ground region GND, a photoelectric conversion region PD, a transfer transistor Tx, and a floating diffusion region FD.

[0013] The ground region GND includes a p-type impurity region A ground voltage VSS is commonly applied to the ground regions GND of the first to fourth pixels PX1 to PX4 through a first node N1.

[0014] The photoelectric conversion region PD is a photodiode including an n-type impurity region and a p-type impurity region. The floating diffusion region FD includes an n-type impurity region. The floating diffusion region FD functions as the drain of the transfer transistor Tx.

[0015] The floating diffusion regions FD of the first to fourth pixels PX1 to PX4 are commonly connected to a second node N2. The second node N2 to which the floating diffusion regions FD of the first to fourth pixels PX1 to PX4 are connected is connected to a source of a conversion gain transistor Cx. The conversion gain transistor Cx is connected to a reset transistor Rx.

[0016] The second node N2 is also electrically connected to a source follower gate SG of a source follower transistor Sx, which is connected to a selection transistor Ax.

[0017] The operation of the image sensor will be described with reference to FIG. 1. First, in a state where light is blocked, a power supply voltage VDD is applied to the drain of the reset transistor Rx and the drain of the source follower transistor Sx, and the reset transistor Rx is turned on to discharge the charge remaining in the floating diffusion region FD. Then, when the reset transistor Rx is turned off and external light is incident on the photoelectric conversion region PD, electron-hole pairs are generated in the photoelectric conversion region PD. The holes move to the p-type impurity region of the photoelectric conversion region PD and the electrons move to the n-type impurity region and are stored there. When the transfer transistor Tx is turned on, the charge such as the electrons and holes is transferred to and stored in the floating diffusion region FD. The gate bias of the source follower transistor Sx changes in proportion to the amount of stored charge, resulting in a change in the source potential of the source follower transistor Sx. At this time, when the selection transistor Ax is turned on, a signal based on the charge is read out to the column line.

[0018] The wiring line is electrically connected to at least one of the transfer gate TG, the source follower gate SG, the reset gate RG, and the selection gate AG. The wiring line is configured to apply a power supply voltage VDD to the drain of the reset transistor Rx or the drain of the source follower transistor Sx. The wiring line includes a column line connected to the selection transistor Ax. The wiring line includes a first conductive structure 830, which will be described later with reference to FIG. 3.

[0019] FIG. 1 illustrates the first to fourth pixels PX1 to PX4 sharing the first node N1 and the second node N2, but the embodiment according to the present invention is not limited to this.

[0020] 2 is a plan view of an image sensor according to an embodiment of the present invention, and FIG 3 is a cross-sectional view taken along line II' of FIG 2.

[0021] 2 and 3, the image sensor includes a sensor chip 10. The sensor chip 10 includes a first substrate 100, a first wiring layer 800, an insulating layer 400, a protective film 470, a color filter CF, a fence pattern 300, and a microlens layer 500.

[0022] In a plan view, the first substrate 100 includes a pixel array region APS, an optical black region OBR, and a pad region PDR. The pixel array region APS is disposed in a central region of the first substrate 100. The pixel array region APS includes a plurality of pixel regions PX. The pixels described with reference to FIG. 1 are provided in the pixel regions PX of the first substrate 100, respectively. For example, components of the pixels in FIG. 1 are provided on the pixel regions PX, respectively. The pixel regions PX output photoelectric signals from incident light.

[0023] The pixel regions PX are arranged two-dimensionally in rows and columns. The rows are parallel to a first direction D1. The columns are parallel to a second direction D2. In this specification, the first direction D1 is parallel to the first surface 100a of the first substrate 100. The second direction D2 is parallel to the first surface 100a of the first substrate 100 and intersects with the first direction D1. For example, the second direction D2 is substantially perpendicular to the first direction D1. The third direction D3 is perpendicular to the first direction D1 and the second direction D2. For example, the third direction D3 is substantially perpendicular to the first surface 100a of the substrate 100.

[0024] The pad region PDR is provided in the edge region of the first substrate 100 and surrounds the pixel array region APS. A pad PAD is provided on the pad region PDR. The pad PAD outputs an electrical signal generated in the pixel region PX to the outside. Also, an external electrical signal or voltage is transmitted to the pixel region PX through the pad PAD. Since the pad region PDR is disposed in the edge region of the first substrate 100, the pad PAD can be easily connected to the outside. The optical black region OBR will be described later. The pixel array region APS of the sensor chip 10 of the image sensor will be described in more detail below.

[0025] The first substrate 100 has a first surface 100a and a second surface 100b facing each other. The first surface 100a of the first substrate 100 is a rear surface, and the second surface 100b is a front surface. Light is incident on the second surface 100a of the first substrate 100. The first substrate 100 is a semiconductor substrate or an SOI (Silicon on Insulator) substrate. The semiconductor substrate includes, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The first substrate 100 further includes a group 3 element. The group 3 element is an impurity of a first conductivity type. Again, the first substrate 100 has a first conductivity type, for example, a p-type. As an example, the impurity of the first conductivity type includes aluminum (Al), boron (B), indium (In), and / or gallium (Ga).

[0026] The first substrate 100 includes a plurality of photoelectric conversion regions PD therein. The photoelectric conversion regions PD are located between the first surface 100a and the second surface 100b of the first substrate 100. The photoelectric conversion regions PD are each provided within a pixel region PX of the first substrate 100. The photoelectric conversion region PD in FIG. 3 is the same as the photoelectric conversion region PD in FIG. 1.

[0027] The photoelectric conversion region PD further includes a group 5 element. The group 5 element is an impurity of a second conductivity type. In other words, the photoelectric conversion region PD is an impurity region of a second conductivity type. The second conductivity type is an n-type different from the first conductivity type. The impurity of the second conductivity type includes phosphorus, arsenic, bismuth, and / or antimony. The photoelectric conversion region PD is adjacent to the first surface 100a of the first substrate 100. The photoelectric conversion region PD extends from the first surface 100a toward the second surface 100b.

[0028] An isolation pattern 200 is provided in the first substrate 100 to define pixel regions PX. For example, the isolation pattern 200 is provided between adjacent pixel regions PX. The isolation pattern 200 is a pixel isolation pattern. The isolation pattern 200 is provided in a first trench 201. The first trench 201 is recessed from the second surface 100b of the first substrate 100 toward the first surface 100a.

[0029] The isolation pattern 200 is a deep trench isolation film. According to the present embodiment, the isolation pattern 200 penetrates the first substrate 100. In another embodiment of the present invention, the isolation pattern 200 does not penetrate the first substrate 100 but is spaced apart from the first surface 100a of the first substrate 100. The width of the isolation pattern 200 adjacent to the second surface 100b is greater than the width of the isolation pattern 200 adjacent to the first surface 100a.

[0030] The color filters CF are disposed on the pixel regions PX on the first surface 100a of the first substrate 100. For example, the color filters CF are provided at positions corresponding to the photoelectric conversion regions PD. In one embodiment of the present invention, each of the color filters CF includes one of a red filter, a blue filter, and a green filter. The color filters CF form a color filter array. For example, the color filters CF are two-dimensionally arranged in a Bayer pattern.

[0031] In another embodiment of the present invention, the color filter CF further includes a white filter, for example, a red filter, a blue filter, a green filter, and a white filter arranged two-dimensionally.

[0032] A fence pattern 300 is disposed on the separation pattern 200. For example, the fence pattern 300 is vertically overlapped with the separation pattern 200. The fence pattern 300 is interposed between two adjacent color filters CF to separate the color filters CF from each other. For example, the fence pattern 300 physically and optically separates the color filters CF from each other.

[0033] The fence pattern 300 has a planar shape corresponding to the separation pattern 200. For example, the fence pattern 300 has a grid shape. In a planar view, the fence pattern 300 surrounds each pixel region PX. The fence pattern 300 surrounds each color filter CF. The fence pattern 300 includes a first portion and a second portion. The first portion extends in parallel to the first direction D1 and is spaced apart from each other in the second direction D2. The second portion extends in parallel to the second direction D2 and is spaced apart from each other in the first direction D1. The second portion intersects with the first portion.

[0034] The fence pattern 300 includes a first fence pattern 310 and a second fence pattern 320. The first fence pattern 310 is disposed between the insulating layer 400 and the second fence pattern 320. The first fence pattern 310 includes a conductive material such as a metal and / or a metal nitride. For example, the first fence pattern 310 includes titanium and / or titanium nitride.

[0035] The second fence pattern 320 is disposed on the first fence pattern 310. The second fence pattern 320 includes a different material from the first fence pattern 310. The second fence pattern 320 includes an organic material. The second fence pattern 320 includes a low refractive index material and has insulating properties.

[0036] The insulating layer 400 is interposed between the first substrate 100 and the color filter CF and between the separation pattern 200 and the fence pattern 300. The insulating layer 400 covers the first surface 100a of the first substrate 100 and the upper surface of the separation pattern 200. The insulating layer 400 is a rear insulating layer. The insulating layer 400 includes a bottom antireflective coating (hereinafter, referred to as BARC) layer. The insulating layer 400 includes a plurality of layers, and the layers of the insulating layer 400 perform different functions.

[0037] As an embodiment of the present invention, the insulating layer 400 includes a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer sequentially stacked on the first surface 100a of the substrate 100. The first insulating layer covers the first surface 100a of the first substrate 100. The first and second insulating layers are fixed charge films. Each of the fixed charge films is made of a metal oxide film or a metal fluoride film. The metal oxide film contains an amount of oxygen that is less than the stoichiometric ratio, and the metal fluoride film contains an amount of fluorine that is less than the stoichiometric ratio.

[0038] For example, the first insulating layer is formed of a metal oxide or metal fluoride containing at least one metal selected from the group including hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium, and lanthanides. The second insulating layer includes a metal oxide or metal fluoride as described in the example of the first insulating layer. However, the second insulating layer includes a material different from that of the first insulating layer. As an example, the first insulating layer includes aluminum oxide, and the second insulating layer includes hafnium oxide.

[0039] Each of the first and second insulating layers has a negative fixed charge, which causes hole accumulation. The first and second insulating layers effectively reduce the generation of dark current and white spots in the first substrate 100. The thickness of the second insulating layer is greater than the thickness of the first insulating layer.

[0040] A third insulating layer is disposed on the second insulating layer. The third insulating layer includes a first silicon-containing material. The first silicon-containing material includes tetraethylorthosilicate (TEOS) or silicon oxide. The third insulating layer has excellent filling properties. The third insulating layer is formed by, for example, but not limited to, plasma enhanced CVD. The thickness of the third insulating layer is greater than the thickness of the first insulating layer and greater than the thickness of the second insulating layer.

[0041] A fourth insulating layer is disposed on the third insulating layer. The fourth insulating layer includes a different material than the third insulating layer. The fourth insulating layer includes a second silicon-containing material, the second silicon-containing material being different than the first silicon-containing material. In one example, the fourth insulating layer includes silicon nitride. A thickness of the fourth insulating layer is greater than a thickness of the third insulating layer.

[0042] A fifth insulating layer is disposed between the fourth insulating layer and the first fence pattern 310 and between the fourth insulating layer and the color filter CF. The fifth insulating layer is in physical contact with the bottom surface of the first fence pattern 310. The fifth insulating layer is an adhesive film or a capping film. The fifth insulating layer includes a high dielectric material or a metal oxide. The fifth insulating layer may include the same material as the second insulating layer. For example, the fifth insulating layer includes hafnium oxide. The thickness of the fifth insulating layer is greater than the thicknesses of the first insulating layer and the second insulating layer, and less than the thicknesses of the third insulating layer and the fourth insulating layer.

[0043] Unlike the above specific examples, the number of layers constituting the insulating layer 400 may be variously modified. For example, at least one of the first to fifth insulating layers may be omitted.

[0044] The protective film 470 covers the insulating layer 400 and the fence pattern 300. The protective film 470 includes a high dielectric material and has insulating properties. For example, the protective film 470 includes aluminum oxide or hafnium oxide. Specifically, the protective film 470 includes, but is not limited to, aluminum oxide. The protective film 470 protects the photoelectric conversion region PD of the first substrate 100 from an external environment such as moisture.

[0045] The color filters CF are provided on the protective film 470. The color filters CF are spaced apart from one another by the fence patterns 300. The top surfaces of the color filters CF are higher than the top surface of the fence patterns 300.

[0046] A microlens layer 500 is provided on the first surface 100a of the first substrate 100. For example, the microlens layer 500 is provided on the color filter CF. A protective film 470 is interposed between the second fence pattern 320 and the microlens layer 500.

[0047] The microlens layer 500 includes a plurality of convex microlenses 510. The microlenses 510 are provided at positions corresponding to the photoelectric conversion regions PD of the first substrate 100. For example, the microlenses 510 are provided on the color filters CF and correspond to the color filters CF. The microlenses 510 form an array arranged along a first direction D1 and a second direction D2 in a plan view. Each of the microlenses 510 protrudes away from the first surface 100a of the first substrate 100. Each of the microlenses 510 has a hemispherical cross section. The microlenses 510 focus incident light.

[0048] Microlens layer 500 is transparent and therefore allows light to pass through. Microlens layer 500 includes an organic material such as a polymer. For example, microlens layer 500 includes a photoresist material or a thermosetting resin.

[0049] A lens coating layer 530 is provided on the microlens layer 500. The lens coating layer 530 is transparent. The lens coating layer 530 conformally covers the top surface of the microlens layer 500. The lens coating layer 530 protects the microlens layer 500.

[0050] The first substrate 100 includes a ground region GND adjacent to a second surface 100b thereof, a floating diffusion region FD, and an impurity region 111. The ground region GND, the floating diffusion region FD, and the impurity region 111 are disposed within each pixel region PX. The bottom surfaces of the ground region GND, the floating diffusion region FD, and the impurity region 111 are vertically spaced apart from the photoelectric conversion region PD.

[0051] The ground region GND is heavily doped with impurities to have a first conductivity type (eg, p+ type), and the floating diffusion region FD and the impurity region 111 are each doped with impurities to have a second conductivity type (eg, n-type).

[0052] The impurity region 111 is an active region for the operation of a transistor, and includes at least one source / drain region of the conversion gain transistor Cx, the reset transistor Rx, the source follower transistor Sx, and the selection transistor Ax described with reference to FIG.

[0053] An isolation pattern 240 is provided adjacent to the second surface 100b of the first substrate 100. The isolation pattern 240 defines an active region within the pixel region PX. Specifically, within the pixel region PX, the isolation pattern 240 defines a ground region GND, a floating diffusion region FD, and an impurity region 111.

[0054] The isolation pattern 240 is provided in the second trench 241, and the second trench 241 is recessed from the second surface 100b of the first substrate 100. The isolation pattern 240 is a shallow isolation STI film. The depth of the isolation pattern 240 is smaller than the depth of the isolation pattern 200. A portion of the isolation pattern 240 is connected to a sidewall of the first isolation pattern 210, which will be described later with reference to FIG. 7. The device isolation pattern 240 includes, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0055] A buried gate pattern 700 is provided on the second surface 100b of the first substrate 100. The buried gate pattern 700 includes a transfer gate TG of the transfer transistor Tx previously described in Figure 1. Although not shown in Figure 3, at least one additional gate pattern is provided on each pixel region PX.

[0056] The additional gate pattern functions as a gate electrode of at least one of the conversion gain transistor Cx, the source follower transistor Sx, the reset transistor Rx, and the selection transistor Ax previously described in Fig. 1. For example, the additional gate pattern includes a conversion gain gate CG, a source follower gate SG, a reset gate RG, or a selection gate AG.

[0057] The buried gate pattern 700 has a buried gate structure. For example, the buried gate pattern 700 includes a first portion 710 and a second portion 720. The first portion 710 of the buried gate pattern 700 is disposed on the second surface 100b of the first substrate 100. The second portion 720 of the buried gate pattern 700 is buried in the first substrate 100. The second portion 720 of the buried gate pattern 700 is connected to the first portion 710. Unlike the illustrated example, the buried gate pattern 700 may have a planar gate structure. In this case, the buried gate pattern 700 may not include the second portion 720. The buried gate pattern 700 includes a metal, a metal silicide, polysilicon, or a combination thereof. In this case, the polysilicon includes doped polysilicon.

[0058] The gate insulating pattern 740 is interposed between the buried gate pattern 700 and the first substrate 100. The gate insulating pattern 740 may include, for example, a silicon-based insulating material (e.g., silicon oxide, silicon nitride, and / or silicon oxynitride) and / or a high-k material (e.g., hafnium oxide and / or aluminum oxide).

[0059] A first pad PAD1 is provided on the ground region GND. The first pad PAD1 is provided on the ground region GND of adjacent pixel regions PX to electrically connect them to each other. The first pad PAD1 includes the first node N1 described in FIG.

[0060] A second pad PAD2 is provided on the floating diffusion region FD. The second pad PAD2 is provided on the ground region GND of the adjacent pixel regions PX to electrically connect them to each other. The second pad PAD2 includes the second node N2 described in FIG.

[0061] The first and second pads PAD1, PAD2 may include a metal, a metal silicide, polysilicon, or a combination thereof. For example, the first and second pads PAD1, PAD2 may include doped polysilicon.

[0062] A first wiring layer 800 is disposed on the second surface 100b of the first substrate 100. The first wiring layer 800 includes a first interlayer insulating film 810, a second interlayer insulating film 820, and a first conductive structure 830. The first interlayer insulating film 810 covers the second surface 100b of the first substrate 100 and the buried gate pattern 700. The second interlayer insulating film 820 is stacked on the first interlayer insulating film 810. The first and second interlayer insulating films 810, 820 include a silicon-based insulating material, such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0063] A first conductive structure 830 is provided in the interlayer insulating films 810 and 820. The first conductive structure 830 includes a contact, a wiring, and a via. The contact is provided in the first interlayer insulating film 810 and is connected to at least one of the buried gate pattern 700, the first and second pads PAD1 and PAD2, and the impurity region 111. The wiring of the first conductive structure 830 is connected to the contact. The via of the first conductive structure 830 penetrates at least one of the second interlayer insulating films 820 and connects the wirings vertically adjacent to each other. A photoelectric signal output from the photoelectric conversion region PD is transmitted to the first conductive structure 830.

[0064] Hereinafter, the circuit chip 20 of the image sensor and the optical black region OBR and pad region PDR of the first substrate 100 will be described. Referring again to FIG. 2 and FIG. 3, the optical black region OBR of the first substrate 100 is interposed between the pixel array region APS and the pad region PDR. The optical black region OBR includes a first reference pixel region RPX1 and a second reference pixel region RPX2. The first reference pixel region RPX1 is disposed between the second reference pixel region RPX2 and the pixel array region APS. In the optical black region OBR, a photoelectric conversion region PD is provided in the first reference pixel region RPX1. The photoelectric conversion region PD of the first reference pixel region RPX1 has the same plane area and volume as the photoelectric conversion region PD of the pixel region PX. The photoelectric conversion region PD is not provided in the second reference pixel region RPX2. An impurity region 111, a buried gate pattern 700, and an isolation pattern 240 are disposed in each of the first and second reference pixel regions RPX1 and RPX2, respectively.

[0065] The insulating layer 400 extends from the pixel array region APS through the optical black region OBR onto the pad region PDR. A light-shielding film 950 is provided on the optical black region OBR. The light-shielding film 950 is disposed on the upper surface of the insulating layer 400. The light-shielding film 950 prevents light from being incident on the photoelectric conversion region PD of the optical black region OBR. The pixels of the first and second reference pixel regions RPX1 and RPX2 of the optical black region OBR do not output photoelectric signals but output noise signals. The noise signals are generated by electrons generated by heat generation, dark current, etc. Since the light-shielding film 950 does not cover the pixel array region APS, light is incident on the photoelectric conversion region PD in the pixel array region APS. The noise signals are removed from the photoelectric signals output from the pixel region PX. The light-shielding film 950 includes a metal such as tungsten, copper, aluminum, or an alloy thereof.

[0066] In the optical black region OBR of the first substrate 100, the first conductive pattern 911 is disposed between the insulating layer 400 and the light-shielding film 950. The first conductive pattern 911 serves as a barrier layer or an adhesion layer. The first conductive pattern 911 includes a metal and / or a metal nitride. For example, the first conductive pattern 911 includes a metal such as copper, tungsten, aluminum, titanium, tantalum, or an alloy thereof. The first conductive pattern 911 does not have to extend onto the pixel array region APS of the first substrate 100.

[0067] In the optical black region OBR of the first substrate 100, a contact plug 960 is provided on the first surface 100a of the first substrate 100. The contact plug 960 is disposed on the outermost isolation pattern 200 in the optical black region OBR. A contact trench penetrating the insulating layer 400 is defined on the first surface 100a of the first substrate 100, and the contact plug 960 is provided in the contact trench.

[0068] The contact plug 960 includes a different material than the light blocking layer 950. For example, the contact plug 960 includes a metal material such as aluminum. The first conductive pattern 911 extends between the contact plug 960 and the insulating layer 400 and between the contact plug 960 and the isolation pattern 200.

[0069] A protective insulating film 471 is provided on the optical black region OBR. The protective insulating film 471 is disposed on an upper surface of the light blocking film 950 and an upper surface of the contact plug 960. The protective insulating film 471 includes the same material as the protective film 470 and is connected to the protective film 470. The protective insulating film 471 is formed integrally with the protective film 470. As another example, the protective insulating film 471 is formed in a process separate from the protective film 470 and is separated from the protective film 470. The protective insulating film 471 includes a high dielectric material (e.g., aluminum oxide and / or hafnium oxide).

[0070] A filtering film 550 is further disposed on the first surface 100a of the optical black region OBR. The filtering film 550 covers the upper surface of the protective insulating film 471. The filtering film 550 blocks light having a wavelength different from that of the color filter CF. For example, the filtering film 550 blocks infrared light. The filtering film 550 includes, but is not limited to, a blue color filter.

[0071] An organic film 501 is provided on the upper surface of the filtering film 550. The organic film 501 is transparent. The upper surface of the organic film 501 is substantially flat. For example, the organic film 501 includes a polymer. The organic film 501 has insulating properties. According to an embodiment of the present invention, unlike the one shown in the figure, the organic film 501 is connected to the microlens layer 500. The organic film 501 includes the same material as the microlens layer 500.

[0072] A coating layer 531 is provided on the organic film 501. The coating layer 531 conformally covers the top surface of the organic film 501. The coating layer 531 includes an insulating material and is transparent. The coating layer 531 includes the same material as the lens coating layer 530.

[0073] The image sensor further includes a circuit chip 20. The circuit chip 20 is stacked on the sensor chip 10. The circuit chip 20 includes a second wiring layer 1800 and a second substrate 1000. The second wiring layer 1800 is interposed between the first wiring layer 800 and the second substrate 1000. An integrated circuit 1700 is disposed on the upper surface of the second substrate 1000 or within the second substrate 1000. The integrated circuit 1700 includes a logic circuit, a memory circuit, or a combination thereof. The integrated circuit 1700 includes, for example, a transistor.

[0074] The second wiring layer 1800 includes a third interlayer insulating film 1820 and a second conductive structure 1830. The second conductive structure 1830 is provided between or within the third interlayer insulating film 1820. The second conductive structure 1830 is electrically connected to the integrated circuit 1700. The second conductive structure 1830 further includes a via pattern, which connects with the second conductive structure 1830 within the third interlayer insulating film 1820.

[0075] The external connection pad 600 is provided on the pad region PDR of the first substrate 100. The external connection pad 600 is adjacent to the first surface 100a of the first substrate 100. The external connection pad 600 is embedded in the first substrate 100. For example, a pad trench 990 is defined on the first surface 100a of the pad region PDR of the first substrate 100, and the external connection pad 600 is provided in the pad trench 990. The external connection pad 600 includes a metal such as aluminum, copper, tungsten, titanium, tantalum, or an alloy thereof. In the mounting process of the image sensor, a bonding wire is formed on the external connection pad 600 to connect with the external connection pad 600. The external connection pad 600 is electrically connected to an external device through the bonding wire.

[0076] A first through hole 901 is defined adjacent to a first side of the external connection pad 600. The first through hole 901 is provided between the external connection pad 600 and the contact plug 960. The first through hole 901 penetrates the insulating layer 400, the first substrate 100, and the first wiring layer 800. The first through hole 901 further penetrates at least a portion of the second wiring layer 1800. The first through hole 901 has a first bottom surface and a second bottom surface. The first bottom surface of the first through hole 901 exposes the first conductive structure 830. The second bottom surface of the first through hole 901 is disposed at a lower level than the first bottom surface. The second bottom surface of the first through hole 901 exposes the second conductive structure 1830.

[0077] The first conductive pattern 911 extends from the optical black region OBR onto the pad region PDR. The first conductive pattern 911 covers the inner wall of the first through hole 901. The first conductive pattern 911 in the first through hole 901 contacts the upper surface of the first conductive structure 830. Therefore, the first conductive structure 830 is electrically connected to the second isolated pattern 220, which will be described later with reference to FIG. 7, through the first conductive pattern 911.

[0078] The first conductive pattern 911 in the first through hole 901 is also connected to the top surface of the second conductive structure 1830. The second conductive structure 1830 is electrically connected to the first conductive structure 830 and the second isolated pattern 220 through the first conductive pattern 911.

[0079] A first filled pattern 921 is provided within the first through hole 901 to fill the first through hole 901. The first filled pattern 921 includes a low refractive index material and has insulating properties. The first filled pattern 921 includes the same material as the first fence pattern 310. The top surface of the first filled pattern 921 has a recess. For example, the center of the top surface of the first filled pattern 921 is lower than its edge.

[0080] A first capping pattern 931 is disposed on the top surface of the first filling pattern 921 to fill the recessed portion. The top surface of the first capping pattern 931 is substantially flat. The first capping pattern 931 includes an insulating polymer, such as a photoresist material.

[0081] A second through hole 902 is defined adjacent to a second side of the external connection pad 600. The second through hole 902 penetrates the insulating layer 400, the first substrate 100, and the first wiring layer 800. The second through hole 902 penetrates a portion of the second wiring layer 1800 to expose the second conductive structure 1830.

[0082] A second conductive pattern 912 is provided on the pad region PDR. The second conductive pattern 912 is provided in the second through hole 902 and conformally covers a sidewall and a bottom surface of the second through hole 902. The second conductive pattern 912 is electrically connected to the second conductive structure 1830.

[0083] The second conductive pattern 912 is interposed between the external connection pad 600 and the pad trench 990, and covers the bottom surface and sidewall of the external connection pad 600. During operation of the image sensor, the integrated circuit 1700 of the circuit chip 20 transmits and receives electrical signals through the second conductive structure 1830, the second conductive pattern 912, and the external connection pad 600.

[0084] A second filled pattern 922 is provided in the second through hole 902 to fill the second through hole 902. The second filled pattern 922 includes a low refractive index material and has insulating properties. For example, the second filled pattern 922 includes the same material as the first fence pattern 310. The top surface of the second filled pattern 922 has a recess.

[0085] A second capping pattern 932 is disposed on the top surface of the second filling pattern 922 to fill the recess. The top surface of the second capping pattern 932 is substantially flat. The second capping pattern 932 includes an insulating polymer, such as a photoresist material.

[0086] The protective insulating film 471 extends from the optical black region OBR onto the pad region PDR. The protective insulating film 471 is provided on the upper surface of the insulating layer 400 and extends into the first through hole 901 and the second through hole 902. The protective insulating film 471 is interposed between the first conductive pattern 911 and the first buried pattern 921 in the first through hole 901. The protective insulating film 471 is interposed between the second conductive pattern 912 and the second buried pattern 922 in the second through hole 902. The protective insulating film 471 exposes the external connection pad 600.

[0087] Figure 4 is a cross-sectional view illustrating an image sensor according to another embodiment of the present invention, taken along line II' in Figure 2. In this embodiment, detailed descriptions of technical features that overlap with those described above with reference to Figures 1 to 3 will be omitted, and differences will be described in detail.

[0088] 2 and 4, the image sensor includes a sensor chip 10 and a circuit chip 20. The sensor chip 10 includes a first connection pad 850. The first connection pad 850 is exposed at the bottom surface of the sensor chip 10. The first connection pad 850 is disposed in the lowermost second interlayer insulating film 820. The first connection pad 850 is electrically connected to the first conductive structure 830. The first connection pad 850 includes a conductive material such as a metal. For example, the first connection pad 850 includes copper. As another example, the first connection pad 850 includes aluminum, tungsten, titanium, and / or an alloy thereof.

[0089] The circuit chip 20 includes a second connection pad 1850. The second connection pad 1850 is exposed on the upper surface of the circuit chip 20. The second connection pad 1850 is disposed in the uppermost third interlayer insulating film 1820. The second connection pad 1850 is electrically connected to the integrated circuit 1700. The second connection pad 1850 includes a conductive material such as a metal. For example, the second connection pad 1850 includes copper. As another example, the second connection pad 1850 includes aluminum, tungsten, titanium, and / or alloys thereof.

[0090] The circuit chip 20 is connected to the sensor chip 10 by direct bonding. For example, the first connection pad 850 and the second connection pad 1850 are vertically aligned with each other, and the first connection pad 850 and the second connection pad 1850 are in contact with each other. Therefore, the second connection pad 1850 is directly bonded to the first connection pad 850. As a result, the integrated circuit 1700 of the circuit chip 20 is electrically connected to the transistor or the external connection pad 600 of the sensor chip 10 through the first and second connection pads 850, 1850.

[0091] The second interlayer insulating film 820 is directly bonded to the third interlayer insulating film 1820. In this case, a chemical bond is formed between the second interlayer insulating film 820 and the third interlayer insulating film 1820.

[0092] The first through hole 901 includes a first through hole portion 91, a second through hole portion 92, and a third through hole portion 93. The first through hole portion 91 penetrates the insulating layer 400, the first substrate 100, and the first wiring layer 800, and has a first bottom surface. The second through hole portion 92 penetrates the insulating layer 400, the first substrate 100, and the first wiring layer 800, and extends into the upper portion of the second wiring layer 1800. The second through hole portion 92 has a second bottom surface, and the second bottom surface exposes the upper surface of the second conductive structure 1830. A sidewall of the second through hole portion 92 is spaced apart from a sidewall of the first through hole portion 91. The third through hole portion 93 is provided between an upper portion of the first through hole portion 91 and an upper portion of the second through hole portion 92, and is connected to an upper portion of the first through hole portion 91 and an upper portion of the second through hole portion 92. A first conductive pattern 911, a protective insulating film 471, and a first filled pattern 921 are provided in the first through hole 901. The first conductive pattern 911 covers the inner walls of the first through hole portion 91, the second through hole portion 92, and the third through hole portion 93.

[0093] Figure 5 is a cross-sectional view illustrating an image sensor according to another embodiment of the present invention, taken along line II-II' in Figure 2. In this embodiment, detailed descriptions of technical features that overlap with those described above with reference to Figures 1 to 4 will be omitted, and differences will be described in detail.

[0094] 2 and 5, the image sensor further includes an intermediate chip 30 interposed between the sensor chip 10 and the circuit chip 20. The intermediate chip 30 includes a third wiring layer 2800 and a third substrate 2000. The third wiring layer 2800 is interposed between the first wiring layer 800 and the third substrate 2000. The second wiring layer 1800 of the circuit chip 20 is provided under the third substrate 2000.

[0095] A driving transistor 2700 is provided on the upper surface of the third substrate 2000. The driving transistor 2700 includes the conversion gain transistor Cx, the reset transistor Rx, the source follower transistor Sx, and the selection transistor Ax described with reference to FIG. 1. That is, according to this embodiment, the photoelectric conversion region PD, the transfer transistor Tx, and the floating diffusion region FD of FIG. 1 are provided in or on the first substrate 100 of the sensor chip 10. The conversion gain transistor Cx, the reset transistor Rx, the source follower transistor Sx, and the selection transistor Ax of FIG. 1 are provided on the third substrate 2000 of the intermediate chip 30.

[0096] The third wiring layer 2800 includes a fourth interlayer insulating film 2820 and a third conductive structure 2830. The third conductive structure 2830 is provided between or within the fourth interlayer insulating film 2820. The third conductive structure 2830 is electrically connected to the driving transistor 2700. The third conductive structure 2830 includes a contact, a line, and a via.

[0097] The sensor chip 10 includes a first connection pad 850. The first connection pad 850 is exposed at the bottom surface of the sensor chip 10. The first connection pad 850 is disposed in the lowermost second interlayer insulating film 820. The first connection pad 850 is electrically connected to the first conductive structure 830.

[0098] The middle chip 30 includes a third connection pad 2850. The third connection pad 2850 is exposed on the upper surface of the middle chip 30. The third connection pad 2850 is disposed in the uppermost fourth interlayer insulating film 2820. The third connection pad 2850 is electrically connected to the driving transistor 2700. The third connection pad 2850 includes a conductive material such as a metal. For example, the third connection pad 2850 includes copper. As another example, the third connection pad 2850 includes aluminum, tungsten, titanium, and / or an alloy thereof.

[0099] The middle chip 30 is connected to the sensor chip 10 by direct bonding. For example, the first connection pad 850 and the third connection pad 2850 are vertically aligned with each other, and the first connection pad 850 and the third connection pad 2850 contact each other. Therefore, the third connection pad 2850 is directly bonded to the first connection pad 850. As a result, the driving transistor 2700 of the middle chip 30 is electrically connected to the floating diffusion region FD of the sensor chip 10 through the first and third connection pads 850 and 2850.

[0100] The second interlayer insulating film 820 is directly bonded to the fourth interlayer insulating film 2820. In this case, a chemical bond is formed between the second interlayer insulating film 820 and the fourth interlayer insulating film 2820.

[0101] The middle chip 30 further includes through vias 2840 that penetrate the third substrate 2000. Each through via 2840 electrically connects the third wiring layer 2800 and the second wiring layer 1800. Again, the middle chip 30 and the circuit chip 20 are electrically connected to each other through the through vias 2840.

[0102] Fig. 6 is a diagram for explaining a color filter and a microlens according to an embodiment of the present invention, and is a plan view showing region M in Fig. 2. Fig. 7 is a cross-sectional view taken along line II' in Fig. 6. In this embodiment, detailed description of technical features that overlap with those previously described with reference to Figs. 1 to 5 will be omitted, and differences will be described in detail.

[0103] 6 and 7, the image sensor includes a first substrate 100. The image sensor further includes an insulating layer 400, a color filter CF, a fence pattern 300, and a microlens layer 500 provided on a first surface 100a of the first substrate 100. In this embodiment, the configuration below the first substrate 100 is omitted, and the detailed description thereof is the same as that described above with reference to FIGS. 3 to 5.

[0104] The pixel array region APS of the first substrate 100 includes a focal pixel region RP and a pixel region PX. In a plan view, the pixel regions PX surround a pair of focal pixel regions RP and are arranged two-dimensionally (see FIG. 6).

[0105] A grid-shaped separation pattern 200 is provided in a first substrate 100. The separation pattern 200 defines a focus pixel region RP and a pixel region PX. Specifically, the separation pattern 200 includes a first separation pattern 210 and a second separation pattern 220.

[0106] The first isolated pattern 210 is interposed between the second isolated pattern 220 and the first substrate 100. For example, the first isolated pattern 210 includes an insulating material such as a silicon oxide film. The second isolated pattern 220 includes a conductive material such as doped polysilicon or a metal. For example, as described above with reference to FIG. 3, the second isolated pattern 220 adjacent to the pad region PDR is electrically connected to the first conductive pattern 911.

[0107] According to the present embodiment, the focus pixel region RP includes a pair of photoelectric conversion regions PD and a separation pattern 200 therebetween. The focus pixel region RP performs a function of correcting the focus of an image output from the pixel region PX, and may not output an image of a subject. For example, the photoelectric conversion regions PD in the focus pixel region RP are spaced apart from each other, and therefore, the lights incident on the photoelectric conversion regions PD in the focus pixel region RP have different phases. The focus of the captured image is corrected by comparing the phase differences of the images acquired in the photoelectric conversion regions PD.

[0108] Specifically, the photoelectric signal output from the focal pixel area RP is compared with the photoelectric signal output from the pixel area PX to correct the focus of the image output from the pixel area PX. Therefore, the image sensor can obtain 3D depth information of the object.

[0109] In another embodiment of the present invention, although not shown, the focus pixel area RP may include three or more photoelectric conversion areas PD, that is, the number of photoelectric conversion areas PD arranged in the focus pixel area RP may be variously modified.

[0110] For example, the color filter CF on the focal pixel region RP may include a red filter, a green filter, or a blue filter, and for another example, the color filter CF on the focal pixel region RP may include a white color filter or a transparent filter.

[0111] 6, the four adjacent color filters CF according to the present embodiment include a first color filter CF1, a pair of second color filters CF2, and a third color filter CF3. For example, the first color filter CF1 is a red filter, the second color filter CF2 is a green filter, and the third color filter CF3 is a blue filter.

[0112] The first color filter CF1, the pair of second color filters CF2, and the third color filter CF3 constitute a color filter array. For example, the first color filter CF1, the pair of second color filters CF2, and the third color filter CF3 are two-dimensionally arranged in a Bayer pattern.

[0113] 7, between the adjacent first and second color filters CF1 and CF2, a fence pattern 300 is provided. A protective layer 470 is interposed between the fence pattern 300 and the first and second color filters CF1 and CF2.

[0114] The protective film 470 according to an embodiment of the present invention includes a first protective film PTL1 and a second protective film PTL2 that are sequentially stacked. The first protective film PTL1 includes a high dielectric material such as aluminum oxide or hafnium oxide. The second protective film PTL2 includes silicon oxide. For example, the second protective film PTL2 is formed by an atomic layer deposition (ALD) process. The second protective film PTL2 is dense and conformal due to the ALD process. The thickness of the second protective film PTL2 is substantially the same as or smaller than the thickness of the first protective film PTL1.

[0115] The top surface of the color filter CF is higher than the top of the second protective layer PTL2. In other words, the color filter CF completely covers the second protective layer PTL2. The fence pattern 300 is separated from the color filter CF by the first and second protective layers PTL1 and PTL2.

[0116] As will be described later in the manufacturing method, the first to third color filters CF1, CF2, and CF3 are formed in sequence. For example, the second color filter CF2, which is a green filter, is formed first, and then the first color filter CF1 is formed. Before forming the first color filter CF1, an etching process is performed to remove the pigment of the second color filter CF2.

[0117] In a comparative example of the present invention, when the second protective film PTL2 is omitted, the pigment on the first protective film PTL1, which is a metal oxide, is not sufficiently removed, resulting in a defect. However, according to an embodiment of the present invention, the pigment on the second protective film PTL2, which is a silicon oxide, is provided on the first protective film PTL1, so that the pigment on the second protective film PTL2 is easily removed. Therefore, defects in the color filter CF can be prevented.

[0118] The second fence pattern 320 includes a low refractive index material formed by a process such as spin coating, and the low refractive index material is porous. Since the second fence pattern 320 is porous, incident light passes through the second fence pattern 320, causing cross-talk between the pixels PX and reducing sensitivity.

[0119] Meanwhile, the second protective layer PTL2 according to the present invention is a dense layer formed through an ALD process and is provided on the second fence pattern 320 to prevent incident light from passing through the second fence pattern 320. Therefore, the present invention can prevent crosstalk between the pixels PX and improve the sensitivity of the image sensor.

[0120] A microlens layer 500 including a microlens 510 is provided on the color filter CF. A lens coating layer 530 is provided on the microlens 510. The microlenses 510 are each provided on the color filter CF. The microlenses 510 include a first microlens 510A, a second microlens 510B, and a third microlens 510C.

[0121] The first and second microlenses 510A and 510B are provided on the pixel regions PX and RP, respectively. The third microlens 510C is an autofocus lens.

[0122] 6, a pair of third microlenses 510C are provided on a pair of focal pixel regions RP, respectively. The pair of third microlenses 510C are adjacent to each other in the second direction D2. The pair of third microlenses 510C are two-dimensionally surrounded by twelve second microlenses 510B. The second microlenses 510B are two-dimensionally surrounded by twenty first microlenses 510A.

[0123] In a plan view, the first to third microlenses 510A, 510B, and 510C have different areas. For example, the area of ​​the first microlens 510A is larger than that of the second microlens 510B. The area of ​​the third microlens 510C is larger than that of the first microlens 510A. The area of ​​each of the second microlenses 510B around the third microlens 510C is reduced by the third microlens 510C, which is the autofocus lens having the largest size. Therefore, the area of ​​the second microlens 510B is smaller than that of the first microlens 510A.

[0124] 7, a first trough (TR1) is defined between a first microlens 510A and an adjacent second microlens 510B. The first microlens 510A has a first crest (CR1) defined at its top. The second microlens 510B has a second crest (CR2) defined at its top.

[0125] A second valley TR2 is defined between the second microlens 510B and the adjacent third microlens 510C. A third valley TR3 is defined between a pair of adjacent third microlenses 510C. The third microlens 510C has a third peak CR3 defined at its top.

[0126] In one embodiment of the present invention, the third peak CR3 is higher than the second peak CR2. The second peak CR2 is higher than the first peak CR1. The third valley TR3 is higher than the second valley TR2. The third valley TR3 is higher than the first valley TR1. The second valley TR2 is higher than the first valley TR1 or is located at the same level as the first valley TR1.

[0127] The level difference between the first valley TR1 and the first peak CR1 is defined as the first height HE1 of the first microlens 510A. The level difference between the first valley TR1 and the second peak CR2 is defined as the second height HE2 of the second microlens 510B. The level difference between the second valley TR2 and the third peak CR3 is defined as the third height HE3 of the third microlens 510C. The third height HE3 is greater than the second height HE2. The second height HE2 is greater than the first height HE1.

[0128] The microlenses according to the present invention have different heights, and the higher the height of the microlens, the more light the microlens receives, and the lower the height of the microlens, the less light the microlens receives.

[0129] Specifically, the third microlens 510C, which is an autofocus lens, has the largest height HE1 and the largest area among the microlenses 510. Therefore, the third microlens 510C receives the largest amount of light among the microlenses 510.

[0130] The second microlens 510B, which is directly adjacent to the third microlens 510C, receives a reduced amount of light due to the third microlens 510C. However, according to an embodiment of the present invention, by making the second height HE2 of the second microlens 510B larger than the first height HE1 of the first microlens 510A, the second microlens 510B can compensate for the reduced amount of light received due to the third microlens 510C.

[0131] As a result, according to the present invention, the difference between the amount of optical signal in a pixel area PX adjacent to the focal pixel area RP and the amount of optical signal in a pixel area PX away from the focal pixel area RP can be compensated for by physically adjusting the height of the microlens 510.

[0132] The lens coating layer 530 according to an embodiment of the present invention includes a first coating layer LTO and a second coating layer ALO. As an example, the first coating layer LTO includes a silicon oxide film formed by a PECVD process. The second coating layer ALO includes a silicon oxide film formed by an ALD process. That is, the first coating layer LTO and the second coating layer ALO include the same silicon-based insulating material.

[0133] The first coating layer LTO is formed by a PECVD process and is therefore a porous film with low density. The first coating layer LTO has the greatest thickness at the peaks of the first to third peaks CR1 to CR3. The first coating layer LTO has the smallest thickness at the bottoms of the first to third valleys TR1 to TR3. Again, the thickness of the first coating layer LTO is non-uniform.

[0134] Meanwhile, since the second coating layer ALO is formed by the ALD process, it has a higher density and is denser than the first coating layer LTO. Since the second coating layer ALO is formed conformally by the ALD process, it has a uniform thickness. For example, the thickness of the second coating layer ALO at the tops of the first to third peaks CR1 to CR3 is substantially the same as the thickness of the second coating layer ALO at the bottoms of the first to third valleys TR1 to TR3. The second coating layer ALO can compensate for the problem that the first coating layer LTO cannot properly cover the first to third valleys TR1 to TR3.

[0135] 8 is a cross-sectional view taken along line II' of FIG. 6, illustrating an image sensor according to a comparative example of the present invention. Referring to FIG. 8, lens coating layer 530 is composed of only first coating layer LTO. That is, second coating layer ALO is omitted from lens coating layer 530. Voids VD are formed in microlens layer 500 through third valley TR3. Since third valley TR3 is deeper than first and second valleys TR1 and TR2, lens coating layer 530 may not be formed correctly in third valley TR3. Therefore, microlens layer 500 is exposed through third valley TR3, and process defects such as voids VD occur.

[0136] 7, the lens coating layer 530 includes not only the first coating layer LTO but also the second coating layer ALO formed by ALD, so that the microlens layer 500 is not exposed through the third valley TR3. Therefore, the present invention can prevent process defects such as voids VD occurring in the microlens layer 500. Therefore, the present invention can improve the reliability and performance of the image sensor.

[0137] 9 to 15 are cross-sectional views taken along line II' of FIG. 6 for explaining a method for manufacturing an image sensor according to an embodiment of the present invention.

[0138] 6 and 9, a first substrate 100 including a focus pixel region RP and a pixel region PX is provided. Specifically, a separation pattern 200 defining the focus pixel region RP and the pixel region PX is formed in the first substrate 100.

[0139] A photoelectric conversion region PD is formed in each of the focus pixel region RP and the pixel region PX by an impurity doping process using an ion implantation process.

[0140] An insulating layer 400 is formed on the planarized first surface 100a of the first substrate 100. In one embodiment of the present invention, forming the insulating layer 400 includes sequentially stacking first to fifth insulating layers on the first surface 100a. The first insulating layer is formed to directly cover the first surface 100a. The first and second insulating layers are fixed charge films. The third insulating layer is formed of a silicon oxide film, and the fourth insulating layer is formed of a silicon nitride film. The fifth insulating layer is an adhesive film or a capping film.

[0141] A light-shielding film 315 and a low-refractive film 325 are sequentially formed on the insulating layer 400. The light-shielding film 315 is formed of a conductive material such as metal and / or metal nitride. The low-refractive film 325 is formed of a low-refractive material having a refractive index of about 1.1 to about 1.3. The low-refractive film 325 includes an organic material and an oxide. The refractive index of the low-refractive film 325 is adjusted by controlling the oxide concentration in the low-refractive film 325. Forming the low-refractive film 325 includes spin-coating a composition including an organic material and a solvent on the light-shielding film 315, and removing the solvent by performing a soft bake process or a drying process.

[0142] 6 and 10, a second fence pattern 320 and a first fence pattern 310 are formed by patterning the low refractive index film 325 and the light blocking film 315. The first and second fence patterns 310 and 320 constitute a fence pattern 300 that defines an area where a color filter is to be formed. The fence pattern 300 has a lattice structure and is vertically overlapped with the separation pattern 200.

[0143] In one embodiment of the present invention, first and second recesses RS1, RS2 are defined by the fence pattern 300. The first and second recesses RS1, RS2 are alternately arranged along the second direction D2.

[0144] A protective film 470 is formed on the fence pattern 300 and the insulating layer 400. Forming the protective film 470 includes sequentially forming a first protective film PTL1 and a second protective film PTL2.

[0145] The first protective layer PTL1 is formed using a CVD process or an ALD process. The first protective layer PTL1 is made of a high dielectric constant material such as aluminum oxide or hafnium oxide. For example, the first protective layer PTL1 is formed to a thickness of 100 Å to 200 Å.

[0146] The second protective film PTL2 is formed on the first protective film PTL1 by using an ALD process. For example, the second protective film PTL2 is made of silicon oxide. The second protective film PTL2 is formed to a thickness of 50 Å to 150 Å.

[0147] 6 and 11, a second color filter CF2 is formed to fill the second recess RS2. The second color filter CF2 is formed directly on the second passivation layer PTL2.

[0148] Specifically, forming the second color filter CF2 includes coating a photoresist composition containing a green pigment on the second protective film PTL2 through a coating process, performing a soft bake process on the photoresist composition, performing an exposure process on the photoresist composition, and developing the photoresist composition to leave the photoresist composition only in the second recess RS2. The photoresist composition containing the green pigment constitutes the second color filter CF2.

[0149] Meanwhile, pigment residue PGR remains in the first recess RS1 from which the photoresist composition has been removed, for example, the pigment residue PGR being a green pigment used in forming the second color filter CF2.

[0150] 6 and 12, a pigment removal process PEP is performed on the first recess RS1 to completely remove the pigment residue PGR in the first recess RS1. The pigment removal process PEP includes an etching process for selectively etching the pigment residue PGR.

[0151] According to an embodiment of the present invention, the pigment residue PGR is attached on the second protective film PTL2. Meanwhile, since the second protective film PTL2 is a silicon oxide film and has low affinity with the pigment residue PGR, the pigment residue PGR on the second protective film PTL2 is easily removed by the pigment removal process PEP. Therefore, the present invention can prevent a process defect in which the pigment residue PGR in the first recess RS1 is not completely removed even after the pigment removal process PEP.

[0152] 6 and 13, a first color filter CF1 is formed to fill the first recess RS1. The first color filter CF1 is formed directly on the second passivation layer PTL2. The formation of the first color filter CF1 is substantially the same as the formation of the second color filter CF2 described above.

[0153] Although not shown in Fig. 13, after the first color filter CF1 is formed, the third color filter CF3 of Fig. 6 is formed. The formation of the third color filter CF3 is substantially the same as the formation of the second color filter CF2 described above.

[0154] A preliminary lens layer 505 is formed on the color filter CF. The preliminary lens layer 505 directly covers the upper surface of the color filter CF. The preliminary lens layer 505 is formed by a spin coating process using a transparent photoresist material or a transparent thermosetting resin.

[0155] 6 and 14, lens mask patterns LMP1 to LMP3 are formed on the preliminary lens layer 505. The lens mask patterns LMP1 to LMP3 include first, second and third lens mask patterns LMP1, LMP2 and LMP3.

[0156] The first and second lens mask patterns LMP1 and LMP2 are formed on the pixel region PX, and the third lens mask pattern LMP3 is formed on the focus pixel region RP.

[0157] The first, second and third lens mask patterns LMP1, LMP2 and LMP3 have different heights. For example, the height of the third lens mask pattern LMP3 is greater than the height of the second lens mask pattern LMP2. The height of the second lens mask pattern LMP2 is greater than the height of the first lens mask pattern LMP1.

[0158] Forming the first to third lens mask patterns LMP1 to LMP3 includes forming a photoresist pattern by a photolithography process and reflowing the photoresist pattern. The reflow process increases the density of the first to third lens mask patterns LMP1 to LMP3, thereby improving chemical resistance. Each of the first to third lens mask patterns LMP1 to LMP3 has a hemispherical shape due to the reflow process.

[0159] 6 and 15, an etching process (eg, an etch-back process) is performed on the first to third lens mask patterns LMP1 to LMP3 and the preliminary lens layer 505 to form a microlens layer 500. As shown in FIG.

[0160] Specifically, the shapes of the first to third lens mask patterns LMP1 to LMP3 are transferred to the preliminary lens layer 505 by an etching process. Therefore, the microlens layer 500 includes first to third microlenses 510A to 510C each having a convex hemispherical shape.

[0161] The first to third microlenses 510A to 510C are transferred from the first to third lens mask patterns LMP1 to LMP3, respectively, and have different heights. First to third valleys TR1 to TR3 are formed between the first to third microlenses 510A to 510C.

[0162] 6 and 7, a first coating layer LTO and a second coating layer ALO are sequentially formed on the microlens layer 500. The first coating layer LTO is formed using a PECVD process. The second coating layer ALO is formed using an ALD process. For example, the second coating layer ALO is formed to a thickness of 50 Å to 1,000 Å. The first and second coating layers LTO and ALO include silicon oxide.

[0163] Since the first coating layer LTO is formed by the PECVD process, the thickness of the first to third valleys TR1, TR2, and TR3 is thin. In particular, the first coating layer LTO may not be formed in the deepest third valley TR3.

[0164] However, since the second coating layer ALO is formed conformally by the ALD process, it is formed with a uniform thickness even in the first to third valleys TR1, TR2, and TR3. Therefore, the second coating layer ALO prevents defects such as the voids VD described above with reference to FIG. 8 so that the microlens layer 500 is not exposed.

[0165] Since the first and second coating layers LTO and ALO contain the same material (eg, silicon oxide), the interface therebetween may not be clearly visible through an electron microscope analysis.

[0166] However, since the first and second coating layers LTO and ALO are formed by different deposition processes, even if they contain the same material, their densities are different. For example, the first coating layer LTO is a porous film and has a lower density than the second coating layer ALO. The second coating layer ALO is a dense film and has a higher density than the first coating layer LTO.

[0167] Figure 16 is a plan view illustrating a color filter and a microlens according to another embodiment of the present invention, showing an M region in Figure 2. Figure 17 is a cross-sectional view taken along line II' in Figure 16. In this embodiment, detailed descriptions of technical features that overlap with those described above with reference to Figures 6 and 7 will be omitted, and differences will be described in detail.

[0168] 16 and 17, the four adjacent color filters CF include a first color filter CF1, a second color filter CF2, a third color filter CF3, and a fourth color filter CF4. For example, the first color filter CF1 is a red filter, the second color filter CF2 is a green filter, the third color filter CF3 is a blue filter, and the fourth color filter is a white filter. The first to fourth color filters CF1 to CF4 are arranged clockwise to form a color filter array. The color filter array composed of the first to fourth color filters CF1 to CF4 is repeatedly arranged.

[0169] 17, the first protective layer PTL1 directly covers the fence pattern 300 and the insulating layer 400. The second protective layer PTL2 is provided to cover not only the first protective layer PTL1 but also the fourth color filter CF4.

[0170] For example, the second protective film PTL2 is interposed between the first color filter CF1 and the first protective film PTL1. The first color filter CF1 does not directly contact the first protective film PTL1, but is separated from the first protective film PTL1 by the second protective film PTL2.

[0171] Meanwhile, the second protective film PTL2 directly covers the upper sidewall CF4S and the top surface CF4T of the fourth color filter CF4 adjacent to the first color filter CF1. The fourth color filter CF4 is in direct contact with the first protective film PTL1. The remaining surfaces CF4S, CF4T of the fourth color filter CF4 that are not covered by the first protective film PTL1 are covered by the second protective film PTL2.

[0172] 18 to 21 are cross-sectional views illustrating a method of manufacturing an image sensor according to another embodiment of the present invention, corresponding to line II' in Fig. 16. In this embodiment, detailed description of the manufacturing method that overlaps with that described above with reference to Figs. 9 and 15 will be omitted, and differences will be described in detail.

[0173] 16 and 18, the second passivation layer PTL2 is omitted from the resultant product of FIG 10. A fourth color filter CF4 is formed on the first passivation layer PTL1. The fourth color filter CF4 fills the second recess RS2.

[0174] Specifically, forming the fourth color filter CF4 includes coating a pigment-free photoresist composition on the first protective film PTL1 in a coating process, performing a soft bake process on the photoresist composition, performing an exposure process on the photoresist composition, and developing the photoresist composition to leave the photoresist composition only in the second recess RS2.

[0175] Since the photoresist composition does not contain a pigment, the fourth color filter CF4 is a white filter. Since the photoresist composition does not contain a pigment, no pigment residue PGR exists in the first recess RS1 even after the fourth color filter CF4 is formed as described above with reference to FIG.

[0176] 16 and 19, a second protective layer PTL2 is formed on the first protective layer PTL1 and the fourth color filter CF4. The second protective layer PTL2 is a silicon oxide layer formed using an ALD process. The second protective layer PTL2 is formed to directly cover the exposed upper sidewall CF4S and the exposed top surface CF4T of the fourth color filter CF4. That is, the fourth color filter CF4 is completely capped by the second protective layer PTL2.

[0177] 16 and 20, a first color filter CF1 is formed to fill the first recess RS1. The first color filter CF1 is formed directly on the second protective layer PTL2. Meanwhile, while the first color filter CF1 is being formed, pigment residue PGR derived from the first color filter CF1 is formed on the top surface CF4T of the fourth color filter CF4.

[0178] 16 and 21, a pigment removal process PEP is performed on the fourth color filter CF4 to completely remove the pigment residue PGR on the fourth color filter CF4. According to an embodiment of the present invention, the pigment residue PGR is attached on the second protective layer PTL2 capping the fourth color filter CF4. Meanwhile, since the second protective layer PTL2 is a silicon oxide layer and has low affinity with the pigment residue PGR, the pigment residue PGR on the second protective layer PTL2 is easily removed by the pigment removal process PEP. Therefore, the present invention can prevent a process defect in which the pigment residue PGR on the fourth color filter CF4 cannot be completely removed even after the pigment removal process PEP.

[0179] 22 is a cross-sectional view corresponding to line I-I' in FIG. 16, illustrating a method for manufacturing an image sensor according to a comparative example of the present invention. Referring to FIG. 22, the formation of the second protective film PTL2 described in FIG. 19 is omitted as a comparative example of the present invention. When the first color filter CF1 is formed, the pigment residue PGR derived from the first color filter CF1 is directly attached onto the upper surface CF4T of the fourth color filter CF4. Meanwhile, since the photoresist material of the fourth color filter CF4 has a high affinity with the pigment residue PGR, the pigment residue PGR cannot be completely removed even through the pigment removal process PEP described above.

[0180] If pigment residue PGR remains on the fourth color filter CF4, the pigment residue PGR reduces the sensitivity of the fourth color filter CF4, causing line-shaped noise in the image output from the image sensor.

[0181] On the other hand, according to an embodiment of the present invention, the pigment residue PGR on the fourth color filter CF4 can be completely removed by forming the second protective layer PTL2 on the fourth color filter CF4, thereby improving the sensitivity of the image sensor and removing the unwanted noise in the output image.

[0182] The above detailed description of the invention is not intended to limit the present invention to the disclosed embodiments, and the present invention can be used in various other combinations, modifications and environments without departing from the spirit and scope of the present invention. [Explanation of symbols]

[0183] 10 Sensor chip 20 Circuit Chip 30 Intermediate Chip 100 First substrate 111 Impurity region 200 Separation Patterns 240 Element isolation pattern 300 fence patterns 310 1st fence pattern 320 1st fence pattern 400 Insulation Layer 470 Protective film 471 Protective insulating film 500 microlens layers 510 Micro Lens 530 Lens Coating Layer 550 Filtering Membrane 600 external connection pad 700 Buried Gate Pattern 740 Gate insulation pattern 800 1st wiring layer 830 First conductive structure 850 1st connecting pad 911 First conductive pattern 921 First embedded pattern 931, 932 1st and 2nd capping patterns 950 Light-shielding film 960 Contact Plug 990 Pad Trench 1000 Second board 1700 Integrated Circuits 1800 2nd wiring layer 1830 Second conductive structure 1850 2nd connecting pad 2000 3rd board 2700 Drive transistor 2800 3rd wiring layer 2830 Third conductive structure 2850 3rd connecting pad ALO 2nd coating layer APS Pixel Array Area CF Color Filter FD Floating diffusion region GND ground area LTO 1st coating layer OBR Optical Black Area PD Photoelectric conversion area PDR Pad Area PTL1 1st protective film PTL2 2nd protective film PX Pixel Area PX1~PX4 pixels RP Focal Pixel Area

Claims

1. A substrate having a first surface and a second surface facing the first surface, The first photoelectric conversion region within the substrate, The second photoelectric conversion region within the substrate, The separation pattern between the first photoelectric conversion region and the second photoelectric conversion region, The fence pattern is arranged on the separation pattern and superimposed perpendicularly with the separation pattern, The aforementioned fence pattern is The first fence pattern on the first surface, The second fence pattern on the first fence pattern, The first protective film on the second fence pattern, The first protective film includes a second protective film on the first protective film, The first protective film covers the left, top, and right sides of the second fence pattern in a cross-sectional view. The second protective film covers the left, top, and right sides of the second fence pattern in a cross-sectional view. The first protective film includes a metal material, The image sensor is characterized in that the second protective film contains a silicon material.

2. The first protective film has a first height on the upper surface of the second fence pattern in a first direction perpendicular to the first surface. The second protective film has a second height on the upper surface of the first protective film in the first direction. The upper surface of the first protective film covers the upper surface of the second fence pattern. The image sensor according to claim 1, characterized in that the first height is different from the second height.

3. The image sensor according to claim 2, characterized in that the first and second protective films include an oxide material.

4. The image sensor according to claim 2, characterized in that the second protective film contains silicon oxide.

5. The image sensor according to claim 2, characterized in that the first protective film contains aluminum oxide.

6. The image sensor according to claim 4, characterized in that the first protective film contains an oxide.

7. Further comprising a color filter, At least a portion of the color filter covers the upper surface of the second protective film. The image sensor according to claim 5, characterized in that the upper surface of the second protective film covers the upper surface of the first protective film.

8. The bottom surface of the second fence pattern has a first width in a second direction perpendicular to the first direction, The upper surface of the second fence pattern has a second width in the second direction perpendicular to the first direction, The first width differs from the second width, The image sensor according to claim 6, characterized in that the bottom surface of the second fence pattern is on the opposite side from the top surface of the second fence pattern in a cross-sectional view.

9. The image sensor according to claim 8, characterized in that the first width is greater than the second width.

10. The image sensor according to claim 9, characterized in that the height of the first fence pattern in the first direction is different from the height of the second fence pattern in the first direction.

11. A substrate having a first surface and a second surface facing the first surface, The first photoelectric conversion region within the substrate, The second photoelectric conversion region within the substrate, A first microlens is arranged so as to overlap perpendicularly with the first photoelectric conversion region within the substrate, A second microlens is positioned so as to overlap perpendicularly with the second photoelectric conversion region within the substrate, The separation pattern between the first photoelectric conversion region and the second photoelectric conversion region, A fence pattern arranged on the separation pattern and superimposed perpendicularly with the separation pattern, including, The aforementioned fence pattern is The first fence pattern on the first surface, The second fence pattern on the first fence pattern, The first protective film on the second fence pattern, The first protective film includes a second protective film on the first protective film, The first protective film covers the left, top, and right sides of the second fence pattern in a cross-sectional view. The second protective film covers the left, top, and right sides of the second fence pattern in a cross-sectional view. The first protective film comprises the first substance, The second protective film contains a second substance different from the first substance, An image sensor characterized in that the height from the first surface to the top of the first microlens in a first direction perpendicular to the first surface is different from the height from the first surface to the top of the second microlens in the first direction.

12. The first protective film has a first height on the upper surface of the second fence pattern in the first direction. The second protective film has a second height on the upper surface of the first protective film in the first direction, and the upper surface of the first protective film covers the upper surface of the second fence pattern. The image sensor according to claim 11, characterized in that the first height is different from the second height.

13. The image sensor according to claim 12, characterized in that the first and second protective films include an oxide material.

14. The image sensor according to claim 13, characterized in that the second protective film contains silicon oxide.

15. The image sensor according to claim 13, characterized in that the first protective film contains aluminum oxide.

16. The image sensor according to claim 14, characterized in that the first protective film contains aluminum oxide.

17. A substrate having a first surface and a second surface facing the first surface, The first photoelectric conversion region within the substrate, The second photoelectric conversion region within the substrate, The separation pattern between the first photoelectric conversion region and the second photoelectric conversion region, A fence pattern arranged on the separation pattern and superimposed perpendicularly with the separation pattern, including, The aforementioned fence pattern is The first fence pattern on the first surface, The second fence pattern on the first fence pattern, The first protective film on the second fence pattern, The first protective film includes a second protective film on the first protective film, The first protective film covers the left, top, and right sides of the second fence pattern in a cross-sectional view. The second protective film covers the left, top, and right sides of the second fence pattern in a cross-sectional view. The first protective film is characterized by containing a metallic substance.

18. The image sensor according to claim 17, characterized in that the first and second protective films contain an oxide.

19. The first protective film has a first height on the upper surface of the second fence pattern in a first direction perpendicular to the first surface. The second protective film has a second height on the upper surface of the first protective film in the first direction, and the upper surface of the first protective film covers the upper surface of the second fence pattern. The image sensor according to claim 17, characterized in that the first height is different from the second height.

20. The image sensor according to claim 17, characterized in that the first protective film contains aluminum oxide.

Images