Sputtering target and method for forming sputtering target

Abstract

To provide a novel sputtering target.SOLUTION: A sputtering target includes a first region and a second region. The first region contains a first metal oxide containing an element M1 (the element M1 is one or more elements selected from Al, Ga, Si, Mg, Zr, and B). The second region contains a second metal oxide containing indium and zinc. The first region and the second region are separated from each other. Each of the first region and the second region is a crystal grain. A crystal grain boundary is observed between the first region and the second region. The diameter of each of the first region and the second region is greater than or equal to 5 nm and smaller than or equal to 10 μm.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an object, a method, or a manufacturing method. The present invention relates to a process, a machine, a manufacture, or a composition of matter. In particular, one embodiment of the present invention relates to a metal oxide, a manufacturing method for the metal oxide, a sputtering target, or a manufacturing method for the sputtering target. One embodiment of the present invention relates to a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.

[0002] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Imaging devices, display devices, liquid crystal display devices, light-emitting devices, electro-optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, and the like), and electronic devices may include semiconductor devices. [Background technology]

[0003] Oxides have been attracting attention as semiconductor materials applicable to transistors. For example, Patent Document 1 discloses a field effect transistor having an amorphous oxide selected from the group consisting of In-Zn-Ga-O-based oxides, In-Zn-Ga-Mg-O-based oxides, In-Zn-O-based oxides, In-Sn-O-based oxides, In-O-based oxides, In-Ga-O-based oxides, and Sn-In-Zn-O-based oxides. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 5118810 Summary of the Invention [Problem to be solved by the invention]

[0005] In Patent Document 1, an active layer of a transistor is formed using an amorphous oxide that is any one of In-Zn-Ga-O oxide, In-Zn-Ga-Mg-O oxide, In-Zn-O oxide, In-Sn-O oxide, In-O oxide, In-Ga-O oxide, and Sn-In-Zn-O oxide. In other words, the active layer of the transistor has an amorphous oxide of any one of the above oxides. If the active layer of the transistor is made of any one of the above amorphous oxides, there is a problem that the on-current, which is one of the electrical characteristics of the transistor, becomes small. Alternatively, if the active layer of the transistor is made of any one of the above amorphous oxides, there is a problem that the reliability of the transistor becomes poor.

[0006] In view of the above problems, an object of one embodiment of the present invention is to provide a novel metal oxide. Another object is to provide a novel sputtering target. Another object is to provide a manufacturing method of a novel sputtering target. Another object is to give good electrical characteristics to a semiconductor device. Another object is to provide a highly reliable semiconductor device. Another object is to provide a semiconductor device with a novel structure. Another object is to provide a display device with a novel structure.

[0007] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0008] One aspect of the present invention is a sputtering target having a first region and a second region. The first region has a first metal oxide containing an element M1 (the element M1 is one or more selected from Al, Ga, Si, Mg, Zr, and B). The second region has a second metal oxide containing indium and an element M2 (the element M2 is one or more selected from Zn, Ti, Ge, Sn, V, Ni, Mo, W, and Ta). The first region and the second region are separated from each other. At least one of the first region and the second region is a crystal grain. A crystal grain boundary is observed between the first region and the second region. The diameter of each of the first region and the second region is 5 nm or more and 10 μm or less.

[0009] In the above sputtering target, the first metal oxide preferably contains indium and zinc in addition to the element M1.

[0010] In the above sputtering target, it is preferable that the element M1 is Ga and the element M2 is Sn.

[0011] One aspect of the present invention is a sputtering target having a first region and a second region. The first region has a first metal oxide containing an element M1 (element M1 is one or more selected from Al, Ga, Si, Mg, Zr, and B). The second region has a second metal oxide containing indium and zinc. The first region and the second region are separated from each other. The first region and the second region are each a crystal grain. A crystal grain boundary is observed between the first region and the second region. The diameter of the first region and the second region is each 5 nm or more and 10 μm or less.

[0012] In the above sputtering target, the first metal oxide preferably contains indium and zinc in addition to the element M1.

[0013] In the above sputtering target, the element M1 is preferably Ga.

[0014] In the above sputtering target, the crystal structure of the first region is preferably different from the crystal structure of the second region.

[0015] One aspect of the present invention includes a step of weighing raw materials for a first sintered body, which are a first indium oxide, an oxide of element M1 (element M1 is one or more selected from Al, Ga, Si, Mg, Zr, and B), and a first zinc oxide, and raw materials for a second sintered body, which are a second indium oxide and a second zinc oxide; a step of mixing the first indium oxide, the oxide of element M1, and the first zinc oxide to prepare a first mixture; a step of forming the first mixture while pressing it to prepare a first molded body; a step of sintering the first molded body to prepare a first sintered body; and a step of powdering the first sintered body to prepare a second sintered body. The method for producing a sputtering target includes the steps of: preparing a first powder; mixing a second indium oxide and a second zinc oxide to prepare a second mixture; pressing the second mixture while molding it to prepare a second molded body; firing the second molded body to prepare a second fired body; powdering the second fired body to prepare a second powder; mixing the first powder and the second powder to prepare a third mixture; and pressing the third mixture while molding it to prepare a third molded body, in which a step of firing the third molded body is not performed after the step of preparing the third molded body.

[0016] One aspect of the present invention includes a step of weighing raw materials for a first sintered body, which are a first indium oxide, an oxide of element M1 (element M1 is one or more selected from Al, Ga, Si, Mg, Zr, and B), and a first zinc oxide, and raw materials for a second sintered body, which are a second indium oxide and a second zinc oxide; a step of mixing the first indium oxide, the oxide of element M1, and the first zinc oxide to prepare a first mixture; a step of forming the first mixture while applying pressure to prepare a first molded body; a step of sintering the first molded body to prepare a first sintered body; a step of powdering the first sintered body to prepare a first powder; and a step of mixing the second indium oxide, the oxide of element M1, and the first zinc oxide to prepare a first mixture. a step of mixing a first zinc oxide and a second zinc oxide to prepare a second mixture, a step of pressing the second mixture while molding it to prepare a second molded body, a step of firing the second molded body to prepare a second fired body, a step of powderizing the second fired body to prepare a second powder, a step of mixing the first powder and the second powder to prepare a third mixture, a step of pressing the third mixture while molding it to prepare a third molded body, and a step of firing the third molded body to prepare a third fired body, wherein the temperature at which the third powder is fired is a temperature at which a portion of the first powder and a portion of the second powder do not combine with each other.

[0017] In the above-mentioned method for producing a sputtering target, the temperature at which the third molded body is fired is preferably lower than both the temperature at which the first molded body is fired and the temperature at which the second molded body is fired.

[0018] One aspect of the present invention includes a step of weighing raw materials for a first sintered body, which are a first indium oxide, an oxide of element M1 (element M1 is one or more selected from Al, Ga, Si, Mg, Zr, and B), and zinc oxide, and raw materials for a second sintered body, which are a second indium oxide and an oxide of element M2 (element M2 is one or more selected from Ti, Ge, Sn, V, Ni, Mo, W, and Ta), a step of mixing the first indium oxide, the oxide of element M1, and the zinc oxide to prepare a first mixture, a step of pressing the first mixture while molding it to prepare a first molded body, and a step of sintering the first molded body to prepare a first sintered body. a step of powdering the first sintered body to produce a first powder, a step of mixing a second indium oxide and an oxide of element M2 to produce a second mixture, a step of pressing the second mixture while molding it to produce a second molded body, a step of sintering the second molded body to produce a second sintered body, a step of powdering the second sintered body to produce the second powder, a step of mixing the first powder and the second powder to produce a third mixture, and a step of pressing the third mixture while molding it to produce a third molded body, wherein the step of sintering the third molded body is not performed after the step of producing the third molded body.

[0019] One aspect of the present invention includes a step of weighing raw materials for a first sintered body, which are a first indium oxide, an oxide of element M1 (element M1 is one or more selected from Al, Ga, Si, Mg, Zr, and B), and zinc oxide, and raw materials for a second sintered body, which are a second indium oxide and an oxide of element M2 (element M2 is one or more selected from Ti, Ge, Sn, V, Ni, Mo, W, and Ta), a step of mixing the first indium oxide, the oxide of element M1, and the zinc oxide to prepare a first mixture, a step of forming the first mixture while pressing it to prepare a first molded body, a step of sintering the first molded body to prepare a first sintered body, and a step of powdering the first sintered body to prepare a second sintered body. a step of mixing a second indium oxide and an oxide of element M2 to prepare a second mixture, a step of pressing the second mixture while molding it to prepare a second molded body, a step of firing the second molded body to prepare a second fired body, a step of powderizing the second fired body to prepare a second powder, a step of mixing the first powder and the second powder to prepare a third mixture, a step of pressing the third mixture while molding it to prepare a third molded body, and a step of firing the third molded body to prepare a third fired body, wherein the temperature at which the third molded body is fired is a temperature at which a portion of the first powder and a portion of the second powder do not combine with each other.

[0020] In the above-mentioned method for producing a sputtering target, the temperature at which the third molded body is fired is preferably lower than both the temperature at which the first molded body is fired and the temperature at which the second molded body is fired.

[0021] One aspect of the present invention is a method for producing a sputtering target, comprising the steps of: weighing an oxide of element M1 (element M1 is one or more selected from Al, Ga, Si, Mg, Zr, and B) and indium oxide and zinc oxide, which are raw materials for a first sintered body; mixing indium oxide and zinc oxide to produce a first mixture; molding the first mixture while applying pressure to produce a first molded body; sintering the first molded body to produce a first sintered body; powdering the first sintered body to produce a first powder; mixing the oxide of element M1 and the first powder to produce a second mixture; and molding the second mixture while applying pressure to produce a second molded body, wherein a step of sintering the second molded body is not performed after the step of producing the second molded body.

[0022] One aspect of the present invention includes a step of weighing an oxide of element M1 (element M1 is one or more selected from Al, Ga, Si, Mg, Zr, and B) and indium oxide and zinc oxide, which are raw materials for a first fired body; a step of mixing indium oxide and zinc oxide to prepare a first mixture; a step of forming the first mixture while pressing it to prepare a first molded body; a step of firing the first molded body to prepare a first fired body; The method for producing a sputtering target includes the steps of: powdering the sintered body of M1 to produce a first powder; mixing an oxide of element M1 with the first powder to produce a second mixture; molding the second mixture while applying pressure to produce a second molded body; and sintering the second molded body to produce a second sintered body, wherein the temperature at which the second molded body is sintered is a temperature at which a portion of the oxide of element M1 and a portion of the first powder do not combine with each other.

[0023] In the above-mentioned method for producing a sputtering target, the temperature at which the second molded body is fired is preferably lower than the temperature at which the first molded body is fired. Effect of the Invention

[0024] According to one embodiment of the present invention, a novel metal oxide can be provided. Alternatively, a novel sputtering target can be provided. Alternatively, a manufacturing method for a novel sputtering target can be provided. Alternatively, favorable electrical characteristics can be imparted to a semiconductor device. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a semiconductor device with a novel structure can be provided. Alternatively, a display device with a novel structure can be provided.

[0025] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract effects other than these from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0026] [Figure 1] 1(A) to 1(D) are schematic diagrams of sputtering targets. [Diagram 2] FIG. 2 is a flow chart of a method for producing a sputtering target. [Diagram 3] FIG. 3 is a flowchart of a method for producing a sputtering target. [Figure 4] FIG. 4 is a flowchart of a method for producing a sputtering target. [Diagram 5] 5(A) and 5(B) are flowcharts of a method for producing a sputtering target. [Figure 6] 6(A) and 6(B) are flowcharts of a method for producing a sputtering target. [Figure 7] FIG. 7 is a flowchart of a method for producing a sputtering target. [Figure 8] 8(A) and 8(B) are diagrams illustrating the range of the atomic ratio of a metal oxide according to one embodiment of the present invention. [Figure 9] FIG. 9 is a schematic diagram illustrating a sputtering apparatus. [Figure 10] 10(A) and 10(B) are schematic diagrams of film formation using a sputtering target. [Figure 11] FIG. 11 is a conceptual diagram illustrating the structure of a metal oxide. [Figure 12] Fig. 12(A) is a top view showing an example of a semiconductor device, Fig. 12(B) and Fig. 12(C) are cross-sectional views showing an example of a semiconductor device, and Fig. 12(D) is a cross-sectional image view. [Figure 13] 13A and 13B are cross-sectional views showing an example of a semiconductor device. [Figure 14] 14(A) and 14(B) are cross-sectional views showing an example of a semiconductor device. [Figure 15] 15(A) and 15(B) are cross-sectional views showing an example of a semiconductor device. [Figure 16] Fig. 16A is a top view illustrating an example of a semiconductor device, Fig. 16B and Fig. 16C are cross-sectional views illustrating an example of the semiconductor device. [Figure 17] Fig. 17A is a top view illustrating an example of a semiconductor device, and Fig. 17B is a cross-sectional view illustrating an example of the semiconductor device. [Figure 18] FIG. 18 is a cross-sectional view showing an example of a semiconductor device. [Figure 19] FIG. 19 is a cross-sectional view showing an example of a semiconductor device. [Figure 20] Fig. 20A is a top view illustrating an example of a semiconductor device, and Fig. 20B is a cross-sectional view illustrating an example of a semiconductor device. [Figure 21] 21(A) and 21(B) are cross-sectional views showing an example of a semiconductor device. [Figure 22] 22A is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention, and FIG 22B is a perspective view illustrating a configuration example of a storage device according to one embodiment of the present invention. [Figure 23] 23A to 23I are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Figure 24] FIG. 24 is a cross-sectional view showing an example of a storage device. [Diagram 25] FIG. 25 is a cross-sectional view showing an example of a storage device. [Figure 26] FIG. 26 is a cross-sectional view showing an example of a storage device. [Figure 27] FIG. 27 is a diagram illustrating an example of a circuit configuration of a memory cell. [Figure 28] 28(A) and 28(B) are diagrams showing an example of an electronic component. [Figure 29] 29(A) and 29(B) are diagrams showing an example of an electronic device, and FIGS. 29(C) to 29(E) are diagrams showing an example of a mainframe computer. [Diagram 30] FIG. 30 is a diagram showing an example of space equipment. [Diagram 31] FIG. 31 is a diagram illustrating an example of a storage system applicable to a data center. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0028] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated explanations are omitted. In addition, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be used.

[0029] In addition, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0030] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking). In addition, an ordinal number attached to a component in one part of this specification may not match an ordinal number attached to the same component in another part of this specification or in the claims.

[0031] The words "film" and "layer" can be interchanged depending on the circumstances. For example, the term "conductive layer" can be interchanged with the term "conductive film". Or, for example, the term "insulating film" can be interchanged with the term "insulating layer". Furthermore, the term "conductor" can be interchanged with the term "conductive layer" or the term "conductive film" depending on the circumstances. Furthermore, the term "insulating body" can be interchanged with the term "insulating layer" or the term "insulating film" depending on the circumstances.

[0032] The openings include, for example, grooves, slits, etc. Furthermore, a region in which an opening is formed may be referred to as an opening portion.

[0033] Although the drawings used in this embodiment mode show the case where the sidewall of the insulator in the opening portion is approximately perpendicular to the substrate surface or the surface on which the insulator is formed, the sidewall may have a tapered shape.

[0034] In this specification, the term "tapered shape" refers to a shape in which at least a part of the side of the structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle between the inclined side and the substrate surface or the surface to be formed (hereinafter, sometimes referred to as the taper angle) is less than 90°. The side of the structure and the substrate surface do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with fine irregularities.

[0035] In this specification, "the heights are the same" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as a substrate surface) are the same in a cross-sectional view. For example, in a manufacturing process of a semiconductor device, a planarization process (typically a CMP (Chemical Mechanical Polishing) process) may be performed to expose the surface of a single layer or multiple layers. In this case, the surfaces to be processed in the CMP process have a configuration in which the heights from the reference surface are the same. However, the heights of multiple layers may differ depending on the processing device, processing method, or material of the processed surface during the CMP process. In this specification, this case is also treated as "the heights are the same". For example, when there are two layers (here, a first layer and a second layer) having different heights with respect to the reference surface, and the difference between the height of the top surface of the first layer and the height of the top surface of the second layer is 20 nm or less, this is also referred to as "the heights are the same".

[0036] In this specification, the term "ends coincide" refers to at least a portion of the contours of stacked layers overlapping when viewed from above. For example, this term includes cases where the upper and lower layers are processed using the same mask pattern or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the term "ends coincide" is also used.

[0037] Generally, it is difficult to clearly distinguish between a "complete match" and a "broad match." For this reason, in this specification and elsewhere, "match" includes both a complete match and a broad match.

[0038] In this specification and the like, the normally-on characteristic refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, whereas the normally-off characteristic refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0039] In this specification, the term "leakage current" may be used to mean the same thing as "off-state current." In this specification, the term "off-state current" may refer to, for example, a current that flows between a source and a drain when a transistor is in an off state.

[0040] (Embodiment 1) In this embodiment, a metal oxide according to one embodiment of the present invention, a sputtering target for depositing the metal oxide, and a method for manufacturing the sputtering target will be described.

[0041] The metal oxide shown in this embodiment preferably has two or three selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a higher bond energy with oxygen than indium. Specific examples of the element M include aluminum (Al), gallium (Ga), tin (Sn), yttrium, titanium (Ti), vanadium (V), chromium, manganese, iron, cobalt, nickel (Ni), zirconium (Zr), molybdenum (Mo), hafnium, tantalum (Ta), tungsten (W), lanthanum, cerium, neodymium, magnesium (Mg), calcium, strontium, barium, boron (B), silicon (Si), germanium (Ge), and antimony. The element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. In this specification, metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification may include metalloid elements.

[0042] Examples of the metal oxide shown in this embodiment include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also written as GZO), aluminum zinc oxide (Al-Zn oxide), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO or IAGZO). Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), or the like can be used.

[0043] In a metal oxide, the field-effect mobility of a transistor can be increased by increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of the main component metal elements. Note that the main component in a metal oxide refers to an element whose ratio to the elements contained in the metal oxide is 1 atomic % or more, for example.

[0044] Note that the metal oxide can have one or more metal elements having a large period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including a metal element having a large period number in the periodic table, the field effect mobility of the transistor can be increased in some cases. Examples of metal elements having a large period number in the periodic table include metal elements belonging to the 5th period and metal elements belonging to the 6th period. Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0045] The metal oxide may contain one or more nonmetallic elements. When the metal oxide contains a nonmetallic element, the field effect mobility of the transistor may be increased. Examples of the nonmetallic element include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0046] In addition, by increasing the ratio of the number of zinc atoms to the total number of atoms of the main metal elements in the metal oxide, the metal oxide can be made highly crystalline and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing the fluctuation of the electrical characteristics of the transistor and improving its reliability.

[0047] In addition, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of the main component metal elements in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. In addition, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0048] Specifically, the metal oxide may have a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, In:M:Zn=2:1:3 [atomic ratio] or a composition close thereto, or In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto. Note that the composition close thereto includes a range of ±30% of the desired atomic ratio. It is also preferable to use gallium as the element M.

[0049] In addition, when a metal oxide film is formed by a sputtering method, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0050] As described above, the electrical characteristics and reliability of a transistor using a metal oxide differ depending on the composition of the metal oxide. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required for a transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0051] The metal oxide described in this embodiment contains oxygen and two or more elements selected from elements other than oxygen. Here, the two or more elements selected from the elements other than oxygen are preferably selected from indium (In), an element selectable as the element M, and zinc (Zn). For example, the two or more elements selected from the elements other than oxygen may be selected from In, Al, Ga, Si, Mg, Zr, B, Ti, Ge, Sn, V, Ni, Mo, W, Ta, and Zn.

[0052] Here, consider the case where the metal oxide has oxygen and three elements selected from elements other than oxygen. Hereinafter, the three elements selected from elements other than oxygen may be expressed as element M1, element M2, and element M3. In this case, the metal oxide has oxygen, element M1, element M2, and element M3. In addition, the terms of the atomic ratio of element M1, element M2, and element M3 may be expressed as [M1], [M2], and [M3], respectively.

[0053] The element M1 is one selected from indium, an element that can be selected as the element M, and zinc, the element M2 is one selected from indium, an element that can be selected as the element M, and zinc and is an element different from the element M1, and the element M3 is one selected from indium, an element that can be selected as the element M, and zinc and is an element different from the elements M1 and M2.

[0054] In addition, when a metal oxide has oxygen and two elements selected from elements other than oxygen, the two elements selected from elements other than oxygen may be expressed as element M1 and element M2. In addition, when a metal oxide has oxygen and four elements selected from elements other than oxygen, the four elements selected from elements other than oxygen may be expressed as element M1, element M2, element M3, and element M4. In addition, when a metal oxide has oxygen and five or more elements selected from elements other than oxygen, the five or more elements selected from elements other than oxygen may be expressed in the same manner.

[0055] <Sputtering target> First, a sputtering target for forming a metal oxide film by a sputtering method will be described with reference to Fig. 1(A) to Fig. 1(D). Fig. 1(A) to Fig. 1(D) show cross-sectional views of a sputtering target 10 for forming a metal oxide film by a sputtering method.

[0056] The sputtering target 10 contains elements contained in metal oxides because it is used when forming a film of a metal oxide by a sputtering method. For example, when a metal oxide film formed using the sputtering target 10 contains elements M1 to M3, the sputtering target 10 contains elements M1 to M3.

[0057] The sputtering target 10 has a first region 11 and a second region 12. The first region 11 and the second region 12 are separated from each other.

[0058] In this specification, the phrase "two regions are separated from each other" can be rephrased as "two regions are distant from each other." Note that "distant" means that two regions are physically separated from each other, but in this specification, the term "distant" also refers to a state in which two regions are close to each other, adjacent to each other, or in contact with each other.

[0059] The sputtering target 10 preferably has a crystalline structure in part. For example, it may have a polycrystalline structure in part. The polycrystalline structure is composed of a plurality of minute single crystals (also called crystal grains, crystallites, or microcrystals). FIG. 1(A) shows an example in which the first region 11 and the second region 12 are crystal grains. When the first region 11 and the second region 12 are crystal grains, the first region 11 can be called the first crystal grains, and the second region 12 can be called the second crystal grains. The first crystal grains described below can be called the first region 11, and the second crystal grains can be called the second region 12.

[0060] When the first region 11 and the second region 12 are each a crystal grain, a crystal grain boundary is observed between the adjacent first region 11 and second region 12. Note that a crystal grain boundary may be observed between adjacent first regions 11 or between adjacent second regions 12. Furthermore, it is preferable that the diameters (diameters of crystal grains) of the first region 11 and the second region 12 are 3 nm or more, or 5 nm or more, respectively, and 10 μm or less, 1 μm or less, 100 nm or less, or 10 nm or less. Note that the diameter of a crystal grain is defined as the maximum value of a straight line connecting two points on the outer contour of a crystal grain.

[0061] The grain boundary refers to the region between the crystal grains. The grain boundary refers to, for example, a portion where the crystal grains are stuck together, a portion where the crystal orientation changes inside the sputtering target 10, that is, a portion where the arrangement of atomic columns in a STEM (Scanning Transmission Electron Microscope) image is discontinuous, a portion containing many crystal defects, a portion where the crystal structure is disordered, etc. The crystal defect refers to a defect that can be observed in a cross-sectional TEM (Transmission Electron Microscope) image, a cross-sectional STEM image, etc., that is, a structure in which other elements have entered between the lattices, a cavity, etc. The grain boundary can be said to be one of the plane defects.

[0062] In addition, when the sputtering target 10 has a crystalline structure in part and the first region 11 and the second region 12 each have microcrystals, it is preferable that the diameter of the microcrystals is 0.5 nm or more and 3 nm or less, or 1 nm or more and 2 nm or less, or a value close to these values.

[0063] 1(B), the first region 11 and the second region 12 may each be particulate. In this case, it is preferable that the diameter of each of the first region 11 and the second region 12 is less than 10 μm. Note that the particulate shape refers to a shape in which the outline in the cross section is composed only of curved lines, or a shape composed of a combination of straight lines and curved lines.

[0064] In sputtering target 10, the combination of elements contained in first region 11 is preferably different from the combination of elements contained in second region 12. For example, it is preferable that at least one of the elements contained in first region 11 is not contained in second region 12. In addition, it is preferable that at least one of the elements contained in second region 12 is not contained in first region 11.

[0065] The combination of elements contained in first region 11 may be the same as the combination of elements contained in second region 12. In this case, first region 11 and second region 12 preferably have different compositions.

[0066] The first crystal grains and the second crystal grains preferably have different crystal structures. In addition, the microcrystals in the first region 11 and the microcrystals in the second region 12 preferably have different crystal structures. For example, In-Ga-Zn oxide has various crystal structures such as a Bixbyite structure, a Spinel structure, a Wurtzite structure, a YbFe2O4 structure, and a Yb2Fe3O7 structure depending on its composition. Therefore, when the composition of the first region 11 and the composition of the second region 12 are different, the crystal structure of the first crystal grains may be different from the crystal structure of the second crystal grains. In addition, the crystal structure of the microcrystals in the first region 11 may be different from the crystal structure of the microcrystals in the second region 12. In other words, the sputtering target 10 having two or more types of crystal structures may have the first region 11 and the second region 12.

[0067] The crystal structure of the sputtering target 10 can be evaluated by an XRD pattern observed by an X-ray diffraction (XRD) method. For example, when a structure analysis is performed using an XRD device on the sputtering target 10 having the first region 11 and the second region 12 with different crystal structures, an XRD pattern derived from the first region 11 and an XRD pattern derived from the second region 12 are observed. When the first crystal grains or the second crystal grains, or the microcrystals in the first region 11 or the second region 12 are very small, the above two XRD patterns may not be observed.

[0068] Alternatively, the crystal structure of the sputtering target 10 can be evaluated by a diffraction pattern (also called a nano beam electron diffraction pattern) observed by nano beam electron diffraction (NBED). For example, when NBED is performed on the sputtering target 10 having the first region 11 and the second region 12 with different crystal structures, a diffraction pattern derived from the crystal structure of the first crystal grains or the microcrystals of the first region 11 and a diffraction pattern derived from the crystal structure of the second crystal grains or the microcrystals of the second region 12 are observed to be different from each other.

[0069] As described above, the electrical characteristics and reliability of a transistor using a metal oxide vary depending on the composition of the metal oxide. Therefore, by setting the composition of the metal oxide according to the electrical characteristics and reliability required for the transistor, a transistor having both excellent electrical characteristics and high reliability and a semiconductor device having the transistor can be obtained. In other words, by varying the ratio of the first region 11 and the second region 12 contained in the sputtering target 10, or by varying the composition of the first region 11 and the composition of the second region 12 according to the electrical characteristics and reliability required for the transistor, a transistor having both excellent electrical characteristics and high reliability and a semiconductor device having the transistor can be obtained.

[0070] In the above-mentioned configuration, the first region 11 has a first metal oxide, and the second region 12 has a second metal oxide. At this time, two solid phases, the first metal oxide and the second metal oxide, exist in the sputtering target 10. Note that in this specification and the like, the first region 11 or the first crystal grains may be referred to as the first metal oxide, and the first metal oxide may be referred to as the first region 11 or the first crystal grains. Similarly, the second region 12 or the second crystal grains may be referred to as the second metal oxide, and the second metal oxide may be referred to as the second region 12 or the second crystal grains.

[0071] Here, a case where the sputtering target 10 is an oxide target containing elements M1 to M3 will be described.

[0072] The first region 11 preferably contains the element M1. The first region 11 may also contain an oxide of the element M1. For example, the first region 11 contains an oxide of the element M1. In this case, the oxide of the element M1 can be said to be the first metal oxide contained in the first region 11. In other words, the first region 11 has a first metal oxide containing the element M1.

[0073] The second region 12 preferably contains the element M2. The second region 12 may also contain an oxide of the element M2. For example, the second region 12 contains an oxide of the element M2. In this case, the oxide of the element M2 can be said to be the second metal oxide contained in the second region 12. In other words, the second region 12 has the second metal oxide containing the element M2.

[0074] The element M3 is contained in one or both of the first region 11 and the second region 12.

[0075] For example, when element M3 is contained in first region 11, first region 11 contains element M1 and element M3. For example, first region 11 contains M1-M3 oxide. In this case, M1-M3 oxide can be said to be the first metal oxide contained in first region 11. In other words, first region 11 has a first metal oxide containing element M1 and element M3. Note that first region 11 may contain one or both of an oxide of element M1 and an oxide of element M3.

[0076] Furthermore, for example, when the element M3 is contained in the second region 12, the second region 12 contains the elements M2 and M3. For example, the second region 12 contains an M2-M3 oxide. In this case, the M2-M3 oxide can be said to be the second metal oxide contained in the second region 12. In other words, the second region 12 has a second metal oxide containing the elements M2 and M3. Note that the second region 12 may contain one or both of an oxide of the element M2 and an oxide of the element M3.

[0077] The first region 11 may contain elements M2 and M3 in addition to the element M1. The first region 11 may contain oxides of the elements M1 to M3. For example, the first region 11 contains an M1-M2-M3 oxide. In this case, the M1-M2-M3 oxide can be said to be the first metal oxide contained in the first region 11. That is, the first region 11 has a first metal oxide containing the elements M1 to M3. The first region 11 may contain one or more of an oxide of the element M1, an oxide of the element M2, an oxide of the element M3, an M1-M2 oxide, an M1-M3 oxide, and an M2-M3 oxide.

[0078] The composition of the sputtering target 10 is determined by the respective compositions of the first region 11 and the second region 12, and the ratio of the first region 11 to the second region 12. For example, if the first region 11 has an oxide of element M1, the second region 12 has a metal oxide with [M2]:[M3]=1:2 [atomic ratio], and the molar ratio of the first region 11 to the second region 12 in the sputtering target 10 is 1:2, the composition of the sputtering target 10 will be [M2]:[M1]:[M3]=2:1:4 [atomic ratio] or a composition close thereto.

[0079] Furthermore, the atomic ratio of the metal oxide film formed using sputtering target 10 varies within ±40% of the atomic ratio of the metal elements contained in sputtering target 10.

[0080] As described above, the metal oxide may contain one or more nonmetallic elements. For example, when the metal oxide contains nitrogen, one or both of the first region 11 and the second region 12 may contain nitrogen. In this case, for example, when the first region 11 contains the element M1 and nitrogen, the first region 11 contains at least one of an oxynitride of the element M1, a nitridized oxide of the element M1, and a nitride of the element M1. The first region 11 may also contain an oxide of the element M1.

[0081] In this specification, an oxynitride refers to a material having a composition in which oxygen is contained more than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained more than oxygen.

[0082] The sputtering target 10 may include a first region 11 and a second region 12. For example, as shown in FIG. 1(C), the sputtering target 10 may include a third region 13 in addition to the first region 11 and the second region 12. The third region 13 includes a third metal oxide formed by combining a part of the first metal oxide with a part of the second metal oxide. That is, the third metal oxide has an element included in the first metal oxide and an element included in the second metal oxide. In this case, the third metal oxide has a composition different from that of each of the first metal oxide and the second metal oxide.

[0083] When the third region 13 is a crystal grain, crystal grain boundaries are observed between adjacent third regions 13 and first regions 11, and between adjacent third regions 13 and second regions 12. The crystal structure of the third region 13 may be the same as one of the first crystal grains and the second crystal grains, or may be different from the crystal structures of the first crystal grains and the second crystal grains.

[0084] In addition, as shown in Figure 1 (D), in a sputtering target 10 including a first region 11, a second region 12, and a third region 13, the first region 11 may be surrounded by a plurality of third regions 13, and the second region 12 may be surrounded by a plurality of third regions 13.

[0085] The metal oxide formed by combining all of the first metal oxide with a portion of the second metal oxide may be considered to be the first metal oxide contained in the first region 11 of the sputtering target 10. Alternatively, the metal oxide formed by combining a portion of the first metal oxide with all of the second metal oxide may be considered to be the second metal oxide contained in the second region 12 of the sputtering target 10.

[0086] For example, when element M1 is Ga, element M2 is In, and element M3 is Zn, first region 11 preferably contains one or more of gallium oxide, Ga-Zn oxide, and In-Ga-Zn oxide, and second region 12 preferably contains one or both of indium oxide and In-Zn oxide. Note that when sputtering target 10 includes third region 13, third region 13 contains In-Ga-Zn oxide.

[0087] Also, for example, when element M1 is Al, element M2 is In, and element M3 is Zn, first region 11 preferably contains one or more of aluminum oxide, Al-Zn oxide, and In-Al-Zn oxide, and second region 12 preferably contains one or both of indium oxide and In-Zn oxide.

[0088] When the sputtering target 10 contains the elements M1 to M4, the element M4 is contained in one or both of the first region 11 and the second region 12.

[0089] For example, when one of the elements M2 and M4 is In and the other of the elements M2 and M4 is one selected from Ti, Ge, Sn, V, Ni, Mo, W, and Ta, it is preferable that the elements M2 and M4 are contained in the second region 12. In this case, the first region 11 has an oxide containing the element M1, and the second region 12 has an oxide containing the element M2 and the element M4. In addition, one or both of the elements M2 and M4 may be contained in the first region 11. Note that the element M3 is contained in one or both of the first region 11 and the second region 12.

[0090] As a specific example, when element M1 is Ga, one of element M2 and element M4 is In, element M3 is Zn, and the other of element M2 and element M4 is Sn, first region 11 preferably contains one or more of gallium oxide, Ga-Zn oxide, In-Ga-Zn oxide, and Ga-Sn-Zn oxide, and second region 12 preferably contains one or both of In-Sn oxide and In-Sn-Zn oxide.

[0091] Alternatively, for example, when one of the elements M1 and M4 is Ga and the other of the elements M1 and M4 is one selected from Al, Si, Mg, Zr, and B, it is preferable that the elements M1 and M4 are contained in the first region 11. In this case, the first region 11 has an oxide containing the elements M1 and M4, and the second region 12 has an oxide containing the element M2. Note that the element M3 is contained in one or both of the first region 11 and the second region 12.

[0092] <How to make a sputtering target> Next, a method for producing the sputtering target 10 will be described with reference to the flowcharts shown in Figures 2 to 7. The sputtering target 10 described in this section is produced using one or both of a sintered body that will become a first metal oxide and a sintered body that will become a second metal oxide. Hereinafter, the sintered body that will become the first metal oxide may be referred to as the first sintered body, and the sintered body that will become the second metal oxide may be referred to as the second sintered body.

[0093] [Production method example 1] First, an example of a method for producing the sputtering target 10 will be described with reference to the flow chart shown in Fig. 2. In the method for producing the sputtering target 10 shown in Fig. 2, a case in which a first sintered body is used will be described. In the production method described with reference to Fig. 2, a case in which the sputtering target 10 contains elements M1 to M3, the first metal oxide contains elements M1 and M3, and the second metal oxide contains element M2 will be described as an example.

[0094] In step S11, the raw materials of the first sintered body are prepared. FIG. 2 shows an example in which two types of powdered raw materials (raw material 1A and raw material 1B) are prepared as the raw materials of the first sintered body. Since the first sintered body contains an element contained in the first metal oxide, for example, raw material 1A and raw material 1B use a powdered oxide of element M1 and a powdered oxide of element M3, respectively. At this time, step S11 can also be said to be a process of weighing the oxide of element M1 and the oxide of element M3, which are the raw materials of the first sintered body. As a specific example, when element M1 and element M3 are Ga and Zn, respectively, raw material 1A and raw material 1B use a powdered gallium oxide and a powdered zinc oxide, respectively.

[0095] By using raw materials with high purity, it becomes easier to obtain a sputtering target 10 with a low impurity concentration later. Specifically, the alkali metals as impurities can be less than 10 ppm by weight, preferably less than 5 ppm by weight, and more preferably less than 2 ppm by weight. The alkaline earth metals as impurities can be less than 5 ppm by weight, and more preferably less than 2 ppm by weight. The halogens as impurities can be less than 10 ppm by weight, preferably less than 5 ppm by weight, and more preferably less than 2 ppm by weight. The impurity concentrations can be measured by secondary ion mass spectrometry (SIMS), glow discharge mass spectrometry (GDMS), inductively coupled plasma-mass spectrometry (ICP-MS), or the like.

[0096] Although the above describes an example in which an oxide of each element is used, an oxynitride, a nitride oxide, a nitride, or the like may also be used.

[0097] Next, in step S12, the weighed raw materials of the first fired body (raw materials 1A and 1B in FIG. 2) are mixed to prepare a mixture. For example, a powdered oxide of element M1 and a powdered oxide of element M3 are mixed to prepare a mixture.

[0098] Next, in step S13, the mixture is spread in a mold and molded. The mixture spread in the mold can be pressed using a press or the like to form a molded body. In other words, step S13 can be said to be a process of producing a molded body by pressing the mixture while molding it.

[0099] Next, in step S14, the molded body is fired. That is, step S14 can be said to be a process of firing the molded body to produce a fired body. A furnace (also called a firing furnace or a sintering furnace) is used for firing. The firing may be performed in an atmosphere containing one or more of a noble gas, a nitrogen gas, and an oxygen gas.

[0100] The temperature at which the molded body is fired is preferably a temperature at which the elements M1 and M3 combine to form an oxide, for example, a temperature at which they react with each other by heat and change into a compound different from the raw materials. For example, the temperature at which the molded body is fired is 400°C or higher and 1700°C or lower, preferably 900°C or higher and 1500°C or lower. Specifically, the temperature at which the molded body is fired may be about 1400°C.

[0101] 2, step S13 for molding and pressurizing is performed and step S14 for firing is performed as separate steps, but the manufacturing method shown in this embodiment is not limited to this. For example, the mixture may be placed in a mold and fired while being pressed by a press device.

[0102] Through the above steps, a first sintered body can be obtained in step S15. At this time, the first sintered body is a sintered body of M1-M3 oxide. As a specific example, when the element M1 and the element M3 are Ga and Zn, respectively, the first sintered body is a sintered body of Ga-Zn oxide.

[0103] Next, in step S16, the first fired body is pulverized into powder to produce a powder.

[0104] In step S20, a raw material of the second metal oxide is prepared. FIG. 2 shows an example in which one type of powdered raw material (raw material 2) is prepared as the raw material of the second metal oxide. For example, a powdered oxide of element M2 is used as raw material 2. In this case, step S20 can also be said to be a process of weighing the oxide of element M2, which is the raw material of the second metal oxide. As a specific example, when element M2 is In, powdered indium oxide is used as raw material 2. Note that, although an example in which an oxide is used has been shown above, an oxynitride, a nitriding oxide, or a nitride may also be used.

[0105] Next, in step S31, the powder of the first fired body produced in step S16 and the raw material of the second metal oxide prepared in step S20 are mixed together to produce a mixture.

[0106] Next, in step S32, the mixture is spread in a mold and molded. The mixture spread in the mold can be pressed using a press or the like to form a molded body. In other words, step S32 can be said to be a process of producing a molded body by pressing the mixture while molding it.

[0107] As shown in the flow chart of Fig. 2, by producing a compact only by pressing without using high-temperature heat treatment such as sintering, it is possible to prevent a part of the powder of the first sintered body from combining with a part of the raw material of the second metal oxide. This makes it possible to provide the first metal oxide and the second metal oxide separately from each other on the sputtering target 10. That is, it is possible to produce a sputtering target 10 in which the first region 11 and the second region 12 are separated from each other.

[0108] Furthermore, in steps S12 to S16, by using a powder (powder of the first fired body) prepared by mixing an oxide of element M1 and an oxide of element M3, the amount of element M1 and element M3 contained in the first region 11 can be increased.

[0109] In step S33, the molded body is subjected to a finishing process to obtain the sputtering target 10. Specifically, the molded body is divided or ground to adjust the length, width, and thickness of the molded body. In addition, since the presence of minute irregularities on the surface can cause abnormal discharge, the surface of the molded body is polished. The polishing process is preferably performed by CMP.

[0110] When mixing the powder of the first fired body and the raw material of the second metal oxide in step S31, water and an organic substance (dispersant and binder) may be further mixed to form a slurry. By forming a slurry and mixing the powder and raw material, the diameters of the first region 11 and the second region 12 included in the sputtering target 10 can be made smaller. Also, when mixing the raw material of the first fired body in step S12, the slurry may be formed in a similar manner.

[0111] When the powder of the first fired body and the raw material of the second metal oxide are mixed to form a slurry, one or more suction ports are provided at the bottom of the mold into which the slurry is poured when molding in step S32, so that water and the like can be sucked in. Also, a filter is provided at the bottom of the mold so that the powder and raw materials are not allowed to pass through, but water and organic matter are allowed to pass through. Specifically, a filter made of woven cloth or felt with a porous resin film attached thereto can be used.

[0112] In step S32, water and other substances are sucked from the slurry through a filter provided at the bottom of the mold, and water and organic matter are removed from the slurry to form a green body.

[0113] Since the obtained molded body still contains water and organic matter, it is subjected to a drying treatment and the organic matter is removed. The drying treatment is preferably performed by natural drying, since the molded body is less likely to crack.

[0114] When the raw materials for the first fired body are slurried and mixed in step S12, a molded body may be formed in the same manner as above.

[0115] In the above, the sputtering target 10 was produced by pressing the mixture of the powder of the first fired body and the raw material of the second metal oxide. More specifically, after the step of pressing the mixture of the powder of the first fired body and the raw material of the second metal oxide to produce a molded body, the sputtering target 10 was produced without performing the step of firing the molded body. Note that the present embodiment is not limited to this. For example, the molded body produced by pressing may be fired to produce a fired body, which is used as the sputtering target 10. A furnace is used for firing. The firing may be performed in an atmosphere containing one or more of a noble gas, nitrogen gas, and oxygen gas.

[0116] The temperature for firing the molded body is preferably a temperature at which the powder of the first fired body and the raw material of the second metal oxide do not combine, in other words, a temperature at which the M1-M3 oxide and the oxide of element M2 do not combine, for example, a temperature at which they do not react with each other due to heat and change into a compound different from the raw materials. Therefore, for example, the molded body may be fired at a temperature lower than the temperature for firing the molded body in step S14. For example, the temperature for firing the molded body is preferably 200°C or higher and lower than 1000°C.

[0117] Alternatively, the temperature at which the molded body is fired may be a temperature at which at least one of the powder of the first fired body and the raw material of the second metal oxide is present after firing. For example, when a part of the powder of the first fired body is present after firing, the second region 12 has a metal oxide formed by combining a part of the first metal oxide with all of the second metal oxide. Also, for example, when a part of the raw material of the second metal oxide is present after firing, the first region 11 has a metal oxide formed by combining a part of the first metal oxide with all of the second metal oxide.

[0118] When the step of firing the above-mentioned molded body at a low temperature is performed, a third metal oxide containing an element contained in the first metal oxide and an element contained in the second metal oxide may be formed in a part of the sputtering target 10. At this time, a third region 13 is formed.

[0119] By producing sputtering target 10 by firing the above-mentioned molded body at a low temperature in this manner, the strength of sputtering target 10 can be further improved.

[0120] Furthermore, when the mixture is slurried to produce the sputtering target 10 as described above, traces of water and organic matter remaining in the molded body can be removed by firing the mixture.

[0121] Furthermore, the firing step does not necessarily have to be a separate step from the molding and pressurizing step S32. For example, the mixture may be placed in a mold and fired at a low temperature while being pressed in a press.

[0122] [Production method example 2] A method for producing a sputtering target 10 different from that shown in Fig. 2 will be described using a flow chart shown in Fig. 3. In the method for producing the sputtering target 10 shown in Fig. 3, a case in which a second fired body is used will be described. In the production method described using Fig. 3, a case in which the sputtering target 10 contains elements M1 to M3, the first metal oxide contains element M1, and the second metal oxide contains elements M2 and M3 will be described as an example.

[0123] The method for producing the sputtering target 10 shown in Fig. 3 differs from the method for producing the sputtering target 10 shown in Fig. 2 mainly in that steps S21 to S26 are performed instead of step S20, and step S10 is performed instead of step S11 to S16. Hereinafter, differences from the production method shown in Fig. 2 will be mainly described, and descriptions of overlapping parts will be omitted.

[0124] In step S10, a raw material of the first metal oxide is prepared. FIG. 3 shows an example in which one type of powdered raw material (raw material 1) is prepared as the raw material of the first metal oxide. Raw material 1 is, for example, a powdered oxide of element M1. In this case, step S10 can also be said to be a process of weighing the oxide of element M1, which is the raw material of the first metal oxide. As a specific example, when element M1 is Ga, raw material 1 is a powdered gallium oxide.

[0125] In step S21, the raw material of the second sintered body is prepared. FIG. 3 shows an example in which two kinds of powdered raw materials (raw material 2A and raw material 2B) are prepared as the raw material of the second sintered body. Since the second sintered body contains an element contained in the second metal oxide, for example, raw material 2A and raw material 2B use a powdered oxide of element M2 and a powdered oxide of element M3, respectively. At this time, step S21 can also be said to be a process of weighing the oxide of element M2 and the oxide of element M3, which are the raw materials of the second sintered body. As a specific example, when element M2 and element M3 are In and Zn, respectively, raw material 2A and raw material 2B use a powdered indium oxide and a powdered zinc oxide, respectively.

[0126] The raw materials may be weighed, for example, so that the atomic ratio of element M2 to element M3 in the powdered oxide of element M2 or the powdered oxide of element M3 is [M2]:[M3]=1:1 (atomic ratio), [M2]:[M3]=2:1 (atomic ratio), or [M2]:[M3]=4:1 (atomic ratio), etc.

[0127] Although the above describes an example in which an oxide of each element is used, an oxynitride, a nitride oxide, a nitride, or the like may also be used.

[0128] Next, in step S22, the weighed raw materials of the second fired body (raw materials 2A and 2B in FIG. 3) are mixed to prepare a mixture. For example, a powdered oxide of element M2 and a powdered oxide of element M3 are mixed to prepare a mixture.

[0129] Next, in step S23, similarly to step S13 above, the mixture is spread in a mold and molded.

[0130] Next, in step S24, the molded body is fired in the same manner as in step S14 above.

[0131] The temperature at which the molded body is fired is preferably a temperature at which the elements M2 and M3 combine to form an oxide, for example, a temperature at which they react with each other by heat and change into a compound different from the raw material. For example, the temperature at which the molded body is fired is 400°C or higher and 1700°C or lower, preferably 900°C or higher and 1500°C or lower. Specifically, the temperature at which the molded body is fired may be about 1400°C.

[0132] 3, step S23 of molding and pressurization and step S24 of firing are separate steps, but the manufacturing method shown in this embodiment is not limited to this. For example, the mixture may be placed in a mold and fired while being pressed by a press.

[0133] Through the above steps, a second sintered body can be obtained in step S25. At this time, the second sintered body is a sintered body of M2-M3 oxide. As a specific example, when the element M2 and the element M3 are In and Zn, respectively, the second sintered body is a sintered body of In-Zn oxide.

[0134] Next, in step S26, the second fired body is pulverized to produce a powder.

[0135] Next, in step S31a, the powder of the second fired body produced in step S26 and the raw material of the first metal oxide prepared in step S10 are mixed together to produce a mixture.

[0136] The steps from step S32 onwards can be performed using a method similar to that shown in the flowchart of Fig. 2. As described above, a sputtering target 10 in which the first region 11 and the second region 12 are separated from each other can be produced.

[0137] In steps S22 to S26, by using a powder (powder of the second fired body) prepared by mixing an oxide of element M2 and an oxide of element M3, the amount of element M2 and element M3 contained in the second region 12 can be increased.

[0138] As described in step S31, when the raw material of the first metal oxide and the powder of the second fired body are mixed in step S31a, water and organic substances (dispersants and binders) may be further mixed to form a slurry. When the raw material of the second fired body is mixed in step S22, a slurry may be formed in a similar manner.

[0139] As described above, the molded body produced by pressing may be sintered at a low temperature to produce a sintered body, which is used as the sputtering target 10. The temperature at which the molded body is sintered is preferably a temperature at which the raw material of the first metal oxide and the powder of the second sintered body do not combine, in other words, a temperature at which the oxide of element M1 and the oxide of M2-M3 do not combine, for example, a temperature at which they do not react with each other due to heat and change into a compound different from the raw materials. Therefore, for example, the molded body may be sintered at a temperature lower than the temperature at which the molded body is sintered in step S24. For example, the temperature at which the molded body is sintered is preferably 200°C or higher and lower than 1000°C.

[0140] Alternatively, the temperature at which the molded body is fired may be a temperature at which at least one of the raw material of the first metal oxide and the powder of the second fired body is present after firing. For example, when a part of the raw material of the first metal oxide is present after firing, the second region 12 has a metal oxide formed by combining a part of the first metal oxide with all of the second metal oxide. Also, for example, when a part of the powder of the second fired body is present after firing, the first region 11 has a metal oxide formed by combining a part of the first metal oxide with all of the second metal oxide.

[0141] When the step of firing the above-mentioned molded body at a low temperature is performed, a third metal oxide containing an element contained in the first metal oxide and an element contained in the second metal oxide may be formed in a part of the sputtering target 10. At this time, a third region 13 is formed.

[0142] [Production method example 3] A method for producing a sputtering target 10 different from those shown in Figures 2 and 3 will be described using a flow chart shown in Figure 4. In the method for producing the sputtering target 10 shown in Figure 4, a case in which a first sintered body and a second sintered body are used will be described. In the production method described using Figure 4, a case in which the sputtering target 10 contains elements M1 to M3, the first metal oxide contains elements M1 and M3, and the second metal oxide contains elements M2 and M3 will be described as an example.

[0143] The method for producing the sputtering target 10 shown in FIG. 4 is mainly different from the method for producing the sputtering target 10 shown in FIG. 2 in that steps S21 to S26 are performed instead of step S20. Also, the method for producing the sputtering target 10 shown in FIG. 3 is mainly different from the method for producing the sputtering target 10 shown in FIG. 3 in that steps S11 to S16 are performed instead of step S10. That is, in the method for producing the sputtering target shown in FIG. 4, the first fired body and the second fired body are produced in parallel. Note that the steps S11 to S16 and the steps S21 to S26 may be performed in any order. Hereinafter, differences from the method for producing the sputtering target shown in FIG. 2 and the method for producing the sputtering target shown in FIG. 3 will be mainly described, and overlapping parts will not be described.

[0144] The raw materials may be weighed by preparing powdered oxides of elements M1, M2, and M3 in the same manner as step S11 shown in Fig. 2 and step S21 shown in Fig. 3. However, since element M3 is contained in both the first metal oxide and the second metal oxide, the oxide of element M3 contained in the first fired body is regarded as the oxide of the first element M3, and the oxide of element M3 contained in the second fired body is regarded as the oxide of the second element M3, and they are separately weighed.

[0145] In step S12 shown in Fig. 4, a mixture may be prepared in the same manner as in step S12 above, using the powdered oxide of element M1 and the powdered oxide of the first element M3 weighed in step S11 shown in Fig. 4. In step S22 shown in Fig. 4, a mixture may be prepared in the same manner as in step S22 above, using the powdered oxide of element M2 and the powdered oxide of the second element M3 weighed in step S21 shown in Fig. 4.

[0146] The above description can be referred to for steps S13 to S16 shown in Fig. 4. Also, the above description can be referred to for steps S23 to S26 shown in Fig. 4.

[0147] Next, in step S31b, the powder of the first fired body produced in step S16 and the powder of the second fired body produced in step S26 are mixed to produce a mixture. The steps from step S32 onwards can be performed using a method similar to that shown in the flowchart in FIG.

[0148] The above is the description of the method for producing the sputtering target 10 shown in FIG.

[0149] [Example of a method for producing a first fired body] 2 and 4 show an example of a manufacturing method when the first metal oxide contains elements M1 and M3. Next, a manufacturing method of a first fired body when the first metal oxide contains elements M1 to M3 will be described with reference to FIGS.

[0150] In step S11a, the raw materials of the first sintered body are prepared. In FIG. 5(A), three kinds of powdered raw materials (raw materials 1A to 1C) are prepared as the raw materials of the first sintered body. Since the first sintered body contains an element contained in the first metal oxide, for example, raw materials 1A, 1B, and 1C use powdered oxide of element M1, powdered oxide of element M3, and powdered oxide of element M2, respectively. At this time, step S11a can also be said to be a process of weighing the oxide of element M1, oxide of element M2, and oxide of element M3, which are the raw materials of the first sintered body. As a specific example, when element M1, element M2, and element M3 are Ga, In, and Zn, raw materials 1A, 1B, and 1C use powdered gallium oxide, powdered zinc oxide, and powdered indium oxide, respectively.

[0151] Since element M2 is contained in both the first metal oxide and the second metal oxide, the oxide of element M2 contained in the first fired body and the oxide of element M2 contained in the second fired body are weighed separately. Also, element M3 may be contained in the second metal oxide. In this case, the oxide of element M3 contained in the first fired body and the oxide of element M3 contained in the second fired body are weighed separately.

[0152] Next, in step S12a, the weighed raw materials of the first fired body (raw materials 1A to 1C in FIG. 5(A)) are mixed to prepare a mixture. For example, a powdered oxide of element M1, a powdered oxide of element M2, and a powdered oxide of element M3 are mixed to prepare a mixture. Steps from step S13 onwards can be performed using a method similar to that shown in the flowchart in FIG. 2.

[0153] In this manner, the first fired body containing the elements M1 to M3 can be produced.

[0154] A method for producing a first sintered body, which is different from the method shown in Fig. 5(A), will be described with reference to the flow chart shown in Fig. 5(B). In the method for producing a first sintered body shown in Fig. 5(B), a case will be described in which a third sintered body produced from raw material 1A and raw material 1B is used.

[0155] The method for producing a first fired body shown in FIG. 5(B) differs from the method for producing a first fired body shown in FIG. 5(A) in that steps S111 to S117 and S12b are performed instead of steps S11a and S12a.

[0156] In step S111, the raw materials of the third fired body are prepared. FIG. 5(B) shows an example in which two types of powdered raw materials (raw material 1A and raw material 1B) are prepared as the raw materials of the third fired body. For example, raw material 1A and raw material 1B are respectively a powdered oxide of element M1 and a powdered oxide of element M3. In this case, step S111 can also be said to be a process of weighing the oxide of element M1 and the oxide of element M3, which are the raw materials of the third fired body.

[0157] Steps S112 to S116 may be performed by referring to the descriptions of steps S12 to S16 shown in FIG.

[0158] In step S117, the raw material of the first sintered body is prepared. FIG. 5(B) shows an example in which one type of powdered raw material (raw material 1C) is prepared as one of the raw materials of the first sintered body. The first sintered body is produced using the powder of the third sintered body and raw material 1C. Since elements M1 and M3 are contained in the third sintered body, raw material 1C is, for example, a powdered oxide of element M2. At this time, step S117 can also be said to be a process of weighing the oxide of element M2, which is one of the raw materials of the first sintered body.

[0159] Next, in step S12b, the powder of the third sintered body produced in step S116 is mixed with one of the raw materials of the first sintered body (raw material 1C) prepared in step S117 to produce a mixture. The steps from step S13 onwards can be performed using a method similar to that shown in the flowchart in FIG.

[0160] In this manner, the first fired body containing the elements M1 to M3 can be produced.

[0161] 5B shows an example in which the first fired body is made using the powder of the third fired body containing elements M1 and M3 and raw material 1C, but the present invention is not limited to this. The first fired body may be made using the powder of the third fired body containing elements M1 and M2 and raw material 1B, or may be made using the powder of the third fired body containing elements M2 and M3 and raw material 1A.

[0162] Furthermore, when the first metal oxide contains elements M1, M3, and M4, the method can be regarded as a method for producing a first sintered body by replacing element M2 described in the above-mentioned [An example of a method for producing a first sintered body] with element M4.

[0163] [An example of a method for producing a second fired body] 3 and 4 show an example of a manufacturing method when the second metal oxide contains elements M2 and M3. Next, a manufacturing method of the second fired body when the second metal oxide contains elements M2 to M4 will be described with reference to FIGS.

[0164] In step S21a, the raw materials of the second sintered body are prepared. In FIG. 6(A), three kinds of powdered raw materials (raw materials 2A to 2C) are prepared as the raw materials of the second sintered body. Since the second sintered body contains an element contained in the second metal oxide, for example, the raw materials 2A, 2B, and 2C are powdered oxide of element M2, powdered oxide of element M3, and powdered oxide of element M4, respectively. At this time, step S21a can be said to be a process of weighing the oxide of element M2, oxide of element M3, and oxide of element M4, which are the raw materials of the second sintered body. As a specific example, when element M2, element M3, and element M4 are In, Zn, and Sn, respectively, the raw materials 2A, 2B, and 2C are powdered indium oxide, powdered zinc oxide, and powdered tin oxide, respectively.

[0165] In addition, the element M3 may also be contained in the first metal oxide. In this case, the oxide of the element M3 contained in the first fired body and the oxide of the element M3 contained in the second fired body are separately weighed.

[0166] Next, in step S22a, the weighed raw materials of the second fired body (raw materials 2A to 2C in FIG. 6(A)) are mixed to prepare a mixture. For example, a powdered oxide of element M2, a powdered oxide of element M3, and a powdered oxide of element M4 are mixed to prepare a mixture. The steps from step S23 onwards can be performed using a method similar to that shown in the flowchart in FIG. 3.

[0167] In this manner, the second fired body containing the elements M2 to M4 can be produced.

[0168] A method for producing a second fired body, which is different from the method shown in Fig. 6(A), will be described with reference to the flow chart shown in Fig. 6(B). In the method for producing a second fired body shown in Fig. 6(B), a fourth fired body produced from raw material 2A and raw material 2B is used.

[0169] The method for producing a second fired body shown in FIG. 6B differs from the method for producing a second fired body shown in FIG. 6A in that steps S121 to S127 and S22b are performed instead of steps S21a and S22a.

[0170] In step S121, the raw materials of the fourth fired body are prepared. FIG. 6(B) shows an example in which two types of powdered raw materials (raw material 2A and raw material 2B) are prepared as the raw materials of the fourth fired body. For example, raw material 2A and raw material 2B are respectively a powdered oxide of element M2 and a powdered oxide of element M3. In this case, step S121 can also be said to be a process of weighing the oxide of element M2 and the oxide of element M3, which are the raw materials of the fourth fired body.

[0171] Steps S122 to S126 may be performed by referring to the descriptions of steps S22 to S26 shown in FIG.

[0172] In step S127, the raw material of the second sintered body is prepared. FIG. 6(B) shows an example in which one type of powdered raw material (raw material 2C) is prepared as one of the raw materials of the second sintered body. The second sintered body is produced using the powder of the fourth sintered body and raw material 2C. Since elements M2 and M3 are contained in the fourth sintered body, raw material 2C is, for example, a powdered oxide of element M4. At this time, step S127 can also be said to be a process of weighing the oxide of element M4, which is one of the raw materials of the second sintered body.

[0173] Next, in step S22b, the powder of the fourth sintered body produced in step S126 is mixed with one of the raw materials of the second sintered body (raw material 2C) prepared in step S127 to produce a mixture. The steps from step S23 onwards can be performed using a method similar to that shown in the flowchart in FIG.

[0174] In this manner, the second fired body containing the elements M2 to M4 can be produced.

[0175] 6B shows an example in which the second sintered body is made using the powder of the fourth sintered body containing the elements M2 and M3 and the raw material 2C, but the present invention is not limited to this. The second sintered body may be made using the powder of the fourth sintered body containing the elements M2 and M4 and the raw material 2B, or may be made using the powder of the fourth sintered body containing the elements M3 and M4 and the raw material 2A.

[0176] A sputtering target 10 containing elements M2 and M3 in the first region 11 and the second region 12, respectively, can be manufactured by using a manufacturing method in which steps S11a and S12a shown in FIG. 5(A) are performed instead of steps S11 and S12 shown in the flowchart shown in FIG. 4. An example of manufacturing a sputtering target 10 having a first region 11 having a composition of [In]:[Ga]:[Zn]=1:3:2 [atomic ratio] and a second region 12 having a composition of [In]:[Zn]=1:1 [atomic ratio] using Ga, In, and Zn as the element M1, element M2, and element M3, respectively, will be described below with reference to FIG. 7. Note that the manufacturing method described below is not limited to the types and compositions of these elements, and the sputtering target 10 may be manufactured by using a similar method by appropriately setting the types and compositions of the elements.

[0177] The weighing of the raw materials may be performed by preparing powdered gallium oxide, indium oxide, and zinc oxide, in the same manner as in step S11a and step S21 described above. However, in order to include indium and zinc in the first region 11 and the second region 12, respectively, the indium oxide to be included in the first fired body is set as the first indium oxide, and the indium oxide to be included in the second fired body is set as the second indium oxide, and they are weighed separately. In addition, the zinc oxide to be included in the first fired body is set as the first zinc oxide, and the zinc oxide to be included in the second fired body is set as the second zinc oxide, and they are weighed separately.

[0178] Therefore, for example, when preparing a sputtering target 10 having a composition of [In]:[Ga]:[Zn]=3:3:4 [atomic ratio], the first indium oxide, the powdered second indium oxide, the powdered gallium oxide, the powdered first zinc oxide, and the powdered second zinc oxide are weighed out so that the atomic ratio of the first indium (hereinafter may be referred to as In1), the second indium (hereinafter may be referred to as In2), the gallium, the first zinc (hereinafter may be referred to as Zn1), and the second zinc (hereinafter may be referred to as Zn2) is [In1]:[In2]:[Ga]:[Zn1]:[Zn2]=1:2:3:2:2 [atomic ratio].

[0179] Next, in step S12a shown in Fig. 7, a mixture may be prepared in the same manner as in step S12a above, using the powdered first indium oxide, powdered gallium oxide, and powdered first zinc oxide weighed in step S11a shown in Fig. 7. In step S12a shown in Fig. 7, the powdered first indium oxide, powdered gallium oxide, and powdered first zinc oxide are mixed in an atomic ratio of [In1]:[Ga]:[Zn1]=1:3:2 to prepare a mixture.

[0180] In the above, an example is shown in which powdered first indium oxide, powdered gallium oxide, and powdered first zinc oxide are mixed in an atomic ratio of [In1]:[Ga]:[Zn1] = 1:3:2 as the raw materials for the first sintered body, but the production method shown in this section is not limited to this, and the mixing amounts of powdered first indium oxide, powdered gallium oxide, and powdered first zinc oxide may be appropriately set.

[0181] For steps S13 to S16, refer to the description of steps S13 to S16 shown in Fig. 2. When firing the molded body made of the first indium oxide, gallium oxide, and first zinc oxide in step S14, the temperature for firing the molded body may be set to 400°C or higher and 2500°C or lower, preferably 900°C or higher and 1900°C or lower.

[0182] Next, in step S22 shown in Fig. 7, a mixture may be prepared in the same manner as in step S22 above, using the powdered second indium oxide and powdered second zinc oxide weighed in step S21 shown in Fig. 7. In step S22, the powdered second indium oxide and the powdered second zinc oxide are mixed in an atomic ratio of [In2]:[Zn2]=1:1 to prepare a mixture.

[0183] In the above, an example is shown in which powdered second indium oxide and powdered second zinc oxide are mixed in an atomic ratio of [In2]:[Zn2] = 1:1 as the raw materials for the second sintered body, but the production method shown in this section is not limited to this, and the mixing amounts of powdered second indium oxide and powdered second zinc oxide may be appropriately set.

[0184] 6(A), the raw material of the second fired body may contain an element other than indium and zinc (for example, the above-mentioned element M4). For example, when Ti, W, or Sn is used as the element, powdered titanium oxide, powdered tungsten oxide, or powdered tin oxide may be used.

[0185] For steps S23 to S26, refer to the description of steps S23 to S26 shown in Fig. 3. When firing a molded body made of the second indium oxide and the second zinc oxide in step S24, the temperature at which the molded body is fired may be 400°C or higher and 1700°C or lower, preferably 900°C or higher and 1500°C or lower. For example, the temperature at which the molded body is fired may be about 1400°C.

[0186] Next, in step S31a shown in FIG. 7, similar to step S31a described above, the powder of the first sintered body produced in step S16 and the powder of the second sintered body produced in step S26 are mixed to produce a mixture.

[0187] Next, in step S32 shown in FIG. 7, the mixture is spread in a mold and molded in the same manner as in step S32 above.

[0188] Next, it is preferable to perform low-temperature firing as step S34 shown in Fig. 7. A furnace is used for firing. The firing may be performed in an atmosphere containing one or more of a noble gas, nitrogen gas, and oxygen gas.

[0189] The temperature at which the molded body is fired is preferably a temperature at which the powder of the first fired body and the powder of the second fired body do not combine, in other words, a temperature at which the In-Ga-Zn oxide contained in the powder of the first fired body and the In-Zn oxide contained in the powder of the second fired body do not combine, for example, a temperature at which they do not react with each other due to heat and change into a compound different from the raw materials. Therefore, for example, the molded body may be fired at a temperature lower than the firing temperature in steps S14 and S24. For example, the molded body may be fired at a temperature about 200°C to 300°C lower than the firing temperature in steps S14 and S24. Specifically, the temperature at which the molded body is fired is preferably 200°C or higher and lower than 1200°C.

[0190] By producing sputtering target 10 by firing the above-mentioned molded body at a low temperature in this manner, the strength of sputtering target 10 can be further improved.

[0191] Furthermore, the low-temperature firing in step S34 does not necessarily have to be a separate process from the molding and pressurizing steps in step S32. For example, the mixture may be placed in a mold and fired at a low temperature while being pressed in a press.

[0192] Furthermore, if the strength of the sputtering target 10 is sufficiently high when step S32 is completed, step S34 may not be performed and the process may proceed to step S33.

[0193] Next, in step S33 shown in FIG. 7, the molded body is subjected to a finishing process in the same manner as in step S33 described above, whereby the sputtering target 10 can be obtained.

[0194] As shown in the flow chart of Fig. 7, after the first and second metal oxides are separately sintered and powdered to produce the first sintered powder and the second sintered powder, the sputtering target 10 is produced without using high-temperature heat treatment. This makes it possible to produce the sputtering target 10 such that the first and second metal oxides do not combine with each other. Therefore, the first region 11 and the second region 12 can be provided in the sputtering target 10 separately from each other.

[0195] Furthermore, by preparing a powder of the first sintered body in advance in steps S12a to S16, the proportion of gallium contained in the first region 11 can be increased. Also, by preparing a powder of the second sintered body in advance in steps S22 to S26, the proportions of indium and zinc contained in the second region 12 can be increased. In this way, the composition of the first region 11 and the composition of the second region 12 of the sputtering target 10 can be made different.

[0196] An example of a method for manufacturing a sputtering target 10 for forming a metal oxide film containing In, Ga, and Zn has been described with reference to FIG. 7. A preferred range of the atomic ratio of indium, gallium, and zinc in the metal oxide according to one embodiment of the present invention will now be described with reference to FIG. 8(A) and FIG. 8(B). Note that the terms for the atomic ratio of indium, gallium, and zinc in the metal oxide are [In], [Ga], and [Zn], respectively. The graphs shown in FIG. 8(A) and FIG. 8(B) are in the form of triangular plots.

[0197] Note that the atomic ratio of oxygen is not shown in Figures 8(A) and 8(B). Metal oxides to which trace amounts of elements other than In, Ga, and Zn are added may also be plotted in Figures 8(A) and 8(B) in some cases.

[0198] The circle plots in FIG. 8(A) and FIG. 8(B) indicate the composition, Hall mobility, and carrier concentration of the metal oxide. For example, the center of the circle indicates the composition of the metal oxide, the diameter of the circle indicates the level of Hall mobility, and the shade of the fill of the circle indicates the level of carrier concentration. Specifically, the larger the diameter of the circle, the higher the Hall mobility of the metal oxide, and the smaller the diameter of the circle, the lower the Hall mobility of the metal oxide. Also, the darker (blacker) the fill of the circle, the higher the carrier concentration of the metal oxide, and the lighter (whiter) the fill of the circle, the lower the carrier concentration of the metal oxide. Also, FIG. 8(B) shows a part of the circle plots in FIG. 8(A).

[0199] The composition of the metal oxide can be evaluated, for example, by ICP-MS, and the Hall mobility and carrier concentration of the metal oxide can be evaluated, for example, by Hall effect measurement.

[0200] The larger the diameter of the circle shown in Figures 8(A) and 8(B), the higher the mobility of the metal oxide, and the lighter (whiter) the circle shown in Figures 8(A) and 8(B), the lower the carrier concentration of the metal oxide. By lowering the carrier concentration of the metal oxide including the channel formation region, the normally-off characteristic of the transistor can be achieved.

[0201] As shown in Figure 8(A), in metal oxides with a high indium content, the diameter of the circle tends to be large and the fill of the circle tends to be dark (black). In other words, a transistor using the metal oxide can achieve high mobility, but there is a concern that the transistor may have normally-on characteristics. Note that the indium content refers to the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide. In addition, the gallium content can be calculated by replacing the indium with gallium.

[0202] In addition, in metal oxides with a high gallium content, the diameter of the circle tends to be small and the fill of the circle tends to be light (white). In other words, the higher the gallium content, the higher the insulating property of the metal oxide. Therefore, in a transistor using the metal oxide, although it is possible to achieve normally-off characteristics, there is a concern that the mobility may be reduced.

[0203] As described above, when the metal oxide includes a first metal oxide having a high content of gallium and a second metal oxide having a high content of indium, a transistor having high mobility and normally-off characteristics can be realized.

[0204] The region indicated by the dotted line in Figure 8 (B) represents the range of compositions that the sputtering target 10 can have when the composition of the first sintered body is [In]:[Ga]:[Zn] = 1:3:2 [atomic ratio] and the composition of the second sintered body is [In]:[Ga]:[Zn] = 1:0:1 [atomic ratio].

[0205] For example, by setting the molar ratio of a first sintered powder having a composition of [In1]:[Ga]:[Zn1]=1:3:2 [atomic ratio] to a second sintered powder having a composition of [In2]:[Zn2]=1:1 [atomic ratio] to be 1:2, a sputtering target 10 having a composition of [In]:[Ga]:[Zn]=3:3:4 [atomic ratio] can be produced.

[0206] The composition of the sputtering target 10 is not limited to the above, and can be any composition by appropriately setting the molar ratio of the powder of the first fired body and the powder of the second fired body. For example, by adjusting the molar ratio of the powder of the first fired body having a composition of [In1]:[Ga]:[Zn1]=1:3:2 [atomic ratio] and the powder of the second fired body having a composition of [In2]:[Zn2]=1:1 [atomic ratio], the composition of the sputtering target 10 can be set to any of the ranges of [In]:[Ga]:[Zn]=1:3:2 [atomic ratio] to [In]:[Ga]:[Zn]=1:0:1 [atomic ratio]. In this way, by making the composition of the first fired body different from the composition of the second fired body and adjusting the ratio of the first fired body to the second fired body, the range of the composition of the sputtering target 10 can be expanded.

[0207] The region indicated by the dashed line in FIG. 8B is the range of the composition that the sputtering target 10 can have when the composition of the first fired body is [In]:[Ga]:[Zn]=1:3:2 [atomic ratio] and the second fired body is an indium oxide to which Sn is added. Since the indium oxide to which Sn is added has a trace amount of Sn added thereto, it may be plotted at a position of [In]:[Ga]:[Zn]=1:0:0 [atomic ratio]. Alternatively, since Sn is a type of element that can be a carrier supply source as described later, [In] in FIG. 8B can be regarded as the sum of the number of atoms of In and the number of atoms of Sn, and the indium oxide to which Sn is added may be plotted at a position of [In]:[Ga]:[Zn]=1:0:0 [atomic ratio].

[0208] For example, by adjusting the molar ratio of a first sintered powder having a composition of [In1]:[Ga]:[Zn]=1:3:2 [atomic ratio] and a second sintered powder having indium oxide with Sn added, the composition of the sputtering target 10 can be set anywhere in the range of [In]:[Ga]:[Zn]=1:3:2 [atomic ratio] to [In]:[Ga]:[Zn]=1:0:0 [atomic ratio].

[0209] <Sputtering equipment> Next, a sputtering apparatus capable of using the sputtering target 10 will be described with reference to Fig. 9. Fig. 9 is a cross-sectional view illustrating a film formation chamber 41 of the sputtering apparatus.

[0210] The film formation chamber 41 shown in FIG. 9 has a substrate holder 62, a sputtering target 10, a backing plate 50, and a magnet unit. One or more magnet units can be provided. The magnet unit can be provided with a fixed or swinging mechanism. The sputtering target 10 is disposed and fixed on the backing plate 50. When the substrate 60 is carried into the film formation chamber 41, the substrate 60 is disposed in contact with the substrate holder 62. The film formation chamber 41 has an intake port 42a and an exhaust port 42b for supplying gas (also called film formation gas). The film formation chamber 41 is supplied with a film formation gas through the intake port 42a, and the film formation gas is exhausted through the exhaust port 42b.

[0211] FIG. 9 shows an example in which magnet units 54a and 54b are provided. The magnet units 54a and 54b are disposed under the sputtering target 10 via a backing plate 50. The magnet units 54a and 54b have a swing mechanism, the magnet unit 54a has a swing range 57a, and the magnet unit 54b has a swing range 57b. The magnet units 54a and 54b swing within the range in which the sputtering target 10 is disposed, thereby forming a uniform film. For example, the magnet unit 54a or the magnet unit 54b may be swung with a beat (which may be rephrased as rhythm, beat, pulse, frequency, period, cycle, etc.) of 0.1 Hz to 1 kHz.

[0212] The magnetic field applied to the sputtering target 10 is determined by the voltage V2 applied to the substrate holder 62 and the voltage V1 applied to the backing plate 50. The magnetic field applied to the sputtering target 10 changes with the oscillation of the magnet unit. A region with a strong magnetic field becomes a high-density plasma region, and therefore the sputtering phenomenon of the sputtering target 10 is likely to occur in the vicinity of the region. When the sputtering target 10 contains multiple elements, the magnetic field strength applied to the sputtering target 10 from the magnet unit 54a can be different from the magnetic field strength applied to the sputtering target 10 from the magnet unit 54b. Elements corresponding to the magnetic field strength are deposited on the substrate 60.

[0213] 9 shows an example in which a parallel plate type sputtering apparatus is used, but the method for forming a metal oxide film according to the present embodiment is not limited to this. For example, a facing target type sputtering apparatus may be used to form a metal oxide film.

[0214] Sputtering allows film formation at low temperatures and can therefore increase the productivity of semiconductor devices using metal oxides.

[0215] <Step of depositing metal oxide on substrate> Next, a process for depositing a metal oxide on a substrate using the sputtering target 10 will be described.

[0216] In a process for depositing a metal oxide on a substrate, for example, argon gas, nitrogen gas, or oxygen gas is ionized and separated into positive ions and electrons to form plasma in a film formation chamber 41 shown in FIG. 9. The positive ions in the plasma are then accelerated toward the sputtering target 10 by a potential applied to the backing plate 50. The positive ions collide with the sputtering target 10 to generate sputtered particles, which are then deposited on the substrate 60.

[0217] 10(A) shows a schematic diagram of the vicinity of a sputtering target 10 during deposition of a metal oxide film. Fig. 10(A) shows a sputtering target 10, plasma 30, cations 20, first sputtered particles 11a, and second sputtered particles 12a.

[0218] In FIG. 10(A), argon gas, oxygen gas, or nitrogen gas is ionized and split into positive ions 20 and electrons (not shown) to form plasma 30. Then, the positive ions 20 in the plasma 30 are accelerated toward the sputtering target 10. The positive ions 20 collide with the sputtering target 10 to generate first sputter particles 11a and second sputter particles 12a, which are then ejected from the sputtering target 10. Since the first sputter particles 11a are ejected from the first region 11, they may form clusters containing a large amount of element M1. Since the second sputter particles 12a are ejected from the second region 12, they may form clusters containing a large amount of element M2.

[0219] First sputtered particles 11a emitted from first region 11 and second sputtered particles 12a emitted from second region 12 are respectively emitted and deposited on the substrate. On the substrate, a region including first sputtered particles 11a and a region including second sputtered particles 12a are unevenly formed.

[0220] When gallium is used as element M1, as shown in FIG. 10(B), a precipitate 14 may be formed on the upper surface of the sputtering target 10. The precipitate 14 is mainly precipitated from gallium contained in the first region 11, and may be formed in a spherical or granular shape due to surface tension. Therefore, the atomic ratio of gallium contained in the precipitate 14 may be greater than the atomic ratio of gallium contained in the first region 11. The content of gallium contained in the precipitate 14 may be greater than the content of gallium contained in the first region 11. In addition, zinc or an oxide of zinc may be formed in the precipitate 14 so as to cover the surface.

[0221] When positive ions 20, such as argon ions, collide with a first region 11 exposed on the upper surface of the sputtering target 10, oxygen is discharged from the first region 11, and elemental substances such as gallium and zinc are formed on the surface of the sputtering target 10. Since elemental gallium has a low melting point of approximately 30°C, the formed elemental gallium is melted by the heat generated by the sputtering process. The molten gallium aggregates due to surface tension, and spherical or granular precipitates 14 are formed.

[0222] Here, the solid solubility of zinc in gallium near the melting point of simple gallium is about 1 atomic %. Therefore, there is almost no zinc inside the precipitate 14, and zinc or zinc oxide may be formed to cover the surface of the precipitate 14.

[0223] The first sputtered particles 11a emitted from the deposition portion 14 often contain more gallium than the first sputtered particles 11a emitted from the first region 11. For this reason, the amount of gallium contained in the region containing the first sputtered particles 11a formed on the substrate by sputtering may be large.

[0224] The above is a description of the process of depositing a metal oxide on a substrate using sputtering target 10.

[0225] Next, a description will be given of the metal oxide film formed using the sputtering target 10. The metal oxide film formed using the sputtering target 10 has a plurality of components.

[0226] The metal oxide film formed using the sputtering target 10 has a first component and a second component. The first component has an oxide containing an element contained in the first region 11 of the sputtering target 10, and the second component has an oxide containing an element contained in the second region 12 of the sputtering target 10.

[0227] Here, a configuration in which the metal oxide contains the elements Ma and Mb will be described with reference to FIG.

[0228] <Metal oxide composition> 11 is a conceptual diagram of a metal oxide having a cloud-aligned composite (CAC) structure according to one embodiment of the present invention. Note that in this specification, when the metal oxide according to one embodiment of the present invention has a semiconductor function, it is defined as a cloud-aligned composite oxide semiconductor (CAC-OS).

[0229] In addition, the metal oxide shown in this embodiment preferably has an element Ma that contributes to the insulating property of the metal oxide and an element Mb that contributes to the electrical conductivity. Note that the contribution to the insulating property or electrical conductivity of the metal oxide is relative, and the contribution of each element changes depending on the combination of elements that constitute the metal oxide. Therefore, it can be said that the element Ma is an element that contributes more to the insulating property of the metal oxide than the element Mb. It can also be said that the element Mb is an element that contributes more to the electrical conductivity of the metal oxide than the element Ma.

[0230] For example, the element Ma may be Al, Ga, Si, Mg, Zr, or B. It is preferable that the element Ma is one or more of the above elements. For example, the element Mb may be In, Zn, Ti, Ge, Sn, V, Ni, Mo, W, or Ta. It is preferable that the element Mb is one or more of the above elements.

[0231] In this case, the element Ma corresponds to the element M1 in the sputtering target 10 described above, and the element Mb corresponds to the element M2 in the sputtering target 10 described above.

[0232] Moreover, the element M3 in the above-mentioned sputtering target 10 is preferably any one of the elements selectable as the above-mentioned element Mb, and is particularly preferably Zn. Note that, in the above-mentioned sputtering target 10, when Zn is selected as one of the elements M1 and M2, the element M3 may be any one of the elements selectable as the element Ma or the element Mb.

[0233] Furthermore, the element M4 in the above-described sputtering target 10 may be any one of elements selectable as the element Ma or the element Mb.

[0234] In the CAC-OS, as shown in Fig. 11, for example, the elements constituting the metal oxide are unevenly distributed to form regions 001 and 002 each mainly composed of the element, and the regions are mixed to form a mosaic shape. That is, the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. In the following, the state in which one or more metal elements are unevenly distributed in the metal oxide and the regions having the metal elements are mixed in a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof, is also referred to as a mosaic shape or a patch shape.

[0235] A Ma-Mb oxide having a CAC structure is a structure in which the material is separated into an oxide containing the element Ma and an oxide containing the element Mb, forming a mosaic structure, and the mosaic-shaped oxide containing the element Ma and the mosaic-shaped oxide containing the element Mb are distributed throughout the film (hereinafter referred to as a cloud-like structure).

[0236] For example, an In-Ga-Zn oxide having a CAC structure is a structure in which the material is separated into gallium oxide and indium oxide or In-Zn oxide, forming a mosaic pattern, and the mosaic pattern of gallium oxide and the mosaic pattern of indium oxide or In-Zn oxide are distributed in the film (hereinafter also referred to as a cloud pattern).

[0237] In other words, the metal oxide of one embodiment of the present invention has at least two or more oxides or components selected from gallium oxide, indium oxide, zinc oxide, In-Ga oxide, Ga-Zn oxide, In-Zn oxide, and In-Ga-Zn oxide. In particular, the two or more oxides are preferably selected from oxides containing Ga and oxides containing In.

[0238] For example, when the element Ma is Ga and the element Mb is In, Sn, and Zn, the metal oxide of one embodiment of the present invention has at least two selected from gallium oxide, indium oxide, tin oxide, zinc oxide, In-Ga oxide, Ga-Sn oxide, Ga-Zn oxide, In-Sn oxide, In-Zn oxide, Sn-Zn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, and In-Ga-Sn-Zn oxide.

[0239] Furthermore, for example, when the element Ma is Ga and Al and the element Mb is In and Zn, the metal oxide of one embodiment of the present invention has at least two selected from gallium oxide, aluminum oxide, indium oxide, zinc oxide, Ga-Al oxide, In-Ga oxide, Ga-Zn oxide, In-Al oxide, Al-Zn oxide, In-Zn oxide, In-Ga-Zn oxide, In-Al-Zn oxide, and In-Al-Ga-Zn oxide.

[0240] In other words, the metal oxide of one embodiment of the present invention can be said to be a composite material having a plurality of materials or a plurality of components, or a composite material.

[0241] Here, it is assumed that the concept shown in FIG. 11 is a Ma-Mb oxide having a CAC structure. In this case, it can be said that region 001 is a region mainly composed of an oxide containing element Ma, and region 002 is a region mainly composed of an oxide containing element Mb. In this case, since the peripheral parts of region 001 and region 002 are unclear (blurred), a clear boundary between them may not be observed. In other words, a Ma-Mb oxide having a CAC structure is a metal oxide in which a region mainly composed of an oxide containing element Ma and a region mainly composed of an oxide containing element Mb are mixed. Therefore, the metal oxide may be described as a composite metal oxide.

[0242] Moreover, it is preferable that the region 001 further contains one type of element Mb, and it is particularly preferable that the region 001 contains zinc. In this case, the region 001 and the region 002 contain zinc in common. Furthermore, it is preferable that the region between the region 001 and the region 002 (for example, the region shown in gray in FIG. 11, including the unclear region around the region 001 and the region 002) also contains zinc. It can also be said that the zinc spreads in a cloud-like shape in the metal oxide, and the region 001 and the region 002 are connected via the region containing zinc. Note that the atomic ratio of zinc contained in the region between the region 001 and the region 002 may be greater than the atomic ratio of zinc contained in the region 001 or the region 002.

[0243] The sizes of the region 001 and the region 002 can be evaluated by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX). For example, the diameter of the region 001 may be observed to be 0.5 nm to 10 nm, or 1 nm to 2 nm, in the EDX mapping of a cross-sectional photograph. In addition, the density of the main component element gradually decreases from the center to the periphery of the region. For example, if the number of elements that can be counted by EDX mapping (hereinafter also referred to as the abundance) is inclined from the center to the periphery, the periphery of the region is observed in an unclear (blurred) state in the EDX mapping of the cross-sectional photograph.

[0244] In addition, in the CAC-OS, there is no particular limitation on the crystal structures of the regions 001 and 002. Furthermore, the regions 001 and 002 may have different crystal structures.

[0245] For example, in the CAC-OS, an oxide semiconductor having a non-single crystal structure is preferable. Examples of the non-single crystal structure include a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-likeOS), and an amorphous oxide semiconductor.

[0246] CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement. CAAC-OS has a region in which a plurality of crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a portion in which the direction of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in the region in which the plurality of crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor having a c-axis aligned and no clear orientation in the ab-plane direction.

[0247] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the maximum diameter of the crystalline region may be about several tens of nm.

[0248] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD device, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. The position of the peak indicating c-axis orientation (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS. For example, a plurality of bright spots are observed in the electron diffraction pattern of the CAAC-OS film. Note that a certain spot and another spot are observed at positions symmetrical to each other with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0249] The nc-OS has periodic atomic arrangement in a microscopic region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. Furthermore, the nc-OS does not exhibit regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor depending on the analysis method.

[0250] For example, when a structural analysis is performed on an nc-OS film using an XRD device, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scans. When an nc-OS film is subjected to electron diffraction (also called selected area electron diffraction) using an electron beam with a probe diameter larger than that of a nanocrystal (e.g., 50 nm or more), a diffraction pattern like a halo pattern is observed. On the other hand, when an nc-OS film is subjected to electron diffraction (also called nanobeam electron diffraction) using an electron beam with a probe diameter equal to or smaller than that of a nanocrystal (e.g., 1 nm or more and 30 nm or less), an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0251] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has an unstable structure compared with the nc-OS and the CAAC-OS.

[0252] The crystallinity of the CAC-OS can be evaluated by electron diffraction. For example, when the CAC-OS is analyzed by electron diffraction, a ring-shaped region with high brightness and a plurality of spots within the ring-shaped region may be observed in an electron diffraction pattern image.

[0253] When evaluating the crystallinity of CAC-OS, different patterns may be observed depending on the electron beam diameter, i.e., the area of ​​the region to be observed. For example, when evaluating the crystallinity of CAC-OS, it is preferable to use an NBED that measures with an electron beam diameter of 1 nmΦ or more and 100 nmΦ or less.

[0254] Moreover, the region where the oxide containing the element Mb is the main component (region 002 in FIG. 11) is a region with higher conductivity than the region where the oxide containing the element Ma is the main component (region 001 in FIG. 11). In other words, the conductivity of a metal oxide is expressed by carriers flowing through the region where the oxide containing the element Mb is the main component. Therefore, a high field effect mobility (μ) can be realized by distributing the region where the oxide containing the element Mb is the main component in a cloud-like shape in the metal oxide. The region where the oxide containing the element Mb is the main component can be said to be a semiconductor region, which has properties close to those of a conductor.

[0255] On the other hand, the region where the oxide containing the element Ma is the main component is a region with lower conductivity than the region where the oxide containing the element Mb is the main component. In other words, the region where the oxide containing the element Ma is the main component is distributed in the metal oxide, so that the off-current can be suppressed and good switching operation can be realized. The region where the oxide containing the element Ma is the main component can be said to be a semiconductor region, close to the properties of an insulator.

[0256] Therefore, when the CAC-OS of Ma-Mb oxide is used in a semiconductor element, the properties attributable to the oxide containing the element Ma and the properties attributable to the oxide containing the element Mb act complementarily, thereby realizing a large on-current, high field-effect mobility, and small off-current.

[0257] Furthermore, as described above, by including zinc in the region 001, the region 002, and the region between the regions 001 and 002, the zinc can serve as a conductive path to electrically connect the region 001 and the region 002. In this way, carriers (electrons) flow in the metal oxide, with the zinc serving as a conductive path.

[0258] Furthermore, the carrier mobility can be increased by including a larger amount of conductive material than insulating material in the metal oxide film formed from the sputtering target 10. To form such a metal oxide film, it is preferable to increase the ratio of conductive material to insulating material in the sputtering target 10.

[0259] In addition, by using an element having a higher valence than In, Ga, and Zn in the metal oxide, the element becomes a carrier supply source, and the carrier concentration of the region containing the element in the metal oxide film formed using the sputtering target 10 can be increased. Examples of the element include Ti, Ge, Sn, V, Ni, Mo, W, and Ta. In particular, Sn has a stronger bond with oxygen than In, Ga, and Zn. Therefore, by making the metal oxide contain Sn, the generation of oxygen vacancies can be suppressed. Therefore, when the metal oxide film formed using the sputtering target 10 is used in the semiconductor layer of a transistor, the field effect mobility of the transistor can be increased and oxygen vacancies can be suppressed, resulting in a highly reliable semiconductor device.

[0260] Note that the structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0261] (Embodiment 2) In this embodiment, a structure example of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 12A to 21B. Note that the semiconductor device according to one embodiment of the present invention includes a transistor.

[0262] <Example of semiconductor device configuration> A structure of a semiconductor device including a transistor 200 will be described with reference to FIGS. 12A to 12D. FIG. 12A is a top view of the semiconductor device, and FIGS. 12B and 12C are cross-sectional views of the semiconductor device. FIG. 12B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 12A, and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 12C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 12A, and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 12D corresponds to a cross-sectional image of an enlarged region P1 shown in FIG. 12B. Note that some elements are omitted in the top view of FIG. 12A for clarity.

[0263] A semiconductor device of one embodiment of the present invention includes an insulator 212 over a substrate (not shown), an insulator 214 over the insulator 212, a transistor 200 over the insulator 214, an insulator 280 over the transistor 200, an insulator 282 over the insulator 280, and an insulator 283 over the insulator 282. The insulator 212, the insulator 214, the insulator 280, the insulator 282, and the insulator 283 function as interlayer films.

[0264] As shown in Figures 12(A) to 12(C), the transistor 200 has an insulator 216 on an insulator 214, a conductor 205 (conductor 205a and conductor 205b) arranged to be embedded in the insulator 216, an insulator 222 on the insulator 216 and the conductor 205, an insulator 224 on the insulator 222, an oxide 230 (oxide 230a and oxide 230b) on the insulator 224, a conductor 242a and a conductor 242b on the oxide 230, an insulator 271a on the conductor 242a, an insulator 271b on the conductor 242b, an insulator 250 on the oxide 230, and a conductor 260 (conductor 260a and conductor 260b) on the insulator 250. In addition, an insulator 275 is provided on the insulators 271a and 271b, and an insulator 280 is provided on the insulator 275.

[0265] In the following, the conductor 242a and the conductor 242b may be collectively referred to as the conductor 242. Furthermore, the insulator 271a and the insulator 271b may be collectively referred to as the insulator 271.

[0266] Openings reaching the oxide 230 are provided in the insulator 280 and the insulator 275. The insulator 250 and the conductor 260 are disposed in the openings. In addition, in the channel length direction of the transistor 200, the conductor 260 and the insulator 250 are provided between the insulator 271a and the conductor 242a and between the insulator 271b and the conductor 242b.

[0267] The conductor 260 has a region that functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 has a region that functions as a second gate (also referred to as a back gate) electrode. The insulator 250 has a region that functions as a first gate insulator, and the insulators 222 and 224 have regions that function as second gate insulators. Note that the gate insulators may be referred to as a gate insulating layer or a gate insulating film. The conductor 242a has a region that functions as one of a source electrode and a drain electrode, and the conductor 242b has a region that functions as the other of the source electrode and the drain electrode. At least a part of a region of the oxide 230 that overlaps with the conductor 260 functions as a channel formation region.

[0268] The oxide 230 preferably has an oxide 230a disposed on the insulator 224 and an oxide 230b disposed on the oxide 230a. By having the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from a structure formed below the oxide 230a to the oxide 230b.

[0269] 12B and 12C show a structure in which the oxide 230 is a two-layer stack of the oxide 230a and the oxide 230b, but the present invention is not limited to this. For example, the oxide 230 may be a single layer or a stack of three or more layers.

[0270] The transistor 200 preferably uses the metal oxide (hereinafter also referred to as an oxide semiconductor) described in the above embodiment for the oxide 230 (the oxide 230a and the oxide 230b) including a channel formation region. The transistor 200 preferably uses the metal oxide formed using the sputtering target described in the above embodiment for the oxide 230.

[0271] Fig. 12(D) is an enlarged cross-sectional image of region P1 when the metal oxide described in the previous embodiment is used for oxide 230b. As shown in region P1 of Fig. 12(D), the upper surface of oxide 230b contacts conductor 242b, so that the contact resistance can be reduced. In addition, since oxide 230b has the CAC configuration shown in Fig. 11, region 002 of the CAC configuration, i.e., a region with high conductivity, contacts conductor 242b, so that the contact resistance can be further reduced. Although not shown, the connection between oxide 230 and conductor 242a is similar to region P1.

[0272] The metal oxide of one embodiment of the present invention has a highly conductive region and has reduced contact resistance with a conductor, so that the field-effect mobility of a transistor including the metal oxide can be increased.

[0273] The oxide 230 preferably has a laminated structure of a plurality of oxide layers with different chemical compositions. For example, in the metal oxide used for the oxide 230a, the atomic ratio of element M to the metal element that is the main component is preferably larger than the atomic ratio of element M to the metal element that is the main component in the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230a, the atomic ratio of element M to In is preferably larger than the atomic ratio of element M to In in the metal oxide used for the oxide 230b. With this configuration, it is possible to suppress the diffusion of impurities and oxygen from structures formed below the oxide 230a to the oxide 230b.

[0274] In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. With this configuration, the transistor 200 can have a large on-state current and high frequency characteristics.

[0275] In addition, since the oxide 230a and the oxide 230b have a common element other than oxygen as a main component, the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced, so that the effect of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain a large on-current and high frequency characteristics.

[0276] Specifically, the oxide 230a may be a metal oxide having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, or In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto. The oxide 230b may be a metal oxide as described in the previous embodiment. Gallium is preferably used as the element M. When the oxide 230 is configured to be a single layer, the oxide 230 may be a metal oxide applicable to the oxide 230a or the oxide 230b.

[0277] Here, an enlarged view of the vicinity of the channel formation region in FIG. 12B is shown in FIG. 13A, and an enlarged view of the vicinity of the channel formation region in FIG. 12C is shown in FIG. 13B. As shown in FIG. 13A, the oxide 230b has a region 230bc that functions as a channel formation region, and regions 230ba and 230bb that are provided on either side of the region 230bc and function as source and drain regions. At least a portion of the region 230bc overlaps with the conductor 260. In other words, the region 230bc is provided in a region between the conductor 242a and the conductor 242b. The region 230ba is provided overlapping with the conductor 242a, and the region 230bb is provided overlapping with the conductor 242b.

[0278] A transistor having an oxide semiconductor in a channel formation region (hereinafter also referred to as an OS transistor) has impurities and oxygen vacancies (V O ), electrical characteristics are likely to fluctuate and reliability may be reduced. In addition, in oxide semiconductors, defects in which hydrogen is inserted into oxygen vacancies (hereafter referred to as V OH) and generate electrons that act as carriers. Also, in the channel formation region, V O When H is formed, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may vary. For this reason, if oxygen vacancies are present in the channel formation region in the oxide semiconductor, the transistor is likely to have normally-on characteristics. Therefore, in the channel formation region in the oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, it is preferable that a region in the oxide semiconductor where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0279] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor and heat treatment is performed. In this way, oxygen is supplied from the insulator to the oxide semiconductor, and oxygen vacancies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or drain region, the on-current of the transistor 200 may be reduced or the field effect mobility may be reduced. Furthermore, the amount of oxygen supplied to the source region or drain region varies within the substrate surface, which causes variations in the characteristics of the semiconductor device having the transistor.

[0280] Therefore, in the oxide semiconductor, the region 230bc that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the regions 230ba and 230bb that function as source and drain regions preferably have a high carrier concentration and are n-type. O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to the regions 230ba and 230bb.

[0281] In other words, in the oxide semiconductor, the regions 230ba and 230bb preferably have high carrier concentrations and are n-type, while the region 230bc preferably has a reduced carrier concentration and is i-type or substantially i-type. In other words, it is preferable that the n-type region does not extend to the channel formation region.

[0282] For example, by reducing oxygen vacancies in the region 230bc or lowering the concentration of impurities such as hydrogen, nitrogen, and metal elements in the region 230bc compared to the regions 230ba and 230bb, the region 230bc can be made into a high-resistance region with a low carrier concentration. In this case, the region 230bc can be said to be i-type (intrinsic) or substantially i-type.

[0283] In addition, for example, by suppressing the reduction in the amount of oxygen vacancies in the regions 230ba and 230bb or by suppressing the reduction in the impurity concentration, the regions 230ba and 230bb can be made into regions with a high carrier concentration and low resistance. In this case, the regions 230ba and 230bb are n-type regions with a high carrier concentration and low resistance compared to the region 230bc.

[0284] Here, the carrier concentration of the region 230bc functioning as a channel forming region is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the region 230bc is not particularly limited, but may be, for example, 1×10 -9 cm -3 It can be said that:

[0285] In addition, a region may be formed between the region 230bc and the region 230ba, in which the carrier concentration is equal to or lower than that of the region 230ba, and equal to or higher than that of the region 230bc. That is, the region functions as a junction region between the region 230bc and the region 230ba. The junction region may have a hydrogen concentration equal to or lower than that of the region 230ba, and equal to or higher than that of the region 230bc. The junction region may have an oxygen vacancy equal to or less than that of the region 230ba, and equal to or more than that of the region 230bc. The same applies to the region between the region 230bc and the region 230bb.

[0286] 13A shows an example in which the regions 230ba, 230bb, and 230bc are formed in the oxide 230b, but the present invention is not limited to this. For example, each of the above regions may be formed in not only the oxide 230b but also the oxide 230a.

[0287] In addition, it may be difficult to clearly detect the boundaries between the regions in the oxide 230. The concentrations of metal elements and impurities such as hydrogen and nitrogen detected in each region may change continuously within each region, not limited to a stepwise change from region to region. In other words, it is sufficient that the concentrations of impurities such as hydrogen and nitrogen are decreased in the region closer to the channel formation region.

[0288] The oxide 230b is preferably a crystalline oxide semiconductor, such as a CAAC-OS, an nc-OS, a polycrystalline oxide semiconductor, or a single-crystalline oxide semiconductor.

[0289] Since it is difficult to identify clear grain boundaries in CAAC-OS, it is said that the decrease in electron mobility caused by grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, metal oxides with CAAC-OS are resistant to heat and highly reliable.

[0290] In the case of the nc-OS, since there is no regularity in the crystal orientation between different nanocrystals, no orientation is observed throughout the film. In other words, when the nc-OS is used as the oxide 230b, the film characteristics of the oxide 230b are constant regardless of the direction of the carriers flowing through the oxide 230b, and the electrical characteristics of the transistor are stable.

[0291] Note that oxide semiconductors have a variety of structures and each structure has different characteristics. The oxide 230b may include two or more of a CAAC-OS, an nc-OS, an a-like OS, an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, and a CAC-OS.

[0292] 12C, the oxide 230 may have a curved surface between the side surface and the top surface in a cross-sectional view in the channel width direction of the transistor 200. With such a shape, the coverage of the oxide 230 with the insulator 250 and the conductor 260 can be improved.

[0293] At least one of the insulators 212, 214, 271, 275, 282, and 283 preferably functions as a barrier insulating film that suppresses diffusion of impurities from the substrate side or from above the transistor 200 to the transistor 200. Therefore, at least one of the insulators 212, 214, 271, 275, 282, and 283 is preferably made of an insulating material that has a function of suppressing diffusion of impurities. Alternatively, it is preferably made of an insulating material that has a function of suppressing diffusion of oxygen.

[0294] In this specification and the like, a barrier insulating film refers to an insulating film having barrier properties. The barrier properties refer to a property that a corresponding substance is difficult to diffuse (also referred to as a property that a corresponding substance is difficult to permeate, a property that the permeability of a corresponding substance is low, or a function of suppressing the diffusion of a corresponding substance). Alternatively, the barrier properties refer to a function of capturing or fixing a corresponding substance (also referred to as gettering). Note that hydrogen in the description of diffusion of hydrogen or incorporation of hydrogen includes, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH. - The term "diffusion of impurities" refers to at least one of hydrogen-bonded substances such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. The term "oxygen" refers to at least one of oxygen atoms, oxygen molecules, etc.

[0295] For the insulators 212, 214, 271, 275, 282, and 283, it is preferable to use an insulator having a function of suppressing diffusion of impurities and oxygen, and for example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable to use silicon nitride or the like, which has a higher barrier property against hydrogen, for the insulators 212, 275, and 283. Furthermore, it is preferable to use an insulator having a function of capturing or fixing hydrogen for the insulators 214, 271, and 282. This can suppress diffusion of impurities from the substrate side to the transistor 200 through the insulators 212 and 214. Alternatively, it can suppress diffusion of impurities from an interlayer insulating film disposed outside the insulator 283 to the transistor 200. Alternatively, oxygen contained in the insulator 224 or the like can be suppressed from diffusing toward the substrate side through the insulators 212 and 214. Alternatively, oxygen contained in the insulator 280 or the like can be suppressed from diffusing upward from the transistor 200 through the insulator 282 or the like. In this manner, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 271, 275, 282, and 283, which have the function of suppressing the diffusion of impurities and oxygen.

[0296] Examples of insulators having a function of capturing or fixing hydrogen include metal oxides having an amorphous structure. For example, it is preferable to use metal oxides such as magnesium oxide or oxides containing one or both of aluminum and hafnium as the insulators 214, 271, and 282. In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have a property of capturing or fixing hydrogen. In other words, it can be said that metal oxides having an amorphous structure have a high ability to capture or fix hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, hydrogen contained in the transistor 200 or hydrogen present around the transistor 200 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in a channel formation region of the transistor 200. With such a configuration, a transistor 200 and a semiconductor device having good characteristics and high reliability can be manufactured.

[0297] Furthermore, the insulators 214, 271, and 282 preferably have an amorphous structure, but may have a crystalline region formed in a part of them. The insulators 214, 271, and 282 may have a multilayer structure in which a layer having an amorphous structure and a layer having a crystalline region are stacked. For example, they may have a stacked structure in which a layer having a crystalline region, typically a layer having a polycrystalline structure, is formed on a layer having an amorphous structure.

[0298] The insulators 212, 214, 271, 275, 282, and 283 may be formed by, for example, a sputtering method. The sputtering method does not require the use of molecules containing hydrogen in the film formation gas, and therefore can reduce the hydrogen concentration in the insulators 212, 214, 271, 275, 282, and 283. Note that the film formation method is not limited to the sputtering method, and a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like may be used as appropriate.

[0299] The insulator 216 and the insulator 280 are preferably made of a material having a lower dielectric constant than the insulator 214. By using a material having a lower dielectric constant as an interlayer film, the parasitic capacitance occurring between wirings can be reduced. For example, silicon oxide, silicon oxynitride, or silicon nitride oxide can be used as the insulator 216 and the insulator 280. For example, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, or silicon oxide to which carbon and nitrogen are added can be used. For example, silicon oxide having vacancies can be used. These silicon oxides may contain nitrogen. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferable because they can easily form a region containing excess oxygen.

[0300] It is preferable that the concentrations of impurities such as water and hydrogen are reduced in the insulator 280. For example, an oxide containing silicon, such as silicon oxide or silicon oxynitride, may be used as the insulator 280. The top surface of the insulator 280 may be planarized.

[0301] As the conductor 242a and the conductor 242b, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or the like is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when they absorb oxygen.

[0302] Note that hydrogen contained in the oxide 230b etc. may diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b etc. is likely to diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b etc. may be absorbed by the conductor 242a or the conductor 242b.

[0303] Furthermore, when heat treatment is performed while the conductor 242a and the oxide 230b are in contact with each other, the sheet resistance of the oxide 230b in the region overlapping with the conductor 242a may decrease. Also, the carrier concentration may increase. Therefore, the resistance of the oxide 230b in the region overlapping with the conductor 242a can be reduced in a self-aligned manner. The same applies to the oxide 230b in the region overlapping with the conductor 242b.

[0304] The conductor 242 is preferably formed using a conductive film having compressive stress. This allows a strain that expands in the tensile direction (hereinafter, sometimes referred to as tensile strain) to be formed in the regions 230ba and 230bb. The tensile strain causes V OBy stably forming H, the regions 230ba and 230bb can be stable n-type regions. The compressive stress of the conductor 242 is a stress that tries to relax the compressed shape of the conductor 242, and is a stress having a vector in the direction from the center of the conductor 242 to the end portion.

[0305] The magnitude of the compressive stress of the conductor 242 may be, for example, 500 MPa or more, preferably 1000 MPa or more, more preferably 1500 MPa or more, and further preferably 2000 MPa or more. The magnitude of the stress of the conductor 242 may be determined by preparing a sample in which a conductive film used for the conductor 242 is formed on a substrate and measuring the stress of the sample.

[0306] Although the above describes the distortion formed in the oxide 230b, the present invention is not limited to this. Similar distortion may be formed in the oxide 230a.

[0307] The conductor 242a and the conductor 242b may have a single-layer structure or a laminated structure. For example, as shown in FIG. 13(A), the conductor 242a and the conductor 242b may each have a two-layer structure. In this case, the conductor 242a is a laminated body of the conductor 242a1 and the conductor 242a2 on the conductor 242a1, and the conductor 242b is a laminated body of the conductor 242b1 and the conductor 242b2 on the conductor 242b1. In this case, it is preferable to use the above-mentioned conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen as the layer in contact with the oxide 230b (the conductor 242a1 and the conductor 242b1). This can suppress the conductor 242a and the conductor 242b from being excessively oxidized by the oxygen contained in the oxide 230b. In addition, it can suppress the decrease in the conductivity of the conductor 242a and the conductor 242b.

[0308] Moreover, the conductor 242a2 and the conductor 242b2 preferably have higher conductivity than the conductor 242a1 and the conductor 242b1. For example, the film thickness of the conductor 242a2 and the conductor 242b2 is preferably larger than the film thickness of the conductor 242a1 and the conductor 242b1. The conductor 242a2 and the conductor 242b2 may be a conductor that can be used for the conductor 205b. The above structure can reduce the resistance of the conductor 242a2 and the conductor 242b2. This allows the conductor 242a and the conductor 242b to function as wirings or electrodes with high conductivity. Furthermore, the operating speed of the transistor 200 can be improved.

[0309] For example, tantalum nitride or titanium nitride can be used as the conductor 242a1 and the conductor 242b1, and tungsten can be used as the conductor 242a2 and the conductor 242b2.

[0310] As shown in Figures 13(A) and 13(B), it is preferable that the insulator 250 has a layered structure of an insulator 250a in contact with the oxide 230, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b.

[0311] It is preferable that the insulator 250b is made of an insulator that is easily permeable to oxygen. With such a configuration, oxygen contained in the insulator 280 can be supplied to the region 230bc via the insulator 250b. It is preferable that the insulator 250b is made of an insulator that can be applied to the insulator 280. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat. In this case, the insulator 250b contains at least oxygen and silicon. It is also preferable that the concentration of impurities such as water and hydrogen in the insulator 250b is reduced.

[0312] The insulator 250a preferably has a barrier property against oxygen. The insulator 250a has a region in contact with the side surface of the conductor 242a and a region in contact with the side surface of the conductor 242b. The insulator 250a has a barrier property against oxygen, which can prevent the side surfaces of the conductor 242a and the conductor 242b from being oxidized and an oxide film from being formed on the side surface. This can prevent the on-current of the transistor 200 from being reduced or the field-effect mobility from being reduced. Examples of the barrier insulator against oxygen include oxides containing one or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0313] The insulator 250a is provided in contact with the top surface and side surface of the oxide 230b and the side surface of the oxide 230a. That is, in a cross-sectional view in the channel width direction, the region 230bc is surrounded by the insulator 250a and the oxide 230a. Since the insulator 250a and the oxide 230a have a barrier property against oxygen, it is possible to suppress the desorption of oxygen from the region 230bc when a heat treatment or the like is performed. Therefore, it is possible to suppress the formation of oxygen vacancies in the region 230bc. This can improve the electrical characteristics and reliability of the transistor 200.

[0314] Furthermore, by providing the insulator 250a, even if an excessive amount of oxygen is contained in the insulator 280, the oxygen can be prevented from being excessively supplied to the region 230bc, and an appropriate amount of oxygen can be supplied to the region 230bc. Therefore, it is possible to prevent the regions 230ba and 230bb from being excessively oxidized, thereby preventing a decrease in the on-state current of the transistor 200 or a decrease in the field-effect mobility.

[0315] It is preferable to use an insulator containing an oxide containing one or both of aluminum and hafnium as the insulator 250a. In this embodiment, aluminum oxide is used as the insulator 250a. In this case, the insulator 250a contains at least oxygen and aluminum.

[0316] The insulator 250c preferably has a barrier property against hydrogen. This can suppress the diffusion of impurities contained in the conductor 260 into the region 230bc. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, silicon nitride oxide, or the like is preferably used as the insulator 250c. Silicon nitride is particularly preferable because it has a high hydrogen barrier property. In this case, the insulator 250c has at least nitrogen and silicon.

[0317] The insulator 250c may further have a barrier property against oxygen. The insulator 250c is provided between the insulator 250b and the conductor 260. Therefore, the oxygen contained in the insulator 250b is prevented from diffusing into the conductor 260, and the oxidation of the conductor 260 can be suppressed. In addition, the decrease in the amount of oxygen supplied to the region 230bc can be suppressed.

[0318] Silicon nitride has a barrier property against oxygen and can therefore be suitably used as the insulator 250c.

[0319] Also, as shown in FIG. 15(A) and FIG. 15(B), a structure may be used in which an insulator 250d is provided between the insulator 250b and the insulator 250c. The insulator 250d preferably has a function of capturing or fixing hydrogen. By providing an insulator having a function of capturing or fixing hydrogen inside the region surrounded by the insulator 250c and the insulator 222, the hydrogen inside the region can be captured or fixed more effectively. In other words, the hydrogen contained in the insulator 250b, the region 230bc of the oxide 230b, and the insulator 224 can be captured or fixed more effectively. This makes it possible to reduce the hydrogen concentration in the region 230bc. Therefore, the V in the region 230bc can be reduced.O H can be reduced to make region 230bc i-type or substantially i-type.

[0320] For example, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulator 250d, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. In this embodiment, hafnium oxide is used as the insulator 250d. In this case, the insulator 250d contains at least oxygen and hafnium. The insulator 250d may also have an amorphous structure.

[0321] The insulator 250d may be an insulator that can be used for the insulator 222 described later. For example, since the insulator 250 has a region that functions as a first gate insulator, an insulator containing a high-k material described later may be used.

[0322] The insulators 250a to 250d are provided in an opening formed in the insulator 280 or the like together with the conductor 260. To miniaturize the transistor 200, the insulators 250a to 250d preferably have a small thickness. The thicknesses of the insulators 250a to 250d are each set to 0.1 nm to 10 nm, preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, further preferably 1.0 nm to 5.0 nm, and further preferably 1.0 nm to 3.0 nm. In this case, the insulators 250a to 250d may have a region having the above thickness at least in part.

[0323] To thin the thicknesses of the insulators 250a to 250d as described above, it is preferable to form the insulators by an ALD method. The ALD method includes a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD method in which a plasma excited reactant is used. The PEALD method may be preferable because it uses plasma, which enables film formation at a lower temperature.

[0324] The ALD method can deposit atoms one layer at a time, and therefore has the following advantages: extremely thin films can be formed, films can be formed on structures with high aspect ratios, films can be formed with fewer defects such as pinholes, films can be formed with excellent coverage, films can be formed at low temperatures, etc. Therefore, the insulator 250 can be formed with good coverage on the side surfaces of the openings formed in the insulator 280, etc., with a thin film thickness as described above.

[0325] In the above, the insulator 250 has been described as having a three-layer structure of the insulators 250a to 250c or a four-layer structure of the insulators 250a to 250d, but the present invention is not limited to this. The insulator 250 can have at least one of the insulators 250a to 250d. By configuring the insulator 250 as one, two, or three layers of the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0326] 13A shows a configuration in which the insulator 250a contacts the side surfaces of the conductor 242a2 and the conductor 242b2, but the present invention is not limited to this. For example, an insulator 255 may be provided between the insulator 250a and the conductor 242a2 and between the insulator 250a and the conductor 242b2.

[0327] 14(A) and 14(B) are enlarged cross-sectional views of the transistor 200 in the channel length direction. The semiconductor device shown in FIG. 14(A) and the semiconductor device shown in FIG. 14(B) are each a modified example of the semiconductor device shown in FIG. 13(A). Specifically, the semiconductor device shown in FIG. 14(A) and the semiconductor device shown in FIG. 14(B) differ from the semiconductor device shown in FIG. 13(A) in that an insulator 255 is provided between the insulator 250a and the conductor 242a2 and between the insulator 250a and the conductor 242b2.

[0328] As shown in FIG. 14A, in a cross-sectional view of the transistor 200 in the channel length direction, the distance between the conductor 242a1 and the conductor 242b1 is smaller than the distance between the conductor 242a2 and the conductor 242b2. With this configuration, it is possible to shorten the distance between the source and the drain, and accordingly shorten the channel length. This improves the frequency characteristics of the transistor 200. In this way, by miniaturizing the semiconductor device, it is possible to provide a semiconductor device with improved operating speed.

[0329] The insulator 255 is preferably an insulator that is not easily oxidized, such as a nitride. The insulator 255 is formed in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2, and has a function of protecting the conductor 242a2 and the conductor 242b2. Since the insulator 255 is exposed to an oxidizing atmosphere, it is preferable that the insulator 255 is an inorganic insulator that is not easily oxidized. Furthermore, since the insulator 255 is in contact with the conductor 242a2 and the conductor 242b2, it is preferable that the insulator 255 is an inorganic insulator that is not easily oxidized. Therefore, it is preferable that the insulator 255 is made of an insulating material that has a barrier property against oxygen. For example, silicon nitride can be used as the insulator 255.

[0330] The transistor 200 shown in FIG. 14A is formed by forming an opening in the insulator 280 and the insulator 275, forming an insulator 255 in contact with a sidewall of the opening, and further dividing the conductor 242a1 and the conductor 242b1 using a mask. Here, the opening overlaps with a region between the conductor 242a2 and the conductor 242b2. Parts of the conductor 242a1 and the conductor 242b1 are formed to protrude into the opening. Thus, the insulator 255 is in contact with the top surface of the conductor 242a1, the top surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2 in the opening. The insulator 250a is in contact with the top surface of the oxide 230 in the region between the conductor 242a1 and the conductor 242b1.

[0331] 14A shows a configuration in which the insulator 250 has a region overlapping with the conductor 242a1 and the conductor 242b1 via the insulator 255, but the present invention is not limited to this. For example, as shown in FIG. 14B, in an opening formed in the insulator 280 and the insulator 275, a side surface of the insulator 255 may coincide with a side surface of the conductor 242a1, and a side surface of the insulator 255 may coincide with a side surface of the conductor 242b1. With such a configuration, the above-mentioned step of separating the conductor 242a1 and the conductor 242b1 using a mask can be omitted, and therefore the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0332] The conductor 260 preferably has a conductor 260a and a conductor 260b on the conductor 260a. For example, the conductor 260a is preferably arranged so as to wrap the bottom and side surfaces of the conductor 260b. As shown in Fig. 12(B) and Fig. 12(C), the upper surface of the conductor 260 coincides with the upper surface of the insulator 250. Note that, although the conductor 260 is shown as having a two-layer structure of the conductor 260a and the conductor 260b in Fig. 12(B) and Fig. 12(C), it may have a single-layer structure or a laminated structure of three or more layers.

[0333] The conductor 260a is preferably made of a conductive material having a function of suppressing the diffusion of impurities. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen. Since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the conductor 260b from being oxidized by the oxygen contained in the insulator 250 and the conductivity from decreasing. As a conductive material having a function of suppressing the diffusion of oxygen, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like. Therefore, the conductor 260a may be made of the above conductive material in a single layer or a multilayer structure. For example, the conductor 260a may be made of titanium nitride.

[0334] In addition, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0335] Moreover, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably disposed in the region between the conductor 242a and the conductor 242b without alignment.

[0336] 12C, in the channel width direction of the transistor 200, the bottom surface of the conductor 260 in a region that does not overlap with the oxide 230b is preferably lower than the bottom surface of the oxide 230b when the insulator 222 is used as a reference. When the conductor 260, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 230b, the electric field of the conductor 260 can be easily applied to the entire channel formation region of the oxide 230b. Thus, the on-current of the transistor 200 can be increased, and the frequency characteristics can be improved.

[0337] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216. In addition, a part of the conductor 205 may be embedded in the insulator 214.

[0338] The conductor 205 includes a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and side wall of an opening formed in the insulator 216. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the upper surface of the conductor 205b is at the same height as the upper surfaces of the conductor 205a and the insulator 216.

[0339] Here, the conductor 205a is preferably made of a conductive material having a function of suppressing the diffusion of impurities and also preferably made of a conductive material having a function of suppressing the diffusion of oxygen.

[0340] By using a conductive material having a function of suppressing the diffusion of impurities for the conductor 205a, it is possible to suppress the diffusion of impurities contained in the conductor 205b into the oxide 230 via the insulator 216, etc. In addition, by using a conductive material having a function of suppressing the diffusion of oxygen for the conductor 205a, it is possible to suppress the conductor 205b from being oxidized and its conductivity from decreasing.

[0341] The conductor 205a may be made of a conductor that can be used for the conductor 260a. The conductor 205b may be made of a conductive material that is mainly composed of tungsten, copper, or aluminum. For example, the conductor 205b may be made of tungsten.

[0342] 12B and 12C show a structure in which the conductor 205a and the conductor 205b are stacked, the present invention is not limited to this. For example, the conductor 205 may have a single layer or a stacked structure of three or more layers.

[0343] The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to not applying a negative potential.

[0344] As shown in FIG. 12(A), the conductor 205 is preferably provided larger than the size of the region of the oxide 230 that does not overlap with the conductor 242a and the conductor 242b. In particular, as shown in FIG. 12(C), the conductor 205 preferably extends in a region outside the ends of the oxide 230a and the oxide 230b in the channel width direction. In other words, outside the side surface of the oxide 230 in the channel width direction, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator. With this configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. In this specification, a structure of a transistor in which the channel formation region is electrically surrounded by at least the electric field of the first gate electrode is called a surrounded channel (S-channel) structure.

[0345] In this specification, etc., a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification, etc. is different from the Fin type structure and the planar type structure. On the other hand, the S-channel structure disclosed in this specification, etc. can also be regarded as a type of Fin type structure. In this specification, etc., the Fin type structure refers to a structure in which the gate electrode is disposed so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By adopting the Fin type structure and the S-channel structure, it is possible to obtain a transistor that is more resistant to the short channel effect, in other words, in which the short channel effect is less likely to occur.

[0346] By making the transistor 200 have the above-mentioned S-channel structure, the channel formation region can be electrically surrounded. Since the S-channel structure electrically surrounds the channel formation region, it can be said that the S-channel structure is substantially equivalent to a GAA (Gate All Around) structure or a LGAA (Lateral Gate All Around) structure. By making the transistor 200 have the S-channel structure, the GAA structure, or the LGAA structure, the channel formation region formed at the interface or in the vicinity of the interface between the oxide 230 and the gate insulator can be the entire bulk of the oxide 230. Therefore, it is possible to improve the current density flowing through the transistor, and therefore it is expected to improve the on-current of the transistor or the field effect mobility of the transistor.

[0347] 12C, the conductor 205 is extended to function as a wiring. However, the present invention is not limited to this, and a conductor functioning as a wiring may be provided under the conductor 205. Also, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0348] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen. The insulator 222 preferably has a function of suppressing the diffusion of oxygen. For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0349] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Alternatively, an oxide containing hafnium and zirconium, for example, hafnium zirconium oxide, may be preferably used. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side and the diffusion of impurities from the periphery of the transistor 200 to the oxide 230. Thus, by providing the insulator 222, the diffusion of impurities to the inside of the transistor 200 can be suppressed, and the generation of oxygen vacancies in the oxide 230 can be suppressed. In addition, the conductor 205 can be suppressed from reacting with oxygen contained in the insulator 224 and the oxide 230.

[0350] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, these insulators may be nitrided. The insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0351] In addition, since the insulator 222 has a region that functions as a second gate insulator, a single layer or a multilayer of an insulator including a high-k material described later may be used as the insulator 222. Note that, in some cases, a material with a high relative dielectric constant, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST), may be used as the insulator 222.

[0352] As shown in FIGS. 13A and 13B, the insulator 222 may have a layered structure of an insulator 222a over the insulator 216 and the conductor 205 and an insulator 222b over the insulator 222a.

[0353] The insulator 222b may be any of the insulators that can be used for the insulator 222 described above.

[0354] The insulator 222a is provided between the insulator 216 and the conductor 205 and the insulator 222b. The insulator 222a preferably has a function of suppressing diffusion of hydrogen. Thus, diffusion of hydrogen from below the insulator 222a to the transistor 200 can be suppressed.

[0355] The insulator 222a is preferably made of silicon nitride formed by, for example, the ALD method (particularly, the PEALD method). By using the ALD method to form the insulator 222a, the insulator 222a can be formed with good coverage even if unevenness is formed between the insulator 216 and the conductor 205. Therefore, it is possible to prevent pinholes or discontinuities from being formed in the insulator 222b formed on the insulator 222a.

[0356] The insulator 224 in contact with the oxide 230 may be made of, for example, silicon oxide, silicon oxynitride, or the like as appropriate.

[0357] One or both of the insulators 222 and 224 may have a stacked structure of two or more layers. In that case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials. The insulator 224 may be formed in an island shape by overlapping with the oxide 230a. In this case, the insulator 275 is configured to contact the side surface of the insulator 224 and the upper surface of the insulator 222. In this specification, the term "island shape" refers to a state in which two or more layers formed in the same process and using the same material are physically separated.

[0358] The insulator 271a is provided in contact with the upper surface of the conductor 242a, and the insulator 271b is provided in contact with the upper surface of the conductor 242b. The insulator 271 preferably functions as a barrier insulating film against oxygen. For example, the insulator 271 preferably has a function of suppressing oxygen diffusion more than the insulator 280.

[0359] Moreover, since the insulators 271a and 271b are in contact with the conductors 242a and 242b, respectively, they are preferably inorganic insulators that do not easily oxidize the conductors 242a and 242b. For example, the insulators 271a and 271b are preferably made of a nitride insulator that can be used for the insulator 250c. For example, silicon nitride can be used as the insulators 271a and 271b.

[0360] Since the insulating layer that becomes the insulator 271a and the insulator 271b functions as a mask for the conductive layer that becomes the conductor 242a and the conductor 242b, the conductor 242a and the conductor 242b do not have a curved surface between the side surface and the top surface. As a result, the end of the conductor 242a where the side surface and the top surface intersect is angular. Since the end of the conductor 242a where the side surface and the top surface intersect is angular, the cross-sectional area of ​​the conductor 242a is larger than when the end has a curved surface. The same is true for the conductor 242b. Furthermore, by using a nitride insulator that does not easily oxidize metal for the insulator 271a and the insulator 271b, it is possible to suppress excessive oxidation of the conductor 242a and the conductor 242b. As a result, the resistance of the conductor 242a and the conductor 242b is reduced, and the on-current of the transistor 200 can be increased.

[0361] The insulator 275 is provided to cover the insulator 224, the oxide 230, the conductor 242, and the insulator 271. It is preferable that the insulator 275 has a function of capturing hydrogen or fixing hydrogen. In that case, it is preferable that the insulator 275 includes an insulator such as silicon nitride or a metal oxide having an amorphous structure, for example, aluminum oxide or magnesium oxide. Also, for example, the insulator 275 may be a laminated film of aluminum oxide and silicon nitride on the aluminum oxide.

[0362] By providing the insulator 271 and the insulator 275 as described above, it is possible to enclose the conductor 242 in a barrier insulating film against oxygen. With this configuration, it is possible to suppress a situation in which the conductor 242 is directly oxidized by oxygen contained in the insulator 280, causing an increase in resistivity and a decrease in on-current.

[0363] The insulator 282 is provided over the insulator 280, the conductor 260, and the insulator 250. The insulator 282 preferably has a function of suppressing diffusion of impurities from above to the insulator 280, and preferably has a function of capturing or fixing impurities such as hydrogen. The insulator 282 preferably functions as a barrier insulating film against oxygen. As the insulator 282, an insulator such as a metal oxide having an amorphous structure, for example, aluminum oxide, may be used. In this case, the insulator 282 contains at least oxygen and aluminum. By providing the insulator 282 having a function of capturing or fixing impurities such as hydrogen in contact with the insulator 280 in a region sandwiched between the insulator 212 and the insulator 283, the impurities such as hydrogen contained in the insulator 280 can be captured or fixed, and the amount of hydrogen in the region can be made constant. This makes it possible to manufacture a transistor 200 and a semiconductor device having excellent characteristics and high reliability.

[0364] It is more preferable to form the insulator 282 by forming an aluminum oxide film by sputtering using an aluminum target in an atmosphere containing oxygen gas. The amount of oxygen injected into the layer below the insulator 282 can be controlled by the magnitude of the RF (Radio Frequency) power applied to the substrate in the sputtering method. For example, the smaller the RF power, the less the amount of oxygen injected into the layer below the insulator 282, and the amount of oxygen is likely to be saturated even if the film thickness of the insulator 282 is thin. Also, the greater the RF power, the more the amount of oxygen injected into the layer below the insulator 282 increases.

[0365] The insulator 283 functions as a barrier insulating film that suppresses diffusion of impurities from above into the insulator 280. As the insulator 283, a nitride containing silicon, such as silicon nitride or silicon nitride oxide, is preferably used. For example, silicon nitride formed by a sputtering method can be used as the insulator 283. By forming the insulator 283 by a sputtering method, a silicon nitride film with high density can be formed.

[0366] Although the insulators 282 and 283 each have a single layer structure in FIGS. 12B and 12C, the present invention is not limited to this and may have a stacked structure of two or more layers.

[0367] <Materials for semiconductor devices> The following describes constituent materials that can be used in the semiconductor device.

[0368] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), and a resin substrate. Examples of semiconductor substrates include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include a semiconductor substrate having an insulating region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of conductive substrates include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Examples of substrates include a substrate having a metal nitride, a substrate having a metal oxide, and the like. Examples of substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0369] <<Insulators>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, each of which has insulating properties.

[0370] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. It is also possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator. On the other hand, by using a material with a low relative dielectric constant for the insulator that functions as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select materials according to the function of the insulator.

[0371] Examples of materials having a high dielectric constant (high-k) include gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0372] Examples of materials with low relative dielectric constants include inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with voids, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic. Note that materials with low relative dielectric constants are also materials with high dielectric strength.

[0373] In addition, the transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing the transmission of impurities and oxygen. As the insulator having a function of suppressing the transmission of impurities and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as the insulator having a function of suppressing the transmission of impurities and oxygen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, or a metal nitride such as aluminum nitride, silicon nitride oxide, or silicon nitride may be used.

[0374] The insulator that functions as the gate insulator is preferably an insulator having a region containing excess oxygen. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing excess oxygen is provided in contact with or near the oxide 230, oxygen vacancies in the oxide 230 can be reduced.

[0375] <<Conductors>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements, etc. As the alloy containing the above-mentioned metal elements as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, and are therefore preferable. In addition, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0376] A plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0377] In addition, when a metal oxide is used for the channel formation region of a transistor, it is preferable to use a stacked structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for a conductor functioning as a gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0378] In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor functioning as a gate electrode. The conductive material containing the above-mentioned metal element and nitrogen may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may also be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added may also be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Alternatively, hydrogen mixed in from an external insulator may be captured.

[0379] The semiconductor device according to this embodiment includes an OS transistor. The OS transistor has a small off-state current, and therefore a semiconductor device with low power consumption can be realized. In addition, the OS transistor has high frequency characteristics, and therefore a semiconductor device with high operation speed can be realized. Furthermore, by using an OS transistor, a semiconductor device with favorable electrical characteristics, a semiconductor device with little variation in the electrical characteristics of transistors, a semiconductor device with large on-state current, and a semiconductor device with high reliability can be realized.

[0380] <Applications of semiconductor devices> An example of a semiconductor device which is one embodiment of the present invention will be described below with reference to FIGS.

[0381] FIG. 16(A) shows a top view of the semiconductor device 500. The X direction shown in FIG. 16(A) is parallel to the channel length direction of the transistor 200, and the Y direction is perpendicular to the X direction. FIG. 16(B) is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in FIG. 16(A), and is also a cross-sectional view of the channel length direction of the transistor 200. FIG. 16(C) is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in FIG. 16(A), and is also a cross-sectional view of the opening region 400 and its vicinity. Note that some elements are omitted from the top view of FIG. 16(A) for clarity.

[0382] 16A to 16C, structures having the same functions as those of the structures constituting the semiconductor device shown in <Configuration Example of Semiconductor Device> are denoted by the same reference numerals. Note that, in this section, the materials described in detail in <Configuration Example of Semiconductor Device> can be used as the materials constituting the semiconductor device.

[0383] The semiconductor device 500 is a modification of the semiconductor device shown in Figures 12(A) to 12(D). The semiconductor device 500 differs from the semiconductor device shown in Figures 12(A) to 12(D) in that an opening region 400 is formed in the insulator 282 and the insulator 280. The semiconductor device 500 also differs from the semiconductor device shown in Figures 12(A) to 12(D) in that a sealing portion 265 is formed to surround the multiple transistors 200.

[0384] The semiconductor device 500 has a plurality of transistors 200 and a plurality of opening regions 400 arranged in a matrix. A plurality of conductors 260 are provided extending in the Y direction. The opening region 400 is formed in a region that does not overlap with the oxide 230 and the conductor 260. A sealing portion 265 is formed so as to surround the plurality of transistors 200, the plurality of conductors 260, and the plurality of opening regions 400. Note that the number, arrangement, and size of the transistors 200, the conductors 260, and the opening regions 400 are not limited to the structure shown in FIG. 16(A), and may be appropriately set according to the design of the semiconductor device 500.

[0385] An insulator 285 is provided over the insulator 283. As the insulator 285, an insulator similar to the insulator 280 can be used.

[0386] As shown in FIG. 16(B) and FIG. 16(C), the sealing portion 265 is provided so as to surround the plurality of transistors 200, the insulator 216, the insulator 222, the insulator 275, the insulator 280, and the insulator 282. In other words, the insulator 283 is provided so as to cover the plurality of transistors 200, the insulator 216, the insulator 222, the insulator 275, the insulator 280, and the insulator 282. In addition, in the sealing portion 265, the insulator 283 is in contact with the upper surface of the insulator 214. In addition, above the sealing portion 265, the insulator 274 is provided between the insulator 283 and the insulator 285. The upper surface of the insulator 274 is flush with the uppermost surface of the insulator 283. In addition, the insulator 274 may be the same as the insulator 280.

[0387] With such a structure, the multiple transistors 200 can be enclosed by the insulator 283, the insulator 214, and the insulator 212. Here, it is preferable that one or more of the insulators 283, 214, and 212 function as a barrier insulating film against hydrogen. This can prevent hydrogen contained outside the region of the sealing portion 265 from mixing into the region of the sealing portion 265.

[0388] 16(C), insulator 282 has an opening in opening region 400. In addition, insulator 280 may have a groove overlapping the opening of insulator 282 in opening region 400. The depth of the groove may be at most until the top surface of insulator 275 is exposed, and may be, for example, approximately ¼ to ½ of the maximum film thickness of insulator 280.

[0389] 16(C), insulator 283 contacts the side of insulator 282, the side of insulator 280, and the top surface of insulator 280 inside opening region 400. Also, a part of insulator 274 may be formed in opening region 400 so as to fill a recess formed in insulator 283. At this time, the top surface of insulator 274 formed in opening region 400 may be flush with the top surface of insulator 283.

[0390] By performing a heat treatment with such an opening region 400 formed and the insulator 280 exposed from the opening of the insulator 282, part of the oxygen contained in the insulator 280 can be diffused outward from the opening region 400 while supplying oxygen to the oxide 230. This makes it possible to supply sufficient oxygen from the insulator 280, which contains oxygen that is desorbed by heating, to the region that functions as the channel formation region and its vicinity, while preventing an excessive amount of oxygen from being supplied.

[0391] At this time, the hydrogen contained in the insulator 280 can be bonded with oxygen and released to the outside through the opening region 400. The hydrogen bonded with oxygen is released as water. Therefore, the hydrogen contained in the insulator 280 can be reduced, and the hydrogen contained in the insulator 280 can be prevented from mixing with the oxide 230.

[0392] 16A, the shape of the opening region 400 in top view is substantially rectangular, but the present invention is not limited thereto. For example, the shape of the opening region 400 in top view may be rectangular, elliptical, circular, rhombic, or a combination of these. The area and the arrangement interval of the opening region 400 can be appropriately set according to the design of the semiconductor device including the transistor 200. For example, in a region where the density of the transistor 200 is low, the area of ​​the opening region 400 may be increased or the arrangement interval of the opening region 400 may be narrowed. For example, in a region where the density of the transistor 200 is high, the area of ​​the opening region 400 may be narrowed or the arrangement interval of the opening region 400 may be widened.

[0393] According to one embodiment of the present invention, a novel transistor can be provided. Alternatively, a semiconductor device having favorable electrical characteristics can be provided. Alternatively, a semiconductor device with favorable reliability can be provided. Alternatively, a semiconductor device with little variation in transistor characteristics can be provided. Alternatively, a semiconductor device with large on-state current can be provided. Alternatively, a semiconductor device with high field-effect mobility can be provided. Alternatively, a semiconductor device with favorable frequency characteristics can be provided. Alternatively, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, a semiconductor device with low power consumption can be provided.

[0394] <Configuration Example of a Semiconductor Device Having a Transistor 200 and a Capacitive Element 100> 17(A) and 17(B) show a semiconductor device including the above-described transistor 200 and the capacitor 100. Fig. 17(A) is a top view of the semiconductor device. Fig. 17(B) is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in Fig. 17(A) and is also a cross-sectional view of the transistor 200 in the channel length direction. Note that some elements are omitted in the top view of Fig. 17(A) for clarity.

[0395] 17A and 17B, the capacitor 100 and the conductor 112 are arranged over the transistor 200. Here, it is preferable that the overlapping area between the capacitor 100 and the transistor 200 is large when viewed from above. With such a structure, the area occupied by a semiconductor device including the capacitor 100 and the transistor 200 can be reduced. This enables miniaturization or high integration of the semiconductor device.

[0396] The semiconductor device has a conductor 240a and a conductor 240b that function as plugs. The conductor 240a is provided inside an opening formed in the insulators 285, 283, 282, 280, 275, and 271a, and the conductor 240b is provided inside an opening formed in the insulators 285, 283, 282, 280, 275, and 271b.

[0397] 17B, ​​the conductor 240a has a region in contact with the conductor 242a and a region in contact with at least a part of the bottom surface of the conductor 112. The conductor 240b has a region in contact with the conductor 242b and a region in contact with at least a part of the bottom surface of the conductor 110 included in the capacitor 100. In other words, the conductor 240a is electrically connected to one of the source electrode and drain electrode of the transistor 200, and the conductor 240b is electrically connected to the other of the source electrode and drain electrode of the transistor 200.

[0398] The conductor 240a and the conductor 240b are preferably made of a conductive material mainly composed of tungsten, copper, or aluminum, etc. Also, each of the conductor 240a and the conductor 240b may have a laminated structure of a first conductor provided along the side and bottom surfaces of the opening and a second conductor on the first conductor.

[0399] When the conductor 240a and the conductor 240b are laminated, it is preferable to use a conductive material having a function of suppressing impurity permeation for the first conductor disposed near the insulator 285 and the insulator 280. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. In addition, the conductive material having a function of suppressing impurity permeation may be used in a single layer or a laminate. With such a configuration, it is possible to suppress impurities contained in layers above the insulator 283 from being mixed into the oxide 230 through the conductor 240a and the conductor 240b. Note that since the second conductor also functions as wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum may be used as the second conductor.

[0400] 17B shows a structure in which a first conductor and a second conductor are stacked, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a stacked structure of three or more layers.

[0401] Insulator 241a is provided in contact with the inner walls of the openings formed in insulators 285, 283, 282, 280, 275, and 271a, and with the side surfaces of conductor 240a. Insulator 241b is provided in contact with the inner walls of the openings formed in insulators 285, 283, 282, 280, 275, and 271b, and with the side surfaces of conductor 240b. Each of insulators 241a and 241b has a structure in which a first insulator is provided in contact with the inner walls of the openings, and a second insulator is provided further inside.

[0402] The insulator 241a and the insulator 241b preferably function as a barrier insulating film against one or both of hydrogen and oxygen. For example, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like is preferably used as the insulator 241a and the insulator 241b. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide can be used. Since the insulator 241a and the insulator 241b are provided in contact with the insulator 283, the insulator 282, and the insulator 275, respectively, impurities contained in the insulator 280, etc. can be prevented from being mixed into the oxide 230 through the conductor 240a and the conductor 240b. In particular, silicon nitride is preferable because it has high barrier properties against hydrogen.

[0403] The insulator 241a is provided between the insulator 280 and the conductor 240a, and the insulator 241b is provided between the insulator 280 and the conductor 240b. The insulator 280 contains excess oxygen and is provided in the vicinity of the oxide semiconductor. The insulators 241a and 241b have a barrier property against oxygen, so that oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b.

[0404] When the insulators 241a and 241b have a layered structure as shown in FIG. 17B, it is preferable that the first insulator in contact with the inner wall of the opening formed in the insulator 280 or the like and the second insulator inside it are made of a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen. For example, aluminum oxide formed by the ALD method may be used as the first insulator, and silicon nitride formed by the PEALD method may be used as the second insulator. With such a structure, oxidation of the conductors 240a and 240b can be suppressed, and further, the intrusion of hydrogen into the conductors 240a and 240b can be suppressed.

[0405] <Capacitive element 100> The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 functioning as a first electrode (also referred to as a lower electrode), a conductor 120 functioning as a second electrode (also referred to as an upper electrode), and an insulator 132 functioning as a dielectric. A pair of electrodes of the capacitor 100 is composed of the first electrode and the second electrode.

[0406] The conductor 110 and the conductor 120 can be made of the materials described above in <<Conductor>>, either in a single layer or in a laminated layer.

[0407] For example, the conductor 112 provided over the conductor 240a and the conductor 110 provided over the conductor 240b can be formed at the same time. At this time, the conductor 112 has the same conductive material as the conductor 110. Note that the conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100 or the transistor 200.

[0408] 17B shows that the conductor 112 and the conductor 110 have a single-layer structure, but the present invention is not limited to this. For example, the conductor 112 and the conductor 110 may have a stacked structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0409] The insulator 132 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be provided as a stacked layer or a single layer. Furthermore, the insulator 132 can be formed using, for example, an insulator in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order.

[0410] Also, for example, it is preferable to use a laminated structure of an insulator containing a material with high dielectric strength (a material with low dielectric constant) and an insulator containing a material with high dielectric constant (high-k) for the insulator 132. With this configuration, the capacitance element 100 can ensure sufficient capacitance by having an insulator containing a high-k material, and the capacitance element 100 can have improved dielectric strength by having an insulator containing a material with high dielectric strength, thereby suppressing electrostatic breakdown of the capacitance element 100.

[0411] An insulator 150 is provided over the conductor 120 and the insulator 132. The insulator 150 functions as an interlayer film.

[0412] For example, the insulator 150 preferably includes the above-mentioned material having a low dielectric constant. Alternatively, the insulator 150 preferably has a laminated structure of an insulator including an inorganic insulating material having a low dielectric constant and an insulator including a resin having a low dielectric constant. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with a resin to form a laminated structure that is thermally stable and has a low dielectric constant. By using a material having a low dielectric constant for the insulator 150, the parasitic capacitance occurring between wirings can be reduced.

[0413] In the semiconductor device shown in Figures 17(A) and 17(B), the shape of the capacitor 100 is a planar type, but the present invention is not limited to this. For example, the shape of the capacitor 100 may be a cylindrical type as shown in Figure 18. In the semiconductor device shown in Figure 18, the configuration below the insulator 150 is similar to that of the semiconductor device shown in Figures 17(A) and 17(B).

[0414] 18, an insulator 150 is disposed on an insulator 132, and an insulator 142 is disposed on the insulator 150. An opening 168 reaching the conductor 110 is formed in the insulators 132, 150, and 142.

[0415] 18 includes a conductor 115, an insulator 145 on the conductor 115 and the insulator 142, and a conductor 125 on the insulator 145. Here, at least a portion of each of the conductor 115, the insulator 145, and the conductor 125 is disposed inside the opening 168.

[0416] An insulator 151 is disposed on the conductor 125 and the insulator 145, an insulator 154 is disposed on the insulator 151, and a conductor 153 and an insulator 156 are disposed on the insulator 154. Also, a conductor 140 is provided inside openings formed in the insulators 132, 150, 142, 145, 151, and 154.

[0417] The conductor 115 functions as a first electrode, the conductor 125 functions as a second electrode, and the insulator 145 functions as a dielectric. The capacitor 100 has a configuration in which the first electrode and the second electrode face each other with a dielectric sandwiched between them not only on the bottom surface but also on the side surface inside the opening 168, and the capacitance per unit area can be increased. Therefore, the deeper the opening, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can promote miniaturization or high integration of semiconductor devices.

[0418] The insulator 151 may be formed using an insulator that can be used for the insulator 150. The insulator 142 may be formed using an insulator that can be used for the insulator 282.

[0419] The shape of the opening 168 as viewed from above may be a rectangle, a polygon other than a rectangle, a polygon with curved corners, or a circle including an ellipse. Here, it is preferable that the area of ​​overlap between the opening 168 and the transistor 200 is large when viewed from above. With such a configuration, the area occupied by a semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0420] The conductor 115 is disposed in contact with each of the side surfaces of the insulator 150 and the insulator 142 in the opening 168. The upper surface of the conductor 115 is preferably at the same height as the upper surface of the insulator 142. The lower surface of the conductor 115 is in contact with the conductor 110 through the opening 168. The conductor 115 is preferably formed by using an ALD method or a CVD method, and for example, a conductor applicable to the conductor 205 may be used.

[0421] The insulator 145 is disposed to cover the conductor 115 and the insulator 142. The insulator 145 is preferably formed by an ALD method, a CVD method, or the like. The insulator 145 can be any insulator that can be used for the insulator 132.

[0422] The conductor 125 is disposed so as to fill the opening 168. The conductor 125 is preferably formed by using an ALD method, a CVD method, or the like, and may be made of a conductor that can be used for the conductor 205, for example.

[0423] The conductor 153 is provided over the insulator 154 and is covered with the insulator 156. The conductor 153 may be a conductor that can be used for the conductor 112. The insulator 156 may be an insulator that can be used for the insulator 150. Here, the conductor 153 is in contact with a top surface of the conductor 140 and functions as a terminal of the capacitor 100 or the transistor 200.

[0424] 18 shows a configuration in which the lower electrode of the cylindrical capacitor 100 is electrically connected to the other of the source electrode and drain electrode of the transistor 200 through the conductor 240b, but the present invention is not limited to this. For example, as shown in FIG. 19, the lower electrode of the cylindrical capacitor may be in contact with the other of the source electrode and drain electrode of the transistor 200.

[0425] Fig. 19 shows a semiconductor device having the above-mentioned transistor 200 and a capacitive element 100 having a cylindrical shape. In Fig. 19, the X direction is parallel to the channel length direction of the transistor 200, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X direction and the Y direction. Hereinafter, the parts different from the semiconductor device shown in Fig. 18 will be mainly described, and the description of the overlapping parts will be omitted.

[0426] An insulator 284 is provided over the insulator 285. The insulator 284 may be any insulator that can be used for the insulator 216.

[0427] The capacitor 100 includes a conductor 153 on the conductor 242b, an insulator 154 on the conductor 153, and a conductor 160 (conductor 160a and conductor 160b) on the insulator 154.

[0428] At least a portion of the conductor 153, the insulator 154, and the conductor 160 is disposed inside the opening formed in the insulator 271b, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285, respectively. The ends of the conductor 153, the insulator 154, and the conductor 160 are located at least on the insulator 282, and preferably on the insulator 285. The insulator 154 is provided so as to cover the end of the conductor 153. This allows the conductor 153 and the conductor 160 to be electrically insulated from each other.

[0429] The conductor 153 has a region that functions as a first electrode (lower electrode). The insulator 154 has a region that functions as a dielectric. The conductor 160 has a region that functions as a second electrode (upper electrode). The capacitor 100 constitutes a metal-insulator-metal (MIM) capacitor.

[0430] In addition, the conductor 242 b provided so as to overlap the oxide 230 functions as a wiring electrically connected to the conductor 153 of the capacitor 100 .

[0431] The conductor 153 and the conductor 160 of the capacitor 100 can be made of a conductor that can be used as the conductor 205, the conductor 242a, the conductor 242b, or the conductor 260. The conductor 153 and the conductor 160 are preferably formed by a film formation method with good coverage such as an ALD method or a CVD method. For example, the conductor 153 can be made of titanium nitride or tantalum nitride formed by an ALD method or a CVD method.

[0432] Furthermore, the upper surface of the conductor 242b contacts the lower surface of the conductor 153. Here, by using a conductive material with good conductivity as the conductor 242b, the contact resistance between the conductor 153 and the conductor 242b can be reduced.

[0433] Also, the conductor 160a may be made of titanium nitride formed by ALD or CVD, and the conductor 160b may be made of tungsten formed by CVD. If the adhesion of tungsten to the insulator 154 is sufficiently high, the conductor 160 may have a single layer structure of tungsten formed by CVD.

[0434] A material with a high dielectric constant is preferably used for the insulator 154 of the capacitor 100. The insulator 154 is preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method.

[0435] Also, it is preferable to use a laminated structure of a material with a high relative dielectric constant and a material with a high dielectric strength as the insulator 154. For example, an insulator laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used as the insulator 154. Also, for example, an insulator laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used. Also, for example, an insulating film laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used. By using a laminated insulator with a relatively high dielectric strength such as aluminum oxide, the dielectric strength is improved and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0436] Furthermore, the insulator 154 may be made of a material that can have ferroelectricity, which will be described later.

[0437] The deeper the openings formed in the insulators 271b, 275, 280, 282, 283, and 285 are (that is, the thicker one or more of the insulators 271b, 275, 280, 282, 283, and 285 are), the larger the capacitance of the capacitive element 100. By increasing the capacitance per unit area of ​​the capacitive element 100, miniaturization or high integration of a semiconductor device can be achieved.

[0438] Here, since the insulators 271b, 275, 282, and 283 function as barrier insulating films, it is preferable to set the film thickness according to the barrier properties required for the semiconductor device. Furthermore, since the film thickness of the conductor 260 functioning as a gate electrode is determined according to the film thickness of the insulator 280, it is preferable to set the film thickness of the insulator 280 according to the film thickness of the conductor 260 required for the semiconductor device.

[0439] Therefore, it is preferable to set the capacitance of the capacitor 100 by adjusting the thickness of the insulator 285. For example, the thickness of the insulator 285 may be set in the range of 50 nm to 250 nm, and the depth of the opening may be set to about 150 nm to 350 nm. By forming the capacitor 100 in such a range, the capacitor 100 can have a sufficient capacitance, and the height of one layer in a semiconductor device in which a plurality of layers including the capacitor 100 are stacked can be prevented from becoming excessively high. Note that the capacitance of the capacitor may be different in each of the plurality of layers. In this configuration, for example, the thickness of the insulator 285 provided in each layer may be different.

[0440] In an opening provided in the insulator 285 or the like in which the capacitor 100 is disposed, the sidewall of the opening may be approximately perpendicular to the top surface of the insulator 222 or may have a tapered shape. By making the sidewall tapered, the coverage of the conductor 153 or the like provided in the opening can be improved and defects such as voids can be reduced.

[0441] The conductor 240 is provided inside an opening formed in the insulator 216, the insulator 222, the insulator 275, the insulator 280, the insulator 282, the insulator 283, the insulator 285, and the insulator 284. The conductor 240 is provided in contact with one of the source electrode and the drain electrode (the conductor 242a) of the transistor 200. The conductor 240 is provided extending in the Z direction.

[0442] Moreover, the conductor 242a provided on the oxide 230 has a region that functions as wiring electrically connected to the conductor 240. For example, in FIG. 19, the upper surface and side end of the conductor 242a are electrically connected to the conductor 240 extending in the Z direction. Since the conductor 240 directly contacts at least one of the upper surface and side end of the conductor 242a, there is no need to provide a separate electrode for connection, and therefore the area occupied by the semiconductor device can be reduced. Note that the conductor 240 preferably contacts a part of the upper surface and the side end of the conductor 242a. Since the conductor 240 contacts multiple surfaces of the conductor 242a, the contact resistance between the conductor 240 and the conductor 242a can be reduced.

[0443] The conductor 240 is preferably a laminated structure of a first conductor and a second conductor. For example, as shown in FIG. 19, the conductor 240 can be structured such that the first conductor is provided in contact with the inner wall of the opening, and the second conductor is provided further inside. That is, the first conductor is disposed closer to the insulators 216, 222, 275, 280, 282, 283, 285, and 284 than the second conductor. The first conductor is in contact with the upper surface and side end of the conductor 242a.

[0444] The first conductor of the conductor 240 may be a conductive material that can be used for the first conductor of the conductor 240a or the conductor 240b described above, and the second conductor of the conductor 240 may be a conductive material that can be used for the second conductor of the conductor 240a or the conductor 240b described above.

[0445] For example, it is preferable to use titanium nitride as the first conductor of conductor 240 and tungsten as the second conductor of conductor 240. In this case, the first conductor of conductor 240 includes titanium and nitrogen, and the second conductor of conductor 240 includes tungsten.

[0446] The conductor 240 may have a single-layer structure or a laminated structure of three or more layers.

[0447] 19, the insulator 241 is preferably provided in contact with the side surface of the conductor 240. Specifically, the insulator 241 is provided in contact with the inner walls of the openings provided in the insulators 216, 222, 275, 280, 282, 283, 285, and 284. The insulator 241 is also formed on the side surfaces of the insulator 224, the oxide 230, and the conductor 242a, which are formed to protrude inward from the openings. Here, at least a portion of the conductor 242a is exposed from the insulator 241 and is in contact with the conductor 240. In other words, the conductor 240 is provided so as to fill the inside of the openings via the insulator 241.

[0448] 19, the uppermost portion of the insulator 241 formed below the conductor 242a is preferably located below the upper surface of the conductor 242a. With this configuration, the conductor 240 can be in contact with at least a portion of the side end portion of the conductor 242a. The insulator 241 formed below the conductor 242a preferably has a region in contact with the side surface of the oxide 230. With this configuration, it is possible to prevent impurities contained in the insulator 280, etc. from being mixed into the oxide 230 through the conductor 240.

[0449] As the insulator 241, an insulator that can be used for the insulator 241a and the insulator 241b described above may be used.

[0450] 19 shows a structure in which the insulator 241 is a single layer, the present invention is not limited to this, and the insulator 241 may have a laminated structure of two or more layers.

[0451] When the insulator 241 has a two-layer structure, a barrier insulating film against oxygen may be used for the first layer in contact with the inner wall of the opening of the insulator 280, etc., and a barrier insulating film against hydrogen may be used for the second layer inside the first layer. For example, aluminum oxide formed by the ALD method may be used for the first layer, and silicon nitride formed by the PEALD method may be used for the second layer. This structure can suppress oxidation of the conductor 240 and further suppress the mixing of hydrogen from the conductor 240 into the oxide 230, etc. This can improve the electrical characteristics and reliability of the transistor 200.

[0452] In the opening where the conductor 240 and the insulator 241 are disposed, the sidewall of the opening may be approximately perpendicular to the upper surface of the insulator 222 or may be tapered. By making the sidewall tapered, the coverage of the insulator 241 and the like provided in the opening is improved.

[0453] A semiconductor device having a transistor 200 and a capacitor 100, in which one of the source and drain of the transistor 200 is electrically connected to one of a pair of electrodes of the capacitor 100, can function, for example, as a memory cell of a memory device.

[0454] <Configuration Example of a Semiconductor Device Having a Transistor 200 and a Capacitive Element 100A> 20(A) and 20(B) show a semiconductor device including the above-described transistor 200 and a capacitor 100A. Fig. 20(A) is a top view of the semiconductor device. Fig. 20(B) is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in Fig. 20(A) and is also a cross-sectional view of the transistor 200 in the channel length direction. Note that some elements are omitted in the top view of Fig. 20(A) for clarity.

[0455] 20A and 20B, a capacitor 100A and a conductor 246 are arranged over a transistor 200. The conductor 246 functions as a wiring. Here, it is preferable that an overlapping area between the capacitor 100A and the transistor 200 is large when viewed from above. With such a structure, the area occupied by a semiconductor device including the capacitor 100A and the transistor 200 can be reduced. This enables miniaturization or high integration of the semiconductor device.

[0456] 20(A) and 20(B) has a configuration below the insulator 285 that is similar to that of the semiconductor device shown in Figures 17(A) and 17(B). In the following, differences from the semiconductor device shown in Figures 17(A) and 17(B) will be mainly described, and descriptions of overlapping parts will be omitted.

[0457] The semiconductor device shown in FIGS. 20A and 20B has an insulator 287 over an insulator 285.

[0458] The conductor 240a is provided inside an opening formed in the insulator 287, the insulator 285, the insulator 283, the insulator 282, the insulator 280, the insulator 275, and the insulator 271a, and the conductor 240b is provided inside an opening formed in the insulator 287, the insulator 285, the insulator 283, the insulator 282, the insulator 280, the insulator 275, and the insulator 271b. As shown in FIG. 20B, the conductor 240a has a region in contact with the conductor 242a and a region in contact with at least a part of the lower surface of the conductor 246. The conductor 240b has a region in contact with the conductor 242b and a region in contact with at least a part of the lower surface of the conductor 110 in the capacitor 100A.

[0459] The conductor 246 may be disposed in contact with the upper surface of the conductor 240a. The conductor 246 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 246 may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above-mentioned conductive material. The conductor 246 is preferably configured to be formed in the same layer as the conductor 110 and from the same material.

[0460] <Capacitive element 100A> The capacitance element 100A has a conductor 110, a conductor 120, and an insulator 130 sandwiched between the conductors 110 and 120. For example, the conductor 110 is disposed on the insulator 287 and the conductor 240b, the insulator 130 is disposed on the conductor 110, and the conductor 120 is disposed on the insulator 130. Here, the conductor 110 functions as a first electrode of the capacitance element 100A, the conductor 120 functions as a second electrode of the capacitance element 100A, and the insulator 130 functions as a dielectric of the capacitance element 100A.

[0461] It is preferable that the insulator 130 is made of a material that can have ferroelectricity. Examples of the material that can have ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. X(X is a real number greater than 0). Examples of materials that can have ferroelectricity include materials in which an element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 can be set appropriately, for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close thereto. Examples of materials that can have ferroelectricity include materials in which an element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide. Also, the ratio of the number of zirconium atoms to the number of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close thereto. In addition, lead titanate (PbTiO X Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0462] Moreover, examples of materials that can have ferroelectricity include metal nitrides having elements MX1, MX2, and nitrogen. Here, the element MX1 is one or more selected from aluminum, gallium, indium, and the like. The element MX2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, and the like. The ratio of the number of atoms of the element MX1 to the number of atoms of the element MX2 can be set appropriately. Also, a metal oxide having the element MX1 and nitrogen may have ferroelectricity even if it does not contain the element MX2. Examples of materials that can have ferroelectricity include materials in which the element MX3 is added to the above metal nitride. The element MX3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, and the like. Here, the ratio of the number of atoms of the element MX1, the number of atoms of the element MX2, and the number of atoms of the element MX3 can be set appropriately.

[0463] Moreover, examples of materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 with a κ-alumina structure.

[0464] In the above description, metal oxides and metal nitrides are exemplified, but the present invention is not limited thereto. For example, metal oxide nitrides in which nitrogen is added to the above-mentioned metal oxides, or metal nitride oxides in which oxygen is added to the above-mentioned metal nitrides, etc. may be used.

[0465] As a material capable of having ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulator 130 can have a laminated structure made of a plurality of materials selected from the materials listed above. However, the crystal structure (characteristics) of the materials listed above may change depending on not only the film formation conditions but also various processes, so in this specification, not only materials that exhibit ferroelectricity are called ferroelectrics, but also materials capable of having ferroelectricity.

[0466] Metal oxides containing one or both of hafnium and zirconium are preferable because they can have ferroelectricity even when processed into a thin film of several nm. Here, the film thickness of the insulator 130 can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically 2 nm or more and 9 nm or less). For example, the film thickness is preferably 8 nm or more and 12 nm or less. By forming a ferroelectric layer that can be thinned, the capacitive element 100A can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device. In this specification, etc., a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. In addition, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device in this specification, etc.

[0467] In addition, a metal oxide containing one or both of hafnium and zirconium is preferable because it can have ferroelectricity even in a small area. For example, when the area (occupied area) of the ferroelectric layer in a top view is 10,000 μm 2 Below, 1000μm 2 Below, 100μm 2 Below, 10μm 2 Below, 1μm 2 Less than or equal to 0.1μm 2 The ferroelectric layer can have ferroelectricity even if it is less than 100. By using a ferroelectric layer with a small area, the area occupied by the capacitive element 100A can be reduced.

[0468] A material that can have ferroelectricity is an insulator, and has a property that polarization occurs inside when an electric field is applied from the outside, and the polarization remains even when the electric field is made zero. Therefore, a nonvolatile memory element can be formed by using a capacitance element (hereinafter, sometimes called a ferroelectric capacitor) using the material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a FeRAM (Ferroelectric Random Access Memory), a ferroelectric memory, etc. For example, a ferroelectric memory has a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, the capacitance element 100A shown in this embodiment is a ferroelectric capacitor, and a semiconductor device having the capacitance element 100A and the above-mentioned transistor 200 can function as a ferroelectric memory.

[0469] It is said that ferroelectricity is expressed by displacing oxygen in the crystals contained in the ferroelectric layer due to an external electric field. It is also presumed that the expression of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulator 130 to express ferroelectricity, the insulator 130 needs to include crystals. In particular, it is preferable for the insulator 130 to include crystals having an orthorhombic crystal structure, since ferroelectricity is expressed. The crystal structure of the crystals contained in the insulator 130 may be one or more selected from the tetragonal, orthorhombic, and monoclinic systems. The insulator 130 may have an amorphous structure. In this case, the insulator 130 may be a composite structure having an amorphous structure and a crystalline structure.

[0470] To form the insulator 130 containing crystals, it is preferable to reduce impurities such as hydrogen or chlorine in the insulator 130. These impurities may form oxygen vacancies in the crystals in the insulator 130. Furthermore, impurities such as hydrogen may bind to the oxygen vacancy sites, which may reduce the crystallinity of the insulator 130. Thus, the inclusion of these impurities in the insulator 130 may inhibit the crystallization of the insulator 130. Thus, to improve the ferroelectricity of the insulator 130, it is preferable to reduce impurities such as hydrogen or chlorine.

[0471] 20B, it is preferable to provide an insulator 152 so as to cover the capacitor 100A and to provide an insulator 155 between the insulator 152 and the insulator 130. In this case, it is preferable that the insulator 155 be in contact with the insulator 287 in a region that does not overlap with the conductor 110.

[0472] The insulator 152 preferably has a function of suppressing the diffusion of hydrogen. Therefore, the insulator 152 preferably has a higher ability to suppress the diffusion of hydrogen than the insulator 130. For example, the insulator that can be used for the insulator 212 described above can be used for the insulator 152. For example, silicon nitride is preferably used as the insulator 152. In this case, the insulator 152 contains at least nitrogen and silicon.

[0473] The insulator 155 has a function of capturing or fixing hydrogen. Therefore, it is preferable that the insulator 155 has a higher ability to capture or fix hydrogen than the insulator 130. The insulator 155 can be any insulator that can be used for the insulator 214 described above. It is preferable to use aluminum oxide, for example, as the insulator 155. In this case, the insulator 155 contains at least oxygen and aluminum.

[0474] The insulator 152 can suppress the diffusion of impurities from outside the insulator 152 to the insulator 130. Furthermore, impurities such as hydrogen present inside the region surrounded by the insulator 152 can be captured or fixed by the insulator 155, thereby reducing the concentration of impurities such as hydrogen contained in the insulator 130. In this way, by eliminating impurities such as hydrogen in the insulator 130 or by reducing the amount of impurities such as hydrogen to an extremely low level, it is possible to improve the crystallinity of the insulator 130 and achieve a structure having high ferroelectricity.

[0475] 20B, the insulator 155 has a layered structure of an insulator 155a and an insulator 155b provided on and in contact with the insulator 155a. The insulator 152 has a layered structure of an insulator 152a and an insulator 152b provided on and in contact with the insulator 152a. Note that the above is not limiting, and one or both of the insulator 155 and the insulator 152 may have a single layer structure or a layered structure of three or more layers.

[0476] The insulator 155a is preferably formed by depositing an insulator applicable to the insulator 155 described above using an ALD method, particularly a thermal ALD method. For example, the insulator 155a can be formed of aluminum oxide deposited by an ALD method. This allows the insulator 155a to be deposited with good coverage, so that even if a pinhole or a step is formed in the insulator 155b deposited by a sputtering method, the diffusion of impurities from the outside of the insulator 155b to the insulator 130 through the pinhole or step can be suppressed.

[0477] The insulator 155b may be formed by using a sputtering method using an insulator that can be used for the insulator 155. For example, the insulator 155b may be formed using aluminum oxide formed by a sputtering method. The sputtering method does not require the use of molecules containing hydrogen in the deposition gas, and therefore the hydrogen concentration in the insulator 155b can be reduced. This allows more impurities such as hydrogen contained in the insulator 130 to be captured or fixed.

[0478] The insulator 152a may be formed by depositing an insulator that can be used for the insulator 152 by a sputtering method. For example, the insulator 152a may be formed using silicon nitride deposited by a sputtering method. The sputtering method does not require the use of molecules containing hydrogen in a deposition gas, and therefore the hydrogen concentration in the insulator 152a can be reduced.

[0479] The insulator 152b is preferably formed by depositing an insulator applicable to the insulator 152 described above using the ALD method, particularly the PEALD method. For example, silicon nitride deposited by the PEALD method can be used as the insulator 152b. As a result, even if pinholes or discontinuities are formed in the insulator 152a deposited by the sputtering method, the portions overlapping the pinholes or discontinuities can be blocked with silicon nitride deposited by the ALD method, which has good coverage. Furthermore, by covering the pinholes or discontinuities with the insulator 152b, the diffusion of impurities from the outside of the insulator 152b to the insulator 130 can be suppressed.

[0480] 20B, the insulator 155 and the insulator 152 are provided to cover not only the capacitor 100A but also the conductor 246. This can suppress diffusion of impurities such as hydrogen into the oxide 230 through the capacitor 100A, the conductor 246, and the conductor 240 during heat treatment. In this manner, the manufacturing process of a high-purity intrinsic ferroelectric capacitor in which impurities such as hydrogen are reduced and a high-purity intrinsic oxide semiconductor in which impurities such as hydrogen are reduced are highly compatible. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0481] The insulator 287 is preferably an insulator having a high ability to suppress the diffusion of impurities, similar to the insulator 152. By configuring the insulator 155 and the insulator 287 to be in contact with each other in a region not overlapping with the capacitor element 100A, the capacitor element 100A is sealed by the insulator 287, the insulator 155, and the insulator 152. This suppresses the diffusion of hydrogen from the outside of the insulator 152 and the insulator 287 to the capacitor element 100A, and further captures or fixes hydrogen inside the region surrounded by the insulator 152 and the insulator 287, thereby reducing the hydrogen concentration in the insulator 130 of the capacitor element 100A. Therefore, the ferroelectricity of the insulator 130 can be improved.

[0482] 20B shows a configuration in which the insulator 287 is in contact with the insulator 155 in a region that does not overlap with the conductor 110; however, the present invention is not limited to this. A configuration in which the lower surface of the conductor 246, the lower surface of the insulator 155a, and the lower surface of the conductor 110 are in contact with the upper surface of the insulator 285 may be used without providing the insulator 287.

[0483] A layer for improving the crystallinity of the insulator 130 may be provided between the insulator 130 and the conductor 110 and / or between the insulator 130 and the conductor 120. As the layer for improving the crystallinity, for example, a layer containing at least one of the elements contained in the insulator 130 is preferably used. Note that it is preferable that the composition of the layer for improving the crystallinity is different from the composition of the insulator 130. For example, HfZrO X When using a metal oxide such as hafnium oxide or zirconium oxide, or a metal such as hafnium or zirconium is preferably used as the layer for enhancing crystallinity.

[0484] The composition of the layer that enhances the crystallinity does not need to include the elements contained in the insulator 130. In this case, elements that can be used include silicon, yttrium, aluminum, and scandium. By providing a layer that enhances the crystallinity, the crystallinity of the insulator 130 can be improved, and the ferroelectricity of the insulator 130 can be enhanced. Since the ferroelectricity of the insulator 130 can be enhanced by improving the crystallinity of the insulator 130, the layer that enhances the crystallinity can be rephrased as a layer that increases the remanent polarization of the insulator 130.

[0485] The conductor 110 may have a single layer structure or a multilayer structure. The conductor 110 may be any conductor that can be used for the conductor 110 of the capacitor 100 described above.

[0486] In FIG. 20B, the conductor 120 has a layered structure of a conductor 120a and a conductor 120b provided on and in contact with the conductor 120a.

[0487] The conductor 120a may be formed by depositing a conductor applicable to the conductor 120 of the above-described capacitor element 100 using a sputtering method, an ALD method, a CVD method, or the like. The conductor 120a may be formed by depositing titanium nitride using a sputtering method, for example.

[0488] Alternatively, the conductor 120a may be formed by depositing titanium nitride using, for example, a thermal ALD method. In this case, the deposition of the conductor 120a may be performed, for example, at a substrate temperature of room temperature or higher, 300° C. or higher, 325° C. or higher, or 350° C. or higher, and 500° C. or lower, or 450° C. or lower. For example, the substrate temperature may be set to about 400° C.

[0489] By forming the conductor 120a in the above-mentioned temperature range, it is possible to impart ferroelectricity to the insulator 130 without performing a high-temperature bake process (for example, a bake process at a heat treatment temperature of 400° C. or higher or 500° C. or higher) after the formation of the conductor 120a. In addition, by forming the conductor 120a using the ALD method, which causes relatively little damage to the base as described above, it is possible to suppress excessive destruction of the crystal structure of the insulator 130, thereby improving the ferroelectricity of the insulator 130. Note that improving the crystallinity or ferroelectricity of the insulator 130 by utilizing the temperature at which the conductor 120 is formed without performing annealing after the formation of the conductor 120a is sometimes referred to as self-annealing.

[0490] The conductor 120b may be formed by depositing a conductor applicable to the conductor 120 of the capacitor 100 by a sputtering method, an ALD method, a CVD method, or the like. For example, a tungsten film may be formed by a sputtering method.

[0491] However, the present invention is not limited to the above, and the conductor 120 may have a single layer structure or a structure of three or more layers.

[0492] <Modifications of Capacitive Element 100A> 20(A) and 20(B) has a configuration in which the side surface of the conductor 110, the side surface of the insulator 130, and the side surface of the conductor 120 are flush with each other, but the present invention is not limited to this. Below, a modified example of the capacitor 100A shown in Fig. 20(A) and Fig. 20(B) will be described with reference to Fig. 21(A) and Fig. 21(B). Hereinafter, the differences from the semiconductor device shown in Fig. 20(A) and Fig. 20(B) will be mainly described, and the description of the overlapping parts will be omitted.

[0493] FIG. 21A is a cross-sectional view of a semiconductor device and a cross-sectional view of a transistor 200 in a channel length direction.

[0494] 21(A), a configuration may be used in which the side surface of the conductor 110 is located inside the side surfaces of the insulator 130 and the conductor 120. The insulator 130 is formed to cover the upper surface and side surfaces of the conductor 110, and the area of ​​the insulator 130 that does not overlap with the conductor 110 contacts the insulator 287. In this case, when viewed from above, the outer periphery of the conductor 110 is located inside the outer peripheries of the insulator 130 and the conductor 120. With this configuration, the insulator 130 can sufficiently separate the conductor 110 and the conductor 120.

[0495] Furthermore, by increasing the area of ​​the conductor 120 when viewed from above, sufficient design margin can be ensured when providing a conductor (not shown) that connects to the conductor 120 and functions as a plug or wiring.

[0496] 20B shows a structure in which the conductor 110 is a single layer, the present invention is not limited to this, and the conductor 110 may have a laminated structure of two or more layers. For example, as shown in FIG 21A, the conductor 110 may have a two-layered structure of a conductor 110a and a conductor 110b on the conductor 110a.

[0497] The conductor 110a may be formed by depositing a conductor applicable to the above-mentioned conductor 110 by a sputtering method, an ALD method, a CVD method, or the like. For example, a tungsten film may be formed by a sputtering method or a CVD method.

[0498] The conductor 110b in contact with at least a portion of the lower surface of the insulator 130 may be formed by depositing a conductor applicable to the conductor 110 described above using an ALD method, a CVD method, or the like. For example, a titanium nitride film may be formed using a thermal ALD method. In addition, it is preferable that the upper surface of the conductor 110b has good flatness. By improving the flatness of the upper surface of the conductor 110b, the crystallinity of the insulator 130 can be improved, and the ferroelectricity of the insulator 130 can be enhanced.

[0499] FIG. 21B is a cross-sectional view of the semiconductor device and also a cross-sectional view of the transistor 200 in the channel length direction.

[0500] As shown in FIG. 21B, an insulator 286 may be provided instead of the insulator 287 shown in FIG. 20B, and a conductor 110 may be provided so as to fill the openings formed in the insulator 286 and the insulator 285.

[0501] The insulator 286 may be made of an insulating material that can be used for the insulator 285 described above.

[0502] The conductor 110 is embedded inside the opening formed in the insulator 286 and the insulator 285. The conductor 110 has a region in contact with the conductor 240b inside the opening formed in the insulator 286 and the insulator 285. By embedding the conductor 110 inside the opening formed in the insulator 286 and the insulator 285, the conductor 110 and the conductor 120 can be sufficiently separated from each other. Therefore, the leakage current of the capacitance element 100A can be suppressed.

[0503] The conductor 110 shown in FIG. 21B can be formed by forming openings in the insulator 286 and the insulator 285, depositing a conductive film to be the conductor 110, and performing planarization until the insulator 286 is exposed. That is, the conductor 110 shown in FIG. 21B can be formed by using a single damascene method. The process of forming such a conductor 110 also serves as a process of improving the flatness of the upper surface of the conductor 110. Therefore, since the insulator 130 is provided on the conductor 110 with good flatness, the flatness of the insulator 130 can also be improved. Therefore, even when the insulator 130 is formed using a thin ferroelectric layer, the leakage current of the capacitance element 100A can be suppressed. Moreover, since the upper surface of the insulator 286 also has good flatness, the process of forming such a conductor 110 is also suitable for the case where a part of the insulator 130 is provided on the insulator 286.

[0504] 21B, the conductor 110 may have a layered structure of a conductor 110c, a conductor 110a on the conductor 110c, and a conductor 110b on the conductor 110a. The conductor 110c is provided in an opening formed in the insulator 286 and the insulator 285, in contact with the side of the insulator 286, the side of the insulator 285, the top surface of the insulator 283, the side of the insulator 241b, and the top surface of the conductor 240b. The conductor 110a is provided so as to fill a part of the recess formed in the conductor 110c. Here, the top surface of the conductor 110a is lower than the top surface of the conductor 110c and the top surface of the insulator 286. The conductor 110b is provided in contact with the top surface of the conductor 110a and the side of the conductor 110c. Here, the upper surface of the conductor 110b is flush with the upper surface of the conductor 110c and the upper surface of the insulator 286. In other words, the conductor 110a is surrounded by the conductors 110c and 110b.

[0505] The conductor 110c may be formed by depositing a conductor applicable to the conductor 205a described above using a sputtering method, an ALD method, a CVD method, or the like. By using a conductive material having a function of suppressing oxygen diffusion for the conductor 110c, it is possible to suppress the conductor 110a from being oxidized and its conductivity from decreasing. For example, the conductor 110c may be formed by depositing titanium nitride using a CVD method.

[0506] The conductor 110b may be formed by depositing a conductor applicable to the conductor 110 described above using an ALD method, a CVD method, or the like. When the conductor 110c is formed by performing a planarization process as described above, the conductor 110c may be formed by using a sputtering method, a CVD method, or a PECVD method, which have a high deposition rate. This allows the semiconductor device to be manufactured with high productivity. For example, the conductor 110b may be formed by depositing titanium nitride using a CVD method.

[0507] 21(B), the side surface of the conductor 110 is located inside the side surface of the insulator 130. At this time, as shown in FIG. 21(B), a part of the region of the insulator 286 that does not overlap with the conductor 120 may be removed.

[0508] FIG. 21B shows a configuration in which the side surface of the conductor 110 is located inside the side surface of the insulator 130, but the present invention is not limited to this. For example, the side surface of the conductor 110 may be located outside the side surface of the insulator 130. With such a configuration, the insulator 130 is surrounded by the conductor 110c, the insulator 155, and the insulator 152. By using a conductive material having a function of reducing hydrogen diffusion for the conductor 110c, it is possible to suppress diffusion of hydrogen from the outside of the insulator 152 and the conductor 110c to the insulator 130, and further to capture or fix hydrogen in the insulator 130, thereby reducing the hydrogen concentration in the insulator 130. Thus, the ferroelectricity of the insulator 130 can be improved. Note that the side surface of the conductor 110 may coincide with the side surface of the insulator 130.

[0509] The conductor 246 has a region in contact with the conductor 240a inside the openings formed in the insulator 286 and the insulator 285. The conductor 246 functions as a wiring or a terminal. The conductor 246 is preferably formed in the same layer and made of the same material as the conductor 110. As shown in FIG. 21(B), when the conductor 110 has the above-mentioned three-layer stacked structure, the conductor 246 and the conductor 110 are formed in the same layer and made of the same material, so that the conductor 246 has a three-layer stacked structure.

[0510] 21B shows the conductor 120 as having a single layer structure. The conductor 120 may have a stacked structure of two or more layers. When the conductor 120 has a single layer structure, the conductor 120 may be formed using a conductor that can be used for the conductor 120a or conductor 120b described above. The conductor 120 may be formed using a method that can be used for the conductor 120a or conductor 120b described above.

[0511] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in the case where a plurality of configuration examples are shown in one embodiment mode in this specification, the configuration examples can be combined as appropriate.

[0512] (Embodiment 3) In this embodiment, a memory device including an OS transistor and a capacitor according to one embodiment of the present invention (hereinafter may be referred to as an OS memory device) will be described with reference to Figures 22A to 27. The OS memory device is a memory device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

[0513] <Storage device configuration example> 22A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0514] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is a wiring connected to a memory cell included in the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.

[0515] A low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are supplied to the memory device 1400 from the outside as power supply voltages. In addition, control signals (CE, WEN, RES), an address signal ADDR, and a data signal WDATA are input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0516] The control logic circuit 1460 processes control signals (CE, WEN, RES) input from the outside to generate control signals for the row decoder and column decoder. The control signal CE is a chip enable signal, the control signal WEN is a write enable signal, and the control signal RES is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as necessary.

[0517] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0518] 22A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but this embodiment is not limited to this. For example, as shown in FIG. 22B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap under the memory cell array 1470. The OS transistor can be formed during a back end of line (BEOL) process in which wiring of a memory device is formed. Therefore, when an OS transistor is used for the memory cell array 1470 and a transistor having silicon in a channel formation region (hereinafter, sometimes referred to as a Si transistor) is used for the peripheral circuit 1411, a technique for forming an OS transistor directly above a Si transistor (referred to as a BEOL-Tr technique) can be applied.

[0519] Moreover, a configuration in which a plurality of memory cell arrays 1470 are stacked may be used. By stacking a plurality of memory cell arrays 1470, memory cells can be integrated and arranged without increasing the area occupied by the memory cell array 1470. That is, a 3D cell array can be configured. In this manner, a semiconductor device with a large memory capacity can be provided by achieving high integration of memory cells. Note that a layer including an OS transistor is preferable because it can be stacked monolithically.

[0520] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary. The memory device of one embodiment of the present invention has high operating speed and can retain data for a long period of time.

[0521] A configuration example of a memory cell that can be applied to the above-mentioned memory cell MC will be described with reference to FIGS.

[0522] [DOSRAM] 23A to 23C show examples of circuit configurations of DRAM memory cells. In this specification and the like, a DRAM using a memory cell with one OS transistor and one capacitor may be referred to as a dynamic oxide semiconductor random access memory (DOSRAM). The memory cell 1471 shown in FIG. 23A includes a transistor M1 and a capacitor CA. Note that the transistor M1 includes a gate (sometimes referred to as a top gate) and a back gate.

[0523] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to a wiring BIL, a gate of the transistor M1 is connected to a wiring WOL, a back gate of the transistor M1 is connected to a wiring BGL, and a second terminal of the capacitance element CA is connected to a wiring LL.

[0524] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring LL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, the wiring LL may be at ground potential or a low-level potential. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0525] The memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 23B. For example, the memory cell MC may be configured as a single-gate transistor, that is, a memory cell including a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 23C.

[0526] Here, a configuration example of a memory device including a DOSRAM is shown in Fig. 24. In the memory device shown in Fig. 24, a transistor 200 is provided above a transistor 300, and a capacitor 100 is provided above the transistors 300 and 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200. The capacitor 100 can be used as the capacitor 100 described in the above embodiment.

[0527] When the memory device illustrated in FIG. 24 is used for the memory cell 1471, the transistor 200 can be used as the transistor M1, and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the off-state current of the transistor M1 can be made very small. That is, written data can be held for a long time by the transistor M1, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. In addition, since the off-state current is very small, multi-level data or analog data can be held in the memory cell 1471. The same applies to the memory cell 1472 and the memory cell 1473.

[0528] Furthermore, in the DOSRAM, if a sense amplifier is provided so as to overlap under the memory cell array 1470 as described above, the bit line can be shortened. This reduces the bit line capacitance and the storage capacitance of the memory cell.

[0529] 24, a wiring 1001 is electrically connected to a source of the transistor 300, a wiring 1002 is electrically connected to a drain of the transistor 300, and a wiring 1007 is electrically connected to a gate of the transistor 300. A wiring 1003 is electrically connected to one of a source and a drain of the transistor 200, a wiring 1004 is electrically connected to a first gate of the transistor 200, and a wiring 1006 is electrically connected to a second gate of the transistor 200. The other of the source and drain of the transistor 200 is electrically connected to one electrode of the capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0530] <Transistor 300> The transistor 300 is provided over a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b functioning as a source region or a drain region. The transistor 300 may be either a p-channel type or an n-channel type.

[0531] Here, in the transistor 300 shown in FIG. 24, a semiconductor region 313 (a part of a substrate 311) in which a channel is formed has a convex shape. A conductor 316 is provided so as to cover the side and top surface of the semiconductor region 313 via an insulator 315. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator that contacts the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Note that, although a case where a convex portion is formed by processing a part of a semiconductor substrate has been shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0532] Note that the transistor 300 illustrated in FIG. 24 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0533] <Wiring layer> Between each structure, a wiring layer having an interlayer film, wiring, plugs, etc. may be provided. Also, a plurality of wiring layers may be provided according to the design. Here, the conductor functioning as a plug or wiring may be collectively given the same symbol as a plurality of structures. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0534] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. A conductor 328 is embedded in the insulator 320 and the insulator 322, and a conductor 330 is embedded in the insulator 324 and the insulator 326. The conductor 328 and the conductor 330 function as plugs or wirings.

[0535] The insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be planarized by a planarization process using a CMP method or the like to enhance the planarity.

[0536] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in Fig. 24, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0537] Similarly, a conductor 218 and a conductor that constitutes the transistor 200 are embedded in the insulator 210, the insulator 212, the insulator 214, and the insulator 216. Note that the conductor 218 functions as a plug or wiring that is electrically connected to the transistor 300.

[0538] Here, similar to the insulator 241a and the insulator 241b described in the previous embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218. The insulator 217 is provided in contact with the inner walls of the openings formed in the insulators 210, 212, 214, and 216. In other words, the insulator 217 is provided between the conductor 218 and the insulators 210, 212, 214, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, and therefore the insulator 217 may be formed in contact with the side surface of the conductor 205.

[0539] As the insulator 217, for example, an insulator applicable to the above-mentioned insulator 241a and insulator 241b may be used. Since the insulator 217 is provided in contact with the insulator 210, the insulator 212, the insulator 214, and the insulator 222, it is possible to prevent impurities contained in the insulator 210 or the insulator 216 from being mixed into the oxide 230 through the conductor 218. In particular, silicon nitride is preferable because it has high barrier properties against hydrogen. In addition, it is possible to prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.

[0540] The insulator 217 can be formed by a method similar to that of the insulators 241a and 241b described above. For example, a silicon nitride film is formed by a PEALD method, and an opening reaching the conductor 356 is formed by anisotropic etching.

[0541] The insulator 210, the insulator 352, the insulator 354, and the like, which function as interlayer films, may be made using any of the insulators that can be used for the insulator 150.

[0542] Furthermore, by surrounding an OS transistor with an insulator that has a function of suppressing the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. Therefore, the insulators that have a function of suppressing the permeation of impurities and oxygen described above in <<Insulators>> can be used for the insulators 214, 212, and 350.

[0543] Conductors functioning as plugs or wiring, such as conductor 328, conductor 330, conductor 356, conductor 218, and conductor 112, can be any of the conductors described above in <<Conductors>>. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form the wiring from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, it is possible to reduce the wiring resistance.

[0544] <Wiring or plug of layer provided with oxide semiconductor> As described in the above embodiment, the transistor 200 may be sealed with the insulators 212, 214, and 283. With such a structure, hydrogen contained in the insulators 274, 150, and the like can be prevented from entering the insulator 280 and the like.

[0545] Note that the conductor 240 penetrates the insulator 283, and the conductor 218 penetrates the insulator 214 and the insulator 212. As shown in Fig. 24, the insulator 241 is provided in contact with the conductor 240, and the insulator 217 is provided in contact with the conductor 218. By using a barrier insulating film against hydrogen as the insulators 241 and 217, it is possible to prevent hydrogen from being mixed into the inside of the insulators 212, 214, and 283 through the conductors 240 and 218. In this manner, the transistor 200 is sealed with the insulators 212, 214, 283, 241, and 217, and it is possible to prevent impurities contained in the insulator 274, etc. from being mixed in from the outside.

[0546] [NOSRAM] 23D to 23G show circuit configuration examples of a gain cell type memory cell having two transistors and one capacitor. A memory cell 1474 shown in FIG. 23D includes a transistor M2, a transistor M3, and a capacitor CB. Note that the transistor M2 has a gate and a backgate. In this specification and the like, a memory device including a gain cell type memory cell using an OS transistor as the transistor M2 may be referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0547] A first terminal of the transistor M2 is connected to a first terminal of the capacitance element CB, a second terminal of the transistor M2 is connected to the wiring WBL, a gate of the transistor M2 is connected to the wiring WOL, and a back gate of the transistor M2 is connected to the wiring BGL. A second terminal of the capacitance element CB is connected to the wiring CAL. A first terminal of the transistor M3 is connected to the wiring RBL, a second terminal of the transistor M3 is connected to the wiring SL, and a gate of the transistor M3 is connected to the first terminal of the capacitance element CB.

[0548] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data and when reading data, it is preferable to apply a high-level potential to the wiring CAL. Also, when data is being held, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. The threshold voltage of the transistor M2 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0549] An example of a storage device having NOSRAM is shown in Fig. 25. In the storage device described below, structures having the same functions as those constituting the storage device shown in Fig. 24 are denoted by the same reference numerals. In the following, differences from the above-mentioned storage device will be mainly described, and overlapping portions will not be described.

[0550] Fig. 25 is a cross-sectional view of a memory device. The memory device in Fig. 25 differs from the memory device in Fig. 24 in that the wiring 1007 is not included and that the gate of the transistor 300 is electrically connected to the other of the source and drain of the transistor 200 and one electrode of the capacitor 100.

[0551] 25, the gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100. The conductor 316 is electrically connected to the capacitor 100 or the transistor 200 through the conductor 328, the conductor 330, the conductor 356, the conductor 218, and the conductor 240.

[0552] 25 is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor CB can be used as the capacitor CB. In addition, the wiring 1003 can be used as the wiring WBL, the wiring 1004 can be used as the wiring WOL, the wiring 1006 can be used as the wiring BGL, the wiring 1005 can be used as the wiring CAL, the wiring 1002 can be used as the wiring RBL, and the wiring 1001 can be used as the wiring SL.

[0553] The memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 23E. For example, the memory cell MC may be configured such that the transistor M2 has a single gate structure, that is, the transistor M2 does not have a back gate, as in the memory cell 1476 shown in FIG. 23F. For example, the memory cell MC may be configured such that the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 23G.

[0554] By using an OS transistor as the transistor M2, the off-state current of the transistor M2 can be made very small. As a result, written data can be held by the transistor M2 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. In addition, since the off-state current is very small, multilevel data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

[0555] The transistor M3 may be a Si transistor. The conductivity type of the Si transistor may be an n-channel type or a p-channel type. A Si transistor may have a higher field-effect mobility than an OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a read transistor. By using a Si transistor for the transistor M3, the transistor M2 can be stacked on the transistor M3, thereby reducing the area occupied by the memory cell and achieving high integration of the memory device.

[0556] In addition, the transistor M3 may be an OS transistor. When the transistors M2 and M3 are OS transistors, the memory cell array 1470 can be configured as a circuit using only n-channel transistors.

[0557] FIG. 23H shows an example of a gain cell type memory cell having three transistors and one capacitor. A memory cell 1478 shown in FIG. 23H includes transistors M4 to M6 and a capacitor CC. The capacitor CC is provided as appropriate. The memory cell 1478 is electrically connected to a wiring BIL, a wiring RWL, a wiring WWL, a wiring BGL, and a wiring GNDL. The wiring GNDL is a wiring that applies a low-level potential. Note that the memory cell 1478 may be electrically connected to a wiring RBL and a wiring WBL instead of the wiring BIL.

[0558] The transistor M4 is an OS transistor having a backgate, and the backgate is electrically connected to the wiring BGL. The backgate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not necessarily have to have a backgate.

[0559] Note that the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors. Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured as a circuit using only n-channel transistors.

[0560] When the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistors M5 and M6 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the off-state current of the transistor M4 can be made extremely small.

[0561] 23I shows an example of a two-transistor gain cell type memory cell. A memory cell 1479 shown in FIG. 23I includes a transistor M7 and a transistor M8. The memory cell 1479 is electrically connected to a wiring BIL, a wiring WWL, a wiring BGL, and a wiring SL.

[0562] The transistor M7 is an OS transistor having a backgate, and the backgate is electrically connected to the wiring BGL. Note that the backgate and the gate of the transistor M7 may be electrically connected to each other. Alternatively, the transistor M7 does not necessarily have to have a backgate.

[0563] 23(I), the gate capacitance of the transistor M8 is used as a storage capacitance. That is, the memory cell 1479 can also be called a capacitor-less memory cell. The memory cell 1479 can be considered to have a configuration in which the capacitor CB is not included in the memory cell 1477 shown in FIG. 23(G), and can also be called a 2-transistor, 0-capacitor gain cell type memory cell.

[0564] By using an OS transistor as the transistor M7, the charge of a node where one of the source electrode or the drain electrode of the transistor M7 and the gate electrode of the transistor M8 are electrically connected can be held for an extremely long time by turning off the transistor M7, thereby realizing a nonvolatile memory cell.

[0565] The transistor M8 may be an n-channel Si transistor or a p-channel Si transistor.

[0566] When the semiconductor device described in the above embodiment is used for the memory cell 1479, the transistor 200 can be used as the transistor M7, and the transistor 300 can be used as the transistor M8.

[0567] Alternatively, the transistor M8 may be an OS transistor, in which case the memory cell array 1470 can be configured using only n-channel transistors.

[0568] When the semiconductor device described in the above embodiment is used for the memory cell 1479, the transistor 200 can be used as the transistor M7 and the transistor M8. With this structure, the transistor M7 and the transistor M8 can be formed in the same layer. Therefore, compared to the case where the transistor M7 and the transistor M8 are provided in different layers, the manufacturing process for stacking layers including the memory cell 1479 can be simplified, and productivity can be improved.

[0569] When the transistor 200 is used as the transistor M7 and the transistor M8, the components of the transistor (including the channel length, channel width, cross-sectional shape, etc.) may be appropriately set in accordance with the characteristics required for the transistor M7 and the transistor M8.

[0570] Regardless of the semiconductor material used for the transistors M1 to M8, the structures of the transistors M1 to M8 are not particularly limited. For example, planar transistors, staggered transistors, inverted staggered transistors, vertical channel transistors, or the like can be used. In addition, the transistors may have either a top-gate or bottom-gate structure. Alternatively, gates may be provided above and below a semiconductor layer in which a channel is formed.

[0571] As described above, a configuration in which a plurality of memory cell arrays 1470 are stacked may be used. By stacking a plurality of memory cell arrays 1470, memory cells can be integrated and arranged without increasing the area occupied by the memory cell arrays 1470. In other words, a 3D cell array can be configured. An example of a memory device having a configuration in which a plurality of memory cell arrays 1470 are stacked is shown in FIG.

[0572] 26 includes a first layer having a transistor 300 and memory cell arrays 1470[1] to 1470[m] (only memory cell array 1470[1] and memory cell array 1470[2] are shown in FIG. 26) on the first layer. Note that m is an integer of 1 or more. The memory device illustrated in FIG. 26 has a configuration below the insulator 326 similar to that of the memory device illustrated in FIG. 24.

[0573] Each of the memory cell arrays 1470[1] to 1470[m] includes a plurality of memory cells MC. Each of the plurality of memory cells MC includes a transistor 200 and a capacitor 100. Here, the transistor 200 corresponds to the transistor 200 described in the above embodiment, and the capacitor 100 corresponds to the capacitor 100 or the capacitor 100A described in the above embodiment. Note that FIG. 26 illustrates an example in which the transistor 200 and the capacitor 100 illustrated in FIG. 19 are used as the transistor 200 and the capacitor 100.

[0574] Between the first layer and the memory cell array 1470, or between two memory cell arrays 1470, a wiring layer provided with an interlayer film, wiring, plugs, and the like may be provided. Also, a plurality of wiring layers may be provided according to design. Also, in this specification and the like, a wiring and a plug electrically connected to the wiring may be integrated. That is, there are cases where a part of a conductor functions as a wiring and cases where a part of a conductor functions as a plug.

[0575] An insulator 210 is provided above the insulator 326, and a conductor 209 is provided inside an opening formed in the insulator 210. Furthermore, an insulator 212 and an insulator 214 are provided on the insulator 210. A part of a conductor 240 provided in the memory cell array 1470[1] is embedded in the openings formed in the insulator 212 and the insulator 214. Here, the insulator 210 can use an insulator that can be used for the insulator 216.

[0576] A conductor (not shown) is provided in contact with the lower surface of the conductor 209. The upper surface of the conductor 209 is provided in contact with the lower surface of the conductor 240 provided in the memory cell array 1470[1]. With this configuration, the conductor 240 functioning as the wiring BL can be electrically connected to a circuit element, wiring, electrode, or terminal, such as a switch, a transistor, a capacitor, an inductor, a resistor, and a diode, provided below the memory cell array 1470.

[0577] Each of the memory cell arrays 1470[1] to 1470[m] includes a plurality of memory cells MC. The conductor 240 of each memory cell MC is electrically connected to the conductor 240 in the upper layer and the conductor 240 in the lower layer.

[0578] 26, adjacent memory cells MC share a conductor 240. Furthermore, in the adjacent memory cells MC, the configuration on the right side and the configuration on the left side are arranged symmetrically with respect to the conductor 240.

[0579] Here, the conductor 160 functioning as the upper electrode of the capacitor 100 in the lower layer (e.g., the layer of the memory cell array 1470[1]) and the conductor 261 functioning as the second gate electrode of the transistor 200 in the upper layer (e.g., the layer of the memory cell array 1470[2]) can be formed in the same layer. In other words, the conductor 160 of the capacitor 100 in the lower layer and the conductor 261 of the transistor 200 in the upper layer can be formed so as to be embedded in openings formed in the same insulator 216. The conductor 160 of the capacitor 100 in the lower layer and the conductor 261 of the transistor 200 in the upper layer are formed by processing one conductive film to obtain the above-mentioned configuration. At this time, the conductor 160 of the capacitor 100 in the lower layer has the same material as the conductor 261 of the transistor 200 in the upper layer.

[0580] As described above, by simultaneously forming the conductor 160 of the capacitor 100 in the lower layer and the conductor 261 of the transistor 200 in the upper layer, the manufacturing process of the memory device according to this embodiment can be reduced, and the productivity of the memory device can be improved.

[0581] In the above-described memory cell array 1470, a plurality of memory cell arrays (memory cell array 1470[1] to memory cell array 1470[m]) can be stacked. The memory cell arrays 1470[1] to 1470[m] included in the memory cell array 1470 can be arranged in the vertical direction on the substrate surface, thereby improving the memory density of the memory cells. The memory cell array 1470 can be manufactured by repeatedly using the same manufacturing process in the vertical direction. The memory device illustrated in FIG. 26 can reduce the manufacturing cost of the memory cell array 1470.

[0582] [Ferroelectric memory] 27 shows an example of a circuit configuration of a memory cell using a ferroelectric capacitor. The memory cell 1480 has a transistor M9 and a capacitor Cfe. Here, a memory device in which a capacitor 100A is provided instead of the capacitor 100 in FIG. 24 can be used as the memory cell 1480. In this case, the transistor 200 can be used as the transistor M9, and the capacitor 100A described in the previous embodiment can be used as the capacitor Cfe. Note that the transistor M9 may or may not have a backgate.

[0583] It is preferable to use the transistor 200 described in the previous embodiment as the transistor M9. An OS transistor has a characteristic that the withstand voltage between the source and drain is high. In other words, an OS transistor can be called a micro high-voltage device. Therefore, by using an OS transistor as the transistor M9, a high voltage can be applied to the transistor M9 even if the transistor M9 is miniaturized. By miniaturizing the transistor M9, the area occupied by the semiconductor device can be reduced. Therefore, the semiconductor devices can be arranged at a high density. This makes it possible to realize a memory device with a large memory capacity.

[0584] The transistor M9 has a source or a drain electrically connected to the wiring BL, the other of the source or the drain electrically connected to one electrode of the capacitor Cfe, and a gate electrically connected to the wiring WL. The other electrode of the capacitor Cfe is electrically connected to the wiring PL.

[0585] The wiring WL functions as a word line, and the on / off state of the transistor M9 can be controlled by controlling the potential of the wiring WL. For example, the transistor M9 can be turned on by setting the potential of the wiring WL to a high potential, and the transistor M9 can be turned off by setting the potential of the wiring WL to a low potential. The wiring WL is electrically connected to a word line driver circuit included in the row circuit 1420, and the potential of the wiring WL can be controlled by the word line driver circuit.

[0586] The wiring BL functions as a bit line, and when the transistor M9 is on, a potential corresponding to the potential of the wiring BL is supplied to one electrode of the capacitor Cfe. The wiring BL is electrically connected to a bit line driver circuit of the column circuit 1430. The bit line driver circuit has a function of generating data to be written to the memory cell MC. The bit line driver circuit also has a function of reading data output from the memory cell MC. Specifically, the bit line driver circuit is provided with a sense amplifier, and the data output from the memory cell MC can be read using the sense amplifier.

[0587] The wiring PL functions as a plate line. A potential is supplied to the other electrode of the capacitance element Cfe through the wiring PL.

[0588] The capacitor element Cfe has a material having ferroelectricity as a dielectric layer between two electrodes. As the material having ferroelectricity, any material applicable to the insulator 130 described above may be used. By making the ferroelectric layer thin, it is possible to realize a memory device combined with a miniaturized transistor. Hereinafter, the dielectric layer of the capacitor element Cfe is referred to as a ferroelectric layer.

[0589] A semiconductor device using a ferroelectric layer for the capacitance element Cfe functions as a non-volatile memory element capable of retaining written information even when the power supply is stopped.

[0590] Furthermore, DRAM requires periodic refresh operations, which increases power consumption. A semiconductor device using a ferroelectric layer for the capacitance element Cfe does not require refresh operations, so power consumption can be reduced.

[0591] In this specification and the like, a memory element or a memory circuit including a ferroelectric layer may be referred to as a "ferroelectric memory" or an "FE memory." Thus, a semiconductor device according to one embodiment of the present invention is both a ferroelectric memory and an FE memory. The FE memory has a capacitance of 1×10 10 More than 1×10 12 More preferably, 1×10 15 It is expected that the FE memory will achieve a rewrite count of 10 MHz or more, and preferably 1 GHz or more.

[0592] In addition, in FE memory, there is a correlation between the remnant polarization 2Pr and data retention, and as the remnant polarization 2Pr decreases, the data retention decreases. In this specification, the period until the remnant polarization 2Pr decreases by 5% (the data retention decreases by 5%) is called the "memory retention period". FE memory can be expected to achieve a memory retention period of 10 days or more, preferably 1 year or more, and more preferably 10 years or more in a temperature environment of 150°C or 200°C.

[0593] In addition, the FE memory can also be applied to cache memories and registers of a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit). By combining the FE memory with the cache memory and registers of a CPU, a normally-off CPU (NoffCPU (registered trademark)) can be realized. By combining the FE memory with the cache memory and registers of a GPU, a normally-off GPU (NoffGPU (registered trademark)) can be realized.

[0594] The structures and methods described in this embodiment can be used in appropriate combination with other structures and methods described in this embodiment or structures and methods described in other embodiments.

[0595] (Embodiment 4) In this embodiment, an OS transistor will be described. Note that in the description of the OS transistor, a comparison with a Si transistor will also be briefly described.

[0596] For the OS transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of a channel formation region of the oxide semiconductor is 1×10 18 cm -3 Less than or equal to 1×10 17 cm -3 less than 1×10 16 cm -3 less than 1×10 13 cm -3 less than 1×10 10 cm -3 Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0597] In addition, a highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor may have a low density of trap states because of its low density of defect states. In addition, charges trapped in the trap states of the oxide semiconductor take a long time to disappear and may behave as if they were fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0598] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen and nitrogen. Note that an impurity in an oxide semiconductor refers to, for example, any element other than the main component constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0599] The band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), and is preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor having a band gap larger than that of silicon, the off-state current (also referred to as Ioff) of a transistor can be reduced.

[0600] Furthermore, in Si transistors, as transistors are miniaturized, a short channel effect (also referred to as a short channel effect: SCE) occurs. This makes miniaturization of Si transistors difficult. One of the factors that causes the short channel effect is the small band gap of silicon. On the other hand, an OS transistor uses an oxide semiconductor, which is a semiconductor material with a wide band gap, and therefore the short channel effect can be suppressed. In other words, an OS transistor is a transistor that does not have the short channel effect or has an extremely small short channel effect.

[0601] The short channel effect is a degradation of electrical characteristics that becomes evident as transistors are miniaturized (reduced channel length). Specific examples of short channel effects include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes written as S value), and an increase in leakage current. Here, the S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.

[0602] Additionally, the characteristic length is widely used as an index of resistance to the short channel effect. The characteristic length is an index of how easily the potential of the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, meaning that the device is more resistant to the short channel effect.

[0603] The OS transistor is an accumulation-type transistor, and the Si transistor is an inversion-type transistor. Therefore, compared with the Si transistor, the OS transistor has a smaller characteristic length between the source region and the channel formation region and between the drain region and the channel formation region. Therefore, the OS transistor is more resistant to the short-channel effect than the Si transistor. That is, when it is desired to manufacture a transistor with a short channel length, the OS transistor is more suitable than the Si transistor.

[0604] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region becomes i-type or substantially i-type, the conduction band minimum of the channel formation region is lowered in a short-channel transistor due to the conduction-band-lowering (CBL) effect, so that the energy difference between the conduction band minimum of the source or drain region and the channel formation region can be reduced to 0.1 eV or more and 0.2 eV or less. As a result, the channel formation region of the OS transistor can be n - The source and drain regions are n-type regions. + The domain of type, n + / n - / n +accumulation-type junction-less transistor structure, or + / n - / n + This can also be regarded as an accumulation-type non-junction transistor structure.

[0605] By forming the OS transistor with the above structure, the OS transistor can have good electrical characteristics even when miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, and 1 nm or more, 3 nm or more, or 5 nm or more. On the other hand, since a short channel effect occurs in a Si transistor, it may be difficult to achieve a gate length of 20 nm or less or 15 nm or less. Therefore, the OS transistor can be suitably used as a transistor having a shorter channel length than that of a Si transistor. Note that the gate length is the length of a gate electrode in a direction in which carriers move inside a channel formation region when the transistor is operating.

[0606] Furthermore, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of the OS transistor is within any of the above ranges, the cutoff frequency of the transistor can be set to 50 GHz or higher, preferably 100 GHz or higher, and more preferably 150 GHz or higher, for example, in a room temperature environment.

[0607] As described above, compared to Si transistors, OS transistors have excellent advantages such as a smaller off-state current and the ability to form transistors with a short channel length.

[0608] The configurations, structures, methods, and the like described in this embodiment can be used in appropriate combination with the configurations, structures, methods, and the like described in other embodiments.

[0609] (Embodiment 5) In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) in which the semiconductor device described in the above embodiment can be used will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0610] [Electronic components] FIG. 28A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 700 is mounted. The electronic component 700 shown in FIG. 28A has a semiconductor device 710 in a mold 711. In FIG. 28A, some parts are omitted in order to show the inside of the electronic component 700. The electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 via wires 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.

[0611] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 is configured by stacking a plurality of memory cell arrays. The memory layer 716 may be configured by providing one layer including a memory cell array. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In the monolithic stacked configuration, each layer can be connected without using a through electrode technology such as TSV (Through Silicon Via) and a bonding technology such as Cu-Cu direct bonding. By stacking the drive circuit layer 715 and the memory layer 716 monolithically, for example, a so-called on-chip memory configuration in which a memory is formed directly on a processor can be formed. By configuring the on-chip memory, it is possible to increase the speed of the operation of the interface portion between the processor and the memory.

[0612] In addition, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSV, and it is also possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also cal...

Claims

1. A sputtering target having a first region and a second region, The first region has a first metal oxide comprising In, Ga, and Zn. The second region has a second metal oxide comprising In and Zn, The first region and the second region are separated from each other. The first region and the second region are each crystal grains, A grain boundary is observed between the first region and the second region. A sputtering target in which the diameters of the first region and the second region are each 5 nm or more and 10 μm or less.

2. A sputtering target having a first region and a second region, The first region has a first metal oxide comprising In, Ga, and Zn. The second region has a second metal oxide comprising In and Sn, The first region and the second region are separated from each other. The first region and the second region are each crystal grains, A grain boundary is observed between the first region and the second region. A sputtering target in which the diameters of the first region and the second region are each 5 nm or more and 10 μm or less.

3. In claim 1 or 2, A sputtering target in which the crystal structure of the first region is different from the crystal structure of the second region.

4. A step of weighing the raw materials for the first calcined body: a first indium oxide, an oxide of element M1 (where element M1 is one or more selected from Al, Ga, Si, Mg, Zr, and B), and a first zinc oxide, and the raw materials for the second calcined body: a second indium oxide and a second zinc oxide. A step of preparing a first mixture by mixing the first indium oxide, the oxide of element M1, and the first zinc oxide, A step of producing a first molded body by molding the first mixture and applying pressure, A step of firing the first molded body to produce the first fired body, A step of pulverizing the first calcined body to produce a first powder, A step of mixing the second indium oxide and the second zinc oxide to produce a second mixture, A step of producing a second molded body by molding the second mixture and applying pressure, A step of firing the second molded body to produce the second fired body, A step of pulverizing the second calcined body to produce a second powder, A step of mixing the first powder and the second powder to produce a third mixture, The process includes a step of pressurizing the third mixture while molding it to produce a third molded body, A method for manufacturing a sputtering target, wherein after the step of manufacturing the third molded body, the step of firing the third molded body is omitted.

5. A step of weighing the raw materials for the first calcined body: a first indium oxide, an oxide of element M1 (where element M1 is one or more selected from Al, Ga, Si, Mg, Zr, and B), and a first zinc oxide, and the raw materials for the second calcined body: a second indium oxide and a second zinc oxide. A step of preparing a first mixture by mixing the first indium oxide, the oxide of element M1, and the first zinc oxide, A step of producing a first molded body by molding the first mixture and applying pressure, A step of firing the first molded body to produce the first fired body, A step of pulverizing the first calcined body to produce a first powder, A step of mixing the second indium oxide and the second zinc oxide to produce a second mixture, A step of producing a second molded body by molding the second mixture and applying pressure, A step of firing the second molded body to produce the second fired body, A step of pulverizing the second calcined body to produce a second powder, A step of mixing the first powder and the second powder to produce a third mixture, A step of producing a third molded body by molding the third mixture and applying pressure, The process includes a step of firing the third molded body to produce a third fired body, A method for manufacturing a sputtering target, wherein the temperature at which the third molded body is fired is such that a portion of the first powder and a portion of the second powder do not combine.

6. In claim 5, A method for manufacturing a sputtering target, wherein the temperature at which the third molded body is fired is lower than the temperature at which the first molded body is fired and the temperature at which the second molded body is fired.

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