Spontaneous light emission display device and driving method of spontaneous light emission display device

Abstract

To provide a spontaneous light emission display device capable of minimizing power consumption while suppressing deterioration of luminance.SOLUTION: A spontaneous light emission display device includes a first transistor that is controlled by using a second control signal to which a first control signal is shifted, and is electrically connected to a first node, a second transistor electrically connected between the first node and a second node, a third transistor that is controlled by using the first control signal to which a third control signal is shifted, and is electrically connected between the second node and a gate electrode of the second transistor, and a fourth transistor that is controlled by using the third control signal so as to supply a reset voltage to the second node and to the gate electrode of the second transistor, and is electrically connected to the second node.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a self-emitting display device and a driving method thereof.

Background Art

[0002] In recent years, self-emitting display devices have been mounted on televisions, smartphones, digital signage (electronic billboards, electronic advertising boards, etc.) and the like, and have become widespread. A self-emitting display device includes, for example, a plurality of pixels and a driver for driving the plurality of pixels. Each of the plurality of pixels includes, for example, a plurality of transistors, a capacitive element, and a light-emitting element. The light-emitting element is, for example, a light-emitting diode (LED), a micro light-emitting diode (micro LED), or an organic electroluminescence (EL) element. In a self-emitting display device, a driver supplies a voltage to each of the plurality of pixels, and a current corresponding to the supplied voltage value flows through the light-emitting elements included in each of the plurality of pixels. Each of the light-emitting elements emits light with a luminance corresponding to the current flowing through the light-emitting element, and a pixel including the light-emitting element can display an image with a gradation corresponding to the luminance. On the other hand, there is an increasing demand for reducing the power consumption of self-emitting display devices.

[0003] For example, Patent Document 1 discloses a pixel including six transistors, one capacitive element, and one light-emitting element, and a self-emitting display device including the pixel. The power consumption of the self-emitting display device described in Patent Document 1 can be reduced, for example, by adjusting the power supply voltage electrically connected to the light-emitting element.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the self-emitting display device described in Patent Document 1, when reducing power consumption by adjusting the power supply voltage electrically connected to the light-emitting element, the luminance of the light-emitting element (self-emitting display device) may decrease.

[0006] In view of such problems, one object of an embodiment of the present invention is to provide a self-emitting display device and a driving method for the self-emitting display device capable of reducing power consumption while suppressing a decrease in the luminance of a light-emitting element (self-emitting display device).

Means for Solving the Problems

[0007] A self-emitting display device according to an embodiment of the present invention is controlled using a second control signal obtained by shifting a first control signal, and includes a first transistor electrically connected to a first node, a second transistor electrically connected between the first node and a second node, a third transistor controlled using the first control signal obtained by shifting a third control signal and electrically connected between the second node and a gate electrode of the second transistor, and a fourth transistor controlled to supply a reset voltage to the second node and the gate electrode of the second transistor using the third control signal and electrically connected to the second node.

[0008] The driving method of the self-emitting display device according to an embodiment of the present invention is controlled using at least a second control signal obtained by shifting a first control signal, and includes a first transistor electrically connected to a first node, a second transistor electrically connected between the first node and a second node, a third transistor controlled using the first control signal obtained by shifting a third control signal and electrically connected between the second node and a gate electrode of the second transistor, and a fourth transistor controlled using the third control signal and electrically connected to the second node. The driving method of the self-emitting display device includes turning on the fourth transistor using the third control signal, turning on the third transistor using the first control signal, supplying a reset voltage to the second node and the gate electrode of the second transistor, turning off the fourth transistor using the third control signal after supplying the reset voltage, turning on the first transistor using the second control signal, and supplying a data voltage to the second node and the first node.

Brief Description of Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings and the like. However, the present invention can be implemented in many different modes and is not to be construed as being limited to the description of the embodiments exemplified below. Also, in order to make the description clearer, the drawings may schematically represent the width, thickness, shape, configuration, etc. of each part compared to the actual mode, but this is only an example and does not limit the interpretation of the present invention. Note that the letters “first” and “second” attached to each element are for convenience of distinguishing each element and have no further meaning unless otherwise specified.

[0011] Also, in this specification, expressions such as “α includes A, B, or C”, “α includes any one of A, B, and C”, “α includes one selected from the group consisting of A, B, and C” do not exclude the case where α includes a plurality of combinations of A to C unless otherwise specified. Furthermore, these expressions do not exclude the case where α includes other elements.

[0012] An organic light-emitting display device according to an embodiment of the present invention is, as an example, a light-emitting device using an EL element as a light-emitting element.

[0013] <1. First Embodiment> <1-1. Outline of the Organic Light-Emitting Display Device 10> Referring to FIGS. 1 and 2, the outline of the self-luminous display device 10 according to the first embodiment will be described. FIGS. 1 and 2 are schematic diagrams showing the configuration of the self-luminous display device 10 according to the first embodiment. The configuration of the self-luminous display device 10 shown in FIGS. 1 and 2 is an example, and the configuration of the self-luminous display device 10 is not limited to the configuration shown in FIGS. 1 and 2.

[0014] As shown in FIG. 1 or FIG. 2, the self-luminous display device 10 includes an array substrate 100, a flexible printed circuit board 160 (FPC 160), and an IC chip 170. Further, the self-luminous display device 10 includes a display area 22 provided on the array substrate 100, a peripheral area 24 surrounding the display area 22, and a terminal area 26.

[0015] In the display area 22, a plurality of pixels 180 are arranged in a matrix. The pixel 180 is the minimum unit that constitutes a part of the image to be displayed in the display area 22. Each of the plurality of pixels 180 may correspond to, for example, a sub-pixel R, a sub-pixel G, and a sub-pixel B. One pixel may be formed by three sub-pixels. There is no limitation on the arrangement of the pixels 180, and the arrangement of the plurality of pixels 180 is, for example, a stripe arrangement. The arrangement of the self-luminous display device 10 may be a delta arrangement, a pentile arrangement, or the like.

[0016] The sub-pixel R, the sub-pixel G, and the sub-pixel B are configured to display images of different colors. For example, each of the sub-pixel R, the sub-pixel G, and the sub-pixel B may include a light-emitting element including a light-emitting layer that emits the three primary colors of red, green, and blue. An arbitrary voltage or current is supplied to each of the three sub-pixels, and the self-luminous display device 10 can display an image.

[0017] In the peripheral region 24, a source driver circuit 110, a first gate driver circuit 120, a first light emission control circuit 130, and a second light emission control circuit 140 are provided. Each of the source driver circuit 110, the first gate driver circuit 120, the first light emission control circuit 130, and the second light emission control circuit 140 is connected to the terminal portion 150 using a connection wiring 341. The peripheral region 24 may be called a frame region. The connection wiring 341 may be called the connection wiring 341 alone, or a bundle of a plurality of connection wirings 341 may be called the connection wiring 341.

[0018] In the terminal region 26, a terminal portion 150 and an FPC 160 electrically connected to the terminal portion 150 are provided. The terminal region 26 is a region on the opposite side of the display region 22 with respect to the peripheral region 24 in the first direction D1.

[0019] The FPC 160 is connected to an external device (not shown) outside the self-emission type display device 10. Therefore, the self-emission type display device 10 is connected to the external device via the FPC 160 and the terminal portion 150 connected to the FPC. A control signal and a voltage are transmitted from the external device to the self-emission type display device 10 via the FPC 160 and the terminal portion 150 connected to the FPC. The self-emission type display device 10 drives each pixel 180 provided in the self-emission type display device 10 using the received control signal and voltage from the external device. As a result, the self-emission type display device 10 can display an image in the display region 22.

[0020] The IC chip 170 is provided, for example, on the FPC 160. The IC chip 170 supplies signals, voltages, etc. for driving each pixel 180 to the source driver circuit 110, the first gate driver circuit 120, the first light emission control circuit 130, the second light emission control circuit 140, and the pixel circuit via the FPC 160, the terminal portion 150, and the connection wiring 341.

[0021] In the first embodiment, each of the source driver circuit 110, the first gate driver circuit 120, the first light emission control circuit 130, the second light emission control circuit 140, and the IC chip 170 may be individually referred to as a control circuit, and a circuit group including some or all of the source driver circuit 110, the first gate driver circuit 120, the first light emission control circuit 130, the second light emission control circuit 140, and the IC chip 170 may also be referred to as a control circuit.

[0022] <1-2. Configuration of Source Driver Circuit 110> Referring to FIGS. 1 and 2, an overview of the source driver circuit 110 will be described. As shown in FIG. 1 or FIG. 2, the source driver circuit 110 is provided at a position adjacent to the display area 22 in the first direction D1 (column direction). The image data signal line 321 extends from the source driver circuit 110 in the first direction D1 and is connected to a plurality of pixels 180 arranged in the first direction D1.

[0023] As shown in FIG. 2, the source driver circuit 110 includes, for example, a plurality of selection circuits 112. Each of the plurality of selection circuits 112 is controlled based on, for example, an on signal and an off signal supplied to the selection signal MUXR, the selection signal MUXG, and the selection signal MUXB. The selection circuit 112 is selected by the on signal supplied to the selection signal (for example, the selection signal MUXR), and supplies the image data signal SL(m + 1) including the data signal VDATA supplied to the input terminal 114 to the image data signal line 321 and the pixel 180 electrically connected to the image data signal line 321. Although details will be described later, the data signal VDATA includes, for example, the voltage RDATA(n), the voltage GDATA(n), or the voltage BDATA(n).

[0024] The selection circuit 112 is, for example, a switch 118 including an input terminal 114 and an output terminal 116. For example, an on signal supplied from the IC chip 170 to the selection signal MUXR conducts (connects) the input terminal 114 and the output terminal 116, and an off signal supplied from the IC chip 170 to the selection signal MUXR disconnects (non - connects) the input terminal 114 and the output terminal 116. The on signal is a signal including a voltage that conducts the input terminal 114 and the output terminal 116, and the off signal is a signal including a voltage that disconnects the input terminal 114 and the output terminal 116.

[0025] In the present invention, the on signal may be high (HI), and the off signal may be low (LO), or the on signal may be low (LO), and the off signal may be high (HI).

[0026] <1 - 3. Configuration of the first gate driver circuit 120 and the second gate driver circuit 190> Referring to FIGS. 1 and 2, the outline of the first gate driver circuit 120 will be described. As shown in FIG. 1 or FIG. 2, the first gate driver circuit 120 is provided at a position adjacent to the display area 22 in the second direction D2 (row direction). The first scanning signal lines 329, 330, 331, 332, and 333 extend from the first gate driver circuit 120 in the second direction D2 and are connected to a plurality of pixels 180 arranged in the second direction D2.

[0027] As shown in FIG. 2, the first gate driver circuit 120 includes a plurality of shift registers (for example, shift registers 121, 122, and 123). The shift registers 121, 122, and 123 sequentially supply scanning signals with different timings (for example, scanning signal GF(n - 1), scanning signal GF(n), scanning signal GF(n + 1)) to each of the first scanning signal lines 329, 330, 331, 332, and 333 based on control signals such as a clock signal and a start pulse supplied from the IC chip 170, and have a role of driving the pixels 180 (pixel circuits) electrically connected to each first scanning signal line.

[0028] For example, the shift register 121 is electrically connected to the shift register 122, and the shift register 122 is electrically connected to the shift register 123. The shift register 121 is electrically connected to the first scanning signal line 329 and supplies, for example, the scanning signal GF(n - 1) to the first scanning signal line 329. Similarly to the shift register 121, the shift register 122 is electrically connected to the first scanning signal line 330 and supplies, for example, the scanning signal GF(n) to the first scanning signal line 330, and the shift register 123 is electrically connected to the first scanning signal line 331 and supplies, for example, the scanning signal GF(n + 1) to the first scanning signal line 331. Although not shown, the next-stage shift register electrically connected to the shift register 123 is electrically connected to the first scanning signal line 332. The scanning signal GF(n) includes a pulse width equivalent to that of the scanning signal GF(n - 1) and is a signal obtained by shifting the scanning signal GF(n - 1). The scanning signal GF(n + 1) includes a pulse width equivalent to that of the scanning signal GF(n) and is a signal obtained by shifting the scanning signal GF(n). Similarly to the scanning signal GF(n + 1), the scanning signal GF(n + 2) includes a pulse width equivalent to that of the scanning signal GF(n + 1) and is a signal obtained by shifting the scanning signal GF(n + 1).

[0029] Referring to FIGS. 1 and 2, the outline of the second gate driver circuit 190 will be described. In the example shown in FIG. 1 or FIG. 2, the second gate driver circuit 190 is provided at a position adjacent to the first gate driver circuit 120 in the second direction D2 (row direction). The position of the second gate driver circuit 190 is not limited to the position shown in FIG. 1 or FIG. 2. The second gate driver circuit 190 may be provided between the first gate driver circuit 120 and the display area 22. The second scanning signal lines 349, 350, 351, and 352 extend from the second gate driver circuit 190 in the second direction D2 and are connected to a plurality of pixels 180 arranged in the second direction D2.

[0030] As shown in FIG. 2, the second gate driver circuit 190 includes a plurality of shift registers (for example, shift registers 191, 192, and 193). The shift registers 191, 192, and 193 have the same configuration and function as the shift registers 121, 122, and 123. The shift registers 191, 192, and 193 supply, based on control signals such as a clock signal and a start pulse supplied from the IC chip 170, scanning signals with different timings (for example, scanning signal GS(n + 1), scanning signal GS(n + 2), scanning signal GS(n + 3)) to each of the second scanning signal lines 349, 350, 351, and 352 in sequence, and have a role of driving the pixel 180 (pixel circuit) electrically connected to each second scanning signal line. Here, the control signals such as the clock signal and the start pulse supplied to the shift registers 191, 192, and 193 are synchronized with the control signals such as the clock signal and the start pulse supplied to the shift registers 121, 122, and 123, and may be the same as the control signals such as the clock signal and the start pulse supplied to the shift registers 121, 122, and 123. That is, the second gate driver circuit 190 is synchronized with the first gate driver circuit 120.

[0031] For example, the shift register 191 is electrically connected to the shift register 192, and the shift register 192 is electrically connected to the shift register 193. The shift register 191 is electrically connected to the second scanning signal line 349 and supplies, for example, the scanning signal GS(n + 1) to the second scanning signal line 349. Similar to the shift register 191, the shift register 192 is electrically connected to the second scanning signal line 350 and supplies, for example, the scanning signal GS(n + 2) to the second scanning signal line 350, and the shift register 193 is electrically connected to the second scanning signal line 351 and supplies, for example, the scanning signal GS(n + 3) to the second scanning signal line 351. The second scanning signal GS(n + 2) includes a pulse width equivalent to that of the second scanning signal GS(n + 1) and is a signal obtained by shifting the scanning signal GS(n + 1). The scanning signal GS(n + 3) includes a pulse width equivalent to that of the scanning signal GS(n + 2) and is a signal obtained by shifting the scanning signal GS(n + 2).

[0032] As described above, the first gate driver circuit 120 and the second gate driver circuit 190 are synchronized. The pulse widths of the respective scanning signals supplied to the respective scanning signal lines by the first gate driver circuit 120 and the second gate driver circuit 190 are equal pulse widths. Further, by synchronizing the first gate driver circuit 120 and the second gate driver circuit 190, the scanning signal GF(n) becomes a signal obtained by shifting the scanning signal GF(n - 1), the scanning signal GS(n + 1) becomes a signal corresponding to a signal obtained by shifting the scanning signal GF(n), the scanning signal GF(n + 1) becomes a signal corresponding to a signal obtained by shifting the scanning signal GS(n + 1), and GS(n + 2) becomes a signal corresponding to a signal obtained by shifting the scanning signal GF(n + 1). That is, the scanning signals sequentially shifted in the order of the shift register 122, the shift register 122, the shift register 191, the shift register 123, the shift register 192, the shift register included in the first gate driver circuit 120 and connected to the shift register 123, and the shift register 193 are output. After that, the shift register included in the first gate driver circuit 120 and the shift register included in the second gate driver circuit 190 alternately output the scanning signals sequentially shifted. The scanning signal GF(n) may be called the first control signal, the scanning signal GS(n + 1) may be called the second control signal, and the scanning signal GF(n - 1) may be called the third control signal.

[0033] <1-4. Configuration of the First Light Emission Control Circuit 130 and the Second Light Emission Control Circuit 140> Referring to FIGS. 1 and 2, an overview of the first light emission control circuit 130 and the second light emission control circuit 140 will be described. As shown in FIG. 1 or FIG. 2, the first light emission control circuit 130 is adjacent to the display area 22 in the second direction D2 (row direction), and is provided on the side opposite to the position where the first gate driver circuit 120 is arranged with respect to the display area 22. The first light emission control signal lines 334, 335, and 336 extend from the first light emission control circuit 130 in the second direction D2 and are connected to a plurality of pixels 180 (pixel circuits) arranged in the second direction D2.

[0034] As shown in FIG. 2, the first light emission control circuit 130 includes a plurality of shift registers (for example, shift registers 131, 132, and 133). The shift registers 131, 132, and 133 sequentially supply first light emission control signals with different timings (for example, first light emission control signal EF(n), first light emission control signal EF(n + 1), first light emission control signal EF(n + 2)) to the respective first light emission control signal lines 334, 335, and 336 based on control signals such as a clock signal and a start pulse supplied from the IC chip 170, and have a role of driving the pixel 180 (pixel circuit) electrically connected to each first light emission control signal line.

[0035] For example, the shift register 131 is electrically connected to the shift register 132, and the shift register 132 is electrically connected to the shift register 133. The shift register 131 is electrically connected to the first light emission control signal line 334 and supplies, for example, the first light emission control signal EF(n) to the first light emission control signal line 334. Similarly to the shift register 131, the shift register 132 is electrically connected to the first light emission control signal line 335 and supplies, for example, the first light emission control signal EF(n + 1) to the first light emission control signal line 335, and the shift register 133 is electrically connected to the first light emission control signal line 336 and supplies, for example, the first light emission control signal EF(n + 2) to the first light emission control signal line 336. The pulse width of the first light emission control signal EF(n + 1) is the same as that of the first light emission control signal EF(n), and the first light emission control signal EF(n + 1) is a signal obtained by shifting the first light emission control signal EF(n). Similarly, the pulse width of the first light emission control signal EF(n + 2) is the same as that of the first light emission control signal EF(n + 1), and the first light emission control signal EF(n + 2) is a signal obtained by shifting the first light emission control signal EF(n + 2). The first light emission control signal EF may be called the fourth control signal.

[0036] As shown in FIG. 2, the second light emission control circuit 140 is adjacent to the first light emission control circuit 130 in the second direction D2 (row direction), and is provided on the side opposite to the position where the first gate driver circuit 120 is arranged with respect to the display area 22. The second light emission control signal lines 337, 338, and 339 extend from the second light emission control circuit 140 in the second direction D2 and are connected to a plurality of pixels 180 (pixel circuits) arranged in the second direction D2.

[0037] The second light emission control circuit 140 includes a plurality of shift registers (for example, shift registers 141, 142, and 143). The shift registers 141, 142, and 143 supply, to each of the second light emission control signal lines 337, 338, and 339, second light emission control signals (for example, second light emission control signal ES(n), second light emission control signal ES(n + 1), second light emission control signal ES(n + 1)) with different timings, based on control signals such as a clock signal and a start pulse supplied from the IC chip 170, and have a role of driving the pixels 180 (pixel circuits) electrically connected to each second light emission control signal line. The second light emission control signal ES may be called the fifth control signal.

[0038] For example, the shift register 141 is electrically connected to the shift register 142, and the shift register 142 is electrically connected to the shift register 143. The shift register 141 is electrically connected to the second light emission control signal line 337 and supplies, for example, the second light emission control signal ES(n) to the second light emission control signal line 337. Similarly to the shift register 141, the shift register 142 is electrically connected to the second light emission control signal line 338 and supplies, for example, the second light emission control signal ES(n + 1) to the second light emission control signal line 338, and the shift register 143 is electrically connected to the second light emission control signal line 339 and supplies, for example, the second light emission control signal ES(n + 2) to the second light emission control signal line 339. The pulse width of the second light emission control signal ES(n + 1) is the same as that of the second light emission control signal ES(n), and the second light emission control signal ES(n + 1) is a signal obtained by shifting the second light emission control signal ES(n). Similarly, the pulse width of the second light emission control signal ES(n + 2) is the same as that of the second light emission control signal ES(n + 1), and the second light emission control signal ES(n + 2) is a signal obtained by shifting the second light emission control signal ES(n + 2).

[0039] Note that the positions of the first light emission control circuit 130 and the second light emission control circuit 140 may be interchanged with respect to the second direction D2 (row direction).

[0040] <1-5. Configuration of Pixel 180> Referring to FIGS. 3 and 4, the outline of the pixel 180 will be described. FIG. 3 is a schematic diagram showing input signals to the pixel circuit 181 included in the pixel 180. FIG. 4 is a circuit diagram showing the configuration of the pixel circuit 181. FIGS. 3 and 4 show, as an example, the configuration of the pixel circuit 181 of the pixel 180 shown in FIGS. 1 and 2. The configurations of the pixel 180 and the pixel circuit 181 are not limited to the configurations shown in FIGS. 3 and 4. The description of the configurations identical or similar to those in FIGS. 1 and 2 will be omitted here.

[0041] The pixel circuit 181 is a circuit for driving the pixel 180. The pixel circuits of the sub-pixels R, G, and B included in the pixel 180 are the same as the pixel circuit 181, but the colors emitted by the light-emitting elements OLED are different. In the following description, as an example, the light-emitting element OLED that mainly emits red light will be mainly described.

[0042] As shown in FIG. 3, the pixel circuit 181 is supplied with a scan signal GF(n - 1), a scan signal GF(n), a scan signal GS(n + 1), an image data signal SL(m + 1), a first light emission control signal EF(n), a second light emission control signal ES(n), a reset voltage VSH, and an initialization voltage VINI. Further, as a power source for driving the pixel 180, the pixel circuit 181 is supplied with a driving voltage VDDEL or a driving voltage VDDELL, and a reference voltage VSSEL.

[0043] The reset voltage VSH is supplied to the reset voltage line VC, the initialization voltage VINI is supplied to the initialization voltage line VM, the drive voltages VDDEL and VDDELL are supplied to the drive power supply line PVDD, and the reference voltage VSSEL is supplied to the reference voltage line PVSS. Each of the reset voltage line VC, the initialization voltage line VM, the drive power supply line PVDD, and the reference voltage line PVSS may be electrically connected to, for example, different connection wirings 341, or may be the different connection wirings 341. The reset voltage VSH, the initialization voltage VINI, the drive voltages VDDEL and VDDELL, and the reference voltage VSSEL may be supplied from an external circuit to a plurality of pixels 180 (pixel circuits 181) via the FPC 160, the terminal portion 150, the reset voltage line VC, the initialization voltage line VM, the drive power supply line PVDD, and the reference voltage line PVSS. Further, the reset voltage VSH, the initialization voltage VINI, the drive voltages VDDEL and VDDELL, and the reference voltage VSSEL may be supplied from the IC chip 170 to a plurality of pixels 180 (pixel circuits 181) via the FPC 160, the terminal portion 150, the reset voltage line VC, the initialization voltage line VM, the drive power supply line PVDD, and the reference voltage line PVSS. The reset voltage VSH and the initialization voltage VINI are smaller than the drive voltages VDDEL and VDDELL. The drive voltage VDDELL is smaller than the drive voltage VDDEL. The reference voltage VSSEL is smaller than the drive voltage VDDELL. The reset voltage VSH is, for example, larger than the voltage included in the data signal VDATA (for example, the voltage RDATA(n), the voltage GDATA(n), or the voltage BDATA(n)).

[0044] As shown in FIG. 4, the pixel circuit 181 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a capacitive element CS, and a light-emitting element OLED. Each of these transistors includes a gate electrode and a pair of electrodes (a source electrode and a drain electrode) composed of a first electrode and a second electrode. Each of the capacitive element CS and the light-emitting element OLED has a pair of electrodes composed of a first electrode and a second electrode.

[0045] The first transistor T1 is a so-called selection transistor. The first transistor T1 has a function of supplying an image data signal SL(m + 1) to the second transistor T2.

[0046] The second transistor T2 is a so-called driving transistor. The second transistor T2 has a function of passing a current through the light-emitting element OLED using the input image data signal SL(m + 1) to cause the light-emitting element OLED to emit light.

[0047] The third transistor T3 conducts the second node N2 and the gate electrode 622 of the second transistor T2 (and the second electrode 694 of the capacitor element CS), supplies a reset voltage VSH to the gate electrode 622 of the second transistor T2, and has a function of resetting the gate electrode 622 of the second transistor T2. Further, the third transistor T3 has a function of accumulating a charge corresponding to the threshold voltage Vth of the second transistor T2 in the gate electrode 622 of the second transistor T2 and the second electrode 694 of the capacitor element CS.

[0048] The fourth transistor T4 controls the connection and disconnection between the driving power supply line PVDD and the second transistor T2. That is, the fourth transistor T4 has a function of supplying a driving voltage VDDEL to the second transistor T2.

[0049] The fifth transistor T5 controls the connection and disconnection between the second transistor T2 and the light-emitting element OLED. That is, the fifth transistor T5 controls the connection and disconnection between the second transistor T2 and the light-emitting element OLED, and has a function of supplying a current to the light-emitting element OLED and controlling the light emission and non-light emission of the light-emitting element OLED.

[0050] The sixth transistor T6 supplies an initialization voltage VINI to the first electrode 654 of the fifth transistor T5, the second electrode 684 of the light-emitting element OLED, and the first electrode 692 of the capacitor element CS, and has a function of initializing the first electrode 654 of the fifth transistor T5, the second electrode 684 of the light-emitting element OLED, and the first electrode 692 of the capacitor element CS.

[0051] The seventh transistor T7 supplies a reset voltage VSH to the first electrode 644 of the fourth transistor T4, the second electrode 626 of the second transistor T2, the second electrode 636 of the third transistor T3, etc., and has a function of resetting the first electrode 644 of the fourth transistor T4, the second electrode 626 of the second transistor T2, and the second electrode 636 of the third transistor T3.

[0052] The capacitor element CS has a function of holding a charge (first charge) corresponding to the threshold voltage Vth of the second transistor T2, for example. Further, the capacitor element CS has a function of holding a charge (second charge) corresponding to a data voltage (for example, RDATA(n) (see FIG. 6)) included in the image data signal SL(m + 1) input to the gate electrode 622 of the second transistor T2.

[0053] The light-emitting element OLED has diode characteristics and has a function of emitting light based on the current flowing through the light-emitting element OLED (that is, the drain current of the second transistor T2).

[0054] The first transistor T1 includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to the second scanning signal line 349. The first electrode 614 is electrically connected to the image data signal line 321. The second electrode 616 is electrically connected to the first node N1, the first electrode 624 of the second transistor T2, and the second electrode 656 of the fifth transistor T5. A scanning signal GS(n + 1) is supplied to the second scanning signal line 349. The first transistor T1 has its conduction state (on state) and non-conduction state (off state) controlled by the scanning signal GS(n + 1). When the signal supplied to the scanning signal GS(n + 1) is low (LO), the first transistor T1 is in a non-conduction state. When the signal supplied to the scanning signal GS(n + 1) is high (HI), the first transistor T1 is in a conduction state.

[0055] The second transistor T2 includes a gate electrode 622, a first electrode 624, and a second electrode 626. The gate electrode 622 is electrically connected to the first electrode 634 of the third transistor T3 and the second electrode 694 of the capacitor element CS. The second electrode 626 is electrically connected to the second node N2, the second electrode 636 of the third transistor T3, the first electrode 674 of the seventh transistor T7, and the first electrode 644 of the fourth transistor T4.

[0056] The third transistor T3 includes a gate electrode 632, a first electrode 634, and a second electrode 636. The gate electrode 632 is electrically connected to the first scanning signal line 330. A scanning signal GF(n) is supplied to the first scanning signal line 330. The third transistor T3 is controlled to be in a conductive state (on state) or a non-conductive state (off state) by the scanning signal GF(n). When the signal supplied to the scanning signal GF(n) is low (LO), the third transistor T3 is in a non-conductive state. When the signal supplied to the scanning signal GF(n) is high (HI), the third transistor T3 is in a conductive state.

[0057] The fourth transistor T4 includes a gate electrode 642, a first electrode 644, and a second electrode 646. The gate electrode 642 is electrically connected to the second light emission control signal line 337. The second electrode 646 is electrically connected to the driving power supply line PVDD. A driving voltage VDDEL is supplied to the driving power supply line PVDD. A second light emission control signal ES(n) is supplied to the second light emission control signal line 337. The fourth transistor T4 is controlled to be in a conductive state (on state) or a non-conductive state (off state) by the second light emission control signal ES(n). When the signal supplied to the second light emission control signal ES(n) is low (LO), the fourth transistor T4 is in a non-conductive state. When the signal supplied to the second light emission control signal ES(n) is high (HI), the fourth transistor T4 is in a conductive state.

[0058] The fifth transistor T5 includes a gate electrode 652, a first electrode 654, and a second electrode 656. The gate electrode 652 is electrically connected to the first light emission control signal line 334. The first electrode 654 is electrically connected to the second electrode 666 of the sixth transistor T6, the first electrode 692 of the capacitor element CS, and the second electrode 684 of the light emitting element OLED. The first light emission control signal EF(n) is supplied to the first light emission control signal line 334. The fifth transistor T5 is controlled to be in a conductive state (on state) or a non-conductive state (off state) by the first light emission control signal EF(n). When the signal supplied to the first light emission control signal EF(n) is low (LO), the fifth transistor T5 is in a non-conductive state. When the signal supplied to the first light emission control signal EF(n) is high (HI), the fifth transistor T5 is in a conductive state.

[0059] The sixth transistor T6 includes a gate electrode 662, a first electrode 664, and a second electrode 666. The gate electrode 662 is electrically connected to the first scanning signal line 330. The first electrode 664 is electrically connected to the initialization voltage line VM. As described above, the scanning signal GF(n) is supplied to the first scanning signal line 330, and the initialization voltage VINI is supplied to the initialization voltage line VM. Similar to the third transistor T3, the sixth transistor T6 is controlled to be in a conductive state (on state) or a non-conductive state (off state) by the scanning signal GF(n). When the signal supplied to the scanning signal GF(n) is low (LO), the sixth transistor T6 is in a non-conductive state. When the signal supplied to the scanning signal GF(n) is high (HI), the sixth transistor T6 is in a conductive state.

[0060] The seventh transistor T7 includes a gate electrode 672, a first electrode 674, and a second electrode 676. The gate electrode 672 is electrically connected to the first scanning signal line 329. A scanning signal GF(n - 1) is supplied to the first scanning signal line 329. The second electrode 676 is electrically connected to the reset voltage line VC. As described above, a reset voltage VSH is supplied to the reset voltage line VC. The seventh transistor T7 is controlled to be in a conductive state (on state) or a non - conductive state (off state) by the scanning signal GF(n - 1). When the signal supplied to the scanning signal GF(n - 1) is low (LO), the seventh transistor T7 becomes non - conductive. When the signal supplied to the scanning signal GF(n - 1) is high (HI), the seventh transistor T7 becomes conductive.

[0061] The first electrode 682 of the light - emitting element OLED is electrically connected to the reference voltage line PVSS. As described above, a reference voltage VSSEL is supplied to the reference voltage line PVSS. The first electrode 682 of the light - emitting element OLED is, for example, a cathode electrode, and the second electrode 684 of the light - emitting element OLED is, for example, an anode electrode.

[0062] In the self - emissive display device 10, the conductive state of the transistor means, for example, that the source electrode and the drain electrode of the transistor are conductive, indicating that the transistor is in an on state. The non - conductive state of the transistor means that the source electrode and the drain electrode of the transistor are non - conductive, indicating that the transistor is in an off state. Note that in each transistor, the source electrode and the drain electrode may be interchanged according to the voltage or potential supplied to each electrode. Also, even when the transistor is in an off state, it is easily understood by those skilled in the art that a small current, such as a leakage current, may flow.

[0063] Each transistor shown in FIG. 4 can have a Group 14 element such as silicon or germanium, or an oxide exhibiting semiconductor characteristics, in its channel region. For example, the channel region of each transistor has low-temperature polysilicon (LTPS). In the self-emission type display device 10, each transistor is formed using a thin-film transistor (TFT) and has an n-channel type field-effect transistor. Each transistor may have either an n-channel type field-effect transistor or a p-channel type field-effect transistor. The self-emission type display device 10 may appropriately adapt the configuration of the transistor, the connection of the holding capacitance, the power supply voltage, etc., according to the application and specifications.

[0064] <1-6. Driving method of the self-emission type display device 10> Referring to FIGS. 5(A) to 14, the driving method of the self-emission type display device 10 will be described. FIGS. 5(A), 5(B), 6, and 13 are schematic diagrams showing the timing charts of the self-emission type display device 10. FIGS. 7 to 12 are schematic diagrams showing the operating states of the pixel 180 (pixel circuit 181) at the timing shown in FIG. 6. FIG. 14 is a schematic diagram showing the operating state of the pixel 180 (pixel circuit 181) at the timing shown in FIG. 13. The driving method of the self-emission type display device 10 is not limited to the driving methods shown in FIGS. 5(A) to 14. For configurations identical or similar to those in FIGS. 1 to 4, the description here will be omitted. Note that the horizontal axis of the timing chart is time (TIME).

[0065] FIG. 5(A) is, for example, a timing chart of the driving method of the self-emission type display device 10 when the self-emission type display device 10 is driven at a high frequency. The high frequency is, for example, 60 Hz, which is the frequency at which 1 frame (1 FRAME) is driven at 60 Hz. FIG. 5(A) shows, for example, the current frame (Kth FRAME), a part of the frame one before the current frame (K - 1st FRAME), and a part of the frame one after the current frame (K + 1st FRAME). The driving method shown in FIG. 5(A) is called high-frequency driving, for example.

[0066] As shown in FIG. 5(A), the driving method of the self-emitting display device 10 includes at least a reset period PRS, a sampling period PWR, and a light-emitting period PEM within one frame. In the pixel 180 (pixel circuit 181) included in the self-emitting display device 10, the sampling period PWR is executed after the reset period PRS, and the light-emitting period PEM is executed after the sampling period PWR. Also, after the light-emitting period PEM of the frame immediately preceding the current frame, the reset period PRS of the current frame is executed, and after the light-emitting period PEM of the current frame, the reset period PRS and the sampling period PWR of the frame immediately following the current frame are executed.

[0067] FIG. 5(B) is a timing chart of the driving method of the self-emitting display device 10 when the self-emitting display device 10 is driven at a low frequency, for example. The low frequency is, for example, 1 Hz, which is the frequency at which one frame (1 FRAME) is driven at 1 Hz. The driving method shown in FIG. 5(B) is called low-frequency driving, for example. Low-frequency driving is a driving method in which, compared with high-frequency driving, a period for displaying black (black period PBWR) is executed multiple times during the light-emitting period PEM. In low-frequency driving, the driving other than the black period PBWR is the same as that in high-frequency driving.

[0068] FIG. 6 is a diagram for explaining a reset period PRS, a sampling period PWR, and a light emission period PEM of a driving method of a pixel 180 (pixel circuit 181) of the self-luminous display device 10. FIG. 6 shows a light emission period PEM of a frame (K-1st FRAME) one frame before the current frame, a reset period PRS, a sampling period PWR, and a light emission period PEM of the current frame (Kth FRAME). Further, FIG. 6 shows a plurality of one horizontal periods (horizontal period N-2nd HP, horizontal period N-1st HP, horizontal period Nth HP, horizontal period N+1st HP, horizontal period N+2nd HP). One horizontal period is, for example, a period during which an image data signal SL(m+1) including a data signal VDATA is input to a pixel (pixel circuit) electrically connected to one second scanning signal line, and the image data signal SL(m+1) including the data signal VDATA is input to all pixels (pixel circuits) electrically connected to the second scanning signal lines, and an image of the current frame corresponding to 1 FRAME is displayed.

[0069] Referring to FIGS. 6 to 12, an example of a driving method in which the pixel 180 (pixel circuit 181) displays an image based on a voltage RDATA(n) included in the data signal VDATA input in one horizontal period Nth HP will be described. In the description of the driving method according to the first embodiment, as an example, a driving voltage VDDEL or a driving voltage VDDELL is supplied to a driving power supply line PVDD, and a reference voltage VSSEL is supplied to a reference voltage line PVSS.

[0070] First, the data signal VDATA, the selection signal MUXR, the selection signal MUXG, and the selection signal MUXB will be described. In accordance with each horizontal period, an image data signal SL(m + 1) including the data signal VDATA is input to each pixel 180 (pixel circuit 181). The data signal VDATA is analog data including, for example, a voltage between a voltage VDL lower than the voltage VDH and the voltage VDH. The voltage VDM is a voltage between a voltage VDL lower than the voltage VDH and the voltage VDH. In each horizontal period, for example, using the selection signal MUXR, the voltage RDATA is selected and supplied to the image data signal line, using the selection signal MUXG, the voltage GDATA is selected and supplied to the image data signal line, and using the selection signal MUXB, the voltage BDATA is selected and supplied to the image data signal line. During a period when data is not selected using the selection signal MUXG, the data signal VDATA is maintained at, for example, the voltage VDM.

[0071] Next, referring to FIGS. 6 and 7, a driving method of the pixel 180 (pixel circuit 181) during the light emission period PEM of the frame immediately preceding the current frame (K - 1st FRAME) will be described. The light emission period PEM of the frame immediately preceding the current frame (K - 1st FRAME) is a period during which the pixel 180 (pixel circuit 181) emits light in accordance with the voltage RDATA(n - 1).

[0072] The gate electrode 622 of the second transistor T2 is supplied with the voltage RDATA(n - 1). The scan signals GF(n - 1), GF(n), and GS(n + 1) are supplied with a low (LO), and the first transistor T1, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are in an off state. Also, the fourth transistor T4 is supplied with a high (HI) from the second light emission control signal ES(n), the fifth transistor T5 is supplied with a high (HI) from the first light emission control signal EF(n), and the fourth transistor T4 and the fifth transistor T5 are in an on state.

[0073] The second transistor T2 is in an on state based on the voltage RDATA(n - 1). As a result, the second transistor T2 can conduct a current IEL based on the gate-source voltage Vgs and the source-drain voltage Vds corresponding to the voltage RDATA(n - 1).

[0074] The fourth transistor T4, the second transistor T2, and the fifth transistor T5 are in an on state, and the current IEL flows from the driving power supply line PVDD to the reference voltage line PVSS. As a result, the current IEL flows through the light-emitting element OLED, and the light-emitting element OLED emits light.

[0075] Next, referring to FIG. 6, the driving method of the pixel 180 (pixel circuit 181) during the period between the light-emitting period PEM of the frame immediately preceding this frame (K - 1stFRAME) and the reset period PRS of this frame will be described. The period between the light-emitting period PEM of the frame immediately preceding this frame (K - 1stFRAME) and the reset period PRS of this frame is a period that overlaps with a part of the one horizontal period N - 2ndHP and a part of the one horizontal period N - 1stHP. During this period, the second light-emitting control signal ES(n) and the first light-emitting control signal EF(n) are supplied from high (HI) to low (LO), and the fifth transistor T5 and the fourth transistor T4 are in an off state. Also, the scanning signal GF(n - 1) is supplied from low (LO) to high (HI), and the seventh transistor T7 is in an on state. The first transistor T1, the third transistor T3, and the sixth transistor T6 remain in an off state. The fourth transistor T4 and the fifth transistor T5 are in an off state, no current flows from the driving power supply line PVDD to the reference voltage line PVSS, and the light-emitting element OLED does not emit light (is non-luminous).

[0076] Next, referring to FIGS. 6 and 8, a driving method of the pixel 180 (pixel circuit 181) during the reset period PRS of the frame will be described. The reset period PRS is a period during which a reset voltage VSH and an initialization voltage VINI are written to the pixel 180 (pixel circuit 181) to initialize the pixel 180 (pixel circuit 181). The reset period PRS of the frame is a period overlapping with a part of the (N - 1)st horizontal period N - 1stHP.

[0077] During the reset period PRS, the scanning signal GF(n) is supplied from low (LO) to high (HI), and the third transistor T3 and the sixth transistor T6 are in an on state. Also, the seventh transistor T7 remains in an on state, and the first transistor T1, the fourth transistor T4, and the fifth transistor T5 remain in an off state.

[0078] Based on the seventh transistor T7 and the third transistor T3 being in an on state, the reset voltage VSH is supplied to the first node N1, the second node N2, each electrode electrically connected to the first node N1, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor element CS. Also, based on the sixth transistor T6 being in an on state, the initialization voltage VINI is supplied to the first electrode 692 of the capacitor element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. As a result, the first node N1, the second node N2, each electrode electrically connected to the first node N1, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor element CS are reset, and the first electrode 692 of the capacitor element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED are initialized. Also, since the fourth transistor T4 and the fifth transistor T5 remain in an off state, no current flows from the driving power supply line PVDD to the reference voltage line PVSS, and the light-emitting element OLED does not emit light (is not emitting light).

[0079] Next, with reference to FIGS. 6 and 9, a method of driving the pixel 180 (pixel circuit 181) during the period between the reset period PRS and the sampling period PWR of the frame will be described. The period between the reset period PRS and the sampling period PWR of the frame is a period overlapping a part of the (N-1)st horizontal period N-1stHP and a part of the Nth horizontal period NthHP.

[0080] During the period between the reset period PRS and the sampling period PWR of the frame, the scanning signal GF(n-1) is supplied from high (HI) to low (LO), and the seventh transistor T7 is in the off state. Also, the third transistor T3 and the sixth transistor T6 remain in the on state, and the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 remain in the off state.

[0081] Also, during the period between the reset period PRS and the sampling period PWR of the frame, the reset voltage VSH is held at the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor element CS. Also, since the sixth transistor T6 remains in the on state, the initialization voltage VINI is supplied to the first electrode 692 of the capacitor element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. Also, since the fourth transistor T4 and the fifth transistor T5 remain in the off state, no current flows from the driving power supply line PVDD to the reference voltage line PVSS, and the light-emitting element OLED does not emit light (is not emitting).

[0082] During the period between the reset period PRS and the sampling period PWR of the frame, based on the on signal being supplied to the selection signal MUXR, the voltage RDATA(n) is selected. Therefore, the image data signal SL(m + 1) includes the voltage RDATA(n). Further, the image data signal SL(m + 1) including the voltage RDATA(n) is supplied to the image data signal line 321. Based on the off signal being supplied to the selection signal MUXR, the image data signal line 321 holds the voltage RDATA(n).

[0083] Next, with reference to FIGS. 6 and 10, a driving method of the pixel 180 (pixel circuit 181) during the sampling period PWR of the frame will be described. The sampling period PWR is a period in which a voltage corresponding to the image data to be displayed by the pixel 180 (pixel circuit 181) is written into the pixel 180 (pixel circuit 181). The sampling period PWR of the frame is a period that overlaps a part of one horizontal period NthHP.

[0084] During the sampling period PWR of the frame, the scanning signal GS(n + 1) is supplied from low (LO) to high (HI), and the first transistor T1 is in the on state. Also, the third transistor T3 and the sixth transistor T6 remain in the on state, and the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 remain in the off state.

[0085] Based on the first transistor T1 being turned on, the voltage RDATA(n) is supplied to the first node N1 and each electrode electrically connected to the first node N1. Also, when the voltage RDATA(n) is supplied to the first node N1, the voltage between the gate and source of the second transistor T2 also changes, and the second transistor T2 turns on. As a result, the voltages of the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor element CS drop from the voltage VSH and become the voltage RDATA(n) + threshold voltage Vth (RDATA(n) + Vth). Thus, the potential difference between the gate electrode 622 and the first electrode 624 of the second transistor T2 becomes the same as the threshold voltage Vth of the second transistor T2. Along with the completion of the voltage drop of the second node N2 etc., the second transistor T2 turns off. Also, since the sixth transistor T6 remains on, the initialization voltage VINI is supplied to the first electrode 692 of the capacitor element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. Also, since the fourth transistor T4 and the fifth transistor T5 remain off, no current flows from the drive power supply line PVDD to the reference voltage line PVSS, and the light-emitting element OLED does not emit light (is not emitting).

[0086] Although detailed illustration is omitted, at this time, since the first transistor T1 remains on, the voltages of the first node N1 and each electrode electrically connected to the first node N1 are fixed at the voltage RDATA(n). Also, a charge corresponding to the threshold voltage Vth is held between the gate electrode 622 and the first electrode 624 of the second transistor T2. Therefore, the sampling period PWR of this frame is a period in which the pixel 180 (pixel circuit 181) writes the voltage corresponding to the image data to be displayed by the pixel 180 (pixel circuit 181), and is also a period (threshold correction period) in which a charge corresponding to the threshold voltage Vth is held between the gate electrode 622 and the first electrode 624 of the second transistor T2 to correct the threshold of the second transistor T2.

[0087] Next, referring to FIGS. 6 and 11, a method of driving pixel 180 (pixel circuit 181) after the sampling period PWR of the frame will be described. The period after the sampling period PWR of the frame is a period that overlaps a part of one horizontal period NthHP and one horizontal period N+1stHP.

[0088] In the period after the sampling period PWR of the frame, the scanning signal GF(n) is supplied from high (HI) to low (LO), and the third transistor T3 is in the off state. Also, the first transistor T1 remains in the on state, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 remain in the off state. A high (HI) is supplied to the scanning signal GS(n+1), and the first transistor T1 is in the on state. Therefore, since the potential difference between the voltage of the first electrode 614 and the voltage of the second electrode 616 of the first transistor T1 is 0, no current flows through the first transistor T1.

[0089] Since the second transistor T2, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are in the off state, a voltage RDATA(n)+threshold voltage Vth (RDATA(n)+Vth) is held at the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitive element CS, and an initialization voltage VINI is held at the first electrode 692 of the capacitive element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. Also, since the fourth transistor T4 and the fifth transistor T5 are in the off state, no current flows from the driving power supply line PVDD to the reference voltage line PVSS, and the light-emitting element OLED does not emit light (is not emitting).

[0090] As shown in FIG. 6, after the scanning signal GF(n) is supplied from high (HI) to low (LO) and the third transistor T3 becomes in the off state, the scanning signal GS(n+1) is supplied from high (HI) to low (LO), and the first transistor T1 becomes in the off state.

[0091] At this time, since the first transistor T1 is in the off state, the voltage RDATA(n) is held at the first node N1 and each electrode electrically connected to the first node N1. Also, since the second transistor T2, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are in the off state, the voltage RDATA(n) + threshold voltage Vth (RDATA(n) + Vth) is held at the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitive element CS. The initialization voltage VINI is held at the first electrode 692 of the capacitive element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. Furthermore, since the fourth transistor T4 and the fifth transistor T5 are in the off state, no current flows from the driving power supply line PVDD to the reference voltage line PVSS, and the light-emitting element OLED does not emit light (is not emitting).

[0092] Next, referring to FIGS. 6, 11, and 12, a driving method of the pixel 180 (pixel circuit 181) during the light-emitting period PEM of the current frame will be described. The light-emitting period PEM of the current frame is a period during which the pixel 180 (pixel circuit 181) emits light according to the voltage RDATA(n). The light-emitting period PEM of the current frame is a period overlapping with one horizontal period N + 2ndHP.

[0093] As shown in FIGS. 6 and 12, the scan signals GF(n - 1), G(n), and GS(n + 1) are supplied with low (LO), and the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are in the off state. Also, the fourth transistor T4 is supplied with high (HI) from the second light emission control signal ES(n), the fifth transistor T5 is supplied with high (HI) from the first light emission control signal EF(n), and the fourth transistor T4 and the fifth transistor T5 are in the on state.

[0094] As shown in FIG. 11, the voltage held by the second electrode 656 of the fifth transistor T5 is RDATA(n), and the voltage held by the first electrode 654 of the fifth transistor T5 is the initialization voltage VINI.

[0095] When the fifth transistor T5 shown in FIGS. 6 and 12 is turned on from the state where the voltage of the second electrode 656 and the voltage of the first electrode 654 of the fifth transistor T5 are the voltage RDATA(n) (RDATA(n)) and the initialization voltage VINI (VINI), a current flows from the second electrode 656 to the first electrode 654 of the fifth transistor T5, charge redistribution occurs, and the voltages of the second electrode 656 and the first electrode 654 become the initialization voltage VINI (VINI). At this time, the gate electrode 622 of the second transistor T2 and the second electrode 694 of the capacitor element CS become the voltage RDATA(n) + threshold voltage Vth - initialization voltage VINI (RDATA(n) + Vth - VINI). Depending on the value of the voltage RDATA(n), the second transistor T2 may be in an on state or an off state.

[0096] Also, for example, as shown in FIGS. 6 and 12, based on the fact that the fifth transistor T5 is in the on state, current flows from the second electrode 656 to the first electrode 654 of the fifth transistor T5, and when the voltages of the second electrode 656 and each electrode electrically connected to the second electrode (the second electrode 684 of the light-emitting element OLED, the second electrode 666 of the sixth transistor T6, and the first electrode 692 of the capacitor element CS) rise from the voltage VINI to the voltage VINI+α, the voltage held by the first node N1 (the second electrode 656 of the fifth transistor T5 and the first electrode 624 of the second transistor T2) decreases from RDATA(n). As the first electrode 692 of the capacitor element CS rises to the voltage VINI+α, by capacitive coupling, the voltages of the gate electrode 622 of the second transistor T2 and the second electrode 694 of the capacitor element CS rise from the voltage RDATA(n)+threshold voltage Vth (RDATA(n)+Vth) to the voltage RDATA(n)+threshold voltage Vth+voltage α (RDATA(n)+Vth+α). As a result, since the gate-source voltage between the gate electrode 622 and the first electrode 624 of the second transistor T2 becomes higher than the threshold voltage Vth of the second transistor T2, the second transistor T2 becomes in the on state.

[0097] The fourth transistor T4, the second transistor T2, and the fifth transistor T5 are in the on state, and a current IELA flows from the drive power supply line PVDD to the reference voltage line PVSS. As a result, the current IELA flows through the light-emitting element OLED, and the light-emitting element OLED emits light. The current IELA is, for example, a current based on the voltage RDATA(n)+threshold voltage Vth+voltage α (RDATA(n)+Vth+α) written in the second transistor T2. Here, for example, the voltage α is a positive value and is a voltage value that changes according to the voltage RDATA(n). For example, when the voltage RDATA(n) increases (becomes larger), the voltage α becomes higher (larger), and when the voltage RDATA(n) decreases (becomes smaller), the voltage α becomes lower (smaller). For example, the voltage α is determined so that the current value flowing through the second transistor T2 according to the gate electrode 622, the first electrode 624, and the second electrode 626 is the same as the current value flowing through the light-emitting element OLED.

[0098] As described above, the self-emitting display device 10 is driven, and image data corresponding to each pixel 180 (pixel circuit 181) is supplied to each pixel 180 (pixel circuit 181). A current corresponding to the image data is supplied to the light-emitting element OLED included in each pixel 180 (pixel circuit 181), and each light-emitting element OLED emits light with a luminance corresponding to the image data. As a result, the self-emitting display device 10 can display a desired image.

[0099] For example, in a conventional driving method of a self-emitting display device different from the present invention, the driving voltage VDDEL is used as a reset voltage during the reset period. That is, in the conventional driving method, the driving voltage VDDEL is supplied from the driving power supply line PVDD to the second node N2 and the gate electrode 622 of the pixel 180. For example, the power consumption of the self-emitting display device is reduced when displaying a low-gray-scale image. At this time, the power supply voltage VDDEL is reduced to, for example, a driving voltage VDDELL lower than the driving voltage VDDEL. However, in the conventional driving method, when the driving voltage VDDEL is reduced to the driving voltage VDDELL, the reset voltage also decreases, so the luminance of the self-emitting display device decreases.

[0100] On the other hand, the self-emitting display device 10 of the present invention includes a seventh transistor T7. Based on the self-emitting display device 10 of the present invention including the seventh transistor T7, the self-emitting display device 10 of the present invention can supply a reset voltage VSH independent of the driving voltage VDDEL to the second node N2 and the gate electrode 622 using the seventh transistor T7. Further, the self-emitting display device 10 of the present invention can supply the driving voltage VDDEL to the driving power supply line PVDD independently of the reset voltage VSH. As a result, as shown in FIG. 6, for example, even if a driving voltage VDDELL lower than the driving voltage VDDEL is supplied to the driving power supply line PVDD, the reset voltage VSH supplied to the gate electrode 622 (second node N2) does not decrease.

[0101] Therefore, in the self-emitting display device 10 of the present invention, there is no decrease in luminance associated with the decrease in the reset voltage VSH. In the self-emitting display device 10, when displaying a low-gray-scale image, by supplying a power supply voltage VDDELL lower than the power supply voltage VDDEL to the pixel 180 (pixel circuit 181), the power consumption can be reduced without a decrease in luminance.

[0102] Next, with reference to FIGS. 5(B), 13, and 14, an example of a driving method in which the pixel 180 (pixel circuit 181) displays black based on the voltage RDATAB included in the data signal VDATA input in one horizontal period NthHP will be described. As described above, in the low-frequency driving, the driving other than the black period PBWR is the same as the high-frequency driving. Therefore, mainly, the driving of the pixel 180 (pixel circuit 181) in the black period PBWR will be described here. For configurations the same as or similar to those in FIGS. 1 to 5(A) and FIGS. 6 to 12, the description here will be omitted. Note that the horizontal axis of the timing chart is time (TIME).

[0103] First, the data signal VDATA, selection signal MUXR, selection signal MUXG, and selection signal MUXB will be described. In accordance with each horizontal period, an image data signal SL(m + 1) including the data signal VDATA is input to each pixel 180 (pixel circuit 181). The data signal VDATA is, for example, analog data including a voltage VDL for displaying black. The voltage VDM is a voltage between the voltage VDL lower than the voltage VDH and the voltage VDH. In each horizontal period, for example, using the selection signal MUXR, the voltage VDL is selected and supplied to the image data signal line, using the selection signal MUXG, the voltage VDL is selected and supplied to the image data signal line, and using the selection signal MUXB, the voltage VDL is selected and supplied to the image data signal line. During a period when data is not selected using the selection signal MUXG, the data signal VDATA is maintained at, for example, the voltage VDM.

[0104] The driving method of pixel 180 (pixel circuit 181) during the light emission period PEM of the frame immediately preceding the current frame (K-1st FRAME) is the same as the driving method described with reference to FIGS. 1 to 5(A), FIGS. 6 to 12. Therefore, the description here is omitted. Note that the voltages of the first node N1, the first electrode 654 of the fifth transistor T5, and the second electrode 684 of the light emitting element OLED from the light emission period PEM to the black period PBWR of the frame immediately preceding the current frame (K-1st FRAME) are voltages between the voltage VDL and the voltage VDH.

[0105] Next, the driving method of pixel 180 (pixel circuit 181) during the period between the light emission period PEM and the black period PBWR of the frame immediately preceding the current frame (K-1st FRAME) will be described. The period between the light emission period PEM and the black period PBWR of the frame immediately preceding the current frame (K-1st FRAME) is a period that overlaps with a part of the one horizontal period N-2nd HP, a part of the one horizontal period N-1st HP, and a part of the one horizontal period Nth HP.

[0106] The scan signal GF(n-1), the scan signal GF(n), the scan signal GS(n+1), the first light emission control signal EF(n), and the second light emission control signal ES(n) are supplied with low (LO). Therefore, all the transistors (the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7) in the pixel circuit 181 are in the off state. Therefore, no current flows from the driving power supply line PVDD to the reference voltage line PVSS, the current IDI flowing through the light emitting element OLED is almost 0, and the light emitting element OLED is non-emitting (not emitting light).

[0107] Next, with reference to FIGS. 13 and 14, the driving method of pixel 180 (pixel circuit 181) during the black period PBWR of the current frame will be described. The black period PBWR of the current frame is a period that overlaps with a part of the one horizontal period Nth HP and a part of the one horizontal period N+1st HP.

[0108] During the black period PBWR of the frame, the scanning signal GS(n + 1) and the first light emission control signal EF(n) are supplied from low (LO) to high (HI), and the first transistor T1 and the fifth transistor T5 are in the on state. Also, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 remain in the off state.

[0109] Based on the first transistor T1 being in the on state, a voltage RDATAB including the voltage VDL is supplied to the first node N1, each electrode electrically connected to the first node N1, the first electrode 654 of the fifth transistor T5, the second electrode 684 of the light emitting element OLED, the second electrode 666 of the sixth transistor T6, and the first electrode 692 of the capacitive element CS. Although not shown in the figure, since the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 remain in the off state, a voltage similar to the voltage between the voltage VDL and the voltage VDH supplied during the light emission period PEM of the previous frame (K - 1stFRAME) of this frame is held at the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitive element CS.

[0110] Also, since the fourth transistor T4 remains in the off state, no current flows from the drive power line PVDD to the reference voltage line PVSS, and current flows from the image data signal line 321 to the reference voltage line PVSS. The current IDI flowing through the light emitting element OLED is a current (almost 0) corresponding to the potential difference (voltage RDATAB - reference voltage VSSEL) between the voltage of the second electrode 684 and the voltage of the first electrode 682 of the light emitting element OLED, and the light emitting element OLED is non - emitting (not emitting light). That is, the pixel 180 (pixel circuit 181) displays black.

[0111] The driving method of pixel 180 (pixel circuit 181) during the light emission period PEM of frame (Kth FRAME) is the same as the driving method of pixel 180 (pixel circuit 181) during the light emission period PEM of the frame immediately preceding this frame (K - 1st FRAME). Therefore, the description here is omitted. Note that the voltages of the first node N1 from the light emission period PEM to the black period PBWR of this frame (Kth FRAME), the first electrode 654 of the fifth transistor T5, and the second electrode 684 of the light emitting element OLED are voltages between voltage VDL and voltage VDH.

[0112] In the self - emissive display device 10, flicker can be adjusted by executing the black period PBWR. As described above, during the black period PBWR, the voltages supplied to the scan signals GF(n - 1) and GF(n) are fixed low, and only the scan signal GS(n + 1) is supplied high. In the self - emissive display device 10, by providing the first gate driver circuit 120 (shift registers 121 to 123) and the second gate driver circuit 190 (shift registers 191 to 193), the voltages supplied to the scan signals GF(n - 1) and GF(n) and the voltage supplied to the scan signal GS(n + 1) can be controlled independently.

[0113] <2. Second Embodiment> Referring to FIGS. 15 to 26, the self - emissive display device 10A according to the second embodiment will be described. In the self - emissive display device 10A, mainly, the light emission of pixels is controlled using one light emission control circuit (light emission control circuit 130A), the fourth transistor T4 and the fifth transistor T5 are controlled by a common light emission control signal EM, and the sixth transistor T6 is a p - channel type field - effect transistor. Other configurations are the same as those of the self - emissive display device 10 described in the first embodiment. by That is. The self - emissive display device 10A shown in FIGS. 15 to 27 is an example, and the self - emissive display device 10A is not limited to the example shown in FIGS. 15 to 27. Regarding the configurations that are the same as or similar to those of the self - emissive display device 10 described in the first embodiment and the configurations that are the same as or similar to those in FIGS. 1 to 14, the description here is omitted.

[0114] <2-1. Overview of the Self-Emitting Display Device 10A> Using FIG. 15, the overview of the self-emitting display device 10A will be described. FIG. 15 is a schematic plan view showing the configuration of the self-emitting display device 10A according to the second embodiment.

[0115] As shown in FIG. 15, the self-emitting display device 10A includes a source driver circuit 110 similar to the source driver circuit 110 shown in FIGS. 1 and 2. Further, the self-emitting display device 10A includes a configuration in which the IC chip 170 shown in FIGS. 1 and 2 is replaced with an IC chip 170A, a configuration in which the first gate driver circuit 120 and the second gate driver circuit 190 shown in FIGS. 1 and 2 are combined into a gate driver circuit 120A, and a configuration in which the first light emission control circuit 130 and the second light emission control circuit 140 shown in FIGS. 1 and 2 are combined into a light emission control circuit 130A. Also, as shown in FIG. 15 or FIG. 16, in the self-emitting display device 10A, the pixel 180 arranged in the display area 22 (FIG. 1) includes a pixel circuit 182.

[0116] The image data signal line 321 extends from the source driver circuit 110 in the first direction D1 and is connected to a plurality of pixels 180 (pixel circuits 182) arranged in the first direction D1. Since the configuration of the source driver circuit 110 other than the above is the same as that of the first embodiment, detailed description thereof is omitted here.

[0117] The IC chip 170A is electrically connected to the source driver circuit 110, the gate driver circuit 120A, and the light emission control circuit 130A using the connection wiring 341. Similar to the IC chip 170, the IC chip 170A supplies signals, voltages, etc. for driving each pixel 180 to the source driver circuit 110, the gate driver circuit 120A, the light emission control circuit 130A, and the pixel circuit 182.

[0118] Similar to the first embodiment, in the second embodiment, each of the source driver circuit 110, the gate driver circuit 120A, the light emission control circuit 130A, and the IC chip 170A may be individually referred to as a control circuit, or a circuit group including some or all of the source driver circuit 110, the gate driver circuit 120A, the light emission control circuit 130A, and the IC chip 170A may be referred to as a control circuit.

[0119] Since the self-emission type display device 10A includes a configuration in which the first gate driver circuit 120 and the second gate driver circuit 190 are combined into the gate driver circuit 120A, and a configuration in which the first light emission control circuit 130 and the second light emission control circuit 140 are combined into the light emission control circuit 130A, by using the self-emission type display device 10A, a display device with a narrow frame area can be provided. Also, compared to a configuration that does not use the self-emission type display device 10A, the circuit configuration of the pixel circuit can be simplified, and the wiring structure such as the routing of the wiring used for the gate electrodes of each transistor can be simplified. As a result, the parasitic capacitance and resistance associated with the routing of the wiring can be reduced. Therefore, the power associated with the charging of the parasitic capacitance and resistance can be reduced. Thus, by using the self-emission type display device 10A, the power consumption of the display device can be suppressed compared to a configuration that does not use the self-emission type display device 10A.

[0120] <2-2. Configuration of Gate Driver Circuit 120A> Referring to FIG. 15, the outline of the gate driver circuit 120A will be described. As shown in FIG. 15, the gate driver circuit 120A is provided at a position adjacent to the display area 22 in the second direction D2 (row direction). The gate driver circuit 120A has a configuration and functions that combine the first gate driver circuit 120 and the second gate driver circuit 190, and the scanning signal lines 369, 370, 371, 372, and 373 extend from the gate driver circuit 120A in the second direction D2 and are connected to a plurality of pixels 180 arranged in the second direction D2.

[0121] As shown in FIG. 15, the gate driver circuit 120A includes a plurality of shift registers (for example, shift registers 121A, 122A, and 123A). The shift registers 121A, 122A, and 123A sequentially supply scanning signals with different timings (for example, scanning signal G(n−1), scanning signal G(n), scanning signal G(n + 1), etc.) to each of the scanning signal lines 369, 370, 371, 372, and 373 based on control signals such as a clock signal and a start pulse supplied from the IC chip 170, and have a role of driving the pixel 180 (pixel circuit 182) electrically connected to each scanning signal line. The scanning signal G(n) may be called a first control signal, the scanning signal G(n + 1) may be called a second control signal, and the scanning signal G(n−1) may be called a third control signal.

[0122] For example, the shift register 121A is electrically connected to the shift register 122A, and the shift register 122A is electrically connected to the shift register 123A. The shift register 121A is electrically connected to the scanning signal line 369 and supplies, for example, the scanning signal G(n−1) to the scanning signal line 369. Similar to the shift register 121A, the shift register 122A is electrically connected to the scanning signal line 370 and supplies, for example, the scanning signal G(n) to the scanning signal line 370, and the shift register 123A is electrically connected to the scanning signal line 371 and supplies, for example, the scanning signal G(n + 1) to the scanning signal line 371. Although not shown, the next-stage shift register electrically connected to the shift register 123A is electrically connected to the scanning signal line 372, and the shift registers of the subsequent stages electrically connected to the next-stage shift register are electrically connected to the scanning signal line 373.

[0123] The scanning signal G(n) includes a pulse width equivalent to that of the scanning signal G(n−1) and is a signal obtained by shifting the scanning signal G(n−1). The scanning signal G(n+1) includes a pulse width equivalent to that of the scanning signal G(n) and is a signal obtained by shifting the scanning signal G(n). Similarly to the scanning signal G(n+1), the scanning signal G(n+2) includes a pulse width equivalent to that of the scanning signal G(n+1) and is a signal obtained by shifting the scanning signal G(n+1). Further, the scanning signal G(n−1) is a signal output at the same timing as the scanning signal GF(n−1) supplied from the shift register 121 of the first gate driver circuit 120 according to the first embodiment, the scanning signal G(n) is a signal output at the same timing as the scanning signal GF(n) supplied from the shift register 122 of the first gate driver circuit 120 according to the first embodiment, and the scanning signal G(n+1) is a signal output at the same timing as the scanning signal GS(n+1) supplied from the shift register 191 of the second gate driver circuit 190 according to the first embodiment.

[0124] <2-3. Configuration of the Light Emission Control Circuit 130A> Referring to FIG. 15, the outline of the light emission control circuit 130A will be described. The light emission control circuit 130A is adjacent to the display area 22 (FIG. 1) where a plurality of pixels 180 are arranged in the second direction D2 (row direction), and is provided on the side opposite to the position where the first gate driver circuit 120 is arranged with respect to the display area 22. The light emission control circuit 130A has a configuration and functions combining the first light emission control circuit 130 and the second light emission control circuit 140. The light emission control signal lines 334A, 335A, and 336A extend from the light emission control circuit 130A in the second direction D2 and are connected to a plurality of pixels 180 (pixel circuits 182) arranged in the second direction D2.

[0125] The light emission control circuit 130A includes a plurality of shift registers (for example, shift registers 131A, 132A, and 133A). Similar to the shift registers 131, 132, and 133, the shift registers 131A, 132A, and 133A supply, based on control signals such as a clock signal and a start pulse supplied from the IC chip 170A, light emission control signals with different timings (for example, light emission control signal EM(n), light emission control signal EM(n + 1), light emission control signal EM(n + 2)) to the respective light emission control signal lines 334A, 335A, and 336A in sequence, and have the role of driving the pixel 180 (pixel circuit 182) electrically connected to each light emission control signal line.

[0126] For example, the shift register 131A is electrically connected to the shift register 132A, and the shift register 132A is electrically connected to the shift register 133A. The shift register 131A is electrically connected to the light emission control signal line 334A and supplies, for example, the light emission control signal EM(n) to the light emission control signal line 334A. Similar to the shift register 131A, the shift register 132A is electrically connected to the light emission control signal line 335A and supplies, for example, the light emission control signal EM(n + 1) to the light emission control signal line 335A, and the shift register 133A is electrically connected to the light emission control signal line 336A and supplies, for example, the light emission control signal EM(n + 2) to the light emission control signal line 336A. The pulse width of the light emission control signal EM(n + 1) is the same as that of the light emission control signal EM(n), and the light emission control signal EM(n + 1) is a signal obtained by shifting the light emission control signal EM(n). Similarly, the pulse width of the light emission control signal EM(n + 2) is the same as that of the light emission control signal EM(n + 1), and the light emission control signal EM(n + 2) is a signal obtained by shifting the light emission control signal EM(n + 2).

[0127] <2-4. Configuration of Pixel 180> Referring to FIGS. 16 and 17, the outline of pixel 180 will be described. FIG. 16 is a schematic diagram showing input signals to pixel circuit 182 included in pixel 180. FIG. 17 is a circuit diagram showing the configuration of pixel circuit 182. FIGS. 16 and 17 show, as an example, the configuration of pixel circuit 182 of pixel 180 shown in FIG. 15. The configurations of pixel 180 and pixel circuit 182 are not limited to the configurations shown in FIGS. 16 and 17. For configurations identical or similar to those in FIGS. 1 to 15, the description here will be omitted.

[0128] Pixel circuit 182 is a circuit for driving pixel 180 in the same manner as pixel circuit 181 and has the same configuration and function as pixel circuit 181. In the description of pixel circuit 182, mainly the differences from pixel circuit 181 will be described.

[0129] As shown in FIG. 16, instead of emission control signals EF(n) and ES(n), an emission control signal EM is supplied to pixel circuit 182. For example, the emission control signal EM is supplied to emission control signal line 334A.

[0130] As shown in FIG. 17, pixel circuit 182 includes, in the same manner as pixel circuit 181, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a capacitive element CS, and a light-emitting element OLED. As described above, the sixth transistor T6 is a p-channel type field-effect transistor.

[0131] The gate electrode 642 of the fourth transistor T4, the gate electrode 652 of the fifth transistor T5, and the gate electrode 662 of the sixth transistor T6 are electrically connected to the light emission control signal line 334A. A light emission control signal EM(n) is supplied to the light emission control signal line 334A. The fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are controlled to be in a conductive state or a non-conductive state by the light emission control signal EM(n). When the signal supplied to the light emission control signal EM(n) is low (LO), the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are in a non-conductive state. When the signal supplied to the light emission control signal EM(n) is high (HI), the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are in a conductive state.

[0132] Each transistor shown in FIG. 17 can have a Group 14 element such as silicon or germanium, or an oxide exhibiting semiconductor characteristics, in the channel region, similar to the first embodiment. For example, the channel region of each transistor has low-temperature polysilicon (LTPS). In the self-emission type display device 10A, each transistor is formed using a thin film transistor (TFT), and each transistor except the sixth transistor T6 has an n-channel type field effect transistor. Similar to the self-emission type display device 10, the self-emission type display device 10A may appropriately adapt the configuration of the transistor, the connection of the holding capacitance, the power supply voltage, etc., according to the application and specifications.

[0133] <2-5. Driving Method of Self-Emission Type Display Device 10A> Referring to FIGS. 18 to 26, a driving method of the self-luminous display device 10A will be described. FIGS. 18 and 25 are schematic diagrams showing the timing charts of the self-luminous display device 10A. FIGS. 19 to 24 are schematic diagrams showing the operating states of the pixel 180 (pixel circuit 182) at the timing shown in FIG. 18. FIG. 26 is a schematic diagram showing the operating state of the pixel 180 (pixel circuit 182) at the timing shown in FIG. 25. For the configurations identical or similar to those in FIGS. 1 to 17, the description here will be omitted. Note that the driving method of the self-luminous display device 10A is executed based on the timing charts of FIGS. 5(A) and 5(B) in the same manner as the driving method of the self-luminous display device 10. The horizontal axis of the timing chart is time (TIME).

[0134] Referring to FIGS. 18 to 24, an example of a driving method in which the pixel 180 (pixel circuit 182) displays an image based on the voltage RDATA(n) included in the data signal VDATA input during one horizontal period NthHP will be described. Note that, similar to the first embodiment, in the description of the driving method according to the second embodiment, as an example, the driving voltage VDDEL or the driving voltage VDDELL is supplied to the driving power supply line PVDD, and the reference voltage VSSEL is supplied to the reference voltage line PVSS.

[0135] Since the driving methods related to the data signal VDATA, the selection signal MUXR, the selection signal MUXG, and the selection signal MUXB are the same as those in the first embodiment, the description here will be omitted.

[0136] Next, referring to FIGS. 18 and 19, a driving method of the pixel 180 (pixel circuit 182) during the light emission period PEM of the frame one frame before the current frame (K-1stFRAME) will be described. The light emission period PEM of the frame one frame before the current frame (K-1stFRAME) is a period during which the pixel 180 (pixel circuit 182) emits light according to the voltage RDATA(n-1).

[0137] The gate electrode 622 of the second transistor T2 is supplied with the voltage RDATA(n - 1). The scan signals G(n - 1), G(n), and G(n + 1) are supplied with LOW (LO), and the first transistor T1, the third transistor T3, and the seventh transistor T7 are in the OFF state. Also, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are supplied with HIGH (HI) from the emission control signal EM(n), the fourth transistor T4 and the fifth transistor T5 are in the ON state, and the sixth transistor T6 is in the OFF state.

[0138] The second transistor T2 is in the ON state based on the voltage RDATA(n - 1). As a result, the second transistor T2 can pass a current IELA based on the gate-source voltage Vgs and the source-drain voltage Vds corresponding to the voltage RDATA(n - 1).

[0139] The fourth transistor T4, the second transistor T2, and the fifth transistor T5 are in the ON state, and the current IELA flows from the driving power supply line PVDD to the reference voltage line PVSS. As a result, the current IELA flows through the light-emitting element OLED, and the light-emitting element OLED emits light.

[0140] Next, referring to FIG. 18, a method of driving the pixel 180 (pixel circuit 182) during the period between the light emission period PEM of the frame one before the current frame (K - 1st FRAME) and the reset period PRS of the current frame will be described. During this period, the emission control signal EM(n) is supplied with LOW (LO) from HIGH (HI), the fifth transistor T5 and the fourth transistor T4 are in the OFF state, and the sixth transistor T6 is in the ON state. Also, the scan signal G(n - 1) is supplied with HIGH (HI) from LOW (LO), and the seventh transistor T7 is in the ON state. The first transistor T1 and the third transistor T3 remain in the OFF state.

[0141] Based on the sixth transistor T6 being turned on, an initialization voltage VINI is supplied to the first electrode 692 of the capacitive element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. As a result, the first electrode 692 of the capacitive element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED are initialized. Also, the fourth transistor T4 and the fifth transistor T5 are in the off state, no current flows from the drive power supply line PVDD to the reference voltage line PVSS, and a current IINI flows from the initialization voltage line VM to the reference voltage line PVSS. The current IINI flowing through the light-emitting element OLED is a current (substantially 0) corresponding to the potential difference (voltage RDATAB - reference voltage VSSEL) between the voltage of the second electrode 684 of the light-emitting element OLED and the voltage of the first electrode 682, and the light-emitting element OLED is non-emitting (not emitting light).

[0142] Next, with reference to FIGS. 18 and 20, a method of driving the pixel 180 (pixel circuit 182) during the reset period PRS of this frame will be described.

[0143] During the reset period PRS, the scan signal G(n) is supplied from low (LO) to high (HI), and the third transistor T3 is in the on state. Also, the sixth transistor T6 and the seventh transistor T7 remain in the on state, and the first transistor T1, the fourth transistor T4, and the fifth transistor T5 remain in the off state.

[0144] Based on the seventh transistor T7 and the third transistor T3 being turned on, a reset voltage VSH is supplied to the first node N1, the second node N2, each electrode electrically connected to the first node N1, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitive element CS. As a result, the first node N1, the second node N2, each electrode electrically connected to the first node N1, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitive element CS are reset. Also, since the sixth transistor T6 remains in the on state, the first electrode 692 of the capacitive element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED are maintained at the initialization voltage VINI. Further, since the fourth transistor T4 and the fifth transistor T5 remain in the off state, no current flows from the drive power supply line PVDD to the reference voltage line PVSS, and a current IINI flows from the initialization voltage line VM to the reference voltage line PVSS. The current IINI flowing through the light-emitting element OLED is, as described above, approximately 0, and the light-emitting element OLED is non-emitting (not emitting light).

[0145] Although detailed illustration is omitted, the second transistor T2 shown in FIG. 20 is in the on state, but when the potential difference between the gate electrode 622 and the first electrode 624 of the second transistor T2 (the potential difference between the gate electrode 622 and the first node N1) becomes equal to the threshold voltage Vth of the second transistor T2, the second transistor T2 becomes in the off state.

[0146] Next, referring to FIGS. 18 and 21, a driving method of pixel 180 (pixel circuit 182) during the period between the reset period PRS and the sampling period PWR of the frame will be described. In the driving method of pixel 180 (pixel circuit 182) during the period between the reset period PRS and the sampling period PWR of the frame, except that the emission control signal EM(n) is supplied and the sixth transistor T6 is a p-channel field effect transistor, the configuration, each signal, the state of each transistor, etc. are the same as those in the driving method of pixel 180 (pixel circuit 181) during the period between the reset period PRS and the sampling period PWR of the frame in the first embodiment (see FIGS. 6 and 9). Therefore, a detailed description here of the driving method of pixel 180 (pixel circuit 182) during the period between the reset period PRS and the sampling period PWR of the frame is omitted. Note that also during the period between the reset period PRS and the sampling period PWR of the frame, as described above, the current IINI flows from the initialization voltage line VM to the reference voltage line PVSS. The current IINI flowing through the light emitting element OLED is almost 0, and the light emitting element OLED is non-emitting (not emitting light).

[0147] Next, referring to FIGS. 18 and 22, a driving method of pixel 180 (pixel circuit 182) during the sampling period PWR of the frame will be described. In the driving method of pixel 180 (pixel circuit 182) during the sampling period PWR of the frame, except that the emission control signal EM(n) is supplied and the sixth transistor T6 is a p-channel field effect transistor, the configuration, each signal, the state of each transistor, etc. are the same as those in the driving method of pixel 180 (pixel circuit 181) during the sampling period PWR of the frame in the first embodiment (see FIGS. 6 and 10). Therefore, a detailed description here of the driving method of pixel 180 (pixel circuit 182) during the sampling period PWR of the frame is omitted. Note that similar to the period between the reset period PRS and the sampling period PWR of the frame, also during the sampling period PWR of the frame, the current IINI flows from the initialization voltage line VM to the reference voltage line PVSS. The current IINI flowing through the light emitting element OLED is almost 0, and the light emitting element OLED is non-emitting (not emitting light).

[0148] Next, with reference to FIGS. 18 and 23, a method for driving pixel 180 (pixel circuit 182) after the sampling period PWR of the frame will be described.

[0149] In the period after the sampling period PWR of the frame, the scanning signal G(n) is supplied from high (HI) to low (LO), and the third transistor T3 is in the off state. Also, the first transistor T1 and the sixth transistor T6 remain in the on state, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 remain in the off state. A high (HI) is supplied to the scanning signal G(n + 1), and the first transistor T1 is in the on state. Therefore, the voltage of the first electrode 614 and the voltage of the second electrode 616 of the first transistor T1 are the voltage RDATA(n). That is, the voltage of the first electrode 614 and the voltage of the second electrode 616 of the first transistor T1 are the same. Therefore, no current flows through the first transistor T1.

[0150] Since the first transistor T1 is in the on state and the second transistor T2, the third transistor T3, and the seventh transistor T7 are in the off state, the voltage RDATA(n) is supplied to the first node N1 and each electrode electrically connected to the first node N1. When the voltage RDATA(n) is supplied to the first node N1, the voltage between the gate and source of the second transistor T2 also changes, and the second transistor T2 becomes in the on state. As a result, the voltages of the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor element CS drop from the voltage VSH and become the voltage RDATA(n) + threshold voltage Vth (RDATA(n) + Vth). Thus, the potential difference between the gate electrode 622 and the first electrode 624 of the second transistor T2 becomes the same as the threshold voltage Vth of the second transistor T2, the voltage drop of the second node N2 and the like ends, and the second transistor T2 becomes in the off state. Also, since the sixth transistor T6 is in the on state, the initialization voltage VINI is supplied to the first electrode 692 of the capacitor element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. Similar to the sampling period PWR of this frame, even in the period after the sampling period PWR of this frame, the current IINI flows from the initialization voltage line VM to the reference voltage line PVSS. The current IINI flowing through the light-emitting element OLED is almost 0, and the light-emitting element OLED is non-luminous (not emitting light).

[0151] As shown in FIG. 18, the scan signal G(n) is supplied from high (HI) to low (LO). After the third transistor T3 becomes in the off state, the scan signal G(n + 1) is supplied from high (HI) to low (LO), and the first transistor T1 becomes in the off state.

[0152] At this time, since the first transistor T1 is in the off state, the voltage RDATA(n) is held at the first node N1 and the voltages of the respective electrodes electrically connected to the first node N1. Also, since the second transistor T1, the third transistor T3, and the seventh transistor T7 are in the off state, the voltage RDATA(n) + threshold voltage Vth (RDATA(n) + Vth) is held at the second node N2, the respective electrodes electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor element CS. Further, since the sixth transistor T6 is in the on state, the initialization voltage VINI is supplied to the first electrode 692 of the capacitor element CS, the respective electrodes electrically connected to the first electrode 692, and the second electrode 684 of the light-emitting element OLED. Therefore, following the period after the sampling period PWR of the frame, a current IINI flows from the initialization voltage line VM to the reference voltage line PVSS. The current IINI flowing through the light-emitting element OLED is almost zero, and the light-emitting element OLED is non-emitting (not emitting light).

[0153] Next, with reference to FIGS. 18 and 24, a method of driving the pixel 180 (pixel circuit 182) during the light-emitting period PEM of the frame will be described.

[0154] As shown in FIGS. 18 and 24, the scan signals G(n - 1), G(n), and G(n + 1) are supplied with a low (LO), and the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are in the off state. Also, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are supplied with a high (HI) from the light emission control signal EM(n), the fourth transistor T4 and the fifth transistor T5 are in the on state, and the sixth transistor T6 is in the off state.

[0155] Similar to the content described with reference to FIG. 11, the voltage held by the second electrode 656 of the fifth transistor T5 is RDATA(n), and the voltage held by the first electrode 654 of the fifth transistor T5 is the initialization voltage VINI. When the fifth transistor T5 turns on from the state where the voltage of the second electrode 656 and the voltage of the first electrode 654 of the fifth transistor T5 are the voltage RDATA(n) (RDATA(n)) and the initialization voltage VINI (VINI), similar to the content described with reference to FIG. 11, a current flows from the second electrode 656 to the first electrode 654 of the fifth transistor T5, charge redistribution occurs, and the voltages of the second electrode 656 and the first electrode 654 become the initialization voltage VINI (VINI). Other operations are also the same as those described with reference to FIG. 11.

[0156] As shown in FIGS. 18 and 24, a driving method similar to the driving method of the pixel 180 (pixel circuit 181) during the light emission period PEM of the frame described with reference to FIGS. 6, 11, and 12 of the first embodiment is executed in the driving method of the second embodiment. Therefore, a detailed description of the driving method of the pixel 180 (pixel circuit 182) during the light emission period PEM of the frame according to the second embodiment is omitted.

[0157] Briefly, similar to the driving method of the pixel 180 (pixel circuit 181) during the light emission period PEM of the frame of the first embodiment, also during the light emission period PEM of the frame according to the second embodiment, since the gate-source voltage between the gate electrode 622 and the first electrode 624 of the second transistor T2 is higher than the threshold voltage Vth of the second transistor T2, the second transistor T2 is turned on. The fourth transistor T4, the second transistor T2, and the fifth transistor T5 are turned on, and a current IELA flows from the driving power supply line PVDD to the reference voltage line PVSS. As a result, the current IELA flows through the light emitting element OLED, and the light emitting element OLED emits light.

[0158] As described above, in the self-emitting display device 10A according to the second embodiment, based on the fact that the sixth transistor T6 is a p-channel field effect transistor, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be controlled at the same timing based on a common one light emission control signal EM. That is, the pixel circuit 182 can be controlled using one light emission control circuit (light emission control circuit 130A), and the light emission of the pixel 180 can be controlled. Also, similar to one light emission control circuit (light emission control circuit 130A), the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be controlled using a shift pulse output by a common one gate driver circuit. Therefore, since the circuit configuration of the self-emitting display device 10A can be simplified compared to a self-emitting display device in which the sixth transistor T6 is not a p-channel transistor, the manufacturing cost of the self-emitting display device 10A can be reduced.

[0159] Next, with reference to FIGS. 25 and 26, an example of a driving method in which the pixel 180 (pixel circuit 182) displays black based on a voltage RDATAB supplied from the initialization voltage line VM will be described. Similar to the first embodiment, in low-frequency driving, the driving other than the black period PBWR is the same as that in high-frequency driving. Therefore, mainly, the driving of the pixel 180 (pixel circuit 182) during the black period PBWR will be described here. For configurations identical or similar to those in FIGS. 1 to 24, the description here will be omitted. Note that the horizontal axis of the timing chart is time (TIME).

[0160] First, since the data signal VDATA, the selection signal MUXR, the selection signal MUXG, and the selection signal MUXB are the same as those described with reference to FIG. 6 of the first embodiment, the description here will be omitted.

[0161] The driving method of pixel 180 (pixel circuit 182) during the light emission period PEM of the frame immediately preceding the current frame (K-1st FRAME) is the same as the driving method described with reference to FIGS. 1 to 5(A), FIGS. 18 to 24 of the first embodiment. Therefore, the description here is omitted. Note that the voltages of the first node N1, the first electrode 654 of the fifth transistor T5, and the second electrode 684 of the light emitting element OLED during the light emission period PEM of the frame immediately preceding the current frame (K-1st FRAME) are voltages between the voltage VDL and the voltage VDH.

[0162] Next, the driving method of pixel 180 (pixel circuit 182) during the black period PBWR that is executed following the light emission period PEM of the frame immediately preceding the current frame (K-1st FRAME) will be described. The black period PBWR of the current frame is a period that overlaps with a part of one horizontal period N-2nd HP, one horizontal period N-1st HP, one horizontal period Nth HP, one horizontal period N+1st HP, and a part of one horizontal period N+2nd HP.

[0163] The scan signal G(n-1), the scan signal G(n), the scan signal G(n+1), and the light emission control signal EM(n) are supplied with low (LO). The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are in the off state, and the sixth transistor T6 is in the on state.

[0164] Since the sixth transistor T6 is in the on state, the voltage RDATAB is supplied to the first electrode 692 of the capacitive element CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light emitting element OLED. Therefore, the current IRB flows from the initialization voltage line VM to the reference voltage line PVSS. The current IRB flowing through the light emitting element OLED is a current for displaying black based on the voltage RDATAB, and the light emitting element OLED hardly emits light (is not emitting light). Therefore, pixel 180 displays black.

[0165] The driving method of pixel 180 (pixel circuit 182) during the light emission period PEM of frame (Kth FRAME) is the same as that of pixel 180 (pixel circuit 182) during the light emission period PEM of the frame immediately preceding this frame (K - 1st FRAME). Therefore, the description here is omitted. Note that the voltages of the first node N1, the first electrode 654 of the fifth transistor T5, and the second electrode 684 of the light emitting element OLED during the light emission period PEM of this frame (Kth FRAME) are voltages between voltage VDL and voltage VDH.

[0166] During the black period PBWR of the self - emissive display device 10A, by supplying voltage RDATAB from the initialization voltage line VM to the second electrode 684 of the light emitting element OLED, the self - emissive display device 10A can display black. As a result, the self - emissive display device 10A can adjust flicker.

[0167] Also, during the black period PBWR of the self - emissive display device 10A, since it is not necessary to supply data for displaying black from the image data signal line 321 to the first node N1 via the first transistor T1, it is not necessary to drive the fifth transistor T5 electrically connected to the first node N1 using the light emission control signal EM. Therefore, during the black period PBWR of the self - emissive display device 10A, since it is not necessary to drive the light emission control circuit 130A, it is possible to simplify the driving method of the self - emissive display device 10A and reduce the power consumption of the self - emissive display device 10A.

[0168] <3. Third Embodiment> Referring to FIGS. 27 to 29, the pixel circuit 183 according to the third embodiment will be described. In the pixel circuit 183, the polarities of the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are opposite to those of the pixel circuit 182. Specifically, in the pixel circuit 182, the fourth transistor T4 and the fifth transistor T5 are n-channel field-effect transistors, and the sixth transistor T6 is a p-channel field-effect transistor, while in the pixel circuit 183, the fourth transistor T4 and the fifth transistor T5 are p-channel field-effect transistors, and the sixth transistor T6 is an n-channel field-effect transistor. The configuration other than the transistor polarities is the same as that of the self-emitting display device 10A and the pixel circuit 182. The pixel circuit 183 shown in FIGS. 27 to 29 is an example, and the pixel circuit 183 is not limited to the example shown in FIGS. 27 to 29. The description of the configurations that are the same as or similar to those of the self-emitting display devices 10 and 10A described in the first and second embodiments, and the configurations that are the same as or similar to those in FIGS. 1 to 26 will be omitted here.

[0169] Referring to FIG. 27, the outline of the pixel circuit 183 will be described. FIG. 27 is a circuit diagram showing the configuration of the pixel circuit 183.

[0170] The pixel circuit 183 is a circuit for driving the pixel 180, similar to the pixel circuit 181 and the pixel circuit 182. As described above, the pixel circuit 183 differs from the pixel circuit 182 in that the fourth transistor T4 and the fifth transistor T5 are p-channel field-effect transistors, and the sixth transistor T6 is an n-channel field-effect transistor.

[0171] Referring to FIGS. 27 to 29, a driving method of the pixel 180 (pixel circuit 183) will be described. FIG. 28 is a diagram for explaining a reset period PRS, a sampling period PWR, and a light emission period PEM of the driving method of the self-luminous display device 10A (pixel 180 (pixel circuit 183)). FIG. 29 is a diagram for explaining a black period PBWR of the driving method of the self-luminous display device 10A (pixel 180 (pixel circuit 183)).

[0172] In the pixel circuit 183 according to the third embodiment, since the fourth transistor T4 and the fifth transistor T5 are p-channel field-effect transistors, and the transistor of the sixth transistor T6 is an n-channel field-effect transistor, the light emission control signal EM(n) is inverted with respect to the pixel circuit 182 according to the second embodiment.

[0173] As shown in FIGS. 28 and 29, in the driving method of the pixel 180 (pixel circuit 183) during the light emission period PEM of the frame one frame before the current frame (K-1st FRAME) and the light emission period PEM of the current frame (Kth FRAME), the light emission control signal EM(n) is supplied with low (LO). Therefore, the fourth transistor T4 and the fifth transistor T5 shown in FIG. 27 are in the on state, and the sixth transistor T6 shown in FIG. 27 is in the off state.

[0174] As shown in FIGS. 28 and 29, in the driving method of the pixel 180 (pixel circuit 183) during the period between the light emission period PEM of the frame one frame before the current frame (K-1st FRAME) and the light emission period PEM of the current frame (Kth FRAME), the light emission control signal EM(n) is supplied with high (HI or HIL). Therefore, the fourth transistor T4 and the fifth transistor T5 shown in FIG. 27 are in the off state, and the sixth transistor T6 shown in FIG. 27 is in the on state.

[0175] In the driving method of the self-emission type display device 10A (pixel 180 (pixel circuit 183)) according to the third embodiment, the configuration other than the light emission control signal EM(n), each signal, the state of each transistor, etc. are the same as the configuration, function, and driving method of the self-emission type display device 10A described with reference to FIGS. 15 to 26 of the second embodiment. Therefore, the description here is omitted.

[0176] For example, in the light emission period PEM of the Kth FRAME, since the fifth transistor T5 is a p-channel type field effect transistor, the light emission control signal EM(n) is supplied with a change from HI to LO. In the pixel circuit 183, since the light emission control signal EM(n) is supplied with a change from HI to LO, the increase in the voltage of the anode electrode due to the coupling between the light emission control signal line 334A and the second electrode 684 (anode electrode) of the light emitting element OLED can be suppressed compared to the case where the light emission control signal EM(n) is supplied with a change from LO to HI. When the voltage of the anode electrode increases, a larger current flows through the light emitting element OLED than when the pixel 180 displays black, making it difficult for the pixel 180 to display black. On the other hand, in the self-emission type display device 10A (pixel 180 (pixel circuit 183)) according to the third embodiment, since the increase in the voltage of the anode electrode can be suppressed, the margin when displaying black can be increased.

[0177] Also, in the driving method of the self-emission type display device 10A (pixel 180 (pixel circuit 183)) according to the third embodiment, since the fourth transistor T4 is a p-channel type field effect transistor, the high voltage of the light emission control signal EM(n) can be reduced from HI to HIL which is lower than HI. As a result, since the voltage supplied to the gate electrode 642 of the fourth transistor T4 can be reduced, the power consumption of the self-emission type display device 10A can be reduced.

[0178] <4. Fourth Embodiment> Referring to FIGS. 30 to 43, an example of a manufacturing method, electrical characteristics, and a pixel circuit of a semiconductor device 40 used in an organic light-emitting display device according to a fourth embodiment will be described. FIGS. 30 and 31 are a cross-sectional view and a plan view showing an outline of a semiconductor device 40 used in an organic light-emitting display device according to an embodiment of the present invention. FIG. 32 is a sequence diagram showing a manufacturing method of the semiconductor device 40. FIGS. 33 to 41 are cross-sectional views showing a manufacturing method of the semiconductor device 40. FIG. 42 is a graph showing an example of electrical characteristics of the semiconductor device 40 and an example of electrical characteristics of a semiconductor device of a comparative example. FIG. 43 is a schematic diagram showing a configuration of a pixel circuit using the semiconductor device 40. Descriptions of configurations identical or similar to those in FIGS. 1 to 29 are omitted here.

[0179] In the description of the fourth embodiment, the direction from the substrate toward the oxide semiconductor layer is referred to as up or upward, and the direction from the oxide semiconductor layer toward the substrate is referred to as down or downward. Also, in the description of the fourth embodiment, for example, the substrate and the oxide semiconductor layer may be arranged so that their positions are reversed up and down. The expression "oxide semiconductor layer on the substrate" merely explains the vertical relationship between the substrate and the oxide semiconductor layer, and other members may be arranged between the substrate and the oxide semiconductor layer. The expressions "upward" or "downward" mean the stacking order in a structure in which a plurality of layers are stacked. For example, when referring to a pixel electrode above a transistor, in a plan view, the positional relationship between the transistor and the pixel electrode may be a non-overlapping positional relationship. On the other hand, when referring to a pixel electrode directly above a transistor in the vertical direction, in a plan view, it means a positional relationship in which the transistor and the pixel electrode overlap.

[0180] <4-1. Configuration of Semiconductor Device 40> As shown in FIG. 30, the semiconductor device 40 is provided above a substrate 400. The semiconductor device 40 includes a gate electrode 405, gate insulating layers 410, 420, a metal oxide layer 430, an oxide semiconductor layer 440, a gate insulating layer 450, a gate electrode 460, insulating layers 470, 480, a source electrode 201, and a drain electrode 203. When the source electrode 201 and the drain electrode 203 are not particularly distinguished, they may be collectively referred to as a source-drain electrode 200.

[0181] The gate electrode 405 is provided on the substrate 400. The gate insulating layer 410 and the gate insulating layer 420 are provided on the substrate 400 and the gate electrode 405. The metal oxide layer 430 is provided on the gate insulating layer 420. The metal oxide layer 430 is in contact with the gate insulating layer 420. The oxide semiconductor layer 440 is provided on the metal oxide layer 430. The oxide semiconductor layer 440 is in contact with the metal oxide layer 430. Among the main surfaces of the oxide semiconductor layer 440, the surface in contact with the metal oxide layer 430 is referred to as the lower surface 442. The end of the metal oxide layer 430 and the end of the oxide semiconductor layer 440 substantially coincide.

[0182] In the fourth embodiment, no semiconductor layer or oxide semiconductor layer is provided between the metal oxide layer 430 and the substrate 400.

[0183] In the fourth embodiment, a configuration in which the metal oxide layer 430 is in contact with the gate insulating layer 420 and the oxide semiconductor layer 440 is in contact with the metal oxide layer 430 is illustrated, but the present invention is not limited to this configuration. Another layer may be provided between the gate insulating layer 420 and the metal oxide layer 430. Another layer may be provided between the metal oxide layer 430 and the oxide semiconductor layer 440.

[0184] In FIG. 30, the side wall of the metal oxide layer 430 and the side wall of the oxide semiconductor layer 440 are aligned in a straight line, but the present invention is not limited to this configuration. The angle of the side wall of the metal oxide layer 430 with respect to the main surface of the substrate 400 may be different from the angle of the side wall of the oxide semiconductor layer 440. The cross-sectional shape of the side wall of at least one of the metal oxide layer 430 and the oxide semiconductor layer 440 may be curved.

[0185] The gate electrode 460 faces the oxide semiconductor layer 440. The gate insulating layer 450 is provided between the oxide semiconductor layer 440 and the gate electrode 460. The gate insulating layer 450 is in contact with the oxide semiconductor layer 440. Of the main surfaces of the oxide semiconductor layer 440, the surface in contact with the gate insulating layer 450 is referred to as the upper surface 441. The surface between the upper surface 441 and the lower surface 442 is referred to as the side surface 443. The insulating layers 470 and 480 are provided over the gate insulating layer 450 and the gate electrode 460. The insulating layers 470 and 480 are provided with openings 471 and 473 that reach the oxide semiconductor layer 440. The source electrode 201 is provided inside the opening 471. The source electrode 201 is in contact with the oxide semiconductor layer 440 at the bottom of the opening 471. The drain electrode 203 is provided inside the opening 473. The drain electrode 203 is in contact with the oxide semiconductor layer 440 at the bottom of the opening 473.

[0186] The gate electrode 405 has a function as a bottom gate of the semiconductor device 40 and a function as a light-shielding film for the oxide semiconductor layer 440. The gate insulating layer 410 has a function as a barrier film that shields impurities diffusing from the substrate 400 toward the oxide semiconductor layer 440. The gate insulating layers 410 and 420 have a function as a gate insulating layer for the bottom gate. The metal oxide layer 430 is a layer containing a metal oxide mainly composed of aluminum and has a function as a gas barrier film that shields gases such as oxygen and hydrogen.

[0187] The oxide semiconductor layer 440 is divided into a source region S, a drain region D, and a channel region CH. The channel region CH is the region directly below the gate electrode 460 in the oxide semiconductor layer 440. The source region S is a region in the oxide semiconductor layer 440 that does not overlap with the gate electrode 460 and is closer to the source electrode 201 than the channel region CH. The drain region D is a region in the oxide semiconductor layer 440 that does not overlap with the gate electrode 460 and is closer to the drain electrode 203 than the channel region CH. The oxide semiconductor layer 440 in the channel region CH has physical properties as a semiconductor. The oxide semiconductor layer 440 in the source region S and the drain region D has physical properties as a conductor.

[0188] The gate electrode 460 functions as a top gate of the semiconductor device 40 and a light-shielding film for the oxide semiconductor layer 440. The gate insulating layer 450 functions as a gate insulating layer for the top gate and has a function of releasing oxygen by heat treatment in the manufacturing process. The insulating layers 470 and 480 insulate the gate electrode 460 from the source / drain electrodes 200 and have a function of reducing the parasitic capacitance therebetween. The operation of the semiconductor device 40 is mainly controlled by the voltage supplied to the gate electrode 460. An auxiliary voltage is supplied to the gate electrode 405. However, when the gate electrode 405 is simply used as a light-shielding film, no specific voltage needs to be supplied to the gate electrode 405, and it may be floating. That is, the gate electrode 405 may simply be called a "light-shielding film".

[0189] In the fourth embodiment, as the semiconductor device 40, a configuration in which a dual-gate transistor having gate electrodes provided above and below the oxide semiconductor layer is used is illustrated, but the present invention is not limited to this configuration. For example, as the semiconductor device 40, a bottom-gate transistor having a gate electrode provided only below the oxide semiconductor layer or a top-gate transistor having a gate electrode provided only above the oxide semiconductor layer may be used. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0190] As shown in FIG. 31, in a plan view, the planar pattern of the metal oxide layer 430 is substantially the same as the planar pattern of the oxide semiconductor layer 440. Referring to FIGS. 30 and 31, the lower surface 442 of the oxide semiconductor layer 440 is covered by the metal oxide layer 430. In particular, in the fourth embodiment, the entire lower surface 442 of the oxide semiconductor layer 440 is covered by the metal oxide layer 430. In the D1 direction, the width of the gate electrode 405 is larger than the width of the gate electrode 460. The D1 direction is the direction connecting the source electrode 201 and the drain electrode 203, and is the direction indicating the channel length L of the semiconductor device 40. Specifically, the length in the D1 direction of the region (channel region CH) where the oxide semiconductor layer 440 and the gate electrode 460 overlap is the channel length L, and the width in the D2 direction of the channel region CH is the channel width W.

[0191] In the fourth embodiment, a configuration in which the entire lower surface 442 of the oxide semiconductor layer 440 is covered by the metal oxide layer 430 is illustrated, but the present invention is not limited to this configuration. For example, a part of the lower surface 442 of the oxide semiconductor layer 440 may not be in contact with the metal oxide layer 430. For example, the entire lower surface 442 of the oxide semiconductor layer 440 in the channel region CH may be covered by the metal oxide layer 430, and all or part of the lower surface 442 of the oxide semiconductor layer 440 in the source region S and the drain region D may not be covered by the metal oxide layer 430. That is, all or part of the lower surface 442 of the oxide semiconductor layer 440 in the source region S and the drain region D may not be in contact with the metal oxide layer 430. However, in the above configuration, a part of the lower surface 442 of the oxide semiconductor layer 440 in the channel region CH may not be covered by the metal oxide layer 430, and the other part of the lower surface 442 may be in contact with the metal oxide layer 430.

[0192] In the fourth embodiment, although the configuration in which the gate insulating layer 450 is formed over the entire surface and openings 471 and 473 are provided in the gate insulating layer 450 is illustrated, the present invention is not limited to this configuration. The gate insulating layer 450 may be patterned into a shape different from the shape in which the openings 471 and 473 are provided. For example, the gate insulating layer 450 may be patterned so as to expose all or part of the oxide semiconductor layer 440 in the source region S and the drain region D. That is, the gate insulating layer 450 in the source region S and the drain region D may be removed, and the oxide semiconductor layer 440 and the insulating layer 470 may be in contact with each other in these regions.

[0193] In FIG. 31, a configuration in which the source / drain electrodes 200 do not overlap with the gate electrode 405 and the gate electrode 460 in a plan view is illustrated, but the present invention is not limited to this configuration. For example, in a plan view, the source / drain electrodes 200 may overlap with at least one of the gate electrode 405 and the gate electrode 460. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0194] <4-2. Materials of Members of Semiconductor Device 40> As the substrate 400, a rigid substrate having translucency such as a glass substrate, a quartz substrate, and a sapphire substrate is used. When the substrate 400 needs to have flexibility, a substrate containing a resin such as a polyimide substrate, an acrylic substrate, a siloxane substrate, and a fluororesin substrate is used as the substrate 400. When a substrate containing a resin is used as the substrate 400, impurities may be introduced into the above resin in order to improve the heat resistance of the substrate 400. In particular, when the semiconductor device 40 is used in a top emission type self-luminous display device, since the substrate 400 does not need to be transparent, impurities that deteriorate the transparency of the substrate 400 may be used.

[0195] As the gate electrodes 405, 460, and the source / drain electrodes 200, common metal materials are used. For example, as these members, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and their alloys or compounds are used. As the gate electrodes 405, 460, and the source / drain electrodes 200, the above materials may be used in a single layer or in a stacked layer.

[0196] As the gate insulating layers 410, 420 and the insulating layers 470, 480, common insulating materials are used. For example, as these insulating layers, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon nitride oxide (SiN x O y ), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), aluminum nitride oxide (AlN x O y ), aluminum nitride (AlN x ) and other inorganic insulating layers are used.

[0197] As the gate insulating layer 450, an insulating layer containing oxygen among the above insulating layers is used. For example, as the gate insulating layer 450, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ) and other inorganic insulating layers are used.

[0198] As the gate insulating layer 420, an insulating layer having a function of releasing oxygen by heat treatment is used. The temperature of the heat treatment for the gate insulating layer 420 to release oxygen is, for example, 600 °C or lower, 500 °C or lower, 450 °C or lower, or 400 °C or lower. That is, the gate insulating layer 420 releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 40 when a glass substrate is used as the substrate 400, for example.

[0199] As the gate insulating layer 450, an insulating layer with few defects is used. For example, when comparing the oxygen composition ratio in the gate insulating layer 450 with the oxygen composition ratio in an insulating layer having the same composition as the gate insulating layer 450 (hereinafter referred to as "other insulating layer"), the oxygen composition ratio in the gate insulating layer 450 is closer to the stoichiometric ratio with respect to the insulating layer than the oxygen composition ratio in the other insulating layer. Specifically, when silicon oxide (SiO x ) is used for each of the gate insulating layer 450 and the insulating layer 480, the oxygen composition ratio in the silicon oxide used as the gate insulating layer 450 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio in the silicon oxide used as the insulating layer 480. For example, as the gate insulating layer 450, a layer in which no defects are observed when evaluated by the electron spin resonance method (ESR) may be used.

[0200] The above SiO x N y and AlO x N y are silicon compounds and aluminum compounds containing nitrogen (N) in a ratio less than that of oxygen (O) (x > y). SiN x O y and AlN x O y are silicon compounds and aluminum compounds containing oxygen in a ratio less than that of nitrogen (x > y).

[0201] As the metal oxide layer 430 and the metal oxide layer 490 used in the manufacturing process as described later, a metal oxide mainly composed of aluminum is used. For example, as the metal oxide layer 430 (or the metal oxide layer 490), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), aluminum nitride oxide (AlN x O y ), aluminum nitride (AlN x ) and other inorganic insulating layers are used. The "metal oxide layer mainly composed of aluminum" means that the ratio of aluminum contained in the metal oxide layer 430 (or the metal oxide layer 490) is 1% or more of the entire metal oxide layer 430 (or the metal oxide layer 490). The ratio of aluminum contained in the metal oxide layer 430 (or the metal oxide layer 490) may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide layer 430. The above ratio may be a mass ratio or a weight ratio.

[0202] As the oxide semiconductor layer 440, a metal oxide having semiconductor characteristics can be used. 。

[0203] The oxide semiconductor layer 440 may be amorphous or crystalline. Also, the oxide semiconductor layer 440 may be a mixed phase of amorphous and crystal. 。 knot Crystalline oxide semiconductors are less likely to form oxygen deficiencies compared to amorphous oxide semiconductors. 。

[0204] <4-3. Problems newly recognized in the process leading to the present invention >

[0205] In the semiconductor device 40, in the heat treatment process of the manufacturing process, hydrogen is released from the layers (for example, gate insulating layers 410 and 420) provided on the substrate 400 side rather than the oxide semiconductor layer 440, and when the hydrogen reaches the oxide semiconductor layer 440, oxygen deficiency occurs in the oxide semiconductor layer 440. The occurrence of this oxygen deficiency is more prominent as the pattern size of the oxide semiconductor layer 440 is larger. In order to suppress the occurrence of such oxygen deficiency, it is necessary to suppress the reach of hydrogen to the lower surface 442 of the oxide semiconductor layer 440. The above content is the first problem.

[0206] Apart from the above problems, there is a second problem shown below. The upper surface 441 of the oxide semiconductor layer 440 is affected by the processes (for example, patterning process or etching process) after the oxide semiconductor layer 440 is formed. On the other hand, the lower surface 442 of the oxide semiconductor layer 440 (the surface on the substrate 400 side of the oxide semiconductor layer 440) is not affected by the above such influence.

[0207] Therefore, the oxygen deficiency formed on the upper surface 441 of the oxide semiconductor layer 440 is more than the oxygen deficiency formed on the lower surface 442 of the oxide semiconductor layer 440. That is, the oxygen deficiency in the oxide semiconductor layer 440 does not exist uniformly in the thickness direction of the oxide semiconductor layer 440, but exists in a non-uniform distribution in the thickness direction of the oxide semiconductor layer 440. Specifically, the oxygen deficiency in the oxide semiconductor layer 440 is less on the lower surface 442 side of the oxide semiconductor layer 440 and more on the upper surface 441 side of the oxide semiconductor layer 440.

[0208] When an oxygen supply process is uniformly performed on the oxide semiconductor layer 440 having the oxygen deficiency distribution as described above, if an amount of oxygen necessary for repairing the oxygen deficiency formed on the upper surface 441 side of the oxide semiconductor layer 440 is supplied, oxygen is excessively supplied to the lower surface 442 side of the oxide semiconductor layer 440. As a result, on the lower surface 442 side, defect levels different from oxygen deficiency are formed by the excessive oxygen, and phenomena such as characteristic variations in the reliability test or a decrease in the field-effect mobility occur. Therefore, in order to suppress such a phenomenon, it is necessary to supply oxygen to the upper surface 441 side of the oxide semiconductor layer 440 while suppressing the oxygen supply to the lower surface 442 side of the oxide semiconductor layer 440.

[0209] The above problems are problems newly recognized in the process leading to the present invention and are not problems conventionally recognized. In the conventional configuration and manufacturing method, even if the initial characteristics of the semiconductor device are improved by the oxygen supply process to the oxide semiconductor layer, there is a trade-off relationship between the initial characteristics and the reliability test in that characteristic variations occur in the reliability test. However, with the configuration according to the fourth embodiment, the above problems are solved, and good initial characteristics and reliability test results of the semiconductor device 40 can be obtained.

[0210] <4-4. Manufacturing Method of Semiconductor Device 40> The manufacturing method of the semiconductor device 40 will be described with reference to FIGS. 32 to 41. Here, an example of the manufacturing method of the semiconductor device 40 in which aluminum oxide is used as the metal oxide layers 430 and 490 will be described.

[0211] As shown in FIGS. 32 and 33, a gate electrode 405 is formed as a bottom gate on a substrate 400, and gate insulating layers 410 and 420 are formed on the gate electrode 405 ("Bottom GI / GE formation" in step S2001 of FIG. 32). As the gate insulating layer 410, for example, silicon nitride is formed. As the gate insulating layer 420, for example, silicon oxide is formed. The gate insulating layers 410 and 420 are formed by a CVD (Chemical Vapor Deposition) method. One or both of the gate insulating layers 410 and 420 may be referred to as the "first insulating layer".

[0212] By using silicon nitride as the gate insulating layer 410, the gate insulating layer 410 can block impurities that diffuse, for example, from the substrate 400 side toward the oxide semiconductor layer 440. The silicon oxide used as the gate insulating layer 420 is a silicon oxide having a physical property of releasing oxygen by heat treatment.

[0213] As shown in FIGS. 32 and 34, a metal oxide layer 430 and an oxide semiconductor layer 440 are formed on the gate insulating layer 420 ("OS / AlOx film formation" in step S2002 of FIG. 32). Regarding this step, it may be called forming the gate insulating layers 410 and 420 on the substrate 400 and forming the metal oxide layer 430 on the gate insulating layers 410 and 420. Or, it may be the case of forming the metal oxide layer 430 on the substrate 400 and forming the oxide semiconductor layer 440 on the metal oxide layer 430. Specifically, the oxide semiconductor layer 440 is formed so as to be in contact with the metal oxide layer 430. The metal oxide layer 430 and the oxide semiconductor layer 440 are formed by a sputtering method or an atomic layer deposition method (ALD: Atomic Layer Deposition).

[0214] The thickness of the metal oxide layer 430 is, for example, 1 nm or more and 100 nm or less, 1 nm or more and 50 nm or less, 1 nm or more and 30 nm or less, or 1 nm or more and 10 nm or less. In the fourth embodiment, aluminum oxide is used as the metal oxide layer 430. Aluminum oxide has a high barrier property against gases. In the fourth embodiment, the aluminum oxide used as the metal oxide layer 430 blocks hydrogen and oxygen released from the gate insulating layer 420 and suppresses the released hydrogen and oxygen from reaching the oxide semiconductor layer 440.

[0215] The thickness of the oxide semiconductor layer 440 is, for example, 10 nm or more and 100 nm or less, 15 nm or more and 70 nm or less, or 20 nm or more and 40 nm or less. 。

[0216] 。 strand When the oxide semiconductor layer 440 is formed by a patterning method, the oxide semiconductor layer 440 is formed while controlling the temperature of the object to be film-formed (the substrate 400 and the structures formed thereon).

[0217] When film formation is performed on the object to be film-formed by a sputtering method, ions generated in the plasma and atoms rebounded by the sputtering target collide with the object to be film-formed, so the temperature of the object to be film-formed rises with the film formation process. In order to control the temperature of the object to be film-formed as described above, for example, film formation can be performed while cooling the object to be film-formed. For example, the object to be film-formed can be cooled from the surface opposite to the film-formed surface (hereinafter referred to as the "film formation temperature") of the object to be film-formed so that the temperature of the film-formed surface (surface) of the object to be film-formed becomes 100 °C or less, 70 °C or less, 50 °C or less, or 30 °C or less. 。

[0218] As shown in FIGS. 32 and 35, a pattern of the oxide semiconductor layer 440 is formed (``OS pattern formation'' in step S2003 of FIG. 32). Although not shown, a resist mask is formed on the oxide semiconductor layer 440, and the oxide semiconductor layer 440 is etched using the resist mask. As the etching of the oxide semiconductor layer 440, wet etching may be used, or dry etching may be used. As the wet etching, etching can be performed using an acidic etchant. As the etchant, for example, oxalic acid or hydrofluoric acid can be used.

[0219] After the pattern of the oxide semiconductor layer 440 is formed, a heat treatment (OS anneal) is performed on the oxide semiconductor layer 440 (``OS anneal'' in step S2004 of FIG. 32) 。

[0220] As shown in FIGS. 32 and 36, a pattern of the metal oxide layer 430 is formed (``AlO x pattern formation'' in step S2005 of FIG. 32) 。 gold As the etching of the metal oxide layer 430, wet etching may be used, or dry etching may be used 。

[0221] As shown in FIGS. 32 and 37, a gate insulating layer 450 is formed over the oxide semiconductor layer 440 (the “GI formation” in step S2006 of FIG. 32). For example, silicon oxide is formed as the gate insulating layer 450. The gate insulating layer 450 is formed by a CVD method. For example, in order to form an insulating layer with few defects as described above as the gate insulating layer 450, the gate insulating layer 450 may be formed at a film formation temperature of 350° C. or higher. The thickness of the gate insulating layer 450 is, for example, 50 nm or more and 300 nm or less, 60 nm or more and 200 nm or less, or 70 nm or more and 150 nm or less. After forming the gate insulating layer 450, a process of implanting oxygen into a part of the gate insulating layer 450 may be performed. The gate insulating layer 450 may be referred to as the “second insulating layer”. A metal oxide layer 490 is formed over the gate insulating layer 450 (the “AlOx film formation” in step S2007 of FIG. 32). The metal oxide layer 490 is formed by a sputtering method. By forming the metal oxide layer 490, oxygen is implanted into the gate insulating layer 450.

[0222] The thickness of the metal oxide layer 490 is, for example, 5 nm or more and 100 nm or less, 5 nm or more and 50 nm or less, 5 nm or more and 30 nm or less, or 7 nm or more and 15 nm or less. In the fourth embodiment, aluminum oxide is used as the metal oxide layer 490. Aluminum oxide has a high barrier property against gas. In the fourth embodiment, the aluminum oxide used as the metal oxide layer 490 suppresses the outward diffusion of the oxygen implanted into the gate insulating layer 450 during the film formation of the metal oxide layer 490.

[0223] For example, when the metal oxide layer 490 is formed by a sputtering method, the process gas used in sputtering remains in the film of the metal oxide layer 490. For example, when Ar is used as the process gas for sputtering, Ar may remain in the film of the metal oxide layer 490. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the metal oxide layer 490.

[0224] A gate insulating layer 450 is formed over the oxide semiconductor layer 440, and a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 440 in a state where a metal oxide layer 490 is formed over the gate insulating layer 450 (the “oxidation annealing” in step S2008 of FIG. 32). In other words, a heat treatment (oxidation annealing) is performed on the metal oxide layer 430 and the oxide semiconductor layer 440 patterned as described above. In the process from when the oxide semiconductor layer 440 is formed until the gate insulating layer 450 is formed over the oxide semiconductor layer 440, many oxygen deficiencies occur on the upper surface 441 and the side surface 443 of the oxide semiconductor layer 440. By the above oxidation annealing, oxygen released from the gate insulating layers 420 and 450 is supplied to the oxide semiconductor layer 440, and the oxygen deficiencies are repaired.

[0225] Due to oxidation annealing, oxygen released from the gate insulating layer 420 is blocked by the metal oxide layer 430, so it is difficult for oxygen to be supplied to the lower surface 442 of the oxide semiconductor layer 440. Oxygen released from the gate insulating layer 420 diffuses from the region where the metal oxide layer 430 is not formed to the gate insulating layer 450 provided over the gate insulating layer 420, and reaches the oxide semiconductor layer 440 through the gate insulating layer 450. As a result, oxygen released from the gate insulating layer 420 is difficult to be supplied to the lower surface 442 of the oxide semiconductor layer 440, and is mainly supplied to the side surface 443 and the upper surface 441 of the oxide semiconductor layer 440. Further, by oxidation annealing, oxygen released from the gate insulating layer 450 is supplied to the upper surface 441 and the side surface 443 of the oxide semiconductor layer 440. By the above oxidation annealing, hydrogen may be released from the gate insulating layers 410 and 420, but the hydrogen is blocked by the metal oxide layer 430.

[0226] As described above, by the oxidation annealing step, it is possible to supply oxygen to the upper surface 441 and the side surface 443 of the oxide semiconductor layer 440 where the amount of oxygen deficiency is large while suppressing the supply of oxygen to the lower surface 442 of the oxide semiconductor layer 440 where the amount of oxygen deficiency is small.

[0227] Similarly, in the above-described oxidation annealing, oxygen implanted into the gate insulating layer 450 is blocked by the metal oxide layer 490, so that it is suppressed from being released into the atmosphere. Therefore, by the oxidation annealing, the oxygen is efficiently supplied to the oxide semiconductor layer 440, and oxygen deficiencies are repaired.

[0228] As shown in FIGS. 32 and 38, after the oxidation annealing, the metal oxide layer 490 is etched (removed) ("AlOx removal" in step S2009 of FIG. 32). As the etching of the metal oxide layer 490, wet etching may be used, or dry etching may be used. As the wet etching, for example, diluted hydrofluoric acid (DHF) is used. By the etching, the metal oxide layer 490 formed over the entire surface is removed. In other words, the removal of the metal oxide layer 490 is performed without using a mask. Further in other words, by the etching, all of the metal oxide layer 490 in the region overlapping with the oxide semiconductor layer 440 formed in one pattern at least in plan view is removed.

[0229] As shown in FIGS. 32 and 39, a gate electrode 460 is formed over the gate insulating layer 450 ("GE formation" in step S2010 of FIG. 32). The gate electrode 460 is formed by a sputtering method or an atomic layer deposition method and is patterned through a photolithography process. As described above, the gate electrode 460 is formed to be in contact with the gate insulating layer 450 exposed by the removal of the metal oxide layer 490.

[0230] With the gate electrode 460 patterned, the source region S and drain region D of the oxide semiconductor layer 440 are made to have lower resistance (the "SD lower resistance" in step S2011 of FIG. 32). Specifically, impurities are implanted into the oxide semiconductor layer 440 through the gate insulating layer 450 from the gate electrode 460 side by ion implantation. For example, argon (Ar), phosphorus (P), and boron (B) are implanted into the oxide semiconductor layer 440 by ion implantation. By forming oxygen vacancies in the oxide semiconductor layer 440 by ion implantation, the oxide semiconductor layer 440 has lower resistance. Since the gate electrode 460 is provided above the oxide semiconductor layer 440 that functions as the channel region CH of the semiconductor device 40, no impurities are implanted into the oxide semiconductor layer 440 in the channel region CH.

[0231] As shown in FIGS. 32 and 40, insulating layers 470 and 480 are formed as interlayer films on the gate insulating layer 450 and the gate electrode 460 (the "interlayer film formation" in step S2012 of FIG. 32). The insulating layers 470 and 480 are formed by CVD. For example, silicon nitride is formed as the insulating layer 470, and silicon oxide is formed as the insulating layer 480. The materials used for the insulating layers 470 and 480 are not limited to the above. The thickness of the insulating layer 470 is 50 nm or more and 500 nm or less. The thickness of the insulating layer 480 is 50 nm or more and 500 nm or less.

[0232] As shown in FIGS. 32 and 41, openings 471 and 473 are formed in the gate insulating layer 450 and the insulating layers 470 and 480 (the "contact opening" in step S2013 of FIG. 32). The oxide semiconductor layer 440 in the source region S is exposed by the opening 471. The oxide semiconductor layer 440 in the drain region D is exposed by the opening 473. By forming the source / drain electrodes 200 on the oxide semiconductor layer 440 exposed by the openings 471 and 473 and on the insulating layer 480 (the "SD formation" in step S2044 of FIG. 32), the semiconductor device 40 shown in FIG. 32 is completed.

[0233] <4-5. An example of the electrical characteristics of the semiconductor device 40> With reference to FIGS. 42 and 43, an example of the electrical characteristics of the semiconductor device 40 will be mainly described. The semiconductor device 40 is used for the channel region CH of the second transistor OT2 in the pixel circuit shown in FIG. 43. The second transistor OT2 is a transistor called a so-called driving transistor. In FIG. 42, the present application invention is described as Present Application, and the comparative example is described as Prior Art. The pixel circuit of the present application invention is the same as the pixel circuit of the comparative example, and the second transistor OT2 and the light-emitting element OLED of the present application invention correspond to the second transistor TR and the light-emitting element POLED of the comparative example. Also, the channel region CH of the second transistor OT2 of the present application invention is formed using the oxide semiconductor layer 440, whereas the channel region of the second transistor TR of the comparative example is formed using, for example, a low-temperature poly-silicon layer (LTPS layer) or an oxide semiconductor layer having characteristics different from those of the oxide semiconductor layer 440.

[0234] Note that the pixel circuit according to the fourth embodiment shown in FIG. 43 is a circuit in which the second transistor T2 of the pixel circuit 183 according to the third embodiment described with reference to FIG. 27 is replaced with the second transistor OT2 formed using the semiconductor device 40. The configuration and function of the pixel circuit according to the fourth embodiment other than the second transistor OT2 are the same as the configuration and function of the pixel circuit 183 according to the third embodiment described with reference to FIG. 27. Therefore, in the fourth embodiment, mainly the second transistor OT2 will be described, and the description of the configuration and function other than the second transistor OT2 will be omitted. Note that the channel regions of transistors other than the second transistor OT2 (the first transistor T1, the third transistor T3 to the seventh transistor T7) are formed using, for example, a low-temperature poly-silicon layer (LTPS layer).

[0235] FIG. 42 is a diagram showing the dependence of the drain current IOT2 on the drain voltage (voltage VANODE) of the second transistor OT2, and is a diagram showing the dependence of the voltage VANODE of the light-emitting element OLED and the current IDI flowing through the light-emitting element OLED. Further, FIG. 42 also shows the dependence of the drain current IOT2 on the drain voltage (voltage VANODE) of the second transistor TR, and the dependence of the voltage VANODE of the light-emitting element POLED and the current IDI flowing through the light-emitting element OLED. Also, in FIG. 42, at the boundary between the linear region and the saturated region, the source-drain voltage (for example, the potential difference (Vds) between the source electrode and the drain electrode) is the same as the value (Vgs - Vth) obtained by subtracting the threshold voltage (Vth) of the semiconductor device 40 from the potential difference (Vgs) between the gate electrode and the source electrode.

[0236] As shown in FIG. 42, at the operating point 50 of the invention of the present application using the semiconductor device 40 (the point where the curve of the second transistor OT2 and the curve of the light-emitting element OLED intersect), the drain voltage is smaller and the drain current is larger than the operating point 50P of the comparative example (the point where the curve of the second transistor TR and the curve of the light-emitting element POLED intersect).

[0237] That is, since the second transistor OT2 can pass the same current as the second transistor TR with a smaller gate-source voltage Vgs than the second transistor TR, the second transistor OT2 can be driven in the saturated region using a smaller source-drain voltage Vds than the second transistor TR. As a result, by using the semiconductor device 40, the pixel circuit of the invention of the present application can be driven at a lower voltage than the pixel circuit of the comparative example.

[0238] Therefore, by using the semiconductor device 40, the potential difference (the potential difference between the driving voltage VDDEL and the reference voltage VSSEL) of the voltages supplied to the first driving power supply line PVDD and the reference voltage line PVSS of the pixel circuit can be set to be small. Since the self-emissive display device using the semiconductor device 40 can reduce the power supply voltage, it can achieve low power consumption.

[0239] As embodiments of the present invention, each of the above-described embodiments or a part of each embodiment can be implemented in appropriate combination as long as they do not contradict each other.

[0240] Even if there are other operational effects different from those brought about by the aspects of each of the above-described embodiments, those that are obvious from the description of this specification or can be easily predicted by those skilled in the art are naturally understood to be brought about by the present invention.

Explanation of Reference Numerals

[0241] 10: Self-luminous display device, 10A: Self-luminous display device, 22: Display area, 24: Peripheral area, 26: Terminal area, 40: Semiconductor device, 50: Operating point (the point where the curve of the second transistor OT2 and the curve of the light-emitting element OLED intersect), 50P: Operating point (the point where the curve of the second transistor TR and the curve of the light-emitting element POLED intersect), 100: Array substrate, 110: Source driver circuit, 112: Selection circuit, 114: Input terminal, 116: Output terminal, 118: Switch, 120: First gate driver circuit, 120A: Gate driver circuit, 121: Shift register, 122: Shift register, 123: Shift register, 121A: Shift register, 122A: Shift register, 123A: Shift register, 130: First light emission control circuit, 130A: Light emission control circuit, 131: Shift register, 131A: Shift register, 132: Shift register, 132A: Shift register, 133: Shift register, 133A: Shift register, 140: Second light emission control circuit, 141: Shift register, 142: Shift register, 143: Shift register, 150: Terminal section, 160: Flexible printed circuit board, 170: IC chip, 170A: IC chip, 180: Pixel, 181: Pixel circuit, 182: Pixel circuit, 183: Pixel circuit, 190: Second gate driver circuit, 191: Shift register, 192: Shift register, 193: Shift register, 200: Source-drain electrode, 201: Source electrode, 203: Drain electrode, 321: Image data signal line, 329: First scanning signal line, 330: First scanning signal line, 331: First scanning signal line, 332: First scanning signal line, 333: First scanning signal line, 334: First light emission control signal line, 334A: Light emission control signal line, 335: First light emission control signal line, 335A: Light emission control signal line, 336: First light emission control signal line, 336A: Light emission control signal line, 337: Second light emission control signal line, 338: Second light emission control signal line, 339: Second light emission control signal line, 341: Connection wiring, 349: Second scanning signal line, 350: Second scanning signal line, 351: Second scanning signal line, 352: Second scanning signal line, 369: Scanning signal line, 370: Scanning signal line, 371: Scanning signal line, 372: Scanning signal line, 373: Scanning signal line, 400: Substrate, 405: Gate electrode, 410: Gate insulating layer, 420: Gate insulating layer, 430: Metal oxide layer, 440: Oxide semiconductor layer,441: Upper surface, 442: Lower surface, 443: Side surface, 450: Gate insulating layer, 460: Gate electrode, 470: Insulating layer, 471: Opening, 473: Opening, 480: Insulating layer, 490: Metal oxide layer, 612: Gate electrode, 614: First electrode, 616: Second electrode, 622: Gate electrode, 624: First electrode, 626: Second electrode, 632: Gate electrode, 634: First electrode, 636: Second electrode, 642: Gate electrode, 644: First electrode, 646: Second electrode, 652: Gate electrode, 654: First electrode, 656: Second electrode, 662: Gate electrode, 664: First electrode, 666: Second electrode, 672: Gate electrode, 674: First electrode, 676: Second electrode, 682: First electrode, 684: Second electrode, 692: First electrode, 694: Second electrode,

Claims

1. a first transistor controlled by a second control signal obtained by shifting a first control signal, the first transistor being electrically connected between an image data signal line and a first node; a second transistor electrically connected between the first node and a second node; a third transistor, the third control signal being controlled using the shifted first control signal, electrically connected between the second node and a gate electrode of the second transistor; a seventh transistor that is controlled to supply a reset voltage to the second node and a gate electrode of the second transistor using the third control signal, and that is electrically connected to the second node.

2. 2. The self-luminous display device according to claim 1, further comprising a control circuit that sequentially shifts and outputs the third control signal, the first control signal, and the second control signal.

3. a light emitting element electrically connected to a reference voltage line to which a reference voltage is supplied; a fourth transistor controlled by a fourth control signal and electrically connected between a driving power supply line to which a driving voltage is supplied and the second node; a fifth transistor controlled by a fifth control signal and electrically connected to the light emitting element and the first node; a sixth transistor that is controlled to supply an initialization voltage to the light emitting element and a terminal of the fifth transistor that is connected to the light emitting element, and that is electrically connected to the light emitting element; a first light emission control circuit that controls a timing at which the fifth control signal is supplied to the fifth transistor; The self-luminous display device according to claim 2 , further comprising: a second light emission control circuit that controls a timing at which the fourth control signal is supplied to the fourth transistor.

4. 4. The self-luminous display device according to claim 3, wherein the driving voltage is a first driving voltage or a second driving voltage lower than the first driving voltage.

5. The self-luminous display device according to claim 3 , wherein the first to seventh transistors are turned on when supplied with an on signal, and turned off when supplied with an off signal.

6. the first transistor to the seventh transistor are n-channel field effect transistors, the sixth transistor is controlled using the second control signal; The self-luminous display device according to claim 5 .

7. the second light emission control circuit supplies an off signal to the fourth control signal; the first light emission control circuit supplies an off signal to the fifth control signal; the control circuit supplies an ON signal to the third control signal, supplies an ON signal to the first control signal, supplies an OFF signal to the second control signal, and supplies the reset voltage to the second node and the gate electrode; 7. The self-luminous display device according to claim 6.

8. the second light emission control circuit supplies an off signal to the fourth control signal; the first light emission control circuit supplies an off signal to the fifth control signal; the control circuit supplies an OFF signal to the third control signal, supplies an ON signal to the first control signal, supplies an ON signal to the second control signal, and supplies image data signals from the image data signal line to the first node, the second node, and the gate electrode; 7. The self-luminous display device according to claim 6.

9. the second light emission control circuit supplies an off signal to the fourth control signal; the first light emission control circuit supplies an on signal to the fifth control signal; the control circuit supplies an OFF signal to the third control signal, supplies an OFF signal to the first control signal, supplies an OFF signal to the second control signal, and supplies an image data signal including a voltage for displaying black to the first node and the light-emitting element from the image data signal line; 7. The self-luminous display device according to claim 6.

10. the first transistor to the fifth transistor and the seventh transistor are n-channel type field effect transistors, and the sixth transistor is a p-channel type field effect transistor; the first light emission control circuit and the second light emission control circuit are the same light emission control circuit, the fourth control signal and the fifth control signal are the same light emission control signal, the fourth transistor to the sixth transistor are controlled using the same light emission control signal; The self-luminous display device according to claim 5 .

11. The same light emission control circuit supplies an off signal to the same light emission control signal, the control circuit supplies an ON signal to the third control signal, supplies an ON signal to the first control signal, supplies an OFF signal to the second control signal, and supplies the reset voltage to the second node and the gate electrode; The self-luminous display device according to claim 10.

12. The same light emission control circuit supplies an off signal to the same light emission control signal, the control circuit supplies an OFF signal to the third control signal, supplies an ON signal to the first control signal, supplies an ON signal to the second control signal, and supplies image data signals from the image data signal line to the first node, the second node, and the gate electrode; The self-luminous display device according to claim 10.

13. The same light emission control circuit supplies an off signal to the same light emission control signal, the control circuit supplies an OFF signal to the third control signal, supplies an OFF signal to the first control signal, supplies an OFF signal to the second control signal, and supplies an image data signal including a voltage for displaying black to the first node and the light-emitting element from the image data signal line; The self-luminous display device according to claim 10.

14. the first transistor to the third transistor, the sixth transistor, and the seventh transistor are n-channel type field effect transistors, and the fourth transistor and the fifth transistor are p-channel type field effect transistors, the first light emission control circuit and the second light emission control circuit are the same light emission control circuit, the fourth control signal and the fifth control signal are the same light emission control signal, the fourth transistor and the fifth transistor are controlled using the same light emission control signal; the sixth transistor is controlled using the second control signal; The self-luminous display device according to claim 5 .

15. The same light emission control circuit supplies an on signal to the same light emission control signal; the control circuit supplies an ON signal to the third control signal, supplies an ON signal to the first control signal, supplies an OFF signal to the second control signal, and supplies the reset voltage to the second node and the gate electrode; The self-luminous display device according to claim 14.

16. The same light emission control circuit supplies an on signal to the same light emission control signal; the control circuit supplies an OFF signal to the third control signal, supplies an ON signal to the first control signal, supplies an ON signal to the second control signal, and supplies image data signals from the image data signal line to the first node, the second node, and the gate electrode; The self-luminous display device according to claim 14.

17. The same light emission control circuit supplies an on signal to the same light emission control signal; the control circuit supplies an OFF signal to the third control signal, supplies an OFF signal to the first control signal, supplies an OFF signal to the second control signal, and supplies an image data signal including a voltage for displaying black to the first node and the light-emitting element from the image data signal line; The self-luminous display device according to claim 14.

18. a channel region of each of the fourth transistor, the fifth transistor, and the sixth transistor comprises low temperature polysilicon; a channel region of the second transistor includes an oxide semiconductor; The self-luminous display device according to claim 14.

19. A method for driving a self-luminous display device including at least a first transistor controlled by a second control signal obtained by shifting a first control signal and electrically connected to a first node, a second transistor electrically connected between the first node and a second node, a third transistor controlled by a third control signal obtained by shifting the first control signal and electrically connected between the second node and a gate electrode of the second transistor, and a fourth transistor controlled by the third control signal and electrically connected to the second node, turning on the fourth transistor using the third control signal and turning on the third transistor using the first control signal; providing a reset voltage to the second node and to a gate electrode of the second transistor; after supplying the reset voltage, turning off the fourth transistor using the third control signal and turning on the first transistor using the second control signal, and supplying a data voltage to the second node and the first node; A method for driving a self-luminous display device.

20. The self-luminous display device includes: a light emitting element electrically connected to a reference voltage line to which a reference voltage is supplied; a fourth transistor controlled by a fourth control signal and electrically connected between a driving power supply line to which a driving voltage is supplied and the second node; a fifth transistor controlled by a fifth control signal and electrically connected to the light emitting element and the first node; a sixth transistor that is controlled to supply an initialization voltage to the light emitting element and a terminal of the fifth transistor that is connected to the light emitting element, and that is electrically connected to the light emitting element; a first light emission control circuit that controls a timing at which the fifth control signal is supplied to the fifth transistor; a second light emission control circuit that controls a timing of supplying the fourth control signal to the fourth transistor; 20. The method of driving a self-luminous display device according to claim 19, further comprising the steps of sequentially shifting the third control signal, the first control signal, and the second control signal and outputting the shifted signal.

Images