Display device and electronic apparatus

Abstract

To provide a display device which can suppress increase of the power consumption for charging and discharging different types of capacities, and an electronic apparatus having the display device.SOLUTION: The display device includes: a light-emitting element; a data line; a wire; a first constant potential line for receiving a first constant potential; a first transistor for supplying a driving current according to a picture signal supplied through the wire and the data line to the light-emitting element; a second transistor for electrically connecting the data line and the first constant potential line to each other; and a switching element for electrically connecting the data line and the wire to each other.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a display device and an electronic device. [Background technology]

[0002] Display devices having light-emitting elements such as organic electroluminescence elements are known. An example of such a display device is an electro-optical device described in Patent Document 1. The electro-optical device described in Patent Document 1 has a display panel that displays an image. The display panel is provided with pixel circuits corresponding to intersections of scanning lines and data lines. The pixel circuits include light-emitting elements and transistor circuits.

[0003] The transistor circuit has a drive transistor and a discharge transistor. The drive transistor supplies a drive current to the light-emitting element according to a data signal indicating the light emission brightness. The discharge transistor is turned on during a horizontal scanning period, which is a non-light-emitting period, and electrically connects a power supply line to which a potential Vorst is applied and an anode of the light-emitting element. When the discharge transistor is turned on, the anode of the light-emitting element is reset to the potential Vorst. When the light-emitting element is reset to the potential Vorst, the charge remaining in the connection node between the transistor circuit and the light-emitting element is discharged. In addition, various capacitances such as a capacitive element and a parasitic capacitance are present in the data line of the display panel. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2018-151506 A Summary of the Invention [Problem to be solved by the invention]

[0005] There is a problem that power consumption increases due to charging and discharging of various capacitances during a horizontal scanning period including an initialization period in which the anode of the light emitting element is reset to the potential Vorst. [Means for solving the problem]

[0006] In order to solve the above problems, a display device according to a preferred embodiment of the present invention comprises a light-emitting element, a data line, a wiring, a first constant potential line to which a first constant potential is supplied, a first transistor to supply a driving current to the light-emitting element according to a video signal supplied via the wiring and the data line, a second transistor electrically connecting the data line and the first constant potential line, and a switching element electrically connecting the data line and the wiring. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view illustrating a display device according to a first embodiment. [Diagram 2] 1 is a block diagram showing a configuration of a display device according to a first embodiment. [Diagram 3] 3 is a diagram illustrating an example of the configuration of a pixel circuit and a data line driving circuit illustrated in FIG. 2. [Figure 4] 4 is a timing chart for explaining the operation of the display device. [Diagram 5] 5 is a diagram illustrating the operation of the display device in the first initialization period of FIG. 4. FIG. [Figure 6] 5 is a diagram illustrating the operation of the display device in the second initialization period of FIG. 4. FIG. [Figure 7] 5 is a diagram illustrating the operation of the display device in the third initialization period of FIG. 4. FIG. [Figure 8] 5 is a diagram for explaining the operation of the display device in the compensation period of FIG. 4. FIG. [Figure 9] 5 is a diagram for explaining the operation of the display device in the writing period of FIG. 4. FIG. [Figure 10] 5 is a diagram for explaining the operation of the display device in the light emission period of FIG. 4. FIG. [Figure 11]FIG. 11 is a diagram illustrating an operation of the display device of the comparative example in a first initialization period. [Figure 12] FIG. 11 is a diagram illustrating an operation of the display device of the comparative example in a second initialization period. [Figure 13] FIG. 11 is a block diagram showing a configuration of a display device according to a second embodiment. [Figure 14] 14 is a diagram showing an example of the configuration of a pixel circuit and a data line driving circuit shown in FIG. 13. [Figure 15] 14 is a diagram for explaining the operation of the display device shown in FIG. [Figure 16] 14 is a diagram for explaining the operation of the display device shown in FIG. [Figure 17] FIG. 11 is a block diagram showing a configuration of a display device according to a third embodiment. [Figure 18] 18 is a diagram showing a configuration example of the upper circuit and the data line driving circuit shown in FIG. 17. [Figure 19] 18 is a diagram showing a configuration example of a lower circuit and a data line driving circuit shown in FIG. 17. [Figure 20] 18 is a diagram for explaining the operation of the upper circuit shown in FIG. 17. [Figure 21] 18 is a diagram for explaining the operation of the upper circuit shown in FIG. 17. [Figure 22] 18 is a diagram for explaining the operation of the lower circuit shown in FIG. 17. [Figure 23] 18 is a diagram for explaining the operation of the lower circuit shown in FIG. 17. [Figure 24] FIG. 11 is a block diagram showing a configuration of a display device according to a third embodiment. [Diagram 25] FIG. 13 is a block diagram showing a display device according to a modified example. [Figure 26] FIG. 1 is a perspective view showing the appearance of a head mounted display as an electronic device equipped with a display device. [Figure 27] FIG. 27 is a diagram showing the optical configuration of the head mounted display shown in FIG. 26. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Note that the dimensions and scale of each part in the drawings may differ from the actual ones, and some parts are shown diagrammatically to facilitate understanding. Furthermore, the scope of the present invention is not limited to these forms unless otherwise specified in the following description to the effect that the present invention is limited. In addition, in this specification, "connection" means a direct or indirect connection between two or more elements.

[0009] A. First embodiment 1. Basic configuration of display device 1 FIG. 1 is a plan view that shows a schematic diagram of a display device 1 according to a first embodiment. The display device 1 shown in FIG. 1 is, for example, a microdisplay that displays an image in a head mounted display. The display device 1 is, for example, an organic EL device including an OLED that is an example of a light emitting element. OLED is an abbreviation for Organic Light Emitting Diode. EL is an abbreviation for Electroluminescence. In this embodiment, the display device 1 is capable of displaying a full-color image. The image includes an image that displays only text information. The display device 1 may also be a device that can display only a single color.

[0010] The display device 1 has a display unit 10 that displays an image, and is housed in a frame-shaped case 71 that opens at the display unit 10. One end of an FPC board 72 is connected to the display device 1. FPC is an abbreviation for Flexible Printed Circuits. The other end of the FPC board 72 is provided with a plurality of terminals 73 for connecting to a host device (not shown). When the plurality of terminals 73 are connected to the host device, various signals are supplied to the display device 1 from the host device via the FPC board 72.

[0011] 2. Circuit configuration of display device 1 Fig. 2 is a block diagram showing the configuration of a display device 1 according to an embodiment. Note that Fig. 2 shows an X-axis and a Y-axis that are perpendicular to each other. The direction along the X-axis is the "row direction", and the direction along the Y-axis is the "column direction".

[0012] 2, the display device 1 includes, in addition to the above-mentioned display unit 10, a control circuit 3, a scanning line driving circuit 4, and a data line driving circuit 5. The display unit 10, the control circuit 3, the scanning line driving circuit 4, and the data line driving circuit 5 are formed on a semiconductor substrate such as a silicon substrate.

[0013] 2-1.Display section 10 2, a plurality of pixel circuits 100 are arranged in a matrix in the row and column directions in the display unit 10. The plurality of pixel circuits 100 are provided corresponding to a plurality of pixels P.

[0014] The display unit 10 is provided with m rows of scanning lines 12 and 3n columns of data lines 14 grouped together in three columns. Here, m and n are integers equal to or greater than 2. n represents the number of groups. Each of the m rows of scanning lines 12 is provided along the X-axis, and each of the 3n columns of data lines 14 is provided along the Y-axis. A plurality of pixel circuits 100 are provided corresponding to the intersections of the m rows of scanning lines 12 and the 3n columns of data lines 14. The plurality of pixel circuits 100 are provided in a one-to-one correspondence with the pixels P, and are grouped, for example, in groups of three aligned in the row direction. Thus, the pixels P are also grouped, for example, in groups of three aligned in the row direction. The three grouped pixels P represent one dot of a pixel that constitutes an image.

[0015] 2-2.Control circuit 3 Digital video data Video output from a host device (not shown) is supplied to the control circuit 3 shown in Fig. 2 in synchronization with a synchronization signal Sync. The control circuit 3 controls each part of the display device 1 based on the video data Video and the synchronization signal Sync. The video data Video specifies the gradation level of a pixel P in an image to be displayed, for example, in 8 bits. The synchronization signal Sync is a signal including a vertical synchronization signal that instructs the start of vertical scanning of the video data Video, a horizontal synchronization signal that instructs the start of horizontal scanning, and a dot clock signal.

[0016] The control circuit 3 generates a control signal Ctr1 based on the synchronization signal Sync and supplies the control signal Ctr1 to the scanning line driving circuit 4, and also generates a control signal Ctr2 based on the synchronization signal Sync and supplies the control signal Ctr2 to the data line driving circuit 5. Each of the control signals Ctr1 and Ctr2 includes a plurality of signals such as a pulse signal, a clock signal, and an enable signal.

[0017] Furthermore, the control circuit 3 generates image data Vid based on the video data Video, and supplies the image data Vid to the data line driving circuit 5. The luminance characteristics may not match between the gradation level indicated by the image data Vid and the light-emitting element 150 (described below) included in the pixel circuit 100. Thus, in order to cause the light-emitting element 150 to emit light at a luminance corresponding to the gradation level indicated by the video data Video, the control circuit 3 generates image data Vid by converting the 8 bits of the video data Video to 10 bits, for example.

[0018] Furthermore, the control circuit 3 generates various control signals based on the synchronization signal Sync, and supplies the various control signals to the data line driving circuit 5. Specifically, the control circuit 3 supplies control signals / Gref, / Gini, Sel, and / Sel to the data line driving circuit 5. The control signal / Gref is a negative logic control signal. The control signal / Gini is a negative logic control signal. The control signal / Sel is in a logically inverted relationship with the control signal Sel.

[0019] The control circuit 3 receives power from a power supply circuit (not shown) and supplies a predetermined potential to the data line driving circuit 5. Specifically, the control circuit 3 supplies potentials Vorst, Vref, Vini, and the like to the data line driving circuit 5. The power supply circuit also supplies a power supply potential to each pixel circuit 100 in the display unit 10, the scanning line driving circuit 4, and the data line driving circuit 5.

[0020] 2-3. Scanning line driving circuit 4 As shown in FIG. 2, the scanning line driving circuit 4 generates a scanning signal / Gwr based on a control signal Ctr1. The scanning signal / Gwr is a signal for sequentially selecting and scanning m rows of scanning lines 12 one by one in each frame period V defined by a vertical synchronization signal. In FIG. 2, the scanning signals / Gwr supplied to the 1st, 2nd, 3rd, ..., mth rows of scanning lines 12 are represented as / Gwr_1, / Gwr_2, / Gwr_3, ..., / Gwr_m. The frame period V refers to a period required for the display device 1 to display one cut of an image. The length of the frame period V is, for example, 1 / 60 seconds when the driving frame rate is 60 Hz. In addition, in this embodiment, the m rows of scanning lines 12 are sequentially selected one by one, but they may be sequentially selected in units of multiple rows.

[0021] Although not shown in FIG. 2, the scanning line driving circuit 4 generates various control signals / Gcmp, / Gorst, / Drst, and / Gel, which will be described later, in addition to the scanning signal / Gwr.

[0022] 2-4. Data line driving circuit 5 2, the data line driving circuit 5 includes a data signal supply circuit 50, n demultiplexers DM, 3n auxiliary circuits 51, and 3n initialization circuits 52. In FIG. 2, the n demultiplexers DM are denoted as DM_1, DM_2, ..., DM_n. The 3n auxiliary circuits 51 and the 3n initialization circuits 52 are connected via 3n wirings 15.

[0023] The data signal supply circuit 50 generates a video signal Vd based on image data Vid and a control signal Ctr2. In FIG. 2, the 3n video signals Vd are represented as Vd_1, Vd_2, Vd_3, Vd_4, Vd_5, Vd_6, ... Vd_3n-2, Vd_3n-1, and Vd_3n. The data signal supply circuit 50 includes, for example, a shift register, a latch circuit, a D / A conversion circuit, and an amplifier group. The data signal supply circuit 50 converts the image data Vid supplied in serial into three-phase parallel conversion, converts it into a grayscale potential according to the grayscale level, and outputs it as a video signal Vd.

[0024] The n demultiplexers DM are provided for each of the three columns of data lines 14 constituting the group. Video signals Vd_1, Vd_2, and Vd_3 are supplied to the demultiplexer DM_1, video signals Vd_4, Vd_5, and Vd_6 are supplied to the demultiplexer DM_2, and video signals Vd_3n-2, Vd_3n-1, and Vd_3n are supplied to the demultiplexer DM_n. The n demultiplexers DM sequentially supply the video signal Vd to the three columns of data lines 14 constituting the group.

[0025] The 3n auxiliary circuits 51 are provided in a one-to-one correspondence with the 3n wirings 15. The 3n initialization circuits 52 are provided in a one-to-one correspondence with the 3n data lines .

[0026] 3. Details of the pixel circuit 100 and its corresponding peripheral circuits Fig. 3 is a diagram showing a configuration example of the pixel circuit 100 and the data line driving circuit 5 shown in Fig. 2. The multiple pixel circuits 100 have the same configuration. Therefore, the following description will focus on any one of the multiple pixel circuits 100 and the elements in the data line driving circuit 5 corresponding to it.

[0027] 3-1. Pixel circuit 100 3, the pixel circuit 100 includes a first transistor 506, transistors 507, 508, and 509, a storage capacitor 110, and a light-emitting element 150. Each of the first transistor 506, and the transistors 507, 508, and 509 is a P-channel MOS transistor. MOS is an abbreviation for Metal-Oxide-Semiconductor field-effect transistor.

[0028] The source of the first transistor 506 is electrically connected to the power supply line 111. A high potential Vel is supplied to the power supply line 111. The first transistor 506 is a drive transistor that passes a drive current corresponding to a potential Vgs between the gate and the source to the light-emitting element 150. The first transistor 506 is connected to the data line 14 via a transistor 507 described below. The first transistor 506 supplies a drive current based on a potential corresponding to a video signal Vd supplied via the wiring 15 and the data line 14 to the light-emitting element 150.

[0029] The gate of the transistor 507 is electrically connected to the scanning line 12. One of the source and drain of the transistor 507 is electrically connected to the data line 14, and the other is electrically connected to the gate of the first transistor 506 and one electrode of the storage capacitor 110. Thus, the transistor 507 controls the electrical connection between the gate of the first transistor 506 and the data line 14. When the transistor 507 is set to on, a potential corresponding to a video signal Vd supplied to the data line 14 is supplied to the gate of the first transistor 506.

[0030] One of the source or drain of the transistor 508 is electrically connected to the data line 14, and the other is electrically connected to the drain of the first transistor 506. Thus, the transistor 508 electrically connects the drain of the first transistor 506 to the data line 14. A control signal / Gcmp is supplied to the gate of the transistor 508. The transistor 508 functions as a threshold compensation transistor that performs threshold potential compensation to converge the potential between the gate and drain of the first transistor 506 to a threshold potential |Vth|. The threshold potential of the first transistor 506 refers to the potential difference between the gate and source when a current starts to flow between the source and drain.

[0031] The source of the transistor 509 is electrically connected to the drain of the first transistor 506, and the drain of the transistor 509 is electrically connected to the anode of the light-emitting element 150. The transistor 509 functions as a control transistor that controls the electrical connection between the drain of the first transistor 506 and the anode of the light-emitting element 150. In addition, a control line 112 is connected to the gate of the transistor 509. A control signal / Gel is supplied to the control line 112.

[0032] The light emitting element 150 has a configuration in which an organic EL layer is sandwiched between an anode and a cathode. The anode of the light emitting element 150 is a pixel electrode provided individually for each pixel circuit 100. In contrast, the cathode of the light emitting element 150 is a common electrode provided in common for all pixel circuits 100, and is connected to a power supply line 118. A potential Vct, which is a fixed potential, is supplied to the power supply line 118.

[0033] One electrode of the storage capacitor 110 is electrically connected to the gate of the first transistor 506, and the other electrode is electrically connected to the power supply line 111. Therefore, the storage capacitor 110 holds the potential between the gate and source of the first transistor 506. Note that the storage capacitor 110 may be a parasitic capacitance that is parasitic on the gate of the first transistor 506, or a capacitive element formed by sandwiching an insulating layer between different conductive layers on a semiconductor substrate such as a silicon substrate.

[0034] The sources and drains of the first transistor 506, and the transistors 507, 508, and 509 may be interchanged depending on the potential relationship between the first transistor 506, and the transistors 507, 508, and 509. The first transistor 506, and the transistors 507, 508, and 509 may be thin film transistors or field effect transistors.

[0035] 3-2. Demultiplexer DM As shown in FIG. 3, each of the n demultiplexers DM has three third transistors 501 corresponding to the three columns constituting each group, and sequentially supplies the video signal Vd to the three columns constituting each group. The third transistor 501 is, for example, a transmission gate. Note that in FIG. 3, one third transistor 501 corresponding to one column is illustrated. Also, although not illustrated in detail, the input terminals of the three third transistors 501 included in each demultiplexer DM are commonly connected to each other. Also, each output terminal of the three third transistors 501 is connected to a second electrode 122 of a capacitance element 120 described later via a second wiring 16. Each third transistor 501 is turned on when the control signal Sel is at H level, and turned off when the control signal Sel is at L level. That is, the third transistor 501 is turned off when the control signal / Sel is at H level, and turned on when the control signal / Sel is at L level. Note that the control signal Sel is supplied exclusively to each column in sequence.

[0036] 3-3.Auxiliary circuit 51 3, the auxiliary circuit 51 is used to compress the voltage amplitude of the video signal Vd. The auxiliary circuit 51 includes a P-channel MOS type fifth transistor 502 and a capacitive element 120. The drain of the fifth transistor 502 is connected to the second wiring 16, and the source of the fifth transistor 502 is connected to a third constant potential line 113 that supplies a potential Vref as a "third constant potential". A control signal / Gref is supplied to the gate of the fifth transistor 502.

[0037] The capacitance element 120 is provided between the wiring 15 and the second wiring 16 and is electrically connected thereto. The capacitance element 120 functions as a coupling capacitance. The capacitance element 120 has a first electrode 121, a second electrode 122, and an insulating layer 123. The first electrode 121 is electrically connected to the wiring 15. The second electrode 122 is disposed opposite to the first electrode 121 and is electrically connected to the second wiring 16. Thus, the second electrode 122 is electrically connected to the third transistor 501. The insulating layer 123 is disposed between the first electrode 121 and the second electrode 122. The capacitance element 120 is provided, for example, to compress the voltage amplitude of the video signal Vd.

[0038] 3-4.Initialization circuit 52 3, the initialization circuit 52 is used to initialize certain elements included in the pixel circuit 100 during an initialization period A described below. The initialization circuit 52 includes a fourth transistor 503 of a P-channel MOS type, a transistor 504, a transistor 505, and a switching element 55.

[0039] The switching element 55 is disposed between the data line 14 and the wiring 15, and controls the electrical connection between the data line 14 and the wiring 15. As will be described in detail later, the provision of the switching element 55 makes it possible to suppress an increase in the parasitic capacitance of the wiring 15 and an increase in power consumption due to charging and discharging of the capacitive element 120.

[0040] The switching element 55 is formed of, for example, a transmission gate. The input terminal of the switching element 55 is connected to the fourth transistor 503, and the output terminal is connected to the transistor 504. The switching element 55 is turned on when the control signal Zgopn is at H level, and turned off when the control signal Zgopn is at L level. That is, the third transistor 501 is turned off when the control signal / Zgopn is at H level, and turned on when the control signal / Zgopn is at L level.

[0041] The drain of the fourth transistor 503 is connected to the wiring 15, and the source of the fourth transistor 503 is connected to a second constant potential line 114 that supplies a potential Vini as a "second constant potential". The potential Vini is a potential between a potential Vel that is a high potential and a potential Vorst that is a low potential described below. A control signal / Gini is supplied to the gate of the fourth transistor 503.

[0042] The drain of the transistor 504 is connected to the data line 14, and the source of the transistor 504 is connected to the power supply line 115 that supplies the potential Vorst, which is a low potential. The gate of the transistor 504 is supplied with a control signal / Gorst.

[0043] The drain of the transistor 505 is connected to the data line 14, and the source of the transistor 505 is connected to the power supply line 116 that supplies a high potential Vel. In other words, the transistor 505 electrically connects the data line 14 and the power supply line 116. A control signal / Drst is supplied to the gate of the transistor 505.

[0044] In this embodiment, the transistor 505 is an example of a "second transistor." The power supply line 116 corresponds to a "first constant potential line," and the potential Vel corresponds to a "first constant potential." The transistor 504 may be considered as a "second transistor." In this case, the power supply line 115 corresponds to a "first constant potential line," and the potential Vorst corresponds to a "first constant potential."

[0045] Further, the data line 14 is connected to the power supply line 117 via a storage capacitor 130. A high potential Vel is supplied to the power supply line 117. The storage capacitor 130 is a parasitic capacitance of the data line 14, and can also be regarded as an inter-wiring capacitance between the data line 14 and the power supply line 117.

[0046] 4. Operation of the Display Device 1 FIG. 4 is a timing chart for explaining the operation of the display device 1. One frame period V shown in FIG. 4 includes a plurality of horizontal scanning periods H and a plurality of light emission periods D. In one frame period V, 1 to m rows of scanning lines 12 are scanned in sequence for each horizontal scanning period H. Note that FIG. 4 shows one horizontal scanning period and one light emission period D in one frame period V. Furthermore, one horizontal scanning period H is a period required for horizontal scanning of one row. One horizontal scanning period H includes an initialization period A, a compensation period B, and a writing period C.

[0047] Note that the operation during one horizontal scanning period H is common to all the pixel circuits 100 in each row. The following description will focus on one arbitrary pixel circuit 100 among the multiple pixel circuits 100 and its corresponding peripheral circuitry.

[0048] 4-1. Frame period V 4-1A.Initialization period A 4, the initialization period A includes a first initialization period A1, a second initialization period A2, and a third initialization period A3. In the initialization period A, predetermined elements of the pixel circuit 100 are initialized.

[0049] 4-1Aa. First initialization period A1 Fig. 5 is a diagram for explaining the operation of the display device 1 in the first initialization period A1 of Fig. 4. Specifically, in the first initialization period A1, a high potential Vel is supplied to the gate of the first transistor 506. The first initialization period A1 is a period for turning off the first transistor 506.

[0050] As shown in FIG. 4, in the first initialization period A1, the scanning signal / Gwr and the control signal / Drst are set to the L level. Therefore, the transistor 507 and the transistor 505 shown in FIG. 5 are turned on. As a result, the high potential Vel is supplied to the gate of the first transistor 506 through the transistor 505, the data line 14, and the transistor 507 in this order. When the high potential Vel is supplied to the gate of the first transistor 506, the potential between the gate and the source becomes zero. Therefore, the first transistor 506 is turned off. In addition, the potential Vel is supplied to one end of the storage capacitor 130 of the data line 14.

[0051] 4, in the first initialization period A1, the control signal / Gcmp is at H level. Therefore, the transistor 508 shown in FIG. 5 is off. Therefore, in the first initialization period A1, the first transistor 506 and the transistor 508 are off. As a result, the path of the current supplied to the light-emitting element 150 is cut off.

[0052] Also, as shown in FIG. 4, in the first initialization period A1, the control signal Zgopn is set to the L level. Therefore, the switching element 55 shown in FIG. 5 is set to the OFF state. Therefore, the data line 14 and the wiring 15 are in a non-connected state. Also, in the first initialization period A1, the control signal / Gref and the control signal / Gini are each set to the L level. Therefore, the fourth transistor 503 and the fifth transistor 502 shown in FIG. 5 are each turned on. Therefore, the potential Vini is supplied to the wiring 15 and the first electrode 121 of the capacitance element 120, and the potential Vref is supplied to the second wiring 16 and the second electrode 122 of the capacitance element 120.

[0053] By providing the switching element 55, it is possible to disconnect the data line 14 from the wiring 15 in the first initialization period A1. Therefore, in the first initialization period A1, a potential different from the potential of the data line 14 is supplied to the wiring 15 and the second wiring 16.

[0054] 4-1Ab.Second initialization period A2 Fig. 6 is a diagram for explaining the operation of the display device 1 in the second initialization period A2 of Fig. 4. In the second initialization period A2, a potential Vorst is supplied as a reset potential to each anode of the light-emitting element 150. The second initialization period A2 is a period for initializing the anode of the light-emitting element 150.

[0055] As shown in FIG. 4, in the second initialization period A2, the control signal / Gel, the control signal / Gcmp, and the control signal / Gorst are each set to the L level. Therefore, each of the transistors 508, 509, and 504 shown in FIG. 6 is turned on. As a result, the potential Vorst, which is a low potential, is applied to the anode of the light-emitting element 150 via the transistor 504, the data line 14, and the transistors 508 and 509. By resetting the anode of the light-emitting element 150 to the potential Vorst, the charge remaining in the connection node between the anode of the light-emitting element 150 and the transistor 509 is discharged. Therefore, in the second initialization period A2, the anode of the light-emitting element 150 is initialized to the potential Vorst.

[0056] As described above, each of the light-emitting elements 150 has an organic EL layer sandwiched between an anode and a cathode. Therefore, when light is emitted, a storage capacitance is parasitic between the anode and the cathode. In the second initialization period A2, the potential Vorst is supplied to the anode, and the potential stored by the storage capacitance between the anode and the cathode is reset. Therefore, when a driving current flows again to the light-emitting element 150, the light-emitting element 150 is not easily affected by the potential stored in the storage capacitance.

[0057] Also, in the second initialization period A2, as in the first initialization period A1, the control signal Zgopn remains at the L level, so the switching element 55 shown in FIG. 6 remains off. Therefore, the data line 14 and the wiring 15 remain in a disconnected state. Also, in the first initialization period A1, the control signal / Gref and the control signal / Gini remain at the L level, so the fourth transistor 503 and the fifth transistor 502 remain on. Therefore, in the second initialization period A2, as in the first initialization period A1, a potential different from the potential of the data line 14 is supplied to the wiring 15 and the second wiring 16.

[0058] 4-1Ac.Third initialization period A3 Fig. 7 is a diagram for explaining the operation of the display device 1 in the third initialization period A3 of Fig. 4. In the third initialization period A3, a potential Vini is supplied to the gate of the first transistor 506. The third initialization period A3 is a pre-processing period for the compensation period B.

[0059] As shown in FIG. 4, in the third initialization period A3, the control signal Zgopn is set to H level. Therefore, the switching element 55 shown in FIG. 7 is turned on. As a result, the data line 14 and the wiring 15 are electrically connected. In addition, in the third initialization period A3, the scanning signal / Gwr and the control signal / Gini are each set to L level. Therefore, the transistor 507 and the fourth transistor 503 shown in FIG. 7 are each turned on. As a result, the potential Vini is supplied to the gate of the first transistor 506 and one end of the storage capacitor 110 through the fourth transistor 503, the wiring 15, the data line 14, and the transistor 507 in this order. The potential Vini is set so that |Vel-Vini| is larger than the threshold potential |Vth| of the first transistor 506. By setting in this manner, the compensation period B described later can be shortened.

[0060] In addition, in the third initialization period A3, the control signal / Gref remains at the L level, so that the fifth transistor 502 remains on. Therefore, in the third initialization period A3, the state in which the potential Vref is supplied to the second wiring 16 and the second electrode 122 of the capacitive element 120 continues.

[0061] 4-1B.Compensation period B Fig. 8 is a diagram for explaining the operation of the display device 1 in the compensation period B of Fig. 4. In the compensation period B, threshold potential compensation is performed to cause the potential between the gate and drain of the first transistor 506 to converge to the threshold potential |Vth|.

[0062] As shown in FIG. 4, in the compensation period B, the control signal Zgopn remains at H level, so that the data line 14 and the wiring 15 shown in FIG. 8 are electrically connected. Also, in the compensation period B, the scanning signal / Gwr and the control signal / Gcmp are each set to L level. Therefore, the transistors 507 and 508 shown in FIG. 8 are each turned on. Therefore, the drain of the first transistor 506 is connected to the gate of the first transistor 506 through the transistor 508, the data line 14, and the transistor 507 in this order. Therefore, the first transistor 506 is in a diode-connected state. Therefore, the potentials of the data line 14 and the gate of the first transistor 506 rise from the potential Vini and are saturated at the potential (Vel-|Vth|). Also, the storage capacitor 110 holds the threshold potential |Vth| of the first transistor 506, and the potential between the gate and drain of the first transistor 506 converges to the threshold potential |Vth|.

[0063] During the compensation period B, the control signal / Gref remains at the L level, so that the fifth transistor 502 remains on. Therefore, during the compensation period B, the state in which the potential Vref is supplied to the second wiring 16 and the second electrode 122 of the capacitive element 120 continues.

[0064] 4-1C. Writing Period C Fig. 9 is a diagram for explaining the operation of the display device 1 in the writing period C of Fig. 4. In the writing period C, a data writing process is performed in which a potential corresponding to the video signal Vd is supplied to the gate of the first transistor 506.

[0065] 4, in the writing period C, the scanning signal / Gwr remains set to the L level, while the control signal / Gcmp is set to the H level. Therefore, as shown in FIG 9, the diode-connected state of the first transistor 506 is released.

[0066] Furthermore, in the writing period C, the control signal Sel is set to the H level, and the control signal / Gref is set to the H level. Therefore, the fifth transistor 502 is turned off, and the third transistor 501 is turned on. Therefore, the potential of one end of the capacitance element 120 changes from the potential Vref to the potential of the video signal Vd. This change in potential is defined as ΔV. This change in potential is propagated to the gate of the first transistor 506 via the second wiring 16, the capacitance element 120, the wiring 15, the data line 14, and the transistor 507 in this order.

[0067] Moreover, the gate of the first transistor 506 has a value (Vel-|Vth|+k1·ΔV) that is shifted upward by the value obtained by multiplying the capacitance ratio k1 by the above-mentioned change in potential ΔV from the potential (Vel-|Vth|) during the compensation period B. Therefore, the potential Vgs between the gate and source of the first transistor 506 becomes Vel-(Vel-|Vth|+k1·ΔV)=(|Vth|-k1·ΔV).

[0068] The capacitance ratio k1 is Crf / (Cpara+Crf). Crf is the capacitance of the capacitance element 120. Cpara is the capacitance of the storage capacitance 130. The capacitance of the storage capacitance 110 is Cpix. The relationship between the capacitance Cpix of the storage capacitance 110, the capacitance Cpara of the storage capacitance 130, and the capacitance Crf of the capacitance element 120 is Cpara>Crf>>Cpix. The capacitance Cpix is ​​sufficiently small compared to the capacitances Crf and Cpara. For this reason, it is not taken into consideration in the above capacitance ratio k1.

[0069] 4-1D. Light Emitting Period D Fig. 10 is a diagram for explaining the operation of the display device 1 in the light emission period D in Fig. 4. In the light emission period D, the light emitting element 150 emits light.

[0070] As shown in FIG. 4, in the light emission period D, the scanning signal / Gwr changes to H level, the scanning signals / Gcmp and / Gorst maintain H level, and the control signal / Gel changes to L level. Therefore, the transistor 507 and the transistor 508 shown in FIG. 10 are turned off, and the transistor 509 is turned on. As a result, a drive current according to the potential Vgs of the first transistor 506 is supplied to the light emitting element 150. The potential Vgs in the light emission period D is a potential level-shifted from the threshold potential of the first transistor 506 according to the potential of the video signal Vd. Therefore, in the light emission period D, a current according to the gradation level is supplied to the light emitting element 150 in a state where the threshold potential of the first transistor 506 is compensated.

[0071] As described above, the display device 1 includes the light-emitting element 150, the data line 14, the wiring 15, the power supply line 116 as a "first constant potential line", the first transistor 506 as a drive transistor, the transistor 505 used in initialization, and the switching element 55. The switching element 55 controls the electrical connection between the data line 14 and the wiring 15. By turning on the switching element 55, the data line 14 and the wiring 15 are connected. By turning off the switching element 55, the data line 14 and the wiring 15 are disconnected.

[0072] By providing such a switching element 55, when the capacitor 120 is provided on the wiring 15, it is possible to suppress an increase in power consumption due to charging and discharging of the capacitor 120. Specifically, in the initialization period A of the horizontal scanning period H, it is possible to suppress an increase in power consumption due to charging and discharging of the capacitor 120.

[0073] As described above, in the first initialization period A1, as shown in FIG. 5, the storage capacitor 130 of the data line 14 and the gate of the first transistor 506 are charged to the high potential Vel from the potential of the data line 14 in the light emission period D. In this first initialization period A1, the switching element 55 is set to OFF, so that the data line 14 and the wiring 15 are not connected. Therefore, in the first initialization period A1, the first electrode 121 of the capacitance element 120 is not charged to the high potential Vel. The first electrode 121 is supplied with a potential Vini, which is an intermediate potential. In addition, the second electrode 122 is supplied with a potential Vref. Therefore, it is possible to reduce the power consumption of the capacitance element 120 compared to the case where the first electrode 121 is charged to the high potential Vel.

[0074] In the second initialization period A2, as shown in FIG. 6, the storage capacitor 130 of the data line 14 and the anode of the light-emitting element 150 are discharged from the high potential Vel to the low potential Vorst. In the second initialization period A2, the switching element 55 is set to OFF, and the data line 14 and the wiring 15 are not connected. Therefore, in the second initialization period A2, the first electrode 121 of the capacitive element 120 is not discharged to the low potential Vorst. The potential of the first electrode 121 is kept at the potential in the first initialization period A1 and remains at the potential Vini. In addition, the second electrode 122 remains at the potential Vref. Therefore, the capacitive element 120 is not charged or discharged. This can reduce power consumption.

[0075] In addition, in the third initialization period A3, the switching element 55 is set to ON, so that the data line 14 and the wiring 15 are electrically connected. Then, as shown in FIG. 7, the storage capacitor 130 of the data line 14 and the gate of the first transistor 506 are charged from the low potential Vorst to the intermediate potential Vini. The potential of the first electrode 121 in the third initialization period A3 is kept at the potential in the first initialization period A1 and the second initialization period A2, and remains at the potential Vini. In addition, the second electrode 122 remains at the potential Vref. Therefore, the capacitive element 120 is not charged or discharged. This makes it possible to reduce power consumption.

[0076] As described above, by providing the switching element 55, the first electrode 121 of the capacitance element 120 is kept constant at the potential Vini during the initialization period A. The second electrode 122 is kept constant at the potential Vref. This prevents the capacitance element 120 from being charged and discharged multiple times during the initialization period A. This makes it possible to suppress an increase in power consumption. Furthermore, it is possible to suppress an increase in power consumption due to charging and discharging of the parasitic capacitance of the wiring 15 on which the capacitance element 120 is provided.

[0077] 11 is a diagram for explaining the operation of a display device 1X of a comparative example in a first initialization period A1. In the comparative example, a switching element 55 and a wiring 15 are not provided, and a capacitive element 120 is provided on a data line 14. As shown in FIG. 11, in the comparative example, in the first initialization period A1, a first electrode 121 of the capacitive element 120 is charged to a high potential Vel from the potential of the data line 14 in the light emission period D.

[0078] Fig. 12 is a diagram for explaining the operation of the display device 1X of the comparative example in the second reset period A2. As shown in Fig. 12, in the comparative example, in the second reset period A2, the first electrode 121 of the capacitive element 120 is discharged from the high potential Vel to the low potential Vorst. In addition, in the third reset period A3, the first electrode 121 of the capacitive element 120 is charged from the low potential Vorst to the intermediate potential Vini.

[0079] In the comparative example, the switching element 55 and the wiring 15 are not provided, and the capacitive element 120 is provided on the data line 14, so that the capacitive element 120 is charged and discharged multiple times in the initialization period A, compared to this embodiment. Therefore, the power consumption in the comparative example is higher than that in this embodiment.

[0080] If the video signal is not compressed, the capacitive element 120 may be omitted. Even in this case, since the switching element 55 and the wiring 15 are included, the charging and discharging of the parasitic capacitance of the wiring 15 can be suppressed by turning off the switching element 55 in the first initialization period A1 and the second initialization period A2. This allows for low power consumption.

[0081] As described above, the display device 1 has the third transistor 501 and the capacitive element 120. The third transistor controls the supply of a potential corresponding to the video signal Vd to the second wiring 16, the wiring 15, and the data line 14. Thus, the potential corresponding to the video signal Vd is supplied to the data line 14 via the second wiring 16 and the wiring 15. As described above, when the capacitive element 120 is present, the provision of the switching element 55 can suppress an increase in power consumption due to charging and discharging. Therefore, when the capacitive element 120 is present, in addition to the charging and discharging of the parasitic capacitance of the wiring 15, an increase in power consumption due to the charging and discharging of the capacitive element 120 can be suppressed. Therefore, when the capacitive element 120 is present, it is particularly effective for the display device 1 to have the switching element 55.

[0082] The display device 1 includes a fourth transistor 503. The fourth transistor 503 electrically connects the first electrode 121 and the second constant potential line 114. Therefore, the first electrode 121 can be kept constant at the potential Vini during the initialization period A. This suppresses an increase in power consumption due to charging and discharging of the capacitive element 120.

[0083] The display device 1 further includes a fifth transistor 502. The fifth transistor 502 electrically connects the second electrode 122 and the third constant potential line 113. This makes it possible to keep the second electrode 122 at a constant potential Vref during the initialization period A. This prevents an increase in power consumption due to charging and discharging of the capacitive element 120.

[0084] B. Second embodiment A second embodiment will be described. In the following examples, elements having the same functions as those in the first embodiment will be designated by the same reference numerals as those in the first embodiment, and detailed descriptions thereof will be omitted as appropriate.

[0085] Fig. 13 is a block diagram showing a configuration of a display device 1A of the second embodiment Fig. 14 is a diagram showing a configuration example of the pixel circuit 100 and the data line driving circuit 5 shown in Fig. 13.

[0086] The display device 1A of the second embodiment differs from the display device 1 of the first embodiment in that it has a plurality of second switching elements 56 and that the data line 14 is divided into a plurality of data lines 14a.

[0087] 13, the display device 1A has a plurality of second switching elements 56. Each second switching element 56 is provided for each row. From another perspective, each second switching element 56 is provided for each pixel circuit 100.

[0088] As shown in FIG. 14, the data line 14 is divided into a plurality of data lines 14a. Specifically, the data line 14 is divided for each row. Therefore, a plurality of data lines 14a are provided for each pixel circuit 100. From another perspective, a plurality of data lines 14a are connected for each column via the second switching element 56. Therefore, one data line 14a is connected to another data line 14a via the second switching element 56. Note that the storage capacitance 130 is a parasitic capacitance for one column.

[0089] Fig. 15 and Fig. 16 are diagrams for explaining the operation of the display device 1A shown in Fig. 13. In this embodiment, the second switching elements 56 are turned off in sequence starting from the rows for which the data writing process has been completed.

[0090] As shown in FIG. 15, first, all the second switching elements 56 are set to ON. In this state, data writing processing is performed in the pixels P corresponding to the first row from the top of the display unit 10. When the data writing processing in the pixels P in the first row is completed, the second switching elements 56 corresponding to the pixels P in the first row are turned OFF. Next, as shown in FIG. 16, data writing processing is performed in the pixels P in the second row. In this data writing processing in the pixels P in the second row, the second switching elements 56 corresponding to the first row are set to OFF, so that the data line 14a corresponding to the first row and the data line 14a corresponding to the second row are not connected. When the data writing processing in the pixels P in the second row is completed, the second switching elements 56 corresponding to the pixels P in the second row are turned OFF. In this manner, the second switching elements 56 are sequentially set to OFF.

[0091] As described above, by providing a plurality of second switching elements 56 for each row, the second switching elements 56 can be turned off sequentially, row by row. As a result, the charge / discharge amount of the storage capacitor 130 in the initialization period A decreases. Therefore, in this embodiment, the increase in power consumption due to the charge / discharge of the storage capacitor 130 can be further suppressed compared to the first embodiment. Therefore, it is possible to achieve lower power consumption compared to the first embodiment.

[0092] Also in this embodiment, as in the first embodiment, the switching element 55 is provided, so that an increase in power consumption due to the parasitic capacitance of the wiring 15 and the charging and discharging of the capacitive element 120 can be suppressed.

[0093] C. Third embodiment A third embodiment will be described. In the following examples, elements having the same functions as those in the first embodiment will be designated by the same reference numerals as those in the first embodiment, and detailed descriptions thereof will be omitted as appropriate.

[0094] Fig. 17 is a block diagram showing a configuration of a display device 1B of a third embodiment. Fig. 18 is a diagram showing a configuration example of the upper circuit 10a and the data line driving circuit 5a shown in Fig. 17. Fig. 19 is a diagram showing a configuration example of the lower circuit 10b and the data line driving circuit 5b shown in Fig. 17.

[0095] A display unit 10B of a display device 1B of the third embodiment differs from the display device 1 of the first embodiment in that it has an upper circuit 10a and a lower circuit 10b, and a data line driving circuit 5a and a data line driving circuit 5b.

[0096] As shown in FIG. 17, each data line 14 is divided into a first data line 141 and a second data line 142. The first data line 141 is provided in the upper circuit 10a, and the second data line 142 is provided in the lower circuit 10b. The first data line 141 of the upper circuit 10a is electrically connected to a data line driving circuit 5a. The second data line 142 of the lower circuit 10b is electrically connected to a data line driving circuit 5b. The data line driving circuits 5a and 5b have the same configuration and function as the data line driving circuit 5 of the first embodiment. Therefore, although not shown in detail, each of the data line driving circuits 5a and 5b includes an initialization circuit 52, an auxiliary circuit 51, a demultiplexer DM, and a data signal supply circuit 50.

[0097] As shown in FIG. 18, a plurality of second switching elements 56a are provided in the upper circuit 10a. Each of the plurality of second switching elements 56a is provided for each row. From another perspective, each of the plurality of second switching elements 56a is provided for each pixel circuit 100. As shown in FIG. 18, the first data line 141 is divided into a plurality of data lines 14a. A plurality of data lines 14a are connected to each column via the second switching elements 56a. Therefore, one data line 14a is connected to another data line 14a via the second switching elements 56a. The storage capacitance 130a is a parasitic capacitance for one column.

[0098] As shown in FIG. 19, a plurality of second switching elements 56b are provided in the lower circuit 10b. Each of the plurality of second switching elements 56b is provided for each row. From another perspective, each of the plurality of second switching elements 56b is provided for each pixel circuit 100. In addition, the second data line 142 is divided into a plurality of data lines 14b. A plurality of data lines 14b are connected to each column via the second switching elements 56b. Therefore, one data line 14b is connected to another data line 14b via the second switching elements 56b. The storage capacitance 130b is a parasitic capacitance for one column.

[0099] Figures 20 and 21 are diagrams for explaining the operation of the upper circuit 10a shown in Figure 17. In the upper circuit 10a, the second switching elements 56a are turned on in sequence starting from the rows in which data writing has been completed.

[0100] As shown in FIG. 20, first, the second switching element 56a corresponding to the first row is set to ON, and the other switching elements are set to OFF. In this state, the data write process in the pixels P in the first row is performed. In this data write process in the pixels P in the first row, the second switching element 56a corresponding to the second row is set to OFF, so that the data line 14a corresponding to the second row and the data line 14a corresponding to the first row are not connected. As shown in FIG. 21, when the data write process in the pixels P in the first row is completed, the second switching element 56a corresponding to the pixels P in the second row is turned ON, and the data write process in the pixels P in the second row is performed. When the data write process in the pixels P in the second row is completed, the second switching element 56a corresponding to the pixels P in the second row is turned ON. In this manner, the multiple second switching elements 56a are sequentially turned ON from the first row.

[0101] As described above, in the upper circuit 10a, a plurality of second switching elements 56a are provided for each row, and the second switching elements 56a are set to ON in order from the top. Therefore, the charge / discharge amount of the storage capacitor 130a gradually increases. However, the increase in power consumption due to the charge / discharge of the storage capacitor 130a as a whole can be suppressed.

[0102] Each of Fig. 22 and Fig. 23 is a diagram for explaining the operation of the lower circuit 10b shown in Fig. 17. In the lower circuit 10b, the second switching elements 56b are set to OFF in sequence starting from the row in which data writing has been completed. In the lower circuit 10b, with all the second switching elements 56 set to ON, data writing processing is performed row by row from the top of the display unit 10 in sequence.

[0103] As shown in FIG. 22, for example, when writing is performed on the m-1th row, the second switching elements 56b corresponding to the m-th row and the m-1th row name are set to ON, and the other second switching elements 56b are set to OFF. In this state, data writing processing is performed on the pixel P on the m-1th row. In this data writing processing on the pixel P on the m-1th row, the second switching elements 56b corresponding to the m-2th row are set to OFF, so that the data line 14a corresponding to the m-1th row and the data line 14a corresponding to the m-2th row are not connected. As shown in FIG. 23, when the data writing processing on the pixel P on the m-1th row is completed, the second switching elements 56b corresponding to the pixel P on the m-1th row are turned OFF, and the data writing processing on the pixel P on the m-th row is performed. In this way, the multiple second switching elements 56b are set to ON sequentially from the top.

[0104] As described above, in the lower circuit 10b, a plurality of second switching elements 56b are provided for each row, and the second switching elements 56b are set to off in order from the top. Therefore, the charge / discharge amount of the storage capacitor 130b in the initialization period A decreases. Therefore, in this embodiment, the increase in power consumption due to the charge / discharge of the storage capacitor 130b can be suppressed compared to the first embodiment. Therefore, it is possible to achieve lower power consumption compared to the first embodiment.

[0105] Also in this embodiment, as in the first embodiment, the switching element 55 is provided, so that an increase in power consumption due to the parasitic capacitance of the wiring 15 and the charging and discharging of the capacitive element 120 can be suppressed.

[0106] D. Fourth embodiment The fourth embodiment will be described. In the following examples, the elements having the same functions as those in the first embodiment will be designated by the reference numerals used in the description of the third embodiment, and detailed descriptions thereof will be omitted as appropriate.

[0107] 24 is a block diagram showing the configuration of a display device 1C of the third embodiment. A display section 10C of the display device 1C of the third embodiment differs from the display device 1 of the first embodiment in that it has a third switching element 57 between the upper circuit 10a and the lower circuit 10b. In addition, in the data line driving circuit 5c of the display device 1C, the auxiliary circuit 51, the demultiplexer DM, and the data signal supply circuit 50 are omitted.

[0108] 24, a third switching element 57 is provided between the first data line 141 and the second data line 142. The third switching element 57 controls the connection between the first data line 141 and the second data line 142. A data line driving circuit 5c is electrically connected to the second data line 142. Although not shown in detail, the data line driving circuit 5c has an initialization circuit 52. However, the auxiliary circuit 51, the demultiplexer DM, and the data signal supply circuit 50 are omitted from the data line driving circuit 5c.

[0109] In this embodiment, a potential corresponding to the video signal Vd is supplied from the data line driving circuit 5b to the upper circuit 10a and the lower circuit 10b. When initializing the upper circuit 10a, the third switching element 57 is turned off, and when writing data, the third switching element 57 is turned on. This makes it possible to suppress an increase in power consumption due to charging and discharging of the storage capacitor 130 during the initialization period A, and also makes it possible to reduce the space required for arranging the data line driving circuit 5c compared to the data line driving circuit 5b.

[0110] Although not shown, in the present embodiment, like the first embodiment, the display device 1C includes a switching element 55. This makes it possible to suppress an increase in power consumption due to the parasitic capacitance of the wiring 15 and the charging and discharging of the capacitive element 120.

[0111] E. Variations The above-described embodiments may be modified in various ways, for example as described below. In addition, the modifications may be combined as appropriate.

[0112] Fig. 25 is a block diagram showing a display device 1D of a modified example. In the display device 1D shown in Fig. 25, the data line 14 is divided into a first data line 141 and a second data line 142. A data line driving circuit 5a is connected to the first data line 141, and a data line driving circuit 5b is connected to the second data line 142. By dividing the data line 14 into two, an increase in power consumption due to charging and discharging of the storage capacitance 130 can be suppressed compared to the first embodiment.

[0113] In the above embodiment, each of the light-emitting elements 150 is an OLED. However, for example, the "light-emitting element" may be an LED, a mini LED, a micro LED, etc. LED is an abbreviation for light-emitting diode.

[0114] F.Electronic equipment The display devices 1, 1A, 1B, 1C, and 1D of the above-described embodiments or modifications can be applied to various electronic devices. The display device 1 according to the above-described embodiments is particularly suitable for electronic devices that are required to display high-definition images of 2K2K or more and are also required to be small.

[0115] Fig. 26 is a perspective view showing the appearance of a head mounted display 300 as an electronic device. Fig. 27 is a diagram showing the optical configuration of the head mounted display 300 shown in Fig. 26. In Fig. 27, the display device 1 for the left eye is represented as a display device 1L, and the display device 1 for the right eye is represented as a display device 1R. Note that instead of the display device 1, display devices 1A, 1B, 1C, or 1D may be used.

[0116] As shown in Fig. 26, the head mounted display 300 includes temples 310, a bridge 320, a projection optical system 301L, a projection optical system 301R, and a control unit 350. Also, as shown in Fig. 27, the head mounted display 300 includes two display devices 1. The control unit 350 includes, for example, a processor and a memory, and controls the operations of the two display devices 1.

[0117] The image light LL formed by the display device 1L is emitted to the projection optical system 301L. The projection optical system 301L includes an optical lens 302L and a half mirror 303L. The image light LL is emitted toward the half mirror 303L through the optical lens 302L. A part of the image light LL is reflected by the half mirror 303L and projected onto the pupil EY of the wearer of the head mounted display 300. A part of the image light LL passes through the half mirror 303L. Similarly, the image light LR formed by the display device 1R is emitted to the projection optical system 301R. The projection optical system 301R includes an optical lens 302R and a half mirror 303R. The image light LR is emitted toward the half mirror 303L through the optical lens 302R. A part of the image light LR is reflected by the half mirror 303R and projected onto the pupil EY of the wearer of the head mounted display 300. A part of the image light LR passes through the half mirror 303R.

[0118] A person wearing the head mounted display 300 can view the image formed by the image lights LL and LR while viewing an outside world image.

[0119] The head mounted display 300 includes the above-mentioned display device 1 and a control unit 350. The display device 1 can reduce power consumption due to charging and discharging of various capacitances. Therefore, by including the display device 1 in the head mounted display 300, it is possible to reduce power consumption of the head mounted display 300.

[0120] In addition, examples of electronic devices to which the display device 1 is applied include electronic devices that are placed close to the eyes, such as a digital scope, digital binoculars, digital still cameras, and video cameras, in addition to the head mounted display 300. Furthermore, the display device 1 can be applied as a display unit provided in electronic devices such as displays of mobile phones, smartphones, smart watches, personal digital assistants (PDAs), car navigation devices, and in-vehicle instrument panels. The display device 1 can also be applied to a light bulb of a projection projector.

[0121] Although the present invention has been described above based on the illustrated embodiment and modified examples, the present invention is not limited to these. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that exhibits the same function as the above-mentioned embodiment, and any configuration can be added. [Explanation of symbols]

[0122] 1...display device, 3...control circuit, 4...scanning line driving circuit, 5...data line driving circuit, 5a...data line driving circuit, 5b...data line driving circuit, 5c...data line driving circuit, 10...display section, 10B...display section, 10C...display section, 10a...upper circuit, 10b...lower circuit, 12...scanning line, 14...data line, 14X...data line, 14a...data line, 14b...data line, 15...wiring, 16...second wiring, 50...data signal supply circuit, 51...auxiliary circuit, 52...initialization circuit, 55...switching element, 56...second Switching element, 56a...second switching element, 56b...second switching element, 57...third switching element, 71...case, 72...FPC board, 73...terminal, 100...pixel circuit, 110...storage capacitor, 111...power supply line, 112...control line, 113...third constant potential line, 114...second constant potential line, 115...power supply line, 116...power supply line, 117...power supply line, 118...power supply line, 120...capacitive element, 120X...capacitive element, 121...first electrode, 121X...first electrode, 122...second electrode, 123...insulation layer, 130...storage capacitance, 130X...storage capacitance, 130a...storage capacitance, 130b...storage capacitance, 141...first data line, 142...second data line, 150...light-emitting element, 300...head mounted display, 301L...projection optical system, 301R...projection optical system, 302L...optical lens, 302R...optical lens, 303L...half mirror, 303R...half mirror, 310...temple, 320...bridge, 350...control unit, 501...third transistor, 502...fifth transistor, 503... Fourth transistor, 504...transistor, 505...transistor, 506...first transistor, 506X...first transistor, 507...transistor, 508...transistor, 509...transistor, A...initialization period, A1...first initialization period, A2...second initialization period, A3...third initialization period, B...compensation period, C...writing period, D...light emission period, DM...demultiplexer, EY...pupil, H...horizontal scanning period, V...frame period, LL...image light, LR...image light, P...pixel.

Claims

1. A light-emitting element; Data lines and Wiring and a first constant potential line to which a first constant potential is supplied; a first transistor that supplies a driving current to the light-emitting element based on a potential corresponding to a video signal supplied via the wiring and the data line; a second transistor electrically connecting the data line and the first constant potential line; a switching element that electrically connects the data line and the wiring; A display device comprising:

2. a third transistor that controls the supply of the video signal to the wiring and the data line; a capacitance element having a first electrode electrically connected to the wiring and a second electrode arranged opposite to the first electrode and electrically connected to the third transistor; The display device according to claim 1 , further comprising:

3. a second constant potential line to which a second constant potential is supplied; a fourth transistor electrically connecting the first electrode and the second constant potential line; The display device according to claim 2 , further comprising:

4. a third constant potential line to which a third constant potential is supplied; a fifth transistor electrically connecting the second electrode and the third constant potential line; The display device according to claim 2 , further comprising:

5. Further comprising a second switching element, The data line is divided into a plurality of data lines, Each of the plurality of data lines is connected to another data line via the second switching element. The display device according to claim 1 further comprising:

6. The data line is divided into a first data line and a second data line, a third switching element electrically connecting the first data line and the second data line; The display device according to claim 1 further comprising:

7. A display device according to claim 1 ; and a control unit for controlling an operation of the display device.

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