Electro-optical device and electronic apparatus

Abstract

To reduce the capacitance value of coupling capacitance in an electro-optical device.SOLUTION: An electro-optical device 10 includes: scan lines 12; data lines 14; pixel circuits 110 that are each provided in correspondence with the intersection of the scan line 12 and data line 14, and each include an OLED; DA conversion circuits 500 that each output a data signal with a potential according to the brightness of the OLED to a data signal output line 14c; capacitive elements 59 that are each connected with the data signal output line 14c at one end and connected with the data line 14 at the other end; capacitive elements 64 that are each connected with the data line 14 at one end; and NOT circuits 62 that each shift the potential at the other end of the capacitive element 64 before the data signal is output or after the data signal is output.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an electro-optical device and an electronic device. [Background technology]

[0002] In recent years, various electro-optical devices using light-emitting elements such as organic light-emitting diodes (hereinafter referred to as "OLEDs") have been proposed. In electro-optical devices, pixel circuits including the light-emitting elements and driving transistors are generally provided at intersections between scanning lines and data lines in correspondence with pixels of an image to be displayed. In such a configuration, when a data signal having a potential corresponding to the grayscale level of a pixel is supplied to the gate node of the driving transistor, the driving transistor supplies a current corresponding to the voltage between the gate node and the source node to the light-emitting element, causing the light-emitting element to emit light with a brightness corresponding to the grayscale level.

[0003] A circuit that outputs a data signal is required to have a high driving capability in order to charge the data line in a short time. On the other hand, in order to display high quality, it is required to express fine changes in gradation by controlling the potential at the gate node of the driving transistor with high precision. Therefore, a technology has been proposed in which the amplitude range of the data signal is compressed by outputting the data signal to the data line via a coupling capacitance, and the data signal is supplied to the gate node of the driving transistor (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2013-171234 A Summary of the Invention [Problem to be solved by the invention]

[0005] In order to make the light-emitting element in a state where no current flows, i.e., in a so-called black display state, the potential of the gate node of the driving transistor must be made close to the potential of the source node of the driving transistor. To achieve this, the capacitance value of the coupling capacitance must be increased, but in order to increase the capacitance value of the coupling capacitance, a certain amount of space must be secured, which makes it difficult to miniaturize the device. [Means for solving the problem]

[0006] In order to solve the above problem, an electro-optical device according to one embodiment of the present disclosure includes a scanning line, a first data line, a first pixel circuit including a first light-emitting element arranged corresponding to an intersection of the scanning line and the first data line and emitting light with a luminance corresponding to a potential of the first data line, an output circuit outputting a first data signal having a potential corresponding to the luminance of the first light-emitting element to a first output line, a first coupling capacitance having two electrodes, one electrode electrically connected to the first output line and the other electrode electrically connected to the first data line, and a shift circuit shifting the potential of the first data line before or after the first data signal is output. [Brief description of the drawings]

[0007] [Figure 1] 1 is a perspective view of an electro-optical device according to a first embodiment. [Diagram 2] FIG. 2 is a block diagram showing an electrical configuration of the electro-optical device. [Diagram 3] FIG. 2 is a diagram illustrating a pixel circuit of the electro-optical device. [Figure 4] 4 is a timing chart showing the operation of the electro-optical device. [Diagram 5] 11A and 11B are diagrams illustrating a comparison of offsets in an electro-optical device. [Figure 6] 10 is a diagram showing high and low potentials in an electro-optical device according to a comparative example. [Figure 7] 10 is a timing chart showing the operation of the electro-optical device according to the second embodiment. [Figure 8] FIG. 11 is a block diagram showing an electrical configuration of an electro-optical device according to a third embodiment. [Figure 9] FIG. 13 is a block diagram showing an electrical configuration of an electro-optical device according to a fourth embodiment. [Figure 10] FIG. 13 is a block diagram showing an electrical configuration of an electro-optical device according to a fifth embodiment. [Figure 11] FIG. 13 is a block diagram showing the electrical configuration of an electro-optical device according to a sixth embodiment. [Figure 12] FIG. 2 is a diagram illustrating a pixel circuit of the electro-optical device. [Figure 13] FIG. 1 is a perspective view showing a head mounted display using an electro-optical device. [Figure 14] FIG. 2 is a diagram showing an optical configuration of a head mounted display. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, electro-optical devices according to embodiments will be described with reference to the drawings. In each drawing, the dimensions and scale of each part are appropriately different from the actual ones. In addition, the embodiments described below are preferred specific examples, and therefore various technically preferable limitations are attached, but the scope of the present disclosure is not limited to these forms unless otherwise specified in the following description to the effect that the present disclosure is limited.

[0009] FIG. 1 is a perspective view showing an electro-optical device 10 according to a first embodiment. The electro-optical device 10 is a micro display panel that displays an image in, for example, a head mounted display. The electro-optical device 10 includes a pixel circuit including an OLED, a drive circuit that drives the pixel circuit, and the like. The pixel circuit, the drive circuit, and the like are integrated on a semiconductor substrate. The semiconductor substrate is typically a silicon substrate, but may be another type of semiconductor substrate.

[0010] The electro-optical device 10 is housed in a frame-shaped case 192 that opens in the display region 100. The electro-optical device 10 is connected to one end of an FPC board 194. FPC is an abbreviation for Flexible Printed Circuits. The other end of the FPC board 194 is provided with a plurality of terminals 196 that are connected to a host device (not shown). When the plurality of terminals 196 are connected to the host device, video data, synchronization signals, and the like are supplied to the electro-optical device 10 from the host device via the FPC board 194.

[0011] In the figure, the X direction indicates the extension direction of the scanning lines in the electro-optical device 10, and the Y direction indicates the extension direction of the data lines. The two-dimensional plane defined by the X and Y directions is the substrate surface of the semiconductor substrate. The Z direction is perpendicular to the X and Y directions and is the emission direction of the light emitted from the OLED.

[0012] 2 is a block diagram showing the electrical configuration of the electro-optical device 10. As shown in the figure, the electro-optical device 10 includes a control circuit 30, a data signal output circuit 50, an offset circuit 60, an initialization circuit 70, a display area 100, and a scanning line driving circuit 120. In the display area 100, m rows of scanning lines 12 are provided along the X direction in the drawing, and n columns of data lines 14 are provided along the Y direction so as to be electrically insulated from each of the scanning lines 12. Here, m and n are integers of 2 or more.

[0013] In the display region 100, pixel circuits 110 are provided corresponding to the intersections of m rows of scanning lines 12 and n columns of data lines 14. Therefore, the pixel circuits 110 are arranged in a matrix of m rows and n columns. In order to distinguish the rows of the matrix arrangement, they may be referred to as 1, 2, 3, ..., (m-1), mth row from the top in the figure. Similarly, in order to distinguish the columns of the matrix, they may be referred to as 1, 2, 3, ..., (n-1), nth column from the left in the figure. In addition, an integer i of 1 or more and m or less is used to generalize the scanning lines 12. Similarly, an integer j of 1 or more and n or less is used to generalize the data lines 14.

[0014] The control circuit 30 controls each unit based on video data Vid and a synchronous signal Sync supplied from a host device. The video data Vid specifies the gradation level of pixels in an image to be displayed, for example, in 8 bits. The synchronization signal Sync includes a vertical synchronization signal that instructs the start of vertical scanning of the video data Vid, a horizontal synchronization signal that instructs the start of horizontal scanning, and a dot clock signal that indicates the timing of one pixel of the video data.

[0015] In this embodiment, the pixels of an image to be displayed and the pixel circuits 110 in the display area 100 correspond one-to-one. The brightness characteristics indicated by the gradation level in the video data Vid supplied from the host device do not necessarily match the luminance characteristics of the OLED included in the pixel circuit 110. Therefore, in order to cause the OLED to emit light at a luminance corresponding to the gradation level specified by the video data Vid, the control circuit 30 up-converts the 8 bits of the video data Vid to, for example, 10 bits in this embodiment and outputs the up-converted data as video data Vdata. Therefore, the 10-bit video data Vdata becomes data corresponding to the gradation level specified by the video data Vid.

[0016] For the up-conversion, a look-up table is used that stores in advance the correspondence between the 8-bit input video data Vid and the 10-bit output video data Vdata. The control circuit 30 generates various control signals to control each unit, as will be described in detail later.

[0017] The scanning line driving circuit 120 is a circuit for outputting various signals to drive the pixel circuits 110 arranged in m rows and n columns, row by row, under the control of the control circuit 30. For example, the scanning line driving circuit 120 supplies scanning signals / Gwr(1), / Gwr(2), ..., / Gwr(m-1), / Gwr(m) to the 1st, 2nd, 3rd, ..., (m-1), mth scanning lines 12 in order. In general, the scanning signal supplied to the ith scanning line 12 is represented as / Gwr(i). The scanning line driving circuit 120 outputs various control signals in addition to the scanning signals / Gwr(1) to / Gwr(m), which will be described in detail later.

[0018] The data signal output circuit 50 is a circuit that outputs a voltage signal according to luminance to the pixel circuits 110 located in a row selected by the scanning line driving circuit 120. In detail, the data signal output circuit 50 includes a selection circuit group 52, a first latch circuit group 54, a second latch circuit group 56, n DA conversion circuits 500, n transistors 58, and n capacitance elements 59. The selection circuit group 52 includes selection circuits 520 in one-to-one correspondence with the n columns, the first latch circuit group 54 includes first latch circuits L1 in one-to-one correspondence with the n columns, and the second latch circuit group 56 includes second latch circuits L2 in one-to-one correspondence with the n columns. In addition, the n transistors 58 and the n capacitance elements 59 are in one-to-one correspondence with the n columns.

[0019] That is, a set of a selection circuit 520, a first latch circuit L1, a second latch circuit L2, a DA conversion circuit 500, a transistor 58, and a capacitance element 59 is provided corresponding to each example. Here, the selection circuit 520 of the jth column instructs the first latch circuit L1 of the jth column to select the video data of the jth column from the video data Vdata output from the control circuit 30, and the first latch circuit L1 of the jth column latches the video data Vdata according to the instruction. The second latch circuit L2 of the jth column outputs the video data Vdata latched by the first latch circuit L1 of the jth column to the DA conversion circuit 500 of the jth column in a writing period described later according to the control of the control circuit 30.

[0020] The jth column DA conversion circuit 500 converts the 10-bit video data Vdata output from the jth column second latch circuit L2 into an analog data signal and outputs it to the data line 14 via the jth column data signal output line 14c and the capacitive element 59 in that order. In other words, the data signal output lines 14c are provided in one-to-one correspondence with the data lines 14, an output end of the jth column DA conversion circuit 500 is connected to the jth column data signal output line 14c, one end of the jth column capacitive element 59 is connected to the jth column data signal output line 14c, and the other end of the jth column capacitive element 59 is connected to the jth column data line 14. Although not actually shown, an amplifier that amplifies the analog data signal by using a power supply voltage is provided at the output stage of the DA conversion circuit 500 of each column. That is, the analog data signal converted by the DA conversion circuit 500 of the jth column is amplified by the jth column amplifier and supplied to the data signal output line 14c of the jth column.

[0021] The source node of the transistor 58 corresponding to the jth column is connected to a power supply line of potential Vref, and the drain node of the transistor 58 is connected to the data signal output line 14c of the jth column. A control signal / Gref from the control circuit 30 is commonly supplied to the gate nodes of the transistors 58 in each column.

[0022] The offset circuit 60 is a set of NOT circuits 62 and capacitive elements 64 provided in one-to-one correspondence with the data lines 14. The high level of the power supply voltage in the NOT circuits 62 in each column is a potential Vad, and the low level is a potential Gnd that is a reference for zero voltage. A control signal Gad is commonly supplied to the input terminals of the NOT circuits 62 in each column. The output terminal of the NOT circuit 62 in the jth column is connected to one terminal of the capacitive element 64 in the jth column, and the other terminal of the capacitive element 64 in the jth column is connected to the data line 14 in the jth column.

[0023] The initialization circuit 70 is a collection of transistors 72 provided in one-to-one correspondence with the data lines 14. The source node of the transistor 72 corresponding to the jth column is connected to a power supply line of potential Vini, and the drain node of the transistor 72 is connected to the jth column data line 14. A control signal / Gini from the control circuit 30 is commonly supplied to the gate nodes of the transistors 72 in each column.

[0024] In the figure, the potentials of the data lines 14 in the 1st, 2nd, ..., (n-1), and nth columns are denoted as Vd(1), Vd(2), ..., Vd(n-1), and Vd(n), respectively. In general, the potential of the data line 14 in the jth column is denoted as Vd(j).

[0025] 3 is a circuit diagram showing a pixel circuit 110. The pixel circuits 110 arranged in m rows and n columns are electrically identical to one another. For this reason, the pixel circuits 110 will be described by taking the pixel circuit 110 located in the i row and j column as a representative.

[0026] As shown in the figure, the pixel circuit 110 includes an OLED 130, p-type transistors 121 to 125, and a capacitance element 140. The transistors 121 to 125 are, for example, MOS type. Note that MOS is an abbreviation for Metal-Oxide-Semiconductor field-effect transistor. Further, in addition to the scanning signal / Gwr(i), the scanning line driving circuit 120 supplies the control signals / Gel(i), / Gcmp(i), and / Gorst(i) to the pixel circuits 110 in the i-th row.

[0027] The control signal / Gel(i) is a generalized representation of the control signals / Gel(1), / Gel(2), ..., / Gel(m-1), / Gel(m) that are supplied in sequence corresponding to the 1st, 2nd, ..., (m-1), mth rows. Similarly, the control signal / Gcmp(i) is a generalized representation of the control signals / Gcmp(1), / Gcmp(2), ..., / Gcmp(m-1), / Gcmp(m) that are supplied in sequence corresponding to the 1st, 2nd, ..., (m-1), mth rows. The same is true for the control signal / Gorst(i), which is a generalized representation of the control signals / Gorst(1), / Gorst(2), ..., / Gorst(m-1), / Gorst(m) that are supplied in sequence corresponding to the 1st, 2nd, ..., (m-1), mth rows.

[0028] The OLED 130 is a display element in which a light-emitting functional layer 132 is sandwiched between a pixel electrode 131 and a common electrode 133. The pixel electrode 131 functions as an anode, and the common electrode 133 functions as a cathode. The common electrode 133 is optically transparent. When a current flows from the anode to the cathode in the OLED 130, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting functional layer 132 to generate excitons, thereby generating white light.

[0029] In the case of color display, the generated white light resonates in an optical resonator composed of, for example, a reflective layer and a semi-reflective semi-transmissive layer (not shown), and is emitted at a resonant wavelength set corresponding to one of the colors R (red), G (green), and B (blue). A color filter corresponding to the color is provided on the light emission side from the optical resonator. Therefore, the light emitted from the OLED 130 is colored by the optical resonator and the color filter in order, and is visually recognized by the observer. Note that the optical resonator is not shown. In addition, when the electro-optical device 10 simply displays a monochromatic image of light and dark only, the color filter is omitted.

[0030] In the transistor 121 of the pixel circuit 110 in the i-th row and j-th column, the gate node g is connected to the drain node of the transistor 122, the source node s is connected to the power supply line 116 to which the potential Vel is supplied, and the drain node d is connected to the source node of the transistor 123 and the source node of the transistor 124. In the capacitance element 140, one end is connected to the gate node g of the transistor 121, and the other end is connected to the power supply line 116. Therefore, the capacitance element 140 holds the voltage between the gate node g and the source node s of the transistor 121. The other end of the capacitive element 140 may be connected to another power supply line other than the power supply line 116 as long as the potential is kept substantially constant. The potential Vel is used as a high-level potential of the power supply voltage.

[0031] In this embodiment, for example, a so-called MOS capacitance formed by sandwiching a gate insulating layer of a transistor between a semiconductor layer (lower electrode) and a gate electrode layer (upper electrode) of a transistor is used as the capacitance element 140. Note that, as the capacitance element 140, a parasitic capacitance of the gate node g of the transistor 121 may be used, or a so-called metal capacitance formed by sandwiching an insulating layer between different conductive layers in a semiconductor substrate may be used.

[0032] In the transistor 122 of the pixel circuit 110 in the i-th row and j-th column, a gate node is connected to the i-th row scanning line 12, and a source node is connected to the j-th column data line 14. In the transistor 123 of the pixel circuit 110 in the i-th row and j-th column, a control signal / Gcmp(i) is supplied to a gate node, and a drain node is connected to the j-th column data line 14. In the transistor 124 of the pixel circuit 110 in the i-th row and j-th column, a control signal / Gel(i) is supplied to a gate node, and a drain node is connected to the pixel electrode 131 which is the anode of the OLED 130 and the drain node of the transistor 125. In the transistor 125 of the pixel circuit 110 in the i-th row and j-th column, a control signal / Gorst(i) is supplied to the gate node, and the source node is connected to a power supply line that is a power supply wiring to which a potential Vorst is supplied.

[0033] The potential Vorst is, for example, the potential Gnd or a low potential close to the potential Gnd. Specifically, the potential Vorst is a potential at which no current flows through the OLED 130 when power is supplied to the pixel electrode 131 in the OLED 130. A potential Vct is supplied to the common electrode 133 that functions as the cathode of the OLED 130. In this description, "electrically connected" or simply "connected" means a direct or indirect connection or coupling between two or more elements, and includes, for example, coupling between two or more elements in a semiconductor substrate via different wiring layers and contact holes even if the elements are not directly connected to each other.

[0034] Next, the operation of the electro-optical device 10 will be described.

[0035] 4 is a timing chart for explaining the operation of the electro-optical device. In the electro-optical device 10, m scanning lines 12 are scanned one by one in the order of 1st, 2nd, 3rd, ..., mth rows during a frame (V) period. In detail, as shown in the figure, the scanning signals / Gwr(1), / Gwr(2), ..., / Gwr(m-1), / Gwr(m) are sequentially and exclusively set to L level by the scanning line driving circuit 120 for each horizontal scanning period (H).

[0036] In this description, the period of one frame (V) refers to the period required to display one frame of an image specified by the video data Vid. If the length of the period of one frame (V) is the same as the vertical synchronization period, for example, if the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60 Hz, it is 16.7 milliseconds, which corresponds to one cycle of the vertical synchronization signal. Also, the horizontal scanning period (H) is the period obtained by excluding the vertical blanking period from the period of one frame (V) divided by m, and simply put, it is the time interval during which the scanning signals / Gwr(1) to / Gwr(m) sequentially become L level.

[0037] In the electro-optical device 10 according to this embodiment, one horizontal scanning period (H) is divided into four periods in chronological order: an initialization period (A), a compensation period (B), an offset period (C), and a writing period (D). In addition to the above four periods, the operation of the pixel circuit 110 further includes a light emission period (E).

[0038] Of each horizontal scanning period (H), during the initialization period (A), the control signal / Gini is at L level, the control signal Gad is at H level, and the control signal / Gref is at L level. During the compensation period (B), the control signal / Gini changes to H level, the control signal Gad remains at H level, and the control signal / Gref remains at L level. During the offset period (C), the control signal / Gini remains at H level, the control signal Gad changes to L level, and the control signal / Gref remains at L level. During the writing period (D), the control signal / Gini remains at H level, the control signal Gad remains at L level, and the control signal / Gref changes to H level.

[0039] The operation during the horizontal scanning period (H) will be described by taking the i-th row as an example. Also, the pixel circuit 110 will be described by taking the pixel circuit 110 in the i-th row and j-th column as an example.

[0040] When the scanning signal / Gwr(i) changes to the L level during the horizontal scanning period (H) of the i-th row, the initialization period (A) of the i-th row begins. The initialization period (A) is a period for resetting the voltage or charge remaining in each section during the horizontal scanning period (H) of the (i-1)th row.

[0041] In the initialization period (A) of the i-th row, the scanning signal / Gwr(i) is at L level, the control signal / Gcmp(i) is at H level, the control signal / Gel(i) is at H level, and the control signal / Gorst(i) is at L level. As a result, in the pixel circuit 110 in the i-th row, the transistor 124 is turned off and the transistor 125 is turned on, so that the pixel electrode 131, which is the anode of the OLED 130, is at the potential Vorst. As a result, the OLED 130 is turned off and the pixel electrode 131 is reset to the potential Vorst. Note that the pixel electrode 131 is reset in order to eliminate the influence of the voltage applied during the immediately preceding light emission period, since the OLED 130 has a parasitic capacitance.

[0042] Furthermore, in the initialization period (A) of the i-th row, the transistor 72 of each column is in the on state, so the data line 14 of each column is at the potential Vini. In the initialization period (A) of the i-th row, the transistor 122 is in the on state in the pixel circuit 110 of the i-th row, so the potential Vini of the data line 14 reaches the gate node g of the transistor 121 of the pixel circuit 110. However, because the transistor 124 of the pixel circuit 110 is in the off state, no current flows from the source node to the drain node of the transistor 121.

[0043] During the initialization period (A) of the i-th row, the transistor 58 of each column is in the on state, so the data signal output line 14c of each column becomes the potential Vref. During the initialization period (A) of the i-th row, the data line 14 of each column is at the potential Vini, so the capacitive element 59 of each column is charged to the voltage (Vini-Vref). During the initialization period (A) of the i-th row, the output terminal of the NOT circuit 62 of each column, i.e., one terminal of the capacitive element 64 of each column, is at the potential Gnd, so the capacitive element 64 of each column is charged to the voltage (Vini-Gnd).

[0044] After the initialization period (A), a compensation period (B) begins. The compensation period (B) is a period for causing the gate node g of each transistor 121 in the n pixel circuits 110 located in the i-th row to converge to a threshold-equivalent potential that corresponds to the threshold voltage of the transistor 121.

[0045] In the initialization period (B) of the i-th row, the scanning signal / Gwr(i) maintains the L level, the control signal / Gcmp(i) changes to the L level, the control signal / Gel(i) maintains the H level, and the control signal / Gorst(i) maintains the L level. In addition, in the compensation period (B) of the i-th row, the transistor 72 of each column changes to the off state. In the pixel circuit 110 in the i-th row, the gate node g of the transistor 121 is at the potential Vini due to the on-state of the transistor 122. With the gate node g at the potential Vini, the transistor 123 is turned on, and the transistor 121 is diode-connected. Therefore, the voltage between the gate node g and the source node s of the transistor 121 converges to the threshold voltage Vth (a voltage close to the threshold voltage) of the transistor 121. That is, the potentials of the gate node g of the transistor 121 and the data line 14 converge to a potential equivalent to the threshold voltage.

[0046] During the compensation period (B) of the i-th row, the transistors 58 of each column maintain the on state, so that the data signal output lines 14c of each column are maintained at the potential Vref. During the compensation period (B) of the i-th row, the data lines 14 of each column converge to a potential equivalent to the threshold value, so that the capacitive elements 59 of each column are charged with one end at the potential Vref and the other end at the threshold convergence potential.

[0047] In this embodiment, after the compensation period (B) ends, the offset period (C) begins. The offset period (C) is a period for offsetting (shifting) the potential of the gate node g of the transistor 121 by a predetermined potential. During the offset period (C) of the i-th row, the scanning signal / Gwr(i) maintains the L level, the control signal / Gcmp(i) changes to the H level, the control signal / Gel(i) maintains the H level, and the control signal / Gorst(i) maintains the L level.

[0048] During the offset period (B) of the i-th row, the transistor 58 of each column maintains the ON state, the transistor 72 of each column maintains the OFF state, and the control signal Gad is inverted to the L level. As a result, one end of the capacitance element of each column rises from the potential Gnd to the potential Vad. This potential rise raises the potential of the data line 14 via the capacitance element 64. During the offset period (C) of the i-th row, the transistor 122 in the pixel circuit 110 of the i-th row is in the ON state, so when the potential of the data line 14 rises, the potential of the gate node g of the transistor 121 in the pixel circuit 110 of the i-th row also rises.

[0049] The potential change of the data line 14 and the gate node g during the offset period is a value obtained by multiplying the potential change at one end of the capacitance element 64 by the ratio of the capacitance value of the capacitance element 64 to the "composite capacitance value." The "composite capacitance value" here refers to the capacitance value of the composite capacitance due to the parasitic capacitances of the capacitance elements 59, 64, and 140 and the data line 14. Note that the capacitance value of the capacitance element 140 can be ignored if it is sufficiently small compared to the other capacitance values.

[0050] In this embodiment, after the offset period (C) ends, a writing period (D) begins. The writing period (D) is a period for applying a voltage according to the luminance to the gate node g of each transistor 121 in the pixel circuits 110 for n columns located in the i-th row.

[0051] In the writing period (D) of the i-th row, the scanning signal / Gwr(i) maintains the L level, the control signal / Gcmp(i) maintains the H level, the control signal / Gel(i) maintains the H level, and the control signal / Gorst(i) maintains the L level. Therefore, the on or off state of the transistors 122 to 125 in the i-th row pixel circuit 110 does not change from the offset period (C).

[0052] However, in the writing period (D), the control signal / Gref is inverted to H level, and the transistor 58 of each column is changed to an OFF state. Also, the DA conversion circuit 500 of each column is supplied with 10-bit video data Vdata corresponding to the i-th row and column. Therefore, the DA conversion circuit 500 outputs a data signal of a potential according to the luminance level corresponding to the i-th row and column to the data signal output line 14c. The potential of one end of the capacitance element 59 in each column rises from the potential Vref to the potential of the data signal. This potential rise reaches the gate node g of the transistor 121 via the capacitance element 59, the data line 14, and the transistor 122 in this order. The potential change amount of the gate node g in the writing period is a value obtained by multiplying the potential rise amount at one end of the capacitance element 59 by the ratio of the capacitance value of the capacitance element 59 to the "composite capacitance value."

[0053] When the scanning signal / Gwr(i) changes to H level, the writing period (D) of the i-th row ends. When the scanning signal / Gwr(i) becomes H level, the transistor 122 in the pixel circuit 110 in the i-th row and j-th column is turned off, but the voltage difference between the potential of the gate node g and the potential Vel is held in the capacitance element 140.

[0054] After the writing period (D) ends, for example, after one horizontal scanning period has elapsed, the light emission period (E) begins. The light emission period (E) is a period for causing a current corresponding to the potential of the gate node g held during the writing period (D) to flow through the OLED 130 to emit light. Before the light emission period (E) of the i-th row, the control signal / Gorst(i) becomes H level, so that the transistor 125 is turned off. When the light emission period (E) of the i-th row is reached, the control signal / Gel(i) is inverted to L level, so that the transistor 124 is turned on. Therefore, a current according to the potential of the gate node g held by the capacitance element 140 flows through the OLED 130 by the transistor 121. Therefore, the OLED 130 emits light in an optical state according to the current, that is, with a luminance according to the current. The potential of the gate node g held by the capacitance element 140 is the potential of the data line 14 supplied via the transistor 122. In other words, the OLED 130 emits light with a luminance according to the potential of the data line 14.

[0055] 4 shows an example in which the light emission period (E) is continuous, the period in which the control signal / Gel(i) is at the L level may be intermittent or may be adjusted according to the brightness adjustment. Also, the level of the control signal / Gel(i) in the light emission period (E) may be an intermediate level between the H level and the L level.

[0056] In the horizontal scanning period (H) of the i-th row, a similar operation is executed for the pixel circuits 110 in columns 1 to n. Also, in Fig. 4, attention is focused on the horizontal scanning period (H) of the i-th row, and the operation in that horizontal scanning period (H) is described, but a similar operation is executed sequentially for the horizontal scanning periods (H) of the 1st, 2nd, 3rd, ..., mth rows.

[0057] The potential of the gate node g in the pixel circuit 110 in the i-th row and j-th column is increased from the threshold-equivalent potential in the compensation period (B) by the potential change amount in the offset period (C), and then changed in the subsequent writing period (D) according to the grayscale level of the i-th row and j-th column. Similar operations are performed in the other pixel circuits 110, so in this embodiment, a current according to the grayscale level flows through the OLED 130 in a state where the thresholds of the transistors 121 are compensated across all pixel circuits 110 in the m-th row and n-th column. Therefore, in this embodiment, the variation in luminance is reduced, enabling a high-quality display.

[0058] In the embodiment, in the horizontal scanning period (H) of the i-th row, the potential Vd(j) of the j-th data line 14 is as shown in FIG. 5(a). In detail, the potential V(j) becomes the potential Vini in the initialization period (A), converges to the threshold-equivalent potential (Vel-Vth) at the end of the compensation period (B), and rises from the threshold-equivalent potential by the potential change amount in the offset period (C). If the potential change amount is denoted as Vofs for convenience, the potential offset in the offset period (C) can be expressed as (Vel-Vth+Vofs). The potential V(j) changes from the potential (Vel-Vth+Vofs) in the writing period (D) in the range from the potential Vwt corresponding to white to the potential Vbk corresponding to black, that is, to a potential corresponding to the gradation level.

[0059] The potential Vbk corresponding to black is a potential corresponding to the lowest gradation level, and the potential Vwt corresponding to white is a potential corresponding to the highest gradation level. In this embodiment, since the scanning signal / Gwr(i) is at L level during the horizontal scanning period (H) of the i-th row, the transistor 122 is in the on state in the pixel circuit 110 of the i-th row. Therefore, during the horizontal scanning period (H) of the i-th row, the potential Vd(j) of the data line 14 is equal to the potential of the gate node g in the pixel circuit 110 of the i-th row and j-th column.

[0060] Here, for convenience of explanation, a comparative example to the embodiment will be described. In terms of configuration, the comparative example does not have an offset circuit 60, and there is no offset period (C). Therefore, in the comparative example, in the horizontal scanning period (H) of the i-th row, the potential Vd(j) of the j-th column data line 14 becomes as shown in FIG. 5(b). In detail, the potential V(j) becomes a potential Vini in the initialization period (A), converges to a threshold equivalent potential (Vel-Vth) at the end of the compensation period (B), and changes from the potential (Vel-Vth) in the range from a potential Vwt corresponding to white to a potential Vbk corresponding to black in the writing period (D). In the comparative example, the potential corresponding to black is lower than that in the example, so that a minute current flows through the OLED 130, causing it to emit light, and the lowest gray scale is displayed brightly, resulting in a decrease in the contrast ratio.

[0061] In order to raise the potential Vbk corresponding to black to approximately the potential Vel during the writing period (D) without offsetting as in the comparative example, it is necessary to lower the potential Vref and raise the black-corresponding potential output from the output stage amplifier in the DA conversion circuit 500, as shown in Fig. 6. For this purpose, it is necessary to design the capacitance value of the capacitance element 59 so that the black-corresponding potential reaches approximately the potential Vel when it reaches the gate node g via the capacitance element 59, which is a coupling capacitance, and the data line 14 in this order during the writing period (D). Since the amplifier in the output stage of the DA conversion circuit 500 is driven by the power supply voltage (Vel-Gnd), the range of the output voltage of the amplifier is narrower than the power supply voltage. If the capacitance value of the capacitive element 59 is designed so that the maximum potential (potential corresponding to black) output from the amplifier is approximately the potential Vel when it reaches the gate node g, as in the above design, the minimum potential (potential corresponding to white) output from the amplifier may become higher than necessary when it reaches the gate node g.

[0062] Furthermore, if the capacitance value of the capacitive element 59 is designed so that the black-corresponding potential is approximately equal to the potential Vel, a large capacitance value is required for the capacitive element 59. Since the capacitive element 59 is provided for each data line 14, if a large capacitance value is required for the capacitive element 59, a large area is required, which not only becomes an obstacle to narrowing the pitch of the data lines 14 but also leads to an increase in the chip size.

[0063] 5(a), in the offset period (C), the potential is increased from the threshold potential (Vel-Vth) by the potential change amount Vofs, and in the write period (D), the black potential, which is the highest potential of the amplifier, reaches the gate node g via the capacitance element 59 and the data line 14 in that order. Therefore, according to the present embodiment, it is not necessary to design the capacitance value of the capacitance element 59 so that the black potential becomes approximately the potential Vel, and therefore not only can the data lines 14 be made to have a narrower pitch (finer), but also an increase in chip size can be avoided.

[0064] In the first embodiment, in the horizontal scanning period (H) of each row, the offset period (C) is followed by the writing period (D), but this order may be reversed. Therefore, a second embodiment will be described in which the writing period (D) comes first and the offset period (C) follows.

[0065] 7 is a timing chart showing the operation of the electro-optical device 10 according to the second embodiment. In the second embodiment, as shown in the figure, the temporal order of the offset period (C) and the writing period (D) is interchanged with that in the first embodiment (see FIG. 4). In detail, in the second embodiment, the compensation period (B) is followed by the writing period (D). Therefore, in the horizontal scanning period (H) of the i-th row, the potential Vd(j) of the j-th column data line is In the writing period (D), the potential changes from the threshold equivalent potential at the end of the compensation period (B) to a potential corresponding to the gray level (a potential in the range of Bk to Wt), and then in the offset period (C), the potential rises by an offset by the potential change amount Vofs.

[0066] The potential change due to the offset period (C) and the potential change due to the writing period (D) are different only in terms of time. Therefore, the potential of the gate node g at the end of the horizontal scanning period (H) is the same as in the first embodiment. Therefore, in the second embodiment as well, similarly to the first embodiment, not only can the pitch be narrowed easily, but also an increase in chip size can be avoided.

[0067] In the first or second embodiment, the capacitive element 59, the DA conversion circuit 500, etc. are provided corresponding to each column of the data lines 14. Therefore, as the pitch of the data lines 14 becomes narrower, it becomes difficult to arrange the capacitive element 59, the DA conversion circuit 500, etc. for each column on the semiconductor substrate. Therefore, if the arrangement of the capacitive element 59, the DA conversion circuit 500, etc. is devised, the parasitic capacitance of the data lines 14 will then differ for each column, resulting in a deterioration in display quality. Therefore, a third embodiment will be described, in which the degradation of display quality is suppressed even if the parasitic capacitance of the data line 14 differs from column to column.

[0068] FIG. 8 is a diagram showing the electrical configuration of the electro-optical device 10 according to the third embodiment, together with the arrangement of each element. In the third embodiment, in the display region 100, pixel circuits 110R, 110G, and 110B are provided corresponding to the scanning lines 12 arranged in m rows and the data lines 14R, 14G, or 14B arranged in n columns as follows. In detail, the red pixel circuit 110R is provided corresponding to the intersection of the scanning line 12 in the i-th row and the data line 14R in the (j-2)-th column. The green pixel circuit 110G is provided corresponding to the intersection of the scanning line 12 in the i-th row and the data line 14G in the (j-1)-th column. The blue pixel circuit 110B is provided corresponding to the intersection of the scanning line 12 in the i-th row and the data line 14B in the j-th column.

[0069] The pixel circuit 110R includes an OLED 130 that emits light containing a red component, the pixel circuit 110G includes an OLED 130 that emits light containing a green component, and the pixel circuit 110B includes an OLED 130 that emits light containing a blue component. One color pixel is expressed by additive color mixing of light emitted from the pixel circuits 110R, 110G, and 110B that are adjacent to each other and belong to the same row. Therefore, in this embodiment, in terms of color pixels, an image is displayed that is arranged in a matrix of m rows by (n / 3) columns.

[0070] In the third embodiment, the data signal output circuit 50 is simplified and shown as a circuit group 51R corresponding to the data lines 14R, a circuit group 51G corresponding to the data lines 14G, and a circuit group 51B corresponding to the data lines 14B. In detail, the circuit groups 51R, 51G, and 51B are a combination of a selection circuit 520, a first latch circuit L1, a second latch circuit L2, a DA conversion circuit 500, a transistor 58, a data signal output line 14c, and a capacitance element 59. Note that in Fig. 8, only the DA conversion circuit 500, the data signal output line 14c, and the capacitance element 59 are illustrated, and other elements are omitted.

[0071] In the third embodiment, the circuit groups 51R, 51G, and 51B are arranged in this order along the Y direction, and are arranged along the X direction at a pitch of three columns of the data lines 14R, 14G, and 14B. In this arrangement, in a plan view, the data line 14G passes through the circuit group 51R, and the data line 14B passes through the circuit groups 51R and 51G. For this reason, in the third embodiment, the lengths of the data lines 14R, 14G, and 14B are shorter in this order. If the lengths of the data lines 14R, 14G, and 14B are different, the capacitance values ​​parasitic to the data lines 14R, 14G, and 14B will also be different. Specifically, the parasitic capacitances of the data lines 14R, 14G, and 14B are 14R<14G<14B The relationship is as follows.

[0072] As described above, the potential change Vofs of the gate node g during the offset period is the potential change at one end of the capacitive element 64 multiplied by the ratio of the capacitance value of the capacitive element 64 to the "composite capacitance value." In the third embodiment, since the parasitic capacitance values ​​of the data lines 14R, 14G, and 14B are different, unless some measure is taken, the potential change Vofs will be different for each of the data lines 14R, 14G, and 14B, causing color shift and unavoidably deteriorating display quality.

[0073] Therefore, in the third embodiment, the capacitance value of the capacitive element 64 in the offset circuit 60 is made different for each of the data lines 14R, 14G, and 14B. In particular, of the capacitive elements 64 in the offset circuit 60, the one corresponding to the data line 14R is called capacitive element 64R, the one corresponding to the data line 14G is called capacitive element 64G, and the one corresponding to the data line 14B is called capacitive element 64B. The capacitance values ​​of the capacitive elements 64R, 64G, and 64B have the following relationship. That is, 64R<64G<64B This is the relationship.

[0074] The potential change Vofs of the gate node g during the offset period is the potential change at one end of the capacitance element 64R / 64G / 64B multiplied by the ratio of the capacitance value of the capacitance element 64 to the "composite capacitance value." In the third embodiment, since the capacitance values ​​of the capacitive elements 64R / 64G / 64B increase in order in response to the increase in the parasitic capacitance values ​​of the data lines 14R / 14G / 14B, the ratio can be made uniform for the data lines 14, 14G, and 14B. Therefore, in the third embodiment, the potential change amount Vofs of each column can be made uniform.

[0075] In this way, according to the third embodiment, even if the parasitic capacitances of the data lines 14R, 14G, and 14B are different, the potential change amount Vofs can be made uniform among the data lines 14R, 14G, and 14B. Therefore, in the third embodiment, color shift is suppressed, and deterioration of display quality can be suppressed.

[0076] In the third embodiment, when the parasitic capacitances of the data lines 14R, 14G, and 14B are different, in order to align the potential change amount Vofs of each column during the offset period (C), a method is adopted in which the capacitance values ​​of the capacitive elements 64R, 64G, and 64 are made different. However, the potential change amount Vofs of each column can also be aligned using other methods. Therefore, a fourth embodiment will be described in which the potential change amount Vofs of each column is made uniform by a method different from that of the third embodiment even if the parasitic capacitance of the data line 14 differs from column to column.

[0077] FIG. 9 is a diagram showing the electrical configuration of an electro-optical device 10 according to a fourth embodiment, together with the arrangement of each element. The fourth embodiment has the following commonalities and differences with the third embodiment. That is, the fourth embodiment is common to the third embodiment in that the parasitic capacitances of the data lines 14R, 14G, and 14B have a relationship of 14R<14G<14B. However, the fourth embodiment differs from the third embodiment in that, firstly, the capacitance values ​​of the capacitive elements 64 in the offset circuit 60 are the same, and, secondly, the power supply potentials of the NOT circuits 62 in the offset circuit 60 differ for each column.

[0078] In the offset circuit 60 of the fourth embodiment, the high level of the power supply voltage of the NOT circuit 62 corresponding to the data line 14R is potential VadR, the high level of the power supply voltage of the NOT circuit 62 corresponding to the data line 14G is potential VadG, and the high level of the power supply voltage of the NOT circuit 62 corresponding to the data line 14B is potential VadB.

[0079] In the fourth embodiment, if the parasitic capacitances of the data lines 14R, 14G, and 14B are in the relationship 14R<14G<14B, as in the third embodiment, the potentials VadR, VadG, and VadB have the following relationship. That is, VadR <VadG<VadB This is the relationship.

[0080] The potential change amount Vofs of the gate node g during the offset period is a value obtained by multiplying the potential change amount at one end of the capacitive element 64 by the ratio of the capacitance value of the capacitive element 64 to the "composite capacitance value". The potential change amount at one end of the capacitive element 64 (the shift amount of the other electrode potential) is equal to the power supply voltage of the NOT circuit 62. If the capacitance value parasitic to the data line 14R, 14G, or 14B increases, the ratio decreases. However, in the fourth embodiment, since the potential change amount at one end of the capacitive element 64 increases, the potential change amount Vofs of each column can be made uniform.

[0081] In this way, according to the fourth embodiment, even if the parasitic capacitances of the data lines 14R, 14G, and 14B are different, the potential change amount Vofs can be made uniform among the data lines 14R, 14G, and 14B. Therefore, in the fourth embodiment, similarly to the third embodiment, color shift can be suppressed, and deterioration of display quality can be suppressed.

[0082] In the electro-optical devices 10 according to the first to fourth embodiments, the data signal output circuit 50, the offset circuit 60, and the initialization circuit 70 are arranged in this order along the opposite direction to the Y direction with respect to the display region 100, but the present invention is not limited to this configuration. Therefore, a fifth embodiment in which the position of the offset circuit 60 is changed will be described.

[0083] 10 is a block diagram showing the electrical configuration of an electro-optical device 10 according to a fifth embodiment. In the electro-optical device 10 according to the fifth embodiment, the offset circuit 60 is disposed on the opposite side of the data signal output circuit 50 and the initialization circuit 70 with respect to the display area 100. With this configuration, it is possible to reduce the region width in the Y direction relative to the display area 100 in the region outside the display area 100 on the semiconductor substrate, i.e., the length along the Y direction in the region where the data signal output circuit 50 and the like are provided.

[0084] In the fifth embodiment, the offset circuit 60 is disposed on the opposite side of the data signal output circuit 50 and the initialization circuit 70 with respect to the display region 100, but the offset circuit 60 and the initialization circuit 70 may be disposed on the opposite side of the data signal output circuit 50 with respect to the display region 100. With this configuration, the length along the Y direction can be further reduced in the region where the data signal output circuit 50 and the like are provided.

[0085] In the electro-optical device 10 according to any of the first to fifth embodiments, one pixel circuit 110 has transistors 121 to 125, which is a so-called 5Tr configuration, but a configuration having a large number of transistors in one pixel circuit 110 makes miniaturization difficult and can cause a decrease in yield. Therefore, a sixth embodiment in which the number of transistors in one pixel circuit 110 is reduced will be described.

[0086] FIG. 11 is a block diagram showing the electrical configuration of an electro-optical device 10 according to a sixth embodiment, and FIG. 12 is a diagram showing a pixel circuit 110 in the electro-optical device 10. As shown in FIG. As shown in FIG. 12, in the sixth embodiment, one pixel circuit 110 has a configuration including transistors 121 to 124, that is, a so-called 4Tr configuration, and does not have the transistor 125 in the pixel circuit 110 of the first embodiment (see FIG. 3).

[0087] 11, instead of the transistor 125, a transistor 74 is provided for each column in the initialization circuit 70. The transistor 74 is, for example, an n-type. A control signal Gorst is commonly supplied to the gate nodes of the transistors 74 in each column. The source node of the transistor 74 in the jth column is connected to the power supply line of the potential Vorst, and the drain node of the transistor 74 in the jth column is connected to the data line 14 in the jth column.

[0088] In the sixth embodiment, although not particularly shown, the initialization period (A) is divided into, for example, (A1) and (A2). In the initialization period (A1), the control signal / Gini and the control signal Gorst are at level H. Therefore, in each column, the transistor 72 is turned off and the transistor 74 is turned on, so that the data line 14 in each column is at potential Vorst. On the other hand, in the initialization period (A1) of the i-th row, the scanning signal / Gwr(i) is in the H level state, and the control signals / Gcmp(i) and / Gel(i) are in the L level. Therefore, in the i-th row pixel circuit 110, the transistor 122 is in the OFF state, and the transistors 123 and 124 are in the ON state. Therefore, in the i-th row pixel circuit 110, the pixel electrode 131 which is the anode of the OLED 130 is grounded to the potential Gnd via the data line 14 and the transistors 123 and 124 in this order. Therefore, the OLED 130 is turned off, and the pixel electrode 131 is reset to the potential Vorst.

[0089] In the initialization period (A2), the control signal / Gini and the control signal Gorst are at level L. Therefore, in each column, the transistor 72 is turned on and the transistor 74 is turned off, so that the data line 14 in each column is at potential Vini. On the other hand, in the initialization period (A1) of the i-th row, the scanning signal / Gwr(i) changes to the L level, and the control signals / Gcmp(i) and / Gel(i) change to the H level. As a result, in the pixel circuit 110 of the i-th row, the transistor 122 changes to the ON state, and the transistors 123 and 124 change to the OFF state. Therefore, in the pixel circuit 110 of the i-th row, the potential Vini of the data line 14 reaches the gate node g of the transistor 121 via the transistor 122 in the ON state, as in the initialization period (A) of the first embodiment.

[0090] In the sixth embodiment, the operation after the compensation period (B) is similar to that of the first or second embodiment.

[0091] In the electro-optical device 10 according to the sixth embodiment, one pixel circuit 110 has transistors 121 to 124, which makes miniaturization easier and suppresses a decrease in yield compared to the first embodiment.

[0092] In the above-described first to sixth embodiments (hereinafter referred to as "embodiments"), various modifications or applications are possible as follows.

[0093] In the embodiment and the like, the OLED 130 has been described as an example of the light-emitting element, but other light-emitting elements may be used. For example, the light-emitting element may be an LED, or a liquid crystal element combined with an illumination mechanism. In other words, the light-emitting element may be an electro-optical element that changes its optical state according to the voltage of the data line 14. In the embodiment and the like, a 10-bit conversion example is shown as the DA conversion circuit 500, but the present invention is not limited to this.

[0094] In the embodiment and the like, the threshold voltage of the transistor 121 in the pixel circuit 110 is compensated for, but the threshold voltage may not be compensated for, specifically, the transistor 123 may be omitted. Also, a configuration in which the light emission period (E) is not controlled, specifically a configuration in which the transistor 124 is omitted, may be used. The channel type of the transistors 121 to 125 etc. is not limited to that in the embodiment etc. Furthermore, these transistors 121 to 125 etc. may be replaced with transmission gates as appropriate.

[0095] Next, an electronic device to which the electro-optical device 10 according to the embodiment is applied will be described. The electro-optical device 10 is suitable for applications requiring small-sized pixels and high-definition display. Therefore, a head-mounted display will be taken as an example of the electronic device.

[0096] FIG. 13 is a diagram showing the appearance of a head mounted display, and FIG. 14 is a diagram showing the optical configuration thereof. First, as shown in Fig. 13, the head mounted display 300 has temples 310, a bridge 320, and lenses 301L and 301R in appearance similar to general eyeglasses. Also, as shown in Fig. 14, the head mounted display 300 has an electro-optical device 10L for the left eye and an electro-optical device 10R for the right eye provided near the bridge 320 and on the rear side of the lenses 301L and 301R (the lower side in the figure). The image display surface of the electro-optical device 10L is disposed to the left in FIG. 14. As a result, the image displayed by the electro-optical device 10L is output in the 9 o'clock direction in the figure via the optical lens 302L. The half mirror 303L reflects the image displayed by the electro-optical device 10L in the 6 o'clock direction, while transmitting light incident from the 12 o'clock direction. The image display surface of the electro-optical device 10R is disposed to the right, opposite the electro-optical device 10L. As a result, the image displayed by the electro-optical device 10R is output in the 3 o'clock direction in the figure via the optical lens 302R. The half mirror 303R reflects the image displayed by the electro-optical device 10R in the 6 o'clock direction, while transmitting light incident from the 12 o'clock direction.

[0097] In this configuration, a person wearing the head mounted display 300 can observe images displayed by the electro-optical devices 10L and 10R in a see-through state in which the images are superimposed on the outside world. Furthermore, in this head mounted display 300, when the electro-optical device 10L displays an image for the left eye and the electro-optical device 10R displays an image for the right eye among the binocular images with parallax, the wearer can perceive the displayed image as if it had depth and a three-dimensional effect.

[0098] In addition, electronic devices including the electro-optical device 10 can be applied to electronic viewfinders in video cameras and interchangeable lens digital cameras, portable information terminals, display units of wristwatches, light bulbs of projection projectors, and the like, in addition to the head mounted display 300.

[0099] From the above-mentioned exemplary embodiments, the following aspects can be understood, for example.

[0100] An electro-optical device according to one embodiment (embodiment 1) includes a scanning line, a first data line, a first pixel circuit including a first light-emitting element arranged corresponding to an intersection of the scanning line and the first data line and emitting light with a luminance corresponding to the potential of the first data line, an output circuit outputting a first data signal having a potential corresponding to the luminance of the first light-emitting element to a first output line, a first coupling capacitance having two electrodes, one electrode electrically connected to the first output line and the other electrode electrically connected to the first data line, and a shift circuit shifting the potential of the first data line before or after the first data signal is output.

[0101] According to the first aspect, the potential of the data line can be shifted (offset) without increasing the capacitance value of the first coupling capacitance, which facilitates miniaturization. Note that if the potential of the other electrode of the first capacitive element is shifted after the first data signal is output, the potential of the data line is stabilized, which improves the display quality. The OLED 130 is an example of a first light-emitting element, the data signal output line 14c is an example of a first output line, and the DA conversion circuit 500 is an example of an output circuit. The capacitance element 59 is an example of a first coupling capacitance, one end of the capacitance element 59 is an example of one electrode in the first coupling capacitance, and the other end of the capacitance element 59 is an example of the other electrode in the first coupling capacitance. The capacitance element 64 is an example of a first capacitance element, one end of the capacitance element 64 is an example of the other electrode in the first capacitance element, and the other end of the capacitance element 64 is an example of one electrode in the first capacitance element. The NOT circuit 62 is an example of a shift circuit.

[0102] An electro-optical device according to a specific aspect 2 of aspect 1 includes a second data line, a second pixel circuit including a second light-emitting element arranged corresponding to an intersection of the scanning line and the second data line and emitting light with a luminance corresponding to a potential of the second data line, a second coupling capacitance having two electrodes, one electrode of which is electrically connected to a second output line and the other electrode of which is electrically connected to the second data line, a first capacitive element having two electrodes, one electrode of which is electrically connected to the first data line, and a second capacitive element having two electrodes, one electrode of which is electrically connected to the second data line, wherein the output circuit outputs a second data signal to the second output line, the shift circuit shifting the potential of the other electrode of the first capacitive element before or after the second data signal is output, thereby shifting the potential of the first data line, and the shift circuit shifting the potential of the other electrode of the second capacitive element, thereby shifting the potential of the first data line, and the capacitance value of the first capacitive element and the capacitance value of the second capacitive element are different.

[0103] According to the second aspect, even if the parasitic capacitance of the first data line and the parasitic capacitance of the second data line are different, the potentials after shifting can be made uniform, thereby improving the display quality. The data line 14G is an example of a second data line, and the data signal output line 14c corresponding to the data line 14G is an example of a second output line. The OLED 130 of the pixel circuit 110R is an example of a first light-emitting element, and the OLED 130 of the pixel circuit 110G is an example of a second light-emitting element. The capacitive element 59R is an example of a first coupling capacitance, the capacitive element 59G is an example of a second coupling capacitance, the capacitive element 64R is an example of a first capacitive element, and the capacitive element 64G is an example of a second capacitive element.

[0104] An electro-optical device according to a specific aspect 3 of aspect 1 includes a second data line, a second pixel circuit including a second light-emitting element provided corresponding to an intersection of the scanning line and the second data line and emitting light with a luminance according to the potential of the second data line, a second coupling capacitance having two electrodes, one electrode electrically connected to a second output line and the other electrode electrically connected to the second data line, a first capacitance element having two electrodes, one electrode electrically connected to the first data line, and a second capacitance element having two electrodes, one electrode electrically connected to the second data line. The output circuit outputs a second data signal, which is a potential corresponding to the luminance of the second light-emitting element, to the second output line, and the shift circuit shifts the potential of the first data line by shifting the other electrode potential of the first capacitive element before or after the second data signal is output, and shifts the potential of the first data line by shifting the other electrode potential of the second capacitive element, wherein the amount of shift of the other electrode potential of the first capacitive element is different from the amount of shift of the other electrode potential of the second capacitive element. According to the third aspect, even if the parasitic capacitance of the first data line and the parasitic capacitance of the second data line are different, the potentials after shifting can be made uniform, thereby improving the display quality.

[0105] In the electro-optical device according to a specific example 4 of example 1, the first pixel circuit is disposed between the first coupling capacitance and the output circuit and the first capacitive element and the shift circuit. According to example 4, it is possible to improve a situation in which the outer region of the region (display region) in which the pixel circuits are arranged is unevenly wide.

[0106] An electronic device according to a fifth aspect includes the electro-optical device according to any one of the first to fourth aspects. [Explanation of symbols]

[0107] 10...electro-optical device, 12...scanning line, 14...data line, 14c...data signal output line, 30...control circuit, 50...data signal output circuit, 41...DA conversion circuit, 59...capacitive element, 60...offset circuit, 62...NOT circuit, 64...capacitive element, 70...initialization circuit, 110, 110R, 110G, 110B...pixel circuit, 120...scanning line driving circuit, 121-125...transistor, 130...OLED.

Claims

1. Scan lines and a first data line; a first pixel circuit including a first light-emitting element provided at a location corresponding to an intersection of the scanning line and the first data line, the first light-emitting element emitting light at a luminance corresponding to the potential of the first data line; an output circuit that outputs a first data signal having a potential corresponding to the luminance of the first light-emitting element to a first output line; a first coupling capacitor having two electrodes, one of which is electrically connected to the first output line and the other of which is electrically connected to the first data line; a shift circuit that shifts the potential of the first data line before or after the first data signal is output; An electro-optical device comprising:

2. a second data line; a second pixel circuit including a second light-emitting element provided at a location corresponding to an intersection of the scanning line and the second data line, the second light-emitting element emitting light at a luminance corresponding to the potential of the second data line; a second coupling capacitor having two electrodes, one of which is electrically connected to the second output line and the other of which is electrically connected to the second data line; a first capacitance element having two electrodes, one of the electrodes being electrically connected to the first data line; a second capacitance element having two electrodes, one of the electrodes being electrically connected to the second data line; Including, the output circuit outputs a second data signal, which is a potential according to the luminance of the second light-emitting element, to the second output line; The shift circuit Before the second data signal is output or after the second data signal is output, shifting the potential of the other electrode of the first capacitance element to shift the potential of the first data line; shifting the potential of the other electrode of the second capacitive element to shift the potential of the second data line; The capacitance value of the first capacitance element is different from the capacitance value of the second capacitance element. The electro-optical device according to claim 1 .

3. a second data line; a second pixel circuit including a second light-emitting element provided at a location corresponding to an intersection of the scanning line and the second data line, the second light-emitting element emitting light at a luminance corresponding to the potential of the second data line; a second coupling capacitor having two electrodes, one of which is electrically connected to the second output line and the other of which is electrically connected to the second data line; a first capacitance element having two electrodes, one of the electrodes being electrically connected to the first data line; a second capacitance element having two electrodes, one of the electrodes being electrically connected to the second data line; Including, the output circuit outputs a second data signal, which is a potential according to the luminance of the second light-emitting element, to the second output line; The shift circuit Before the second data signal is output or after the second data signal is output, shifting the potential of the other electrode of the first capacitance element to shift the potential of the first data line; shifting the potential of the other electrode of the second capacitive element to shift the potential of the second data line; The amount of shift of the potential of the other electrode of the first capacitance element is different from the amount of shift of the potential of the other electrode of the second capacitance element. The electro-optical device according to claim 1 .

4. The first pixel circuit is disposed between the first coupling capacitance and the output circuit and the first capacitance element and the shift circuit. The electro-optical device according to claim 1 .

5. 5. An electronic device comprising the electro-optical device according to claim 1.

Images