Semiconductor device

Abstract

To provide a semiconductor device having a vertical type Hall element with which it is possible to cancel offsets with high accuracy.SOLUTION: A semiconductor device 1 comprises: a sensor signal transmission circuit 10 provided with a first vertical type Hall element 100 disposed in a first region of a semiconductor substrate 2 and having electrodes 111-115 arranged on a first line L1-L1 with a prescribed space therebetween, a current source 120, a first amplifier 110, and a first path and a second path that are openable and closable; and a sensor signal transmission circuit 20 provided with a second vertical type Hall element 200 disposed in a second region of the semiconductor substrate which is different from the first region, and having electrodes 211-215 arranged on a second line L2-L2 parallel to the first line L1-L1 with a prescribed space therebetween in the same number as the electrodes 111-115, a current source 220, a second amplifier 210, and a third path and a fourth path which are openable and closable and different from the first path and second path.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a vertical Hall element for detecting a magnetic field in a horizontal direction. [Background technology]

[0002] Hall elements are used in a variety of applications as magnetic sensors because they are capable of contactless position and angle detection. Among them, magnetic sensors using horizontal Hall elements that detect magnetic field components perpendicular to the surface of a semiconductor substrate (vertical magnetic field) are generally well known, but various magnetic sensors using vertical Hall elements that detect magnetic field components parallel to the surface of a semiconductor substrate (horizontal magnetic field) have also been proposed.

[0003] In a vertical Hall element, it is difficult to achieve a highly geometrically symmetric structure, so that the so-called offset voltage, which is output even when no magnetic field is applied, is more likely to occur than in a horizontal Hall element. Therefore, when using it as a magnetic sensor, it is necessary to remove such offset voltage, and the spinning current method is known as a method for doing so.

[0004] As a method for removing the offset voltage of a vertical Hall element using the spinning current method, there is a technique in which two (or more) vertical Hall elements having similar configurations are arranged in parallel, and the signals obtained by switching the connections of the electrodes of the vertical Hall elements are processed (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent Application Publication No. 2014 / 0210461 Summary of the Invention [Problem to be solved by the invention]

[0006] However, even if multiple vertical Hall elements are simultaneously formed on the same substrate by a semiconductor manufacturing process, it is extremely difficult to make the impurity concentration distribution and the like completely the same among the multiple vertical Hall elements. This results in characteristic variations among the multiple vertical Hall elements. Therefore, in each phase when the spinning current method is performed, the resistance of the current path is not completely equal, and there is a limit to improving the accuracy of offset cancellation.

[0007] In addition, when using the spinning current method to drive a vertical Hall element with a combination of, for example, four different current directions, offset cancellation is possible with a spinning current if an ideal power supply is used. However, since there is variation in the characteristics of actual power supplies, there is variation in the ability to drive the Hall element. For this reason, when higher accuracy in offset cancellation is required, the effect of variation in the characteristics of the power supply cannot be ignored.

[0008] The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a semiconductor device having a vertical Hall element that can achieve offset cancellation by the spinning current method with higher accuracy. [Means for solving the problem]

[0009] The semiconductor device of the present invention includes a first vertical Hall element provided in a first region of a semiconductor substrate, the first vertical Hall element having at least four electrodes arranged on a first straight line at a predetermined interval in the order of a first electrode, a second electrode, a third electrode, and a fourth electrode, a first driving power source for driving the first vertical Hall element, and a first driving power source configured to openably connect the first electrode and the third electrode of the first vertical Hall element to the first driving power source, while not connecting the second electrode and the fourth electrode of the first vertical Hall element to the first driving power source, a first path formed by connecting the second electrode and the fourth electrode of the first vertical Hall element to the first amplifier in an openable and closable manner, respectively, while the first electrode and the third electrode of the first vertical Hall element to the first amplifier in a non-connectable manner, and a first sensor signal transmission circuit for obtaining a first output signal from the first amplifier; a second vertical Hall element having the same number of electrodes as the first vertical Hall element, including at least four electrodes arranged on a straight line at a predetermined interval therebetween in the order of a first electrode, a second electrode, a third electrode and a fourth electrode; a second driving power source provided separately from the first driving power source for driving the second vertical Hall element; and a power source for connecting the second electrode and the fourth electrode of the second vertical Hall element to the second driving power source in an openable manner, while connecting the first electrode and the third electrode of the second vertical Hall element to the second driving power source in an openable manner. a third path formed so as to be disconnected from the first amplifier and a second amplifier provided separately from the first amplifier and amplifying an output voltage from the second vertical Hall element; a fourth path formed so as to openably and closably connect the first electrode and the third electrode of the second vertical Hall element to the second amplifier, respectively, while the second electrode and the fourth electrode of the second vertical Hall element are not connected to the second amplifier, and a second sensor signal transmission circuit for obtaining a second output signal from the second amplifier. Effect of the Invention

[0010] According to the present invention, the spinning current method can be performed in a state where the characteristics of a plurality of vertical Hall elements, including the characteristics of the power source for driving the vertical Hall elements, are substantially the same, thereby enabling more accurate offset cancellation. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a schematic diagram for explaining a semiconductor device (first phase) having a vertical Hall element according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a schematic diagram for explaining a semiconductor device (second phase) having a vertical Hall element according to the first embodiment of the present invention. [Diagram 3] FIG. 3 is a cross-sectional view corresponding to the cross section taken along line III-III (FIG. 1). [Figure 4] FIG. 11 is a schematic diagram for explaining a semiconductor device (first phase) having a vertical Hall element according to a second embodiment of the present invention. [Diagram 5] FIG. 11 is a circuit diagram illustrating a schematic configuration of an amplifier in a semiconductor device having a vertical Hall element according to a second embodiment of the present invention. [Figure 6] FIG. 11 is a schematic diagram for explaining a semiconductor device (first phase) having a vertical Hall element according to a third embodiment of the present invention. [Figure 7] 13 is an explanatory diagram for explaining magnetoelectric conversion characteristics of a semiconductor device having a vertical Hall element according to a third embodiment. FIG. [Figure 8] 13 is a schematic diagram for explaining a second configuration example of a semiconductor device having a vertical Hall element according to a third embodiment. FIG. [Figure 9] 13 is a schematic diagram for explaining a third configuration example of a semiconductor device having a vertical Hall element according to a third embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiment of the present invention will be described in detail with reference to the drawings. In the description, directions such as up, down, left, and right are based on the illustrated state unless otherwise specified. X, Y, and Z shown in Fig. 1 represent the axes constituting a three-axis Cartesian coordinate system.

[0013] [First embodiment] 1 and 2 are schematic diagrams for explaining a semiconductor device 1 as a semiconductor device having a vertical Hall element according to a first embodiment of the present invention. More specifically, Fig. 1 shows a case where the direction of current flowing through the vertical Hall elements 100 and 200 during the spinning current method is set to a first state (first phase), and Fig. 2 shows a case where the direction of current flowing through the vertical Hall elements 100 and 200 during the spinning current method is set to a second state that is the opposite direction to the first state (second phase).

[0014] The semiconductor device 1 includes a plurality of sensor signal transmission circuits 10, 20, for example two, formed on the same semiconductor substrate 2, and an adder 130 that adds up the output signals of the sensor signal transmission circuits 10, 20. Although not shown in Figures 1 and 2, the semiconductor device 1 includes a power supply terminal that supplies a first power supply voltage, and a ground terminal that supplies a power supply voltage of 0V (zero volts) (hereinafter referred to as "ground voltage") as an example of a power supply voltage that is different from the first power supply voltage and serves as a reference for circuit operation.

[0015] The sensor signal transmission circuit 10 includes a vertical Hall element 100, a current source 120 as a drive power supply, an amplifier 110, switches S11 to S14, and switches S15 to S18. The sensor signal transmission circuit 20 includes a vertical Hall element 200, a current source 220 as a drive power supply, an amplifier 210, switches S21 to S24, and switches S25 to S28.

[0016] The vertical Hall elements 100 and 200 have, for example, five electrodes 111-115 and electrodes 211-215 arranged at predetermined intervals on a straight line L1-L1 and a straight line L2-L2, respectively, shown in Fig. 1, and have substantially the same structure. Moreover, the vertical Hall elements 100 and 200 are arranged such that the straight line L1-L1 and the straight line L2-L2 are parallel to each other.

[0017] The current source 120 is openably connected to the electrodes 111, 113, and 115, which are part of the electrodes 111-115 of the vertical Hall element 100, via the switches S11-S14, while being disconnected from the electrodes 112 and 114, which are the other part of the electrodes 111-115. That is, the input terminal of the current source 120 is connected to the electrodes 111 and 115 via the switch S11, and is connected to the electrode 113 via the switch S12. The output terminal of the current source 120 is connected to the electrodes 111 and 115 via the switch S13, and is connected to the electrode 113 via the switch S14.

[0018] On the other hand, the current source 220 is openably connected to the electrodes 212 and 214 which are part of the electrodes 211 to 215 included in the vertical Hall element 200 via the switches S21 to S24, but is not connected to the electrodes 211, 213, and 215 which are the other part of the electrodes 211 to 215. That is, the input terminal of the current source 220 is connected to the electrode 212 via the switch S21, and is connected to the electrode 214 via the switch S22. The output terminal of the current source 220 is connected to the electrode 212 via the switch S23, and is connected to the electrode 214 via the switch S24.

[0019] Here, the positional relationship between the electrodes 111, 113, and 115 connected to the current source 120 in an openable / closeable manner in the vertical Hall element 100 and the electrodes 212 and 214 connected to the current source 220 in an openable / closeable manner in the vertical Hall element 200 is an exclusive relationship. Explaining with reference to Fig. 1, the electrodes 111, 113, and 115 connected to the current source 120 in an openable / closeable manner are the first, third, and fifth from the left, while the electrodes 212 and 214 connected to the current source 220 in an openable / closeable manner are the second and fourth from the left, which are the remaining portions. Conversely, the electrodes 112 and 114 not connected to the current source 120 are the second and fourth from the left, while the electrodes 211, 213, and 215 not connected to the current source 220 are the first, third, and fifth from the left, which are the remaining portions.

[0020] The amplifier 110 is configured to be connected to the vertical Hall element 100 via switches S15 to S18. That is, a non-inverting input terminal (+) of the amplifier 110 is connected to the electrode 112 via switch S15 and to the electrode 114 via switch S16, and an inverting input terminal (-) of the amplifier 110 is connected to the electrode 112 via switch S17 and to the electrode 114 via switch S18. The electrodes 111, 113, and 115 other than the electrodes 112 and 114 connected to the amplifier 110 are not connected to the amplifier 110.

[0021] On the other hand, the amplifier 210 is configured to be connected to the vertical Hall element 200 via switches S25 to S28. That is, an inverting input terminal (-) of the amplifier 210 is connected to the electrodes 211 and 215 via switch S25, and is connected to the electrode 213 via switch S26. A non-inverting input terminal (+) of the amplifier 210 is connected to the electrodes 211 and 215 via switch S27, and is connected to the electrode 213 via switch S28. The electrodes 212 and 214 other than the electrodes 211, 213, and 215 connected to the amplifier 210 are not connected to the amplifier 210.

[0022] The vertical Hall element 100 and the vertical Hall element 200 are simultaneously formed on the same semiconductor substrate by a semiconductor manufacturing process. An example of the structure of the vertical Hall elements 100 and 200 will now be described with reference to Fig. 3. Fig. 3 is a cross-sectional view corresponding to the cross section taken along line III-III of the semiconductor device shown in Fig. 1.

[0023] The vertical Hall elements 100 and 200 are formed in regions RA and RB, respectively, of a P-type (first conductivity type) semiconductor substrate 101. The regions RA and RB are electrically isolated from each other by a P-type element isolation diffusion layer 103 formed in an N-type (second conductivity type) semiconductor layer 102 provided on the semiconductor substrate 101. The electrodes 111-115 of the vertical Hall element 100 and the electrodes 211-215 of the vertical Hall element 200 are formed of N-type impurity regions having a higher concentration than the semiconductor layer 102 and provided adjacent to the surface of the semiconductor layer 102 in the regions RA and RB, respectively.

[0024] Although not shown in FIG. 3, the current sources 120 and 220, the amplifiers 110 and 210, and the switches S11 to S18 and S21 to S28 shown in FIGS. 1 and 2 are also formed in a region other than the regions RA and RB of the semiconductor substrate 101 and are electrically isolated from the vertical Hall elements 100 and 200 by the element isolation diffusion layer 103.

[0025] 3 shows an example in which the vertical Hall element 100 and the vertical Hall element 200 are arranged side by side in the X (horizontal) direction, that is, the straight line L1-L1 and the straight line L2-L2 shown in FIG. 1 are arranged in the same straight line, but the vertical Hall element 100 and the vertical Hall element 200 may be arranged in any manner as long as the straight line L1-L1 and the straight line L2-L2 are arranged in parallel. For example, the vertical Hall element 100 and the vertical Hall element 200 may be arranged side by side in the Y (vertical) direction, that is, the vertical Hall element 100 may be arranged on the front side (front) of the paper and the vertical Hall element 200 may be arranged on the back side (rear) of the paper in FIG. 1 and FIG. 2. Furthermore, the vertical Hall element 100 and the vertical Hall element 200 do not necessarily need to be arranged adjacent to each other. For example, it is also possible to arrange the current sources 120 and 220, the amplifiers 110 and 210, etc. between the vertical Hall element 100 and the vertical Hall element 200.

[0026] Next, a method of offset cancellation by the spinning current method using the vertical Hall elements 100 and 200 in the semiconductor device of this embodiment (hereinafter referred to as the "first offset cancellation method") will be described. A magnetic field is applied in the direction of the arrow B shown in Figs. 1 and 2.

[0027] 1, in the first phase, the switches S11, S14, S15, and S18 connected to the vertical Hall element 100 and the switches S21, S24, S25, and S28 connected to the vertical Hall element 200 are turned on (closed), and the switches S12, S13, S16, and S17 connected to the vertical Hall element 100 and the switches S22, S23, S26, and S27 connected to the vertical Hall element 200 are turned off (open). The switches S11 to S18 and S21 to S28 are switched on and off by a control circuit (not shown).

[0028] As a result, a drive current is supplied from the current source 120 to the vertical Hall element 100 so that the current flows from the electrode 113 to the electrodes 111 and 115 at both ends (the direction of the current at this time is referred to as the “first current direction”), and a potential difference is generated between the electrodes 112 and 114. Since the switches S15 and S18 are on and the non-inverting input terminal (+) of the amplifier 110 is connected to the electrode 112 and the inverting input terminal (−) is connected to the electrode 114, the amplifier 110 amplifies the potential difference between the electrodes 112 and 114 and outputs it to the adder 130.

[0029] A drive current is supplied from the current source 220 to the vertical Hall element 200 so that the current flows from the electrode 212 to the electrode 214 (the direction of the current at this time is referred to as the “second current direction”), and a potential difference is generated between the electrode 213 and the electrodes 211 and 215. Since the switches S25 and S28 are on and the non-inverting input terminal (+) of the amplifier 210 is connected to the electrode 213 and the inverting input terminal (−) is connected to the electrodes 211 and 215, the amplifier 210 amplifies the potential difference between the electrode 213 and the electrodes 211 and 215 and outputs it to the adder 130.

[0030] Adder 130 adds the output signal of amplifier 110 and the output signal of amplifier 210, and outputs the first phase output voltage (hereinafter referred to as "output voltage VOUT1") to output terminal 131. The output voltage VOUT1 is held by a sample-and-hold circuit (not shown in FIGS. 1 and 2) or the like.

[0031] Next, as shown in FIG. 2, in the second phase, the switches S12, S13, S16, and S17 connected to the vertical Hall element 100 and the switches S22, S23, S26, and S27 connected to the vertical Hall element 200 are turned on (closed), and the switches S11, S14, S15, and S18 connected to the vertical Hall element 100 and the switches S21, S24, S25, and S28 connected to the vertical Hall element 200 are turned off (open).

[0032] As a result, a drive current is supplied from the current source 120 to the vertical Hall element 100 so that a current flows from the electrodes 111 and 115 at both ends to the electrode 113, i.e., in a direction opposite to the first current direction (the current direction at this time is referred to as a “third current direction”), and a potential difference is generated between the electrodes 112 and 114. Since the switches S16 and S17 are on and the non-inverting input terminal (+) of the amplifier 110 is connected to the electrode 114 and the inverting input terminal (−) is connected to the electrode 112, the amplifier 110 amplifies the potential difference between the electrodes 114 and 112 and outputs it to the adder 130.

[0033] A drive current is supplied from the current source 220 to the vertical Hall element 200 so that the current flows from the electrode 214 to the electrode 212, i.e., in a direction opposite to the second current direction (the current direction at this time is referred to as a “fourth current direction”), and a potential difference is generated between the electrodes 211 and 215 and the electrode 213. Since the switches S26 and S27 are on and the non-inverting input terminals (+) of the amplifier 210 are connected to the electrodes 211 and 215 and the inverting input terminal (−) is connected to the electrode 213, the amplifier 210 amplifies the potential difference between the electrodes 211 and 215 and the electrode 213 and outputs it to the adder 130.

[0034] The adder 130 adds the output signal of the amplifier 110 and the output signal of the amplifier 210 together, and outputs to the output terminal 131 an output voltage of the second phase (hereinafter, referred to as an “output voltage VOUT2”).

[0035] Then, by subtracting the output voltage VOUT1 obtained in the first phase from the output voltage VOUT2 obtained in the second phase, it is possible to obtain the final output voltage VOUT from which the offset voltage has been removed (hereinafter referred to as the "final output voltage").

[0036] Although the vertical Hall element 100 and the vertical Hall element 200 are simultaneously formed on the same semiconductor substrate by a semiconductor manufacturing process, it is very difficult to make the impurity concentration distribution and the like completely the same between the two elements. For this reason, there is a characteristic variation between the vertical Hall element 100 and the vertical Hall element 200.

[0037] Therefore, in this embodiment, the vertical Hall element 100 and the vertical Hall element 200 are configured to be driven by separate current sources 120 and 220. With this configuration, the drive currents of the vertical Hall element 100 and the vertical Hall element 200 can be adjusted separately.

[0038] That is, the current value of the current source 120 and the current value of the current source 220 are set to the same current value (hereinafter referred to as "initial current value") in advance, and the output voltages of the vertical Hall element 100 and the vertical Hall element 200 are measured when driving currents of the same direction and current amount are supplied to them. Then, based on the difference between the measured output voltages, the current value of the current source 120 and the current value of the current source 220 are adjusted so as to correct this difference. This makes it possible to substantially compensate for the characteristic variation between the vertical Hall element 100 and the vertical Hall element 200. Therefore, it becomes possible to perform offset cancellation by the spinning current method with high accuracy.

[0039] It is preferable to adjust the current values ​​of the current sources 120 and 220 so that the total current value (drive current) is constant by, for example, increasing the current value of the current source 120 by α from the initial current value and decreasing the current value of the current source 220 by α from the initial current value. This makes it possible to eliminate the need to adjust the circuits of the amplifiers 110, 210, etc. on the output side of the vertical Hall elements 100 and 200.

[0040] In addition, in this embodiment, the outputs of the vertical Hall elements 100 and 200 are amplified by separate amplifiers 110 and 210, respectively. By adjusting the gains of the amplifiers 110 and 210, it is also possible to compensate for the characteristic variation between the vertical Hall elements 100 and 200.

[0041] On the other hand, although not shown in the figure, the output sides of the vertical Hall elements 100 and 200 may be appropriately connected and the output voltage may be amplified by one amplifier. In this case, it is no longer possible to compensate for the characteristic variation between the vertical Hall element 100 and the vertical Hall element 200 by adjusting the gains of the two amplifiers 110 and 210 as described above, but the circuit scale can be reduced because only one amplifier is required.

[0042] Furthermore, according to this embodiment, the directions of the drive currents in the first and second phases of each of the vertical Hall elements 100 and 200 are the same but opposite, so that even if there is a characteristic variation in the current sources 120 and 220 serving as drive power sources, the influence of the characteristic variation can be eliminated. That is, the spinning current method can be performed in a state in which the characteristics of the current sources 120 and 220 that drive the vertical Hall elements 100 and 200 are substantially the same. Therefore, offset cancellation with higher accuracy is possible.

[0043] [Second embodiment] FIG. 4 is a schematic diagram for explaining a semiconductor device 31 (first phase) as a semiconductor device having a vertical Hall element according to the second embodiment of the present invention.

[0044] The semiconductor device 31 differs from the semiconductor device 1 in that it includes sensor signal transmission circuits 10A and 20A instead of the sensor signal transmission circuits 10 and 20, but is not substantially different in other respects. To explain in more detail, the sensor signal transmission circuit 10A differs from the sensor signal transmission circuit 10 in that it includes an amplifier 170 capable of individually adjusting a tail current instead of the amplifier 110, and the sensor signal transmission circuit 20A differs from the sensor signal transmission circuit 20 in that it includes an amplifier 270 capable of individually adjusting a tail current instead of the amplifier 210. However, the sensor signal transmission circuits 10A and 20A are not substantially different from the sensor signal transmission circuits 10 and 20 in other respects except that they include the amplifiers 170 and 270, respectively. Therefore, in this embodiment, the sensor signal transmission circuits 10A and 20A will be mainly described, and components that are not substantially different from the sensor signal transmission circuits 10 and 20 will be denoted by the same reference numerals and their description will be omitted.

[0045] The semiconductor device 31 includes a plurality of sensor signal transmission circuits 10A, 20A, for example, two, formed on the same semiconductor substrate 2. The sensor signal transmission circuit 10A includes a vertical Hall element 100, a current source 120, an amplifier 170, switches S11 to S14, and switches S15 to S18. The sensor signal transmission circuit 20A includes a vertical Hall element 200, a current source 220, an amplifier 270, switches S21 to S24, and switches S25 to S28. The amplifiers 170 and 270 are configured by adding a current value adjustment function for the tail current of the differential pair to the amplifiers 110 and 210, respectively. The current value adjustment function for the tail current is provided by variable current sources 179, 279.

[0046] FIG. 5 is a circuit diagram showing a schematic configuration example of the amplifiers 170 and 270. As shown in FIG. The amplifier 170 includes, for example, a differential pair including NMOS transistors 177 and 178, and a variable current source 179 capable of adjusting the current value of the tail current of the differential pair. The variable current source 179 has a first terminal connected to each of the sources of the NMOS transistors 177 and 178, and a second terminal connected to the ground terminal 3.

[0047] The amplifier 270 has, for example, a differential pair including NMOS transistors 277 and 278, and a variable current source 279 capable of adjusting the current value of the tail current of the differential pair. The variable current source 279 has a first end connected to the sources of the NMOS transistors 277 and 278, and a second end connected to the ground terminal 3. The drain of the NMOS transistor 277 is connected to the drain of the NMOS transistor 177. The drain of the NMOS transistor 278 is connected to the drain of the NMOS transistor 178. That is, the amplifiers 170 and 270 are connected by a drain connection.

[0048] The method of offset cancellation by the spinning current method using the vertical Hall elements 100 and 200 in the semiconductor device 31 (hereinafter referred to as the "second offset cancellation method") differs from the first offset cancellation method in that it further includes a step of adjusting the current value of the tail current of the differential pair, which is performed as necessary, but is not substantially different in other respects. The step of adjusting the current value of the tail current of the NMOS transistors 177 and 178 constituting the differential pair in the amplifier 170 is performed by adjusting the current value of the variable current source 179. The step of adjusting the current value of the tail current of the NMOS transistors 277 and 278 constituting the differential pair in the amplifier 270 is performed by adjusting the current value of the variable current source 279.

[0049] According to this embodiment, in addition to obtaining the same effects as those of the semiconductor device 1 and the first offset cancellation method, when the drive current difference between the vertical Hall elements 100 and 200 alone is not sufficient for compensation, an additional compensation effect can be obtained by utilizing the tail current difference.

[0050] [Third embodiment] FIG. 6 is a schematic diagram for explaining a semiconductor device 51 (first phase) as a semiconductor device having a vertical Hall element according to the third embodiment of the present invention.

[0051] Semiconductor device 51 differs from semiconductor device 1 in that it further includes a sample-and-hold circuit 140, a comparator 150, and a reference voltage circuit 152, i.e., in that the current values ​​of current sources 120 and 220 are adjustable and a hysteresis characteristic is added to the output voltage of semiconductor device 1 output from output terminal 131; however, there is no substantial difference in other respects.

[0052] In addition, the semiconductor device 51 includes the semiconductor device 1, and the open / close states of the switches S11 to S18 and the switches S21 to S28 in the first and second phases of the semiconductor device 51 are the same as the open / close states of the switches S11 to S18 and the switches S21 to S28 in the first and second phases of the semiconductor device 1. That is, if the semiconductor device 1 shown in Fig. 2 is further provided with a sample-and-hold circuit 140, a comparator 150, and a reference voltage circuit 152, the semiconductor device 51 will be in the second phase. Therefore, in this embodiment, components different from the semiconductor device 1 will be mainly described, and components that are not substantially different from the semiconductor device 1 will be denoted by the same reference numerals and their description will be omitted.

[0053] The semiconductor device 51 further includes a sample hold circuit 140, a comparator 150, and a reference voltage circuit 152 in addition to the configuration of the semiconductor device 1. The sample hold circuit 140 has an input terminal connected to the adder 130 and an output terminal connected to the comparator 150. The comparator 150 has a non-inverting input terminal (+) connected to the output terminal of the sample hold circuit 140, an inverting input terminal (-) connected to the positive terminal of the reference voltage circuit 152, and an output terminal 151. The output terminal 151 of the comparator 150 is connected to the output terminal 131 of the semiconductor device 51. The node N1, which is the same as the connection point between the output terminal 151 and the output terminal 131, is connected to the control terminals of the current sources 120 and 220.

[0054] The sample and hold circuit 140 holds the output voltage VOUT1 in the above-mentioned first phase, and further subtracts the held output voltage VOUT1 from the output voltage VOUT2 in the second phase, and outputs the subtraction result to the non-inverting input terminal (+) of the comparator 150 as the final output voltage VOUT.

[0055] The final output voltage VOUT, which is the output voltage of the sample and hold circuit 140, is input to a non-inverting input terminal (+) of the comparator 150. The positive terminal of a reference voltage circuit 152 is connected to an inverting input terminal (-) of the comparator 150, and a reference voltage VREF is input thereto. The negative terminal of the reference voltage circuit 152 is connected to the ground terminal 3. The comparator 150 compares the final output voltage VOUT with the reference voltage VREF and outputs the result as an output signal CMPOUT from an output terminal 151. The output signal CMPOUT is input to the current sources 120 and 220, respectively.

[0056] As described above, the current values ​​of the current sources 120 and 220 are adjusted in advance to compensate for the characteristic variation between the vertical Hall element 100 and the vertical Hall element 200, and the current values ​​of the current sources 120 and 220 are configured to be switched between two values ​​based on the adjusted current value according to the output signal CMPOUT of the comparator 150.

[0057] Here, since the reference voltage VREF (≧0V) is input to the inverting input terminal (−) of the comparator 150, the comparator 150 outputs an output signal CMPOUT according to the voltage value of the final output voltage VOUT at the non-inverting input terminal (+) as follows: When VOUT>VREF, CMPOUT=“H” V <VREFのとき、CMPOUT=“L”

[0058] Next, the operation of the semiconductor device according to this embodiment will be described with reference to Fig. 7. The arrows marked with circled numbers 1, 2, 3, and 4 shown in Fig. 7 will be referred to as "Arrow 1," "Arrow 2," "Arrow 3," and "Arrow 4," respectively.

[0059] Fig. 7 is an explanatory diagram for explaining the magnetoelectric conversion characteristics of the semiconductor device 51. In Fig. 7, the horizontal axis represents the applied magnetic flux density B, and the vertical axis represents the final output voltage VOUT of the sample-and-hold circuit 140 (the input voltage to the non-inverting input terminal (+) of the comparator 150). In order to simplify the explanation, Fig. 7 also shows the case where a reference voltage VREF of 0V is input.

[0060] If the current values ​​of the current sources 120 and 220 are I1 and I2, respectively, and α and β are constants, then When CMPOUT = “H”, I1 = I(1 + α + β), I2 = I(1-α-β) When CMPOUT = “L”, I1 = I(1+α-β), I2 = I(1-α+β) As described above, by switching the current values ​​of the current sources 120 and 220 between two values ​​according to the output signal CMPOUT of the comparator 150, the final output voltage VOUT of the sample-and-hold circuit 140 can be given magnetoelectric conversion characteristics with equal slopes and intercepts (the value of VOUT when B=0) offset by ±VOS.

[0061] Here, α is a value adjusted in advance to compensate for the characteristic variation between the vertical Hall element 100 and the vertical Hall element 200. The straight line corresponding to β=0 represents the magnetoelectric conversion characteristic in which the characteristic variation is compensated for by adding or subtracting the above α to each of the current value I1 of the current source 120 and the current value I2 of the current source 220. β is set arbitrarily according to the desired hysteresis width BHYS.

[0062] When the applied magnetic flux density B increases from zero in the positive (south pole) direction, the final output voltage VOUT of the sample-and-hold circuit 140 increases along the straight line corresponding to CMPOUT="L" (corresponding to arrow 1 in the figure). When VOUT>0, the output signal CMPOUT of the comparator 150 transitions from "L" to "H", and the magnetoelectric conversion characteristic for the applied magnetic flux density B is switched to the straight line corresponding to CMPOUT="H" (corresponding to arrow 2 in the figure). The applied magnetic flux density B at this time is the operating point BOP.

[0063] Next, when the applied magnetic flux density B increases in the negative (N pole) direction, the final output voltage VOUT of the sample-and-hold circuit 140 decreases along the straight line corresponding to CMPOUT="H" (corresponding to arrow 3 in the figure). When VOUT<0, the output signal CMPOUT of the comparator 150 transitions from "H" to "L", and the magnetoelectric conversion characteristic for the applied magnetic flux density B is switched again to the straight line corresponding to CMPOUT="L" (corresponding to arrow 4 in the figure). The applied magnetic flux density B at this time is the return point BRP.

[0064] In this way, by providing hysteresis to the magnetoelectric conversion characteristic, it is possible to realize an alternating detection characteristic with a hysteresis width BHYS. Therefore, a circuit for switching the signal transmission polarity of the signal path, which is usually provided to add a hysteresis characteristic to the output side of the sample-and-hold circuit 140 (the rear stage of the sample-and-hold circuit 140), is not required, and it is only necessary to add a comparator with a simple configuration, so that the occupied area can be reduced.

[0065] A predetermined voltage other than 0V may be input as the reference voltage VREF to the inverting input terminal (-) of the comparator 150. In that case, the inversion level of the magnetoelectric conversion characteristic of the final output voltage VOUT of the sample-and-hold circuit 140 becomes VREF instead of 0. When VOUT>VREF, CMPOUT=“H” V <VREFのとき、CMPOUT=“L” and the operating point BOP and the return point BRP are offset according to the absolute value and polarity of a predetermined reference voltage VREF. In other words, if a reference voltage VREF (>0) is input so that the operating point BOP and the return point BRP are both positive, an S-pole detection characteristic having an operating point BOP and a return point BRP on the S-pole side can be realized. Also, if a reference voltage VREF (<0) is input so that the operating point BOP and the return point BRP are both negative, an N-pole detection characteristic having an operating point BOP and a return point BRP on the N-pole side can be realized.

[0066] As for the method of performing offset cancellation by the spinning current method using the vertical Hall elements 100 and 200 in the semiconductor device 51, the processing steps are not substantially different from those of the first offset cancellation method described above, and therefore a description thereof will be omitted.

[0067] As described above, according to the semiconductor device of the above-mentioned embodiment of the present invention, the current source 220 for driving the vertical Hall element 200 is provided separately from the current source 120 for driving the vertical Hall element 100. Therefore, by adjusting the direction of the driving current to the same path and opposite direction while making the current values ​​of the current sources 120 and 220 the same in the first phase and the second phase, even if the current sources 120 and 220 have characteristic variations, the influence of the characteristic variations can be eliminated. That is, the spinning current method can be performed in a state where the characteristics of the current sources 120 and 220 for driving the vertical Hall elements 100 and 200 are substantially the same. Therefore, highly accurate offset cancellation is possible.

[0068] It is also possible to add hysteresis characteristics to the final output voltage VOUT by controlling the switching of the current values ​​of the current source 120 and the current source 220 based on the output signal CMPOUT of the comparator 150. Therefore, it is not necessary to add a special circuit for adding hysteresis characteristics, which is usually provided in the subsequent stage of the final output voltage VOUT, and therefore the area of ​​the entire semiconductor device can be reduced.

[0069] Although the embodiment of the present invention has been described above, it goes without saying that the present invention is not limited to the above embodiment, and various modifications are possible without departing from the spirit of the present invention.

[0070] For example, the semiconductor device according to the present embodiment, such as the semiconductor device 1, includes the adder 130, but the adder 130 may be provided in a separate device. That is, the semiconductor device according to the present embodiment may include at least sensor signal transmission circuits having different transmission paths connecting the driving power supplies to the amplifiers, and may be configured to be able to extract amplifier output signals transmitted through the different transmission paths.

[0071] The semiconductor device 51 (FIG. 6) illustrated as an example of the semiconductor device according to the third embodiment is a configuration example (first configuration example) in which a hysteresis characteristic is added to the final output voltage VOUT of the semiconductor device 1, but is not limited to this example. It is also applicable to semiconductor devices other than the semiconductor device 1 in which a hysteresis characteristic is not added to the final output voltage VOUT.

[0072] 8 and 9 are schematic diagrams for explaining other (second and third configuration examples) of the semiconductor device having the vertical Hall element according to the third embodiment, respectively.

[0073] For example, the semiconductor device 71 (FIG. 8) is an example of a configuration in which a hysteresis characteristic can be added to the final output voltage VOUT of the semiconductor device 31. The semiconductor device 51 shown in FIG. 6 and the semiconductor device 71 shown in FIG. 8 are examples in which the current values ​​of both the current sources 120 and 220 are switched by the output signal CMPOUT of the comparator 150, but the current value of one of the current sources 120 and 220 may be configured to be switchable while the current value of the other may not be switchable. The semiconductor device 71 may also be configured such that the current values ​​of both or either of the variable current sources 179 and 279 are switched by the output signal CMPOUT of the comparator 150. Furthermore, the semiconductor device 71 may be used in combination with a configuration in which the current values ​​of both or either of the current sources 120 and 220 are switched by the output signal CMPOUT of the comparator 150.

[0074] Furthermore, in the above embodiment, an example in which a current source is used as a driving power source is shown, but a voltage source can be used instead of the current source. In this case, the driving current of the vertical Hall element is adjusted by adjusting the voltage value of the voltage source. For example, the current sources 120 and 220 of the semiconductor device 71 (FIG. 8) may be replaced with voltage sources 160 and 260, and the voltage value of the voltage source 260 among the voltage sources 160 and 260 may be switched, or a semiconductor device 91 (FIG. 9) may be configured to switch the current value of the variable current source 279 in addition to the voltage value of the voltage source 260.

[0075] In the above embodiment, the semiconductor device having two vertical Hall elements is described as an example, but the present invention can also be applied to a semiconductor device having three or more vertical Hall elements. In that case, as in the above embodiment, the same number of driving power supplies as the number of vertical Hall elements are provided, and each vertical Hall element is driven by an independent driving power supply, so that characteristic errors occurring in the semiconductor manufacturing process of the vertical Hall elements can be corrected. In particular, if four vertical Hall elements are provided, driving currents in the first current direction to the fourth current direction can be supplied to each vertical Hall element at once, so that the time required for offset cancellation can be shortened. Furthermore, if eight vertical Hall elements are provided, driving currents in four directions can be supplied to two vertical Hall elements each, so that even more accurate offset cancellation is possible.

[0076] In the above embodiment, the amplifier 110 and the amplifier 210 are connected to the vertical Hall element 100 and the vertical Hall element 200, respectively, and the output signal of the amplifier 110 and the output signal of the amplifier 210 are added by the adder 130. However, it is also possible to obtain a signal by adding output signals obtained from one amplifier, such as the amplifier 110, by time-division processing using the one amplifier.

[0077] More specifically, first, the output voltage difference obtained by driving the vertical Hall element 100 in the state shown in FIG. 1 is amplified by the one amplifier to obtain a first output signal, then the output voltage difference obtained by driving the vertical Hall element 200 in the state shown in FIG. 1 is amplified by the same amplifier to obtain a second output signal, then the output voltage difference obtained by driving the vertical Hall element 100 in the state shown in FIG. 2 is amplified by the same amplifier to obtain a third output signal, and finally the output voltage difference obtained by driving the vertical Hall element 200 in the state shown in FIG. 2 is amplified by the same amplifier to obtain a fourth output signal, and the fourth output signal may be added or subtracted from the first output signal. This reduces the number of amplifiers to one, making it possible to reduce the circuit scale. However, since the process is time-division, the time required for offset cancellation is long, so that when high speed is required, it is preferable to provide an amplifier corresponding to each vertical Hall element as described above.

[0078] In the above embodiment, the vertical Hall element 100 and the vertical Hall element 200 have five electrodes 111-115 and five electrodes 211-215, respectively, but the present invention is not limited to this. As long as the number of electrodes of the vertical Hall element 100 and the vertical Hall element 200 is equal to or greater than four, the vertical Hall elements 100 and 200 may have any number of electrodes. For example, in the case of the vertical Hall elements 100 and 200 illustrated in FIG. 1 and the like, the electrodes 111 or 115 and the electrodes 211 or 215 may be omitted to have four electrodes each.

[0079] In the above embodiment, the first conductivity type is P type and the second conductivity type is N type, but the conductivity types may be interchanged, with the first conductivity type being N type and the second conductivity type being P type. These embodiments and modifications are included within the scope and spirit of the invention, and are included in the claims and their equivalents. [Explanation of symbols]

[0080] 1,31,51,71,91 Semiconductor device 2. Semiconductor Substrate 10,10A,20,20A Sensor signal transmission circuit 100, 200 Vertical Hall element 110,170,210,270 Amplifier 111~115,211~215 electrode 120,220 Current source (driving power supply) 130 Adder 131 Output terminal 140 Sample and hold circuit 150 Comparator 160,260 Voltage source (driving power supply) S11~S18, S21~S28 Switches RA,RB area L1-L1 First line L2-L2 Second line

Claims

1. a first vertical Hall element provided in a first region of a semiconductor substrate, the first vertical Hall element having at least four electrodes arranged in the order of a first electrode, a second electrode, a third electrode, and a fourth electrode at predetermined intervals on a first straight line; a first driving power supply for driving the first vertical Hall element; a first path that connects the first electrode and the third electrode of the first vertical Hall element to the first driving power supply in an openable and closable manner, respectively, while disconnecting the second electrode and the fourth electrode of the first vertical Hall element from the first driving power supply, respectively; a first amplifier that amplifies an output voltage from the first vertical Hall element; a second path that connects the second electrode and the fourth electrode of the first vertical Hall element to the first amplifier in an openable and closable manner, while disconnecting the first electrode and the third electrode of the first vertical Hall element from the first amplifier; a first sensor signal transmission circuit that obtains a first output signal from the first amplifier; a second vertical Hall element having the same number of electrodes as the first vertical Hall element, the second vertical Hall element including at least four electrodes arranged in a second region of the semiconductor substrate different from the first region, the first electrode, the second electrode, the third electrode, and the fourth electrode in this order, at the predetermined intervals on a second straight line parallel to the first straight line; a second driving power supply provided separately from the first driving power supply and configured to drive the second vertical Hall element; a third path that connects the second electrode and the fourth electrode of the second vertical Hall element to the second driving power supply in an openable and closable manner, respectively, while disconnecting the first electrode and the third electrode of the second vertical Hall element from the second driving power supply, respectively; a second amplifier provided separately from the first amplifier and configured to amplify an output voltage from the second vertical Hall element; a fourth path that connects the first electrode and the third electrode of the second vertical Hall element to the second amplifier in an openable and closable manner, while disconnecting the second electrode and the fourth electrode of the second vertical Hall element from the second amplifier; a second sensor signal transmission circuit that obtains a second output signal from the second amplifier; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , further comprising an adder that adds the first output signal and the second output signal.

3. 2. The semiconductor device according to claim 1, wherein the driving power supply is either a current source or a voltage source.

4. an adder that adds the first output signal and the second output signal; a sample-and-hold circuit that holds a first output voltage output from the adder when the directions of currents flowing through the first and second vertical Hall elements, respectively, from the first and second driving power supplies are set to a first state, adds or subtracts a second output voltage output from the adder when the directions of currents flowing through the first and second vertical Hall elements, respectively, from the first and second driving power supplies are set to a second state, and outputs the result of the addition or subtraction as a final output voltage; a comparator having one input terminal to which the final output voltage is input and another input terminal to which a predetermined reference voltage is input, the comparator comparing the final output voltage with the reference voltage and outputting the result as an output signal; The semiconductor device according to claim 1 , further comprising:

5. 5. The semiconductor device according to claim 4, wherein at least one of the first drive power supply and the second drive power supply has a current value or a voltage value that is switched in response to an output signal of the comparator.

6. the first driving power source and the second driving power source each have an input end and an output end; the first amplifier and the second amplifier each have a first input terminal and a second input terminal; a first switch connecting an input terminal of the first driving power supply and the first electrode of the first vertical Hall element; a second switch connecting an input terminal of the first driving power supply and the third electrode of the first vertical Hall element; a third switch connecting an output terminal of the first driving power supply and the first electrode of the first vertical Hall element; a fourth switch connecting an output terminal of the first driving power supply and the third electrode of the first vertical Hall element; a fifth switch connecting an input terminal of the second driving power supply and the second electrode of the second vertical Hall element; a sixth switch connecting an input terminal of the second driving power supply and the fourth electrode of the second vertical Hall element; a seventh switch connecting an output terminal of the second driving power supply and the second electrode of the second vertical Hall element; an eighth switch connecting an output terminal of the second driving power supply and the fourth electrode of the second vertical Hall element; a ninth switch connecting a first input terminal of the first amplifier and the second electrode of the first vertical Hall element; a tenth switch connecting a first input terminal of the first amplifier and the fourth electrode of the first vertical Hall element; an eleventh switch connecting a second input terminal of the first amplifier and the second electrode of the first vertical Hall element; a twelfth switch connecting a second input terminal of the first amplifier and the fourth electrode of the first vertical Hall element; a thirteenth switch connecting a first input terminal of the second amplifier and the first electrode of the second vertical Hall element; a fourteenth switch connecting a first input terminal of the second amplifier and the third electrode of the second vertical Hall element; a fifteenth switch connecting a second input terminal of the second amplifier and the first electrode of the second vertical Hall element; a sixteenth switch connecting a second input terminal of the second amplifier and the third electrode of the second vertical Hall element; The semiconductor device according to claim 1 , comprising:

7. The semiconductor device according to claim 6 , further comprising a control circuit that controls opening and closing of the first switch to the sixteenth switch, respectively.

8. 8. The semiconductor device according to claim 1, wherein the first vertical Hall element and the second vertical Hall element have substantially the same structure.

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