Information processing method and communication device

Abstract

To disclose an encoding method, a device, a communication device, and a communication system.SOLUTION: A method includes a step for encoding an input bit series by using a low density parity check LDPC matrix, a base graph of the LDPC matrix is represented by a matrix of m rows and n columns, wherein m is an integer of five or more, and n is an integer is 27 or more, the base graph includes at least a partial matrix A and a partial matrix B, the partial matrix A is a matrix of five rows and 22 columns, the partial matrix B is a matrix of five rows and five columns, and the partial matrix B includes a row with weight being three, and a partial matrix B' having a bidiagonal structure. According to an encoding method, a device, a communication device, and a communication system of the present disclosure, requirements of encoding an information bit series of a plurality of lengths can be supported.SELECTED DRAWING: Figure 3a

Description

[Technical field]

[0001] TECHNICAL FIELD Embodiments of the present application relate to the field of communications, and in particular to an information processing method and a communication device. [Background technology]

[0002] Low density parity check (LDPC) code is a kind of linear block code with sparse check matrix, characterized by flexible structure and low decoding complexity. Since decoding LDPC code uses partially parallel iterative decoding algorithm, LDPC code has higher throughput than normal turbo code. LDPC code can be used as error correcting code in communication system to improve channel transmission reliability and power utilization. In addition, LDPC code can be widely used in space communication, optical fiber communication, personal communication system, ADSL, magnetic recording device, etc. LDPC code is currently considered as one of the channel coding modes of the 5th generation mobile communication.

[0003] In practical applications, LDPC matrices characterized by different special structures can be used. The LDPC matrix H characterized by special structures can be obtained by extending an LDPC base matrix with a quasi cycle (QC) structure. QC-LDPC is suitable for hardware with high parallelism and provides a relatively high throughput. It is possible to design an LDPC matrix that is suitable for channel coding. Summary of the Invention [Means for solving the problem]

[0004] SUMMARY OF THE PRESENT APPLICATIONS Embodiments of the present application provide an information processing method, a communication device, and a communication system for supporting encoding and decoding of information bit sequences of multiple lengths and meeting flexible code length and coding rate requirements of the system.

[0005] According to a first aspect, an encoding method and an encoder are provided, where the encoder encodes an input sequence by using a Low Density Parity Check (LDPC) matrix.

[0006] According to a second aspect, a decoding method and a decoder are provided, where the decoder decodes an input sequence by using a Low Density Parity Check (LDPC) matrix.

[0007] In a first implementation of the first or second aspect, a base graph of an LDPC matrix is ​​represented by a matrix with m rows and n columns, where m is an integer equal to or greater than 5, and n is an integer equal to or greater than 27. The base graph includes at least submatrix A and submatrix B. Submatrix A is a matrix with 5 rows and 22 columns. Submatrix B is a matrix with 5 rows and 5 columns, and includes a column with weight 3 and a submatrix B' having a bi-diagonal structure.

[0008] Arbitrarily, in submatrix A, one column has a weight of 5, one column has a weight of 4, and the other 20 columns have a weight of 3.

[0009] Optionally, in submatrix B, one column has weight 3 and three columns have weight 2.

[0010] Based on the above implementation, the submatrix B further includes one column with weight 1.

[0011] In a second implementation of the first or second aspect, a basis graph of the LDPC matrix is ​​represented by a matrix with m rows and n columns, where m is an integer equal to or greater than 5, and n is an integer equal to or greater than 27. The basis graph includes at least submatrix A and submatrix B. Submatrix A is a matrix with 5 rows and 22 columns, and submatrix B is a matrix with 5 rows and 5 columns. In the matrix including submatrix A and submatrix B, one column has a weight of 5, one column has a weight of 4, 21 columns have a weight of 3, three columns have a weight of 2, and one column has a weight of 1.

[0012] Optionally, in a matrix including submatrix A and submatrix B, one row has a weight greater than or equal to 1 and less than or equal to 5, and the other four rows have weights greater than or equal to 17 and less than or equal to 21.

[0013] For example, in a matrix including submatrix A and submatrix B, one row has weight 3 and the other four rows have weight 19. In this case, the matrix including submatrix A and submatrix B may include the rows or columns of the block of matrices including five rows from row 0 to row 4 and columns from column 0 to column 26 of base graph 30a shown in FIG. 3a. The rows may be swapped with each other, and the columns may also be swapped with each other. For example, in the block of matrices including submatrix A and submatrix B of base graph 30a, row 3 and row 0 may be swapped with each other, row 2 and row 1 may be swapped with each other, and column 23 and column 25 may be swapped with each other to obtain the core matrix of base graph 80a shown in FIG. 8a.

[0014] Based on the above implementation, the portions in the basis matrix of the LDPC matrix that correspond to submatrix A and submatrix B may be represented, for example, by any one of basis matrices 30b-1, 30b-2, 30b-3, 30b-4, and 30b-5 shown in FIG. 3b-1, and 30b-6, 30b-7, 30b-8, 30b-9, and 30b-10 shown in FIG. 3b-2.

[0015] The portions of the basis matrix of the LDPC matrix that correspond to submatrix A and submatrix B may be represented by a matrix obtained by performing a column permutation, a row permutation, or a row and column permutation on any one of basis matrices 30b-1, 30b-2, 30b-3, 30b-4, 30b-5, 30b-6, 30b-7, 30b-8, 30b-9, or 30b-10. For example, the portions of the basis matrix of the LDPC matrix that correspond to submatrix A and submatrix B may include rows or columns of any one of basis matrices 30b-1, 30b-2, 30b-3, 30b-4, 30b-5, 30b-6, 30b-7, 30b-8, 30b-9, or 30b-10.

[0016] Based on the above implementation, the portions in the basis matrix of the LDPC matrix corresponding to submatrix A and submatrix B may be represented by any one of basis matrices 80b-1, 80b-2, 80b-3, 80b-4, 80b-5 shown in Fig. 8b-1, or 80b-6 shown in Fig. 8b-2. 80b-4 is a matrix obtained by performing row permutations and column permutations on basis matrix 30b-3, 80b-5 is a matrix obtained by performing row permutations and column permutations on basis matrix 30b-4, and 80b-6 is a matrix obtained by performing row permutations and column permutations on basis matrix 30b-5.

[0017] To support different block lengths, the LDPC code requires different lifting factors Z. Based on the above implementation, in a possible implementation, a basis matrix corresponding to the different lifting factors Z is used based on the different lifting factors Z.

[0018] for example, If the lifting factor Z is one of {16, 18, 20, 22, 24, 26, 28, 30}, then the portion in the basis matrix of the basis graph 30a that corresponds to the submatrix A and the submatrix B may be the basis matrix 30b-1 shown in FIG. 3b-1; or If the lifting factor Z is one of {32, 36, 40, 44, 48, 52, 56, 60}, then the portion in the basis matrix of the basis graph 30a that corresponds to the submatrix A and the submatrix B may be the basis matrix 30b-2 shown in FIG. 3b-1; or If the lifting factor Z is one of {60, 64, 72, 80, 88, 96, 104, 112, 120}, then the portion in the basis matrix of the basis graph 30a that corresponds to the submatrix A and the submatrix B may be the basis matrix 30b-3 shown in FIG. 3b-1; or If the lifting factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, the portion in the basis matrix of the basis graph 30a that corresponds to the submatrix A and the submatrix B may be the basis matrix 30b-4 shown in FIG. 3b-1; or If the lifting factor Z is one of {256, 288, 320, 352, 384}, the portion in the basis matrix of the basis graph 30a that corresponds to the submatrix A and the submatrix B may be the basis matrix 30b-5 shown in FIG. 3b-1.

[0019] In another possible implementation, If the lifting factor Z is one of {24, 26, 28, 30}, the portion in the basis matrix of the basis graph 80a that corresponds to the submatrix A and the submatrix B may be the basis matrix 80b-1 shown in FIG. 8b-1; or If the lifting factor Z is one of {32, 36, 40, 44}, the portion in the basis matrix of the basis graph 80a that corresponds to the submatrix A and the submatrix B may be the basis matrix 80b-2 shown in FIG. 8b-1; or If the lifting factor Z is one of {48, 52, 56, 60}, the portion in the basis matrix of the basis graph 80a that corresponds to the submatrix A and the submatrix B may be the basis matrix 80b-3 shown in FIG. 8b-1; or If the lifting factor Z is one of {60, 64, 72, 80, 88, 96, 104, 112, 120}, then the portion in the basis matrix of the basis graph 80a that corresponds to the submatrix A and the submatrix B may be the basis matrix 80b-4 shown in FIG. 8b-1; or If the lifting factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, the portion in the basis matrix of the basis graph 80a that corresponds to the submatrix A and the submatrix B may be the basis matrix 80b-5 shown in FIG. 8b-1; or If the lifting factor Z is one of {256, 288, 320, 352, 384}, the portion in the basis matrix of the basis graph 80a that corresponds to the submatrix A and the submatrix B may be the basis matrix 80b-6 shown in FIG. 8b-2.

[0020] In another possible implementation, submatrix A may further include two columns of built-in puncture bits.

[0021] Furthermore, to obtain flexible coding rates, submatrix C, submatrix D, and submatrix E of corresponding sizes may be added based on the core matrix to obtain different coding rates.

[0022] The submatrix C has 5 rows and m D is an all-zero matrix with columns, The submatrix D is m D is a matrix with 27 rows and 27 columns, The submatrix E is m D Row and m D is the column identity matrix, m D is an integer, 0≦m D ≦41.

[0023] The submatrix D is the mth of the matrix F. D rows, matrix F has 41 rows and 27 columns, and the row weights of matrix F are 7, 7, 9, 8, 7, 7, 8, 6, 6, 5, 6, 5, 5, 6, 5, 5, 5, 5, 4, 4, 4, 5, 4, 4, 4, 3, 4, 4, 4, 4, 3, 3, 4, 4, 3, 3, 3, and 4, respectively.

[0024] In a possible implementation, the matrix F is the matrix that includes rows 5 through 45 and columns 0 through 26 of the base graph 30a.

[0025] In a possible implementation, the shift matrix of matrix F may be represented by any one of basis matrices 30c-1 shown in FIG. 3c-2, 30c-2 shown in FIG. 3c-3, 30c-3 shown in FIG. 3c-4, 30c-4 shown in FIG. 3c-5, or 30c-5 shown in FIG. 3c-6.

[0026] In another possible implementation, rows 17 and 19 of base graph 30a may be swapped with each other, and columns 39 and 41 may be swapped with each other, to obtain base graph matrix 80a shown in FIG. 8a. As another example, submatrix D may be the mth submatrix of matrix F. D It contains m rows, and the permutation of the rows is D No substitutions are performed between m lines, or D , the submatrix D may be performed between one or more of the m rows of the matrix F, so that the submatrix E still has a diagonal structure. For example, to obtain the base graph 80a, the submatrix D may be D rows, rows 12 and 14 of matrix F are swapped with each other, and submatrix E continues to have a diagonal structure.

[0027] To support different block lengths, the LDPC code requires different lifting factors Z. Based on the above implementation, in a possible implementation, basis matrices corresponding to different lifting factors Z are used based on the different lifting factors Z. For example, A possible implementation would be: When the lifting factor Z is one of {16, 18, 20, 22, 24, 26, 28, 30}, the submatrix D of the basis matrix is ​​m of the shift matrix 30c-1 shown in FIG. D may contain rows, or When the lifting factor Z is one of {32, 36, 40, 44, 48, 52, 56, 60}, the submatrix D of the basis matrix is ​​m of the shift matrix 30c-2 shown in FIG. D may contain rows, or When the lifting factor Z is one of {60, 64, 72, 80, 88, 96, 104, 112, 120}, the submatrix D of the basis matrix is ​​m of the shift matrix 30c-3 shown in FIG. D may contain rows, or When the lifting factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, the submatrix D of the basis matrix is ​​m of the shift matrix 30c-4 shown in FIG. D may contain rows, or When the lifting factor Z is one of {256, 288, 320, 352, 384}, the submatrix D of the basis matrix is ​​m of the shift matrix 30c-5 shown in FIG. D It may contain rows.

[0028] In another possible implementation, the set of lifting factors could be {24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384}.

[0029] If the lifting factor Z is one of {24, 26, 28, 30}, the shift matrix of the matrix F may be 80c-1 shown in FIG. 8c-2; or If the lifting factor Z is one of {32, 36, 40, 44}, the shift matrix of the matrix F may be 80c-2 shown in FIG. 8c-3; or If the lifting factor Z is one of {48, 52, 56, 60}, the shift matrix of the matrix F may be 80c-3 shown in FIG. 8c-4; or If the lifting factor Z is one of {60, 64, 72, 80, 88, 96, 104, 112, 120}, the shift matrix of the matrix F may be 80c-4 shown in FIG. 8c-5; or If the lifting factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, the shift matrix of the matrix F may be 80c-5 shown in FIG. 8c-6; or When the lifting factor Z is one of {256, 288, 320, 352, 384}, the shift matrix of the matrix F may be 80c-6 shown in FIG. 8c-7.

[0030] The basis graph and basis matrix of the LDPC matrix of the first implementation can meet the performance requirements of code blocks with block lengths from 352 to 8448 bits.

[0031] Based on any one of the above-mentioned aspects or possible implementations of the aspects, in another possible implementation, the method further includes determining a lifting factor Z. For example, the value of the lifting factor Z is determined based on the length K of the input sequence. For example, when the length of the input sequence is K, a minimum value among the lifting factors that satisfy 22*Z≧K may be determined from a plurality of lifting factors defined in the system.

[0032] For a communication device at a transmitting end, encoding an input sequence by using an LDPC matrix includes: It involves encoding the input sequence by using an LDPC matrix corresponding to the lifting factor Z.

[0033] For a communication device at a receiving end, decoding an input sequence by using an LDPC matrix includes: It includes decoding the input sequence by using the LDPC matrix corresponding to the lifting factor Z.

[0034] Based on any one of the above-mentioned aspects or possible implementations of the aspects, in another possible implementation, a basis matrix of the LDPC matrix may be stored in a memory.

[0035] Based on any one of the above-mentioned aspects or possible implementations of the aspects, in another possible implementation, a basis graph of the LDPC matrix may be stored in a memory, and shift values ​​of non-zero elements of a basis matrix of the LDPC matrix may be stored in the memory.

[0036] Based on the above possible implementations, in a possible design, at least one of a basis graph and a basis matrix for encoding or decoding an LDPC is obtained by performing row permutation, or column permutation, or row permutation and column permutation on at least one of a basis graph and a basis matrix of an LDPC matrix.

[0037] According to a third aspect, a communication apparatus is provided, the apparatus may include software modules and / or hardware components configured to perform any one of the possible implementations of the first aspect of the design of the method described above.

[0038] In a possible design, a communication device provided in a third aspect includes the encoder, the determination unit, and the processing unit described in the first aspect. The determination unit is configured to determine a lifting factor Z required to encode an input sequence. The processing unit is configured to encode the input sequence by using an LDPC matrix corresponding to the lifting factor Z.

[0039] Optionally, the communication device further includes a transceiver, the transceiver configured to transmit a signal corresponding to the encoded information data.

[0040] According to a fourth aspect, a communication device is provided, the device may include a module configured to perform any one of the possible implementations of the second aspect of the design of the above-mentioned method. The module may be software and / or hardware.

[0041] In a possible design, a communication device provided in a fourth aspect includes the decoder, the obtaining unit, and the processing unit described in the second aspect. The obtaining unit is configured to obtain a soft value of the LDPC code and a lifting factor Z. The processing unit calculates a basis matrix H corresponding to the lifting factor Z to obtain an information bit sequence. B The soft decision value of the LDPC code is decoded based on the

[0042] The communication device further includes a transceiver, the transceiver configured to receive a signal including the LDPC code.

[0043] According to a fifth aspect, a communications apparatus is provided that includes one or more processors.

[0044] In one possible design, one or more processors may implement the functionality of the encoder of the first aspect. In another possible design, the encoder of the first aspect may be part of a processor, and the processor may implement other functionality in addition to the functionality of the encoder of the first aspect.

[0045] In one possible design, one or more processors may implement the functionality of the decoder of the second aspect. In another possible design, the decoder of the second aspect may be part of the processor.

[0046] Optionally, the communication device may further include a transceiver and an antenna.

[0047] Optionally, the communication device may further include a component configured to generate a cyclic redundancy check (CRC) of the transport block, a component used for segmentation and CRC checking of the code block, an interleaver used for interleaving, a modulator used for modulation processing, etc.

[0048] Optionally, the communication device may further include a demodulator used for demodulation, a deinterleaver used for deinterleaving, a component used for rate dematching, etc. The functionality of these components may be implemented by one or more processors.

[0049] In a possible design, the functionality of these components may be implemented by one or more processors.

[0050] According to a sixth aspect, an embodiment of the present application provides a communication system, the system including a communication device as described in the third aspect and a communication device as described in the fourth aspect.

[0051] According to a seventh aspect, an embodiment of the present application provides a communication system, the system including one or more communication devices as described in the fifth aspect.

[0052] According to another aspect, an embodiment of the present application provides a computer storage medium, the computer storage medium storing a program which, when executed, causes a computer to perform the method described in the above aspect.

[0053] According to another aspect of the present application, there is provided a computer program product comprising instructions which, when executed on a computer, cause the computer to perform the method of the above-mentioned aspect.

[0054] According to the information processing method, apparatus, communication device, and communication system of the embodiments of the present application, the flexible code length and code rate requirements of the system can be met in terms of coding performance and error floor. [Brief description of the drawings]

[0055] [Figure 1] 1 shows a schematic diagram of a basis graph, a basis matrix, and a cyclic permutation matrix of an LDPC code. [Diagram 2] 1 is a schematic structural diagram of a base graph of an LDPC code. [Figure 3a] 1 is a schematic diagram of a basis graph of an LDPC code according to an embodiment of the present application; [Figure 3b-1] 1 shows a schematic diagram of a basis matrix of an LDPC code according to an embodiment of the present application; [Figure 3b-2] 1 is a schematic diagram of a basis matrix of an LDPC code according to an embodiment of the present application; [Figure 3c-1] 2 shows a schematic diagram of a basis matrix of an LDPC code according to another embodiment of the present application; [Figure 3c-2] FIG. 2 is a schematic diagram of a basis matrix of an LDPC code according to another embodiment of the present application; [Figure 3c-3] FIG. 2 is a schematic diagram of a basis matrix of an LDPC code according to another embodiment of the present application; [Figure 3c-4] FIG. 2 is a schematic diagram of a basis matrix of an LDPC code according to another embodiment of the present application; [Figure 3c-5] FIG. 2 is a schematic diagram of a basis matrix of an LDPC code according to another embodiment of the present application; [Figure 3c-6] FIG. 2 is a schematic diagram of a basis matrix of an LDPC code according to another embodiment of the present application; [Figure 3c-7] FIG. 2 is a schematic diagram of a basis matrix of an LDPC code according to another embodiment of the present application; [Figure 3c-8] FIG. 2 is a schematic diagram of a basis matrix of an LDPC code according to another embodiment of the present application; [Figure 3c-9] FIG. 2 is a schematic diagram of a basis matrix of an LDPC code according to another embodiment of the present application; [Figure 3c-10] FIG. 2 is a schematic diagram of a basis matrix of an LDPC code according to another embodiment of the present application; [Figure 3c-11] FIG. 2 is a schematic diagram of a basis matrix of an LDPC code according to another embodiment of the present application; [Figure 4] 1 is a schematic performance diagram provided by an embodiment of the present application. [Diagram 5] FIG. 2 is a schematic performance diagram provided by another embodiment of the present application. [Figure 6] 1 is a schematic block diagram of an information processing device according to an embodiment of the present application. [Figure 7] 1 is a schematic block diagram of a communication system according to an embodiment of the present application; [Figure 8a] FIG. 2 is a schematic diagram of a basis graph of an LDPC code according to another embodiment of the present application; [Figure 8b-1] 1 shows a schematic diagram of a basis matrix of an LDPC code according to yet another embodiment of the present application; [Figure 8b-2] 1 shows a schematic diagram of a basis matrix of an LDPC code according to yet another embodiment of the present application; [Figure 8c-1] 1 shows a schematic diagram of a basis matrix of an LDPC code according to yet another embodiment of the present application; [Figure 8c-2] 1 shows a schematic diagram of a basis matrix of an LDPC code according to yet another embodiment of the present application; [Figure 8c-3] 1 shows a schematic diagram of a basis matrix of an LDPC code according to yet another embodiment of the present application; [Figure 8c-4] 1 shows a schematic diagram of a basis matrix of an LDPC code according to yet another embodiment of the present application; [Figure 8c-5] 1 shows a schematic diagram of a basis matrix of an LDPC code according to yet another embodiment of the present application; [Figure 8c-6] 1 shows a schematic diagram of a basis matrix of an LDPC code according to yet another embodiment of the present application; [Figure 8c-7] 1 shows a schematic diagram of a basis matrix of an LDPC code according to yet another embodiment of the present application; [Figure 8c-8] 1 shows a schematic diagram of a basis matrix of an LDPC code according to yet another embodiment of the present application; [Figure 8c-9] 1 shows a schematic diagram of a basis matrix of an LDPC code according to yet another embodiment of the present application; [Fig. 8c-10] 1 shows a schematic diagram of a basis matrix of an LDPC code according to yet another embodiment of the present application; [Figure 9] FIG. 2 is a schematic performance diagram of an LDPC code according to an embodiment of the present application. [Figure 10] FIG. 2 is a schematic performance diagram of an LDPC code according to another embodiment of the present application. [Figure 11a] FIG. 13 is a schematic diagram of a basis graph of an LDPC code according to yet another embodiment of the present application; [Figure 11b] FIG. 11b is a schematic diagram of a basis matrix based on the basis graph of the LDPC code provided in FIG. [Figure 12] FIG. 13 is a schematic diagram of a basis graph according to yet another embodiment of the present application; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0056] For ease of understanding, some terms in this application are explained below.

[0057] In this application, the terms "network" and "system" are often used interchangeably, and "apparatus" and "device" are often used interchangeably. The meaning of these terms is understood by those skilled in the art. A "communication device" may be a chip (such as a baseband chip, a digital signal processing chip, or a general-purpose chip), a terminal, a base station, or any other networking device.

[0058] A terminal is a device having a communication capability. A terminal may be a handheld device, an in-vehicle device, a wearable device, a computing device, or any other processing device connected to a wireless modem and having wireless communication capability. A terminal may be called by different names in different networks, such as a user equipment, a mobile station, a subscriber unit, a station, a cellular telephone, a personal digital assistant, a wireless modem, a wireless communication device, a handheld device, a laptop computer, a cordless telephone, and a wireless local loop station. For ease of explanation, these devices are simply called terminals in this application.

[0059] A base station (BS), also called a base station device, is a device that is deployed in a radio access network to provide wireless communication functions. A base station may be called by different names in different wireless access systems. For example, a base station in a Universal Mobile Telecommunications System (UMTS) network is called a NodeB, a base station in a LTE network is called an evolved NodeB (eNB or eNodeB), and a base station in a new radio (NR) network is called a transmission reception point (TRP) or a generation nodeB (gNB). A base station in other networks may be called by other names. This is not limited in the present application.

[0060] Below, technical solutions of the embodiments of the present application are described with reference to the accompanying drawings.

[0061] An LDPC code may be represented by a parity check matrix H. The parity check matrix H code may be obtained by using a base graph and a shift value. The base graph is a matrix with m rows and n columns, and includes m*n matrix elements (also called entries). The value of each matrix element is either 0 or 1. An element with a value of 0 is called a zero element and may be replaced by an all-zero matrix with Z rows*Z columns. An element with a value of 1 is called a non-zero element and may be replaced by a circular permutation matrix with Z rows*Z columns. That is, each element of the base graph represents one all-zero matrix or one cyclic permutation matrix. 10a of FIG. 1 shows an element of an exemplary base graph of an LDPC code with a QC structure, where m=4 and n=20.

[0062] It should be noted that, in this specification, the row and column indices of the base graphs and matrices are numbered starting from 0, but this is merely for ease of explanation. For example, column 0 indicates the first column of the base graph or matrix, column 1 indicates the second column of the base graphs and matrices, row 0 indicates the first row of the base graphs and matrices, row 1 indicates the second row of the base graphs and matrices, and so on.

[0063] It will be understood that the row and column indices may alternatively be numbered starting from 1, in which case the row and column indices shown herein are incremented by 1 to obtain the corresponding row and column indices. For example, if the row and column indices are numbered starting from 1, column 1 refers to the first column of the base graphs and matrices, column 2 refers to the second column of the base graphs and matrices, row 1 refers to the first row of the base graphs and matrices, row 2 refers to the second row of the base graphs and matrices, and so on.

[0064] The element in row i and column j of the ground graph has value 1, and the element is shifted by the shift value P i,j was assigned, P i,j If is an integer greater than or equal to 0, then the element in row i and column j of the ground graph with value 1 is P i,j is replaced by the Z*Z cyclic permutation matrix corresponding to P i,j The corresponding cyclic permutation matrix is ​​a unit matrix of size Z*Z on the right, P i,j To obtain the parity check matrix of the LDPC code, each element of the basis graph with value 0 is replaced by an all-zero matrix of size Z*Z, and each element with value 1 is replaced by a cyclic permutation matrix of size Z*Z that corresponds to the shift value of the element. The position of the shift value may be indicated in the basis graph, and the non-zero elements of the basis graph correspond to that shift value.

[0065] Z is a positive integer, a lifting factor, or may be called a lifting size or lifting factor. Z may be determined based on the code block size and the size of the information data supported by the system. For a basis graph with m rows and n columns, it can be seen that the parity check matrix H has a size of (m*Z)*(n*Z). For example, if the lifting factor Z is 4, each zero element of the basis graph 10a is replaced by one all-zero matrix 11a of size 4*4. P 2,3 If P is 2, then the non-zero elements in row 2 and column 3 of the base graph are replaced by a cyclic permutation matrix 11d of size 4*4, which is obtained by circularly shifting the identity matrix 11b of size 4*4 twice to the right. 2,4 is 0, then the non-zero element in row 2 and column 4 is replaced by identity matrix 11b. Note that merely examples are described herein and the examples do not constitute a limitation.

[0066] P i,j The value of may depend on the lifting factor Z. For elements of the ground graph with the same position and value 1, P i,j may be different for different lifting factors Z. To facilitate implementation, an m*n basis matrix may be defined. The elements of the basis matrix have a one-to-one correspondence with the elements of the basis graph. A zero element of the basis graph has the same position in the basis matrix, and the element is denoted by -1. A non-zero element in row i and column j that has value 1 in the basis graph has the same position in the basis matrix, and the element is denoted by -1. i,j and P i,j is a positive integer equal to or greater than 0. In this embodiment of the present application, the basis matrix may also be referred to as a shift matrix of the matrix of the basis graph.

[0067] FIG. 1 shows a basis matrix 10b corresponding to a basis graph 10a.

[0068] Typically, the basis graph or basis matrix of an LDPC code may further include p columns of built-in puncture bits, where p may be an integer ranging from 0 to 2. These columns may be used in encoding, but the system bits corresponding to the columns are not transmitted. The coding rate of the basis matrix of an LDPC code satisfies R = (n - m) / (n - p). If a basis matrix with 4 rows and 20 columns (4*20) includes two columns of built-in puncture bits, the coding rate is (20 - 4) / (20 - 2) = 8 / 9.

[0069] The LDPC code used in the wireless communication system is a QC-LDPC code, and some of the parity bits of the QC-LDPC code have a double diagonal structure or a raptor-like structure, so that the encoding can be simplified and incremental redundancy hybrid repeat can be supported. In a decoder for a QC-LDPC code, a QC-LDPC shift network (QSN), a Banyan network, or a Benes network is usually used to implement the circular shift of information.

[0070] The basis graph of the QC-LDPC code with a raptor-like structure is a matrix with m rows and n columns, and the basis graph may usually include five submatrices A, B, C, D, and E. The weight of the matrix is ​​determined by the amount of non-zero elements. The row weight (row weight) is the amount of non-zero elements in a row, and the column weight (column weight) is the amount of non-zero elements in a column. The following is shown in 200 of FIG. 2.

[0071] The submatrix A is m A Row and n A A is a matrix with m columns. A *n A Each column corresponds to Z system bits of the LDPC code, which are also called information bits.

[0072] The submatrix B is m A Row and m A The submatrix B is a square matrix of m A *m A Each column corresponds to Z parity bits of the LDPC code. As shown in 20a of FIG. 2, submatrix B includes submatrix B' having a bidiagonal structure and a matrix column with a weight of 3 (abbreviated as weight 3 column), which is to the left of submatrix B'. As shown in 20b or 20c of FIG. 2, submatrix B may further include a matrix column with a weight of 1 (abbreviated as weight 1 matrix column), which may be in the first or last column of submatrix B, and the non-zero elements of the weight 1 matrix column are in the last row of submatrix B, so that the weight of the last row of submatrix B is 1.

[0073] Generally, the matrix generated based on submatrix A and submatrix B is a core matrix that can be used to support high code rate encoding.

[0074] The submatrix C is an all-zero matrix, and the submatrix C is m A ×(n-(m A +n A )).

[0075] The submatrix E is an identity matrix, and the submatrix E is (m - m A )×(m - m A ) size.

[0076] The submatrix D is (m - m A )×(n A + m A ), and submatrix D may be used to generate parity bits for low code rates.

[0077] It will be understood that since the basis graph is represented mathematically and C is an all-zero matrix and E is an identity matrix, in a possible implementation, a matrix including submatrix A and submatrix B, or a matrix including submatrix A, submatrix B, and submatrix D, may be used simply to represent the basis graph of a matrix for encoding or decoding.

[0078] Since the structures of submatrix B, submatrix C, and submatrix E are relatively defined, the structures of submatrix A and submatrix D become one of the factors affecting the encoding and decoding performance of the LDPC code.

[0079] When an LDPC matrix having a raptor-like structure is used for encoding, in a possible implementation, a portion of the matrix including submatrix A and submatrix B, i.e., the core matrix, may be first encoded to obtain one or more parity bits corresponding to submatrix B, and then the entire matrix is ​​encoded to obtain one or more parity bits corresponding to submatrix E. Because submatrix B may include submatrix B' having a bidiagonal structure and a weight 1 matrix column, during encoding, one or more parity bits corresponding to submatrix B' having a bidiagonal structure may be first obtained, and then one or more parity bits corresponding to the weight 1 matrix column may be obtained.

[0080] An exemplary encoding implementation is given below. Let H be the core matrix including submatrix A and submatrix B. core Assuming that the weight 1 matrix column and the row with nonzero elements in the column are the matrix H core-dual To get H core The parity bit is removed from core-dual The inner part is H e = [H e1 H e2 ] and H e1 is the weight 3 matrix column, H e2 has a bidiagonal structure. According to the definition of the matrix of the LDPC code, H core-dual · [SP e ] T= 0, S is the input sequence, a vector containing information bits, and P e is a vector containing parity bits, [SP e ] T are the input sequences S and P e Therefore, H core-dual The parity bits corresponding to the input sequences S and H core-dual The input sequence S includes all information bits. Then, the parity bits corresponding to the weight 1 columns in the submatrix B can be calculated based on H core-dual and the input sequence S. In this case, all the parity bits corresponding to the submatrix B can be obtained. Then, the parity bits corresponding to the submatrix E are obtained by encoding by using the submatrix D based on the input sequence S and the parity bits corresponding to the submatrix B to obtain all the information bits and all the parity bits. The sequence includes all the information bits and all the parity bits obtained by performing encoding, that is, the LDPC code sequence.

[0081] Optionally, the LDPC coding may further include shortening and puncturing operations, where the shortened and punctured bits are not transmitted.

[0082] The shortening is usually performed from the last information bit and can be performed in different ways. For example, the amount of shortened bits is s0, and the last s0 bits of the input sequence S can be set to a known bit, e.g., set to 0 or null or another value, to obtain an input sequence S', and then the input sequence S' is encoded by using an LDPC matrix. As another example, the last (s0 mod Z) bits of the input sequence S can be set to a known bit, e.g., set to 0 or null or another value, to obtain an input sequence S', and the last (s0 mod Z) bits of the submatrix A can be set to a known bit, e.g., set to 0 or null or another value, to obtain an input sequence S'.

[0083]

number

[0084] The columns are deleted to obtain the LDPC matrix H', and the input sequence S' is encoded by using the LDPC matrix H', or the last

[0085]

number

[0086] The sequence does not take part in the encoding of the input sequence S'. After encoding, the shortened bits are not transmitted.

[0087] Puncturing may be performed on one or more built-in puncture bits or one or more parity bits in the input sequence. Also, usually, puncturing the parity bits is from the last one bit of the parity bits. Alternatively, puncturing may be performed based on the system's preset puncturing pattern. In a possible implementation, the input sequence is first coded, and then the last p bits of the parity bits are selected based on the amount p of bits that need to be punctured, or p bits are selected based on the system's preset puncturing pattern, and p bits are not transmitted. In another possible implementation, p columns in the matrix corresponding to the punctured bits and p rows with non-zero elements in these columns may also be determined, and the rows and columns are not used in coding, and therefore the corresponding parity bits are not generated.

[0088] It should be noted that the implementation of the encoding described in this specification is used only as an example. Other encoding implementations known to those skilled in the art may be used based on the basis graph and / or basis matrix provided in this specification, and the implementation of the encoding is not limited in this specification. The decoding of this specification may be performed in multiple decoding methods, for example, the min-sum (MS) decoding method or the belief propagation decoding method. The MS decoding method may be called the Flood MS decoding method. For example, an input sequence is initialized, and one or more iterations are performed. A hard decision detection is performed after the iteration, and the result of the hard decision is checked. If the decoding result satisfies the check equation, the decoding is successful, the iteration is terminated, and the decision result is output. If the decoding result does not satisfy the check equation, the iteration is performed again within the maximum amount of iterations, and if the check still fails, the decoding fails when the maximum amount of iterations is reached. The principle of MS decoding is understood by those skilled in the art, and the details are not described in this specification.

[0089] It should be noted that the decoding method is used in this specification only as an example, and other decoding methods known to those skilled in the art may be used based on the basis graph and / or basis matrix provided in this application, and the decoding method is not limited in this application.

[0090] An LDPC code may be obtained based on a basis graph and a basis matrix, and an upper limit of the performance of the LDPC code may be determined by performing density evolution on the basis graph or the basis matrix. An error floor of the LDPC code is determined based on a shift value of the basis matrix. Improving the performance of encoding and decoding and reducing the error floor are some of the purposes of designing the basis graph and the basis matrix. The code length is flexible in a wireless communication system. The code block may have a short block length such as 40 bits or 1280 bits, or the code block may have a long block length such as 5000 bits or 8448 bits. Figures 3a, 3b-1 and 3b-2, and 3c-1 to 3c-11 are examples of basis graphs and basis matrices of LDPC codes, and the examples can meet the performance requirements of code blocks with block lengths up to 8448 bits. 8a, 8b-1 and 8b-2, and 8c-1 to 8c-10 provide examples of basis graphs and basis matrices of another LDPC code. FIG. 11a and 11b provide examples of basis graphs and basis matrices of another LDPC code. For ease of explanation and understanding, row indexes and column indexes are shown at the topmost and leftmost sides of FIG. 3a, 3b-1 and 3b-2, and 3c-1 to 3c-11, respectively. FIG. 4 and FIG. 5 provide schematic diagrams of the performance of the LDPC codes shown in FIG. 3a and 3c-1 to 3c-11, respectively, for two different coding rates. FIG. 3a shows an example of a basis graph 30a of an LDPC code. In the figure, 0 to 67 in the topmost row indicate column indexes, and 0 to 45 in the leftmost column indicate row indexes. Specifically, the basis graph has 46 rows and 68 columns.

[0091] Submatrix A corresponds to the system bits, has 5 rows and 22 columns, and includes elements from row 0 to row 4 and column 0 to column 21 of base graph 30a.

[0092] Submatrix B corresponds to the parity bits, has 5 rows and 5 columns, and includes elements from rows 0 to 4 and columns 22 to 26 of base graph 30a.

[0093] Submatrix A and submatrix B form a core matrix in the basis graph of the LDPC code, specifically, a matrix with 5 rows and 27 columns, which can be used for high code rate encoding. For example, in the core matrix including submatrix A and submatrix B, one column has a weight of 5, one column has a weight of 4, 21 columns have a weight of 3, three columns have a weight of 2, and one column has a weight of 1.

[0094] Submatrix A may include two columns of embedded puncture bits, and after puncturing, the code rate that may be supported by the core matrix is ​​22 / (27-2) = 0.88. In submatrix A, one column has a weight of 5, one column has a weight of 4, and the other 20 columns have a weight of 3. For example, the weights of the two columns of embedded puncture bits may be 5 and 4, respectively.

[0095] The weight of the last row (row 4) and the weight of the last column (column 4 of submatrix B, i.e., column 26 of the core matrix) of submatrix B are both 1. Submatrix B contains one weight 3 column, specifically, column 0 of submatrix B (column 22 of the core matrix) has a weight of 3. Columns 1 through 3 of submatrix B (columns 23 through 25 of the core matrix) and rows 0 through 3 of submatrix B form a bidiagonal structure.

[0096] The core matrix of the base graph 30a includes four rows with a weight of 19 and one row with a weight of 3. The weights of the rows of the core matrix including submatrix A and submatrix B are 19, 19, 19, 19, and 3. Note that the rows of the core matrix may be swapped, e.g., rows 0 and 2 are swapped with each other, and rows 1 and 3 are swapped with each other. The row with weight 3 may be row 4 from columns 0 to 26 of the core matrix of the base graph 30a, and the row with weight 19 may be rows 0 to 3 from columns 0 to 26 of the core matrix of the base graph 30a, respectively. These rows may be swapped with each other, and the columns may also be swapped with each other. For example, columns 8 and 25 of the core matrix may be swapped with each other, and columns 10 and 26 may be swapped with each other. For example, rows 3 and 0 of the core matrix may be swapped with each other, and rows 2 and 1 may be swapped with each other. In order to keep the bidiagonal structure of the submatrix B, on this basis, columns 23 and 25 can be exchanged with each other to obtain the core matrix of the basis graph 80a shown in Fig. 8a, i.e., the matrix including rows 0 to 5 and columns 0 to 26 of 80a. It should be noted that only examples are provided herein. In practical applications, the row permutations and column permutations can be flexibly designed based on the requirements of the system.

[0097] Table 1 shows an example of column permutation for base graph 80a. For ease of explanation, a sequence obtained by column permutation of the 27 columns of the core matrix is ​​given herein. Column index is the column index of the matrix after permutation and is numbered from 0. Column index before permutation is the column index of the matrix before permutation. As shown in Table 1, columns 8 and 10 of the matrix before permutation are moved to columns 25 and 26, column 9 of the matrix before permutation is moved to column 8, columns 11 to 21 of the matrix before permutation are moved to columns 9 to 19, and columns 25 and 26 of the matrix before permutation are moved to columns 20 and 21. In this way, the performance of a particular code rate and a particular code length can be improved. For example, FIG. 9 is a schematic diagram of the performance based on the base matrix shown in Table 1. The performance is improved for a code rate of 2 / 3, a block error rate (BLER) of 1E-2, and code lengths ranging from 672 to 960. Figure 10 is a schematic diagram of the performance based on the basis matrix shown in Table 1. The performance is improved for a code rate of 2 / 3, a BLER of 1E-2, and code lengths ranging from 1952 to 2624.

[0098] [Table 1]

[0099] It will be understood that in a matrix, rows can be swapped with each other and columns can be swapped with each other, and since row permutations do not change the column weights of the matrix and column permutations do not change the row weights of the matrix, the amount of non-zero elements of the matrix remains unchanged. The row weights of the base graph 80a after row permutations and column permutations remain unchanged. Performance is not affected with respect to the base graph obtained by performing row permutations, or column permutations, or row and column permutations.

[0100] It should be noted that in this application, performance is not affected means that the impact is tolerable and falls within an acceptable range overall, e.g., performance may be degraded within an acceptable range in some scenarios or to some extent, but improved in some scenarios or to some extent so that overall it is barely affected.

[0101] The core matrix of the base graph 30a and the core matrix of the base graph 80a are used as examples. After the row permutation is performed on the base graph 30a, the core matrix of the base graph 80a still contains the columns of the core matrix of the base graph 30a, except that the order of the rows changes, and one row has a weight of 3, and the other four rows have a weight of 19. If the column permutation is performed on the base graph 30a, for example, columns 5 and 7 are swapped with each other, it can be seen that the core matrix of the base graph 30a and obtained by performing the column permutation still contains the columns of the core matrix of the base graph 30a. Except that the order of the columns changes, one column has a weight of 5, one column has a weight of 4, 21 columns have a weight of 3, three columns have a weight of 2, and one column has a weight of 1. It should be noted that what is given in this specification is merely an example, and the examples are not limiting.

[0102] For a given base graph or a given base matrix of an LDPC code, the performance impact of some changes to matrix elements is usually acceptable. For example, in implementation, some changes can be made based on the core matrix of the base graph 30a. For example, one row has a weight of 1 or more and 5 or less, and the other four rows have weights of 17 or more and 21 or less, respectively. For example, one row has a weight of 2, and the other four rows have a weight of 18, or one row has a weight of 4, and the other four rows have weights of 17, 18, 19, and 19, respectively. With reference to the solution provided in this application, it will be understood that the weight of some rows can be increased or decreased by 1 or 2, and this is not limited in this application.

[0103] Submatrix A may also include one row in which elements other than the elements in the column of embedded puncture bits are zero elements. Furthermore, in order to minimize the weight of a row of the core matrix or the matrix of the base graph, the row is usually the same as the row with weight 1 in submatrix B. For example, as shown in the base graph 30a or 80a, there are two columns of embedded puncture bits, specifically, columns 0 and 1 are columns of embedded puncture bits. In row 4, the elements in columns 0 and 1 are non-zero elements, the elements in columns 2 to 25 are zero elements, the elements in column 26 are non-zero elements, and the weight of row 4 is 3. Row 4 has the smallest weight in the core matrix and even in the entire matrix of the base graph. Such a setting can improve the performance of encoding and decoding.

[0104] To support different block lengths, the LDPC code requires different lifting factors Z. For example, the lifting factor Z may be one or more of the following values: 16, 18, 20, 22, 24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, or 384. To ensure the performance of the LDPC code for different block lengths, basis matrices corresponding to different lifting factors Z may be used based on the different lifting factors Z. Figures 3b-1 and 3b-2 show examples of multiple basis matrices of the core matrix of the basis graph 30a. The basis matrix is ​​obtained based on the core matrix of the basis graph 30a and the lifting factor Z. The non-zero elements of row i and column j of the basis graph 30a are calculated by the shift value P i,j and zero elements of the basis graph 30a are represented by −1 or null in the basis matrix.

[0105] A possible implementation would be: If the lifting factor Z is one of {16, 18, 20, 22, 24, 26, 28, 30}, the portions in the basis matrix of the basis graph 30a that correspond to the submatrix A and the submatrix B may be shown in the basis matrix 30b-1 of FIG. 3-1b, or If the lifting factor Z is one of {32, 36, 40, 44, 48, 52, 56, 60}, the portions in the basis matrix of the basis graph 30a that correspond to the submatrix A and the submatrix B may be shown in the basis matrix 30b-2 of FIG. 3b-1, or If the lifting factor Z is one of {60, 64, 72, 80, 88, 96, 104, 112, 120}, the portions in the basis matrix of the basis graph 30a that correspond to the submatrix A and the submatrix B may be shown in the basis matrix 30b-3 of FIG. 3b-1, or If the lifting factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, the portions in the basis matrix of the basis graph 30a that correspond to the submatrix A and the submatrix B may be shown in the basis matrix 30b-4 of FIG. 3b-1, or If the lifting factor Z is one of {256, 288, 320, 352, 384}, the portions in the basis matrix of the basis graph 30a that correspond to submatrix A and submatrix B may be shown in basis matrix 30b-5 of FIG. 3b-1.

[0106] In another possible implementation, the set of lifting factors could be {24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384}.

[0107] If the lifting factor Z is one of {24, 26, 28, 30}, the portion in the basis matrix of the basis graph 30a that corresponds to the submatrix A and the submatrix B may be the basis matrix 30b-6 shown in FIG. 3b-2; or If the lifting factor Z is one of {32, 36, 40, 44}, the portion in the basis matrix of the basis graph 30a that corresponds to the submatrix A and the submatrix B may be the basis matrix 30b-7 shown in FIG. 3b-2; or If the lifting factor Z is one of {48, 52, 56, 60}, the portion in the basis matrix of the basis graph 30a that corresponds to the submatrix A and the submatrix B may be the basis matrix 30b-8 shown in FIG. 3b-2; or If the lifting factor Z is one of {60, 64, 72, 80, 88, 96, 104, 112, 120}, then the portion in the basis matrix of the basis graph 30a that corresponds to the submatrix A and the submatrix B may be the basis matrix 30b-3 shown in FIG. 3b-1; or If the lifting factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, then the portion in the basis matrix of the basis graph 30a that corresponds to the submatrix A and the submatrix B may be the basis matrix shown in 30b-4 of FIG. 3b-1; or If the lifting factor Z is one of {256, 288, 320, 352, 384}, the portion in the basis matrix of the basis graph 30a that corresponds to the submatrix A and the submatrix B may be the basis matrix 30b-5 shown in FIG. 3b-1.

[0108] Based on the above implementation, in another possible implementation, in order to further improve the performance, the base graph may correspond to more base matrices, and the parts in the base matrix of the base graph 30a corresponding to the submatrix A and the submatrix B may correspond to different base matrices. For example, If the lifting factor Z is one of {24, 26, 28, 30}, the portion in the basis matrix of the basis graph 30a that corresponds to the submatrix A and the submatrix B may be the basis matrix 30b-6 shown in FIG. 3b-2; or If the lifting factor Z is one of {32, 36, 40, 44}, the portion in the basis matrix of the basis graph 30a that corresponds to the submatrix A and the submatrix B may be the basis matrix 30b-7 shown in FIG. 3b-2; or If the lifting factor Z is one of {48, 52, 56, 60}, the portion in the basis matrix of the basis graph 30a that corresponds to the submatrix A and the submatrix B may be the basis matrix 30b-8 shown in FIG. 3b-2; or If the lifting factor Z is one of {64, 72, 80, 88}, the portion in the basis matrix of the basis graph 30a that corresponds to the submatrix A and the submatrix B may be the basis matrix 30b-9 or 30b-10 shown in FIG. 3b-2; or If the lifting factor Z is one of {96, 104, 112, 120}, the portion in the basis matrix of the basis graph 30a that corresponds to the submatrix A and the submatrix B may be the basis matrix 30b-3 shown in FIG. 3b-1; or If the lifting factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, the portion in the basis matrix of the basis graph 30a that corresponds to the submatrix A and the submatrix B may be the basis matrix 30b-4 shown in FIG. 3b-1; or If the lifting factor Z is one of {256, 288, 320, 352, 384}, the portion in the basis matrix of the basis graph 30a that corresponds to the submatrix A and the submatrix B may be the basis matrix 30b-5 shown in FIG. 3b-1.

[0109] 8b shows examples of multiple basis matrices of the core matrix of the basis graph 80a. The basis matrices are obtained based on the core matrix of the basis graph 80a and the lifting factor Z. The non-zero elements of row i and column j of the basis graph 80a are calculated by the shift value P i,j and zero elements of the base graph 80a are represented by −1 or null in the shift matrix.

[0110] In another possible implementation, the set of lifting factors could be {24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384}.

[0111] If the lifting factor Z is one of {24, 26, 28, 30}, the portion in the basis matrix of the basis graph 80a that corresponds to the submatrix A and the submatrix B may be the basis matrix 80b-1 shown in FIG. 8b-1; or If the lifting factor Z is one of {32, 36, 40, 44}, the portion in the basis matrix of the basis graph 80a that corresponds to the submatrix A and the submatrix B may be the basis matrix 80b-2 shown in FIG. 8b-1; or If the lifting factor Z is one of {48, 52, 56, 60}, the portion in the basis matrix of the basis graph 80a that corresponds to the submatrix A and the submatrix B may be the basis matrix 80b-3 shown in FIG. 8b-1; or If the lifting factor Z is one of {60, 64, 72, 80, 88, 96, 104, 112, 120}, then the portion in the basis matrix of the basis graph 80a that corresponds to the submatrix A and the submatrix B may be the basis matrix 80b-4 shown in FIG. 8b-1; or If the lifting factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, the portion in the basis matrix of the basis graph 80a that corresponds to the submatrix A and the submatrix B may be the basis matrix 80b-5 shown in FIG. 8b-1; or If the lifting factor Z is one of {256, 288, 320, 352, 384}, the portion in the basis matrix of the basis graph 80a that corresponds to the submatrix A and the submatrix B may be the basis matrix 80b-6 shown in FIG. 8b-2.

[0112] Based on the above implementation, in another possible implementation, in order to further improve the performance, the base graph may correspond to more base matrices, and the parts in the base matrix of the base graph 80a corresponding to the submatrix A and the submatrix B may correspond to different base matrices. For example, If the lifting factor Z is one of {24, 26, 28, 30}, the portion in the basis matrix of the basis graph 80a that corresponds to the submatrix A and the submatrix B may be the basis matrix 80b-1 shown in FIG. 8b-1; or If the lifting factor Z is one of {32, 36, 40, 44}, the portion in the basis matrix of the basis graph 80a that corresponds to the submatrix A and the submatrix B may be the basis matrix 80b-2 shown in FIG. 8b-1; or If the lifting factor Z is one of {48, 52, 56, 60}, the portion in the basis matrix of the basis graph 80a that corresponds to the submatrix A and the submatrix B may be the basis matrix 80b-3 shown in FIG. 8b-1; or If the lifting factor Z is one of {64, 72, 80, 88}, the part in the basis matrix of the basis graph 80a that corresponds to the submatrix A and the submatrix B may be the basis matrix 80b-7 or 80b-8 shown in FIG. 8b-2; or If the lifting factor Z is one of {96, 104, 112, 120}, the portion in the basis matrix of the basis graph 80a that corresponds to the submatrix A and the submatrix B may be the basis matrix 80b-4 shown in FIG. 8b-1; or If the lifting factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, the portion in the basis matrix of the basis graph 80a that corresponds to the submatrix A and the submatrix B may be the basis matrix 80b-5 shown in FIG. 8b-1; or If the lifting factor Z is one of {256, 288, 320, 352, 384}, the portion in the basis matrix of the basis graph 80a that corresponds to the submatrix A and the submatrix B may be the basis matrix 80b-6 shown in FIG. 8b-2.

[0113] In another possible implementation, the portion in the basis matrix of the basis graph 80a that corresponds to submatrix A and submatrix B may be basis matrix 80b-9 shown in Fig. 8b-2. Because the lifting factors Z may be classified in multiple ways, the basis matrix used for a group of lifting factors Z may be considered accordingly in terms of performance.

[0114] For example, the value of the lifting factor Z is determined based on the length K of the input sequence. For example, when the length of the input sequence is K, the minimum value among the lifting factors that satisfy 22*Z≧K may be determined from the multiple lifting factors defined in the system and used as the value of the lifting factor of the matrix. Furthermore, a corresponding basis matrix may be selected based on the determined lifting factor. Table 2 shows an example of the correspondence between the basis matrices and the lifting factors. The multiple lifting factors defined in the system are classified into eight groups, i.e., eight sets, and the indexes of the sets are from 1 to 8. Correspondingly, there are eight basis matrices PCM1 (parity-check matrix, PCM) to PCM8.

[0115] [Table 2]

[0116] For example, a basis matrix 80b-9 may be used as PCM8, where the lifting factor Z is any one of 15, 30, 60, 120, or 240, and 80b-9 may be used as a basis matrix, and the basis matrix is ​​correspondingly lifted by using the lifting factor Z to obtain a parity check matrix of an LDPC. Furthermore, when Z is 24 or more, the basis matrix 80b-9 has a relatively high performance.

[0117] Similarly, within a base matrix, rows may be swapped with one another and columns may be swapped with one another. If at least one of a row permutation or a column permutation is performed on a base graph, the same permutation is also performed on the corresponding base matrix.

[0118] In the above implementation, 80b-1 is a basis matrix obtained by performing row permutations and column permutations on basis matrix 30b-6, 80b-2 is a basis matrix obtained by performing row permutations and column permutations on basis matrix 30b-7, 80b-3 is a basis matrix obtained by performing row permutations and column permutations on basis matrix 30b-8, and 80b-4 is a basis matrix obtained by performing row permutations and column permutations on basis matrix 30b-3. , 80b-5 is a basis matrix obtained by performing row and column permutations on basis matrix 30b-4, 80b-6 is a basis matrix obtained by performing row and column permutations on basis matrix 30b-5, 80b-7 is a basis matrix obtained by performing row and column permutations on basis matrix 30b-9, and 80b-8 is a basis matrix obtained by performing row and column permutations on basis matrix 30b-10.

[0119] Indeed, it will be understood that the portions of the basis matrix of the LDPC matrix that correspond to submatrix A and submatrix B may include rows or columns of any one of basis matrices 30b-1, 30b-2, 30b-3, 30b-4, 30b-5, 30b-6, 30b-7, 30b-8, 30b-9, or 30b-10, i.e., a matrix obtained by performing a column permutation, or a row permutation, or a row permutation and a column permutation is performed on any one of basis matrices 30b-1, 30b-2, 30b-3, 30b-4, 30b-5, 30b-6, 30b-7, 30b-8, 30b-9, or 30b-10.

[0120] In order to obtain flexible coding rates, submatrix C, submatrix D, and submatrix E of corresponding sizes may be added based on the core matrix to obtain different coding rates. Since submatrix C is an all-zero matrix and submatrix E is an identity matrix, the sizes of submatrix C and submatrix E are determined based on the coding rate, and the structures of submatrix C and submatrix E are relatively fixed. Mainly, the core matrix and submatrix D affect the performance of encoding and decoding. Rows and columns may be added based on the core matrix to form corresponding C, D, and E, so that different coding rates may be obtained. For example, the core matrix of base graph 30a or the core matrix of base graph 80a may be used as the core matrix, and corresponding submatrix C, D, and E are added to meet the requirements of encoding or decoding for different coding rates.

[0121] The number of columns of the submatrix D is the sum of the numbers of columns of the submatrix A and the submatrix B, and the number of rows of the submatrix D is mainly related to the coding rate. The basis graph 30a is used as an example. The number of columns m of the corresponding submatrix D is D is (n A + m A ) = 27 columns. The coding rate supported by the LDPC code is R m If , the size of the basis graph or basis matrix of the LDPC code is m*n, where n = n A / R m + p, and m = n - n A= n A / R m + p - n A The minimum coding rate R m is 1 / 3 and the amount of columns of embedded puncture bits p is 2, in the example of the base graph 30a, n = 68, m = 46, and the number of rows m of the submatrix D D is at most m - m A = 46 - 5 = 41, 0 ≤ m D ≦41.

[0122] For ease of explanation, a matrix F with 41 rows and 27 columns can be defined. In this case, the submatrix D is the m D rows, with corresponding sizes of submatrix D, submatrix A, submatrix B, and submatrix E each having a coding rate of 22 / (25 + m D In the basis graph 30a, m D = 41, and submatrix D correspondingly includes 41 rows and 27 columns. Specifically, submatrix D is matrix F, and the corresponding code rate supported by the LDPC code is 22 / 66 = 1 / 3. It may be known that the matrix including rows 5 to 45 and columns 0 to 26 of base graph 30a is matrix F.

[0123] The row weights of the matrix F shown in the example basis graph 30a are, in order, 7, 7, 9, 8, 7, 7, 8, 6, 6, 5, 6, 5, 5, 6, 5, 5, 5, 5, 4, 4, 4, 5, 4, 5, 4, 4, 4, 3, 4, 4, 4, 3, 3, 4, 4, 3, 3, 3, and 4.

[0124] Since submatrix E is an identity matrix, the row weights of base graph 30a are 8, 8, 10, 9, 8, 8, 9, 7, 7, 6, 7, 6, 6, 7, 6, 6, 6, 6, 5, 5, 5, 6, 5, 6, 5, 5, 5, 4, 5, 5, 5, 4, 4, 5, 5, 4, 4, 4, and 5.

[0125] In this application, two adjacent rows in the same column of the base graph have at most one non-zero element, so the two rows are orthogonal to each other.

[0126] In a possible implementation, the matrix F may be a matrix with a quasi-orthogonal structure. In a block of the matrix including columns other than the embedded puncture bits of the matrix F, there is at most one nonzero element in any two adjacent rows in the same column, i.e., the block of the matrix including columns other than the embedded puncture bits of the matrix F has an orthogonal structure. In the example of the basis graph 30a, the matrix F is a matrix including rows 5 to 45 and columns 0 to 26, where columns 0 and 1 are the embedded puncture bits. In the block of the matrix including rows 5 to 45 and columns 2 to 26, rows 5 and 6 are mutually orthogonal, rows 6 and 7 are mutually orthogonal, rows 23 and 24 are mutually orthogonal, rows 32 and 33 are mutually orthogonal, and so on. D = 15, then the submatrix D of the base graph of the LDPC code has 15 rows and 27 columns. Submatrix D may be a matrix that includes rows 0 to 14 of matrix F of base graph 30a, i.e., rows 5 to 19 and columns 0 to 26 of base graph 30a. The corresponding code rate supported by the LDPC code is 22 / 40 = 0.55. At this code rate, the base graph of the LDPC code corresponds to a matrix that includes rows 0 to 19 and columns 0 to 41 of base graph 30a. Submatrix E is an identity matrix with 15 rows and 15 columns, and submatrix C is an all-zero matrix with 5 rows and 15 columns.

[0127] m D= 19, then the submatrix D of the base graph of the LDPC code has 19 rows and 27 columns. Submatrix D may be a matrix that includes rows 0 to 18 of matrix F of base graph 30a, i.e., rows 5 to 23 and columns 0 to 26 of base graph 30a. The corresponding code rate supported by the LDPC code is 22 / 44 = 1 / 2. At this code rate, the base graph of the LDPC code corresponds to a matrix that includes rows 0 to 23 and columns 0 to 41 of base graph 30a. Submatrix E is an identity matrix with 19 rows and 19 columns, and submatrix C is an all-zero matrix with 5 rows and 19 columns.

[0128] This is m D This also applies when x is another value, and the details will not be described.

[0129] It should be noted that in the basis graphs and matrices of an LDPC code, rows may be swapped with each other, and columns may also be swapped with each other. For example, to obtain the basis graph matrix 80a shown in FIG. 8a, rows 17 and 19 of basis graph 30a may be swapped with each other, and columns 39 and 41 may be swapped with each other. As another example, submatrix D may be obtained by swapping m of matrix F. D It contains m rows, and the permutation of the rows is D No replacement is performed between m rows or rows. D , submatrix E continues to have a diagonal structure, and no row or column permutations are performed on submatrix E. For example, to obtain a basis graph 80a, rows 12 and 14 of matrix F are swapped with each other, and submatrix D is obtained by swapping the m rows of submatrix F. Drows, and the sub-matrix E continues to have a diagonal structure. Before the row permutation, the matrix F is a quasi-orthogonal matrix, and after the permutation, the matrix F continues to be a quasi-orthogonal matrix. For example, in the base graph 80a, the matrix F is a matrix including rows 5 to 45 and columns 0 to 26, where columns 0 and 1 are columns of embedded puncture bits. In the block of the matrix including rows 5 to 45 and columns 2 to 26, rows 5 and 6 are orthogonal to each other, rows 29 and 30 are orthogonal to each other, and so on. It will be understood that when the base graph or base matrix includes a sub-matrix D, when columns of the core matrix are swapped with each other, the corresponding columns of the sub-matrix D also need to be swapped with each other. For example, if columns 23 and 25 of the core matrix are swapped with each other, correspondingly, columns 23 and 25 of the sub-matrix D also need to be swapped with each other. Mere examples are provided herein, and the examples are not limiting.

[0130] In the embodiment of the present application, the submatrix D has a quasi-orthogonal structure, specifically, the two adjacent rows of each column other than the column of the embedded puncture bit are orthogonal. For example, in the basis graph 30a, the basis graph 80a, the basis graph 170a shown in FIG. 11a, and the basis graph shown in FIG. 12 given in the submatrix D according to the embodiment of the present application, column 0 and column 1 are the columns of the embedded puncture bit, and the two adjacent rows of each of the other columns are orthogonal. Please note that the column of the embedded puncture bit can be the other column. This is not limited in this specification.

[0131] In another possible implementation, a matrix F having a quasi-orthogonal structure may include at least two orthogonal rows, where there is at most one nonzero element in each of columns 0 to 26 of two adjacent rows in the at least two orthogonal rows. For example, m D>30, the corresponding code rate supported by the LDPC code is less than 2 / 5, and the last 11 rows of matrix F, i.e., the submatrix including rows 30 to 40 and columns 0 to 26 of matrix F, may be orthogonal. Specifically, in matrix F, there is at most one nonzero element in columns other than the embedded puncture bit columns in two adjacent rows from rows 0 to 29, and there is at most one nonzero element in each of columns 0 to 26 in two adjacent rows from rows 30 to 40.

[0132] As another example, the submatrix including rows 26 to 40 and columns 0 to 26 of matrix F may be orthogonal. Specifically, in matrix F, there is at most one nonzero element in columns other than the embedded puncture bit columns of two adjacent rows among rows 0 to 25, and there is at most one nonzero element in each of columns 0 to 26 of two adjacent rows among rows 26 to 40. In the basis graph 170a shown in FIG. 11a, matrix F is a matrix including rows 5 to 45 and columns 0 to 26 of the basis graph, matrix F has a quasi-orthogonal structure, rows 26 to 40 of matrix F are orthogonal, and there is at most one nonzero element in each column of two adjacent rows among rows 26 to 40.

[0133] The core matrix of base graph 170a is the same as the core matrix of base graph 80a. For submatrix D at each code rate, changes can be made to one or two nonzero elements or one or two zero elements in each row without affecting the performance of submatrix D.

[0134] As another example, D>20, the last 21 rows of matrix F, i.e., the submatrix including rows 25 to 45 and columns 0 to 26 of matrix F, may be orthogonal. Specifically, in matrix F, there is at most one nonzero element in columns other than the embedded puncture bit columns in two adjacent rows among rows 0 to 19, and there is at most one nonzero element in each of columns 0 to 26 in two adjacent rows among rows 20 to 40. The core matrix of basis graph 170a shown in FIG. 11a is the same as the core matrix of basis graph 80a. Rows 5 to 45 satisfy a quasi-orthogonal structure, or rows 5 to 25 satisfy a quasi-orthogonal structure, and rows 25 to 45 satisfy a quasi-orthogonal structure.

[0135] The core matrix of the base graph shown in FIG. 12 is the same as the core matrix of base graph 80a, and rows 5 through 45 of the core matrix have a quasi-orthogonal structure.

[0136] The basis matrix 30c shown in FIG. 3c-1 is an example of a basis matrix for the basis graph 30a shown in FIG. 3a. The non-zero elements in row i and column j of the basis graph 30a have the same position in the basis matrix 30c, and the values ​​of the non-zero elements are shifted by the shift value P i,j The submatrix D is the mth shift matrix of the matrix F. D For the basis matrix 30c shown in FIG. D = 41, m D may be selected based on different coding rates. The shift matrix corresponding to the sub-matrix D is the shift matrix of the matrix F. In this specification, the shift matrix of the matrix F is defined as shifting the non-zero elements in row i and column j of the matrix F by a shift value P i,j where zero elements are represented by -1 or null in the shift matrix. Note that only examples are provided herein, and the base graphs may be 80a, 180a, etc., and the base graphs are not described one by one in this specification.

[0137] In a possible implementation, the shift matrix of the matrix F may include any one of the rows or columns of matrices 30c-1 to 30c-10 shown in FIG. 3c-2 to FIG. 3c-11. For example, If the lifting factor Z is one of {16, 18, 20, 22, 24, 26, 28, 30}, the shift matrix of the matrix F may be the matrix 30c-1 shown in FIG. 3c-2 or a matrix obtained by performing row / column permutation on the matrix 30c-1; or If the lifting factor Z is one of {32, 36, 40, 44, 48, 52, 56, 60}, the shift matrix of the matrix F may be the matrix 30c-2 shown in FIG. 3c-3 or a matrix obtained by performing row / column permutation on the matrix 30c-2; or If the lifting factor Z is one of {60, 64, 72, 80, 88, 96, 104, 112, 120}, the shift matrix of the matrix F may be the matrix 30c-3 shown in FIG. 3c-4 or a matrix obtained by performing row / column permutation on the matrix 30c-3; or If the lifting factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, the shift matrix of the matrix F may be the matrix 30c-4 shown in FIG. 3c-5 or a matrix obtained by performing row / column permutation on the matrix 30c-4; or When the lifting factor Z is one of {256, 288, 320, 352, 384}, the shift matrix of the matrix F may be the matrix 30c-5 shown in FIG. 3c-6 or a matrix obtained by performing row / column permutation on the matrix 30c-5.

[0138] The submatrix D of the basis matrix 30c is for a different coding rate, and m of each shift matrix of the matrix F is subtracted to obtain a basis matrix corresponding to the basis graph 30a. D is replaced by m lines. D= 41, the matrix including rows 5 to 45 and columns 0 to 26 of basis matrix 30c are replaced by shift matrices of matrix F to obtain basis matrices with 46 rows and 68 columns corresponding to basis graph 30a. In this case, the coding rate is 1 / 3.

[0139] In another possible implementation, the set of lifting factors could be {24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384}.

[0140] If the lifting factor Z is one of {24, 26, 28, 30}, the shift matrix of the matrix F may be the matrix 30c-6 shown in FIG. 3c-7 or a matrix obtained by performing row / column permutation on the matrix 30c-6; or If the lifting factor Z is one of {32, 36, 40, 44}, the shift matrix of the matrix F may be the matrix 30c-7 shown in FIG. 3c-8 or a matrix obtained by performing row / column permutation on the matrix 30c-7; or If the lifting factor Z is one of {48, 52, 56, 60}, the shift matrix of the matrix F may be the matrix 30c-8 shown in FIG. 3c-9 or a matrix obtained by performing row / column permutation on the matrix 30c-8; or If the lifting factor Z is one of {60, 64, 72, 80, 88, 96, 104, 112, 120}, the shift matrix of the matrix F may be the matrix 30c-3 shown in FIG. 3c-4 or a matrix obtained by performing row / column permutation on the matrix 30c-3; or If the lifting factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, the shift matrix of the matrix F may be the matrix 30c-4 shown in FIG. 3c-5 or a matrix obtained by performing row / column permutation on the matrix 30c-4; or When the lifting factor Z is one of {256, 288, 320, 352, 384}, the shift matrix of the matrix F may be the matrix 30c-5 shown in FIG. 3c-6 or a matrix obtained by performing row / column permutation on the matrix 30c-5.

[0141] Based on the above implementation, in another possible implementation, there are more choices for the shift matrix of matrix F to further improve performance. For example, the shift matrix of matrix F can be matrix 30c-9 shown in FIG. 3c-10 or a matrix obtained by performing row / column permutation on matrix 30c-9, or can be matrix 30c-10 shown in FIG. 3c-11 or a matrix obtained by performing row / column permutation on matrix 30c-10. For example, the lifting factor can be designed as follows:

[0142] If the lifting factor Z is one of {24, 26, 28, 30}, the shift matrix of the matrix F may be the matrix 30c-6 shown in FIG. 3c-7 or a matrix obtained by performing row / column permutation on the matrix 30c-6; or If the lifting factor Z is one of {32, 36, 40, 44}, the shift matrix of the matrix F may be the matrix 30c-7 shown in FIG. 3c-8 or a matrix obtained by performing row / column permutation on the matrix 30c-7; or If the lifting factor Z is one of {48, 52, 56, 60}, the shift matrix of the matrix F may be the matrix 30c-8 shown in FIG. 3c-9 or a matrix obtained by performing row / column permutation on the matrix 30c-8; or When the lifting factor Z is one of {64, 72, 80, 88}, the shift matrix of the matrix F may be the matrix 30c-9 shown in FIG. 3c-10 or a matrix obtained by performing row / column permutation on the matrix 30c-9, or may be the matrix 30c-10 or a matrix obtained by performing row / column permutation on the matrix 30c-10, or If the lifting factor Z is one of {96, 104, 112, 120}, the shift matrix of the matrix F may be the matrix 30c-3 shown in FIG. 3c-4 or a matrix obtained by performing row / column permutation on the matrix 30c-3; or If the lifting factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, the shift matrix of the matrix F may be the matrix 30c-4 shown in FIG. 3c-5 or a matrix obtained by performing row / column permutation on the matrix 30c-4; or When the lifting factor Z is one of {256, 288, 320, 352, 384}, the shift matrix of the matrix F may be the matrix 30c-5 shown in FIG. 3c-6 or a matrix obtained by performing row / column permutation on the matrix 30c-5.

[0143] In another possible implementation, the shift matrix of the matrix F may include any one of the rows or columns of the matrices 80c-1 to 80c-9 shown in Figures 8c-2 to 8c-10. For example, the set of lifting factors may be {24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384}.

[0144] If the lifting factor Z is one of {24, 26, 28, 30}, the shift matrix of the matrix F may be the matrix 80c-1 shown in FIG. 8c-2 or a matrix obtained by performing row / column permutation on the matrix 80c-1; or If the lifting factor Z is one of {32, 36, 40, 44}, the shift matrix of the matrix F may be the matrix 80c-2 shown in FIG. 8c-3 or a matrix obtained by performing row / column permutation on the matrix 80c-2; or If the lifting factor Z is one of {48, 52, 56, 60}, the shift matrix of the matrix F may be the matrix 80c-3 shown in FIG. 8c-4 or a matrix obtained by performing row / column permutation on the matrix 80c-3; or If the lifting factor Z is one of {60, 64, 72, 80, 88, 96, 104, 112, 120}, the shift matrix of the matrix F may be the matrix 80c-4 shown in FIG. 8c-5 or a matrix obtained by performing row / column permutation on the matrix 80c-4; or If the lifting factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, the shift matrix of the matrix F may be the matrix 80c-5 shown in FIG. 8c-6 or a matrix obtained by performing row / column permutation on the matrix 80c-5; or When the lifting factor Z is one of {256, 288, 320, 352, 384}, the shift matrix of the matrix F may be the matrix 80c-6 shown in FIG. 8c-7 or a matrix obtained by performing row / column permutation on the matrix 80c-6.

[0145] Based on the above implementation, in another possible implementation, to further improve performance, the lifting factor Z may be designed with finer granularity, and thus there are more choices for the shift matrix of the matrix F. For example, the shift matrix of the matrix F may be the matrix 80c-7 or a matrix obtained by performing row / column permutation on the matrix, or may be the matrix 80c-8 or a matrix obtained by performing row / column permutation on the matrix. For example, the lifting factor may be designed as follows:

[0146] If the lifting factor Z is one of {24, 26, 28, 30}, the shift matrix of the matrix F may be the matrix 80c-1 shown in FIG. 8c-2 or a matrix obtained by performing row / column permutation on the matrix 80c-1; or If the lifting factor Z is one of {32, 36, 40, 44}, the shift matrix of the matrix F may be the matrix 80c-2 shown in FIG. 8c-3 or a matrix obtained by performing row / column permutation on the matrix 80c-2; or If the lifting factor Z is one of {48, 52, 56, 60}, the shift matrix of the matrix F may be the matrix 80c-3 shown in FIG. 8c-4 or a matrix obtained by performing row / column permutation on the matrix 80c-3; or When the lifting factor Z is one of {64, 72, 80, 88}, the shift matrix of the matrix F may be the matrix 80c-7 shown in FIG. 8c-8 or a matrix obtained by performing row / column permutation on the matrix 80c-7, or may be the matrix 80c-8 shown in FIG. 8c-9 or a matrix obtained by performing row / column permutation on the matrix 80c-8, or If the lifting factor Z is one of {96, 104, 112, 120}, the shift matrix of the matrix F may be the matrix 80c-4 shown in FIG. 8c-5 or a matrix obtained by performing row / column permutation on the matrix 80c-4; or If the lifting factor Z is one of {128, 144, 160, 176, 192, 208, 224, 240}, the shift matrix of the matrix F may be the matrix 80c-5 shown in FIG. 8c-6 or a matrix obtained by performing row / column permutation on the matrix 80c-5, or When the lifting factor Z is one of {256, 288, 320, 352, 384}, the shift matrix of the matrix F may be the matrix 80c-6 shown in FIG. 8c-7 or a matrix obtained by performing row / column permutation on the matrix 80c-6.

[0147] In another possible implementation, when the lifting factor Z is any one of 15, 30, 60, 120, or 240, the shift matrix of matrix F may be matrix 80c-9 shown in FIG. 8c-10 or a matrix obtained by performing row / column permutation on matrix 80c-9. Furthermore, when Z is 24 or more, the performance of the shift matrix of matrix F is relatively high when the shift matrix is ​​80c-9.

[0148] Similarly, within a base matrix, rows may be swapped with one another and columns may be swapped with one another. If at least one of a row permutation or a column permutation is performed on a base graph, the same permutation is also performed on the corresponding base matrix.

[0149] In the above implementation, it may be known that 80c-1 is a basis matrix obtained by performing a row permutation on basis matrix 30c-6, 80c-2 is a basis matrix obtained by performing a row permutation on basis matrix 30c-7, 80c-3 is a basis matrix obtained by performing a row permutation on basis matrix 30c-8, 80c-4 is a basis matrix obtained by performing a row permutation on basis matrix 30c-3, 80c-5 is a basis matrix obtained by performing a row permutation on basis matrix 30c-4, 80c-6 is a basis matrix obtained by performing a row permutation on basis matrix 30c-5, 80c-7 is a basis matrix obtained by performing a row permutation on basis matrix 30c-9, and 80c-8 is a basis matrix obtained by performing a row permutation on basis matrix 30c-10.

[0150] The submatrix D of the basis matrix 80c is for a different coding rate, and m of each shift matrix of the matrix F is subtracted to obtain a basis matrix corresponding to the basis graph 80a. D is replaced by m lines. D = 41, the matrix including rows 5 to 45 and columns 0 to 26 of basis matrix 80c are replaced by shift matrices of matrix F to obtain basis matrices with 46 rows and 68 columns corresponding to basis graph 80a. In this case, the coding rate is 1 / 3.

[0151] Since rows may be swapped and columns may be swapped in the base graph and base matrix, in a possible implementation, the core matrix of the base graph 30a may be used as the core matrix of the base graph, i.e., the part including submatrix A and submatrix B, and the submatrix D of the base graph may be the m-th matrix including rows 5 to 45 and columns 0 to 26 of the base graph 30a. DNote that the basis matrix may include m rows. Correspondingly, the core matrix of the basis matrix may be one of 30b-3, 30b-4, 30b-5, 30b-6, 30b-7, 30b-8, 30b-9, or 30b-10, and the corresponding submatrix D may be one of the following matrices: 30c-3, 30c-4, 30c-5, 30c-6, 30c-7, 30c-8, 30c-9, or 30c-10. D rows. The core matrix and the corresponding sub-matrix D may be selected based on the lifting factors.

[0152] In another possible implementation, the core matrix of the base graph 80a may be used as the core matrix of the base graph, i.e., the part that includes submatrix A and submatrix B, and the submatrix D of the base graph may be the m part of the matrix that includes rows 5 to 45 and columns 0 to 26 of the base graph 80a. D Correspondingly, the core matrix of the basis matrix may be one of 80b-1, 80b-2, 80b-3, 80b-4, 80b-5, 80b-6, 80-7, 80b-8, or 80b-9, and the corresponding submatrix D may be one of the following matrices: 80c-1, 80c-2, 80c-3, 80c-4, 80c-5, 80c-6, 80c-7, 80c-8, or 80c-9. D rows. The core matrix and the corresponding sub-matrix D may be selected based on the lifting factors.

[0153] In another possible implementation, the core matrix of base graph 80a may be used as the core matrix of the base graph, i.e., the portion including submatrix A and submatrix B, and the submatrix D of the base graph may be the mth matrix including rows 5 to 45 and columns 0 to 26 of base graph 170a, as shown in base graph 170a. D Correspondingly, the basis matrix may include m rows in rows 5 to 45 and rows 0 to 4 of the basis matrix 170b shown in FIG. D It may contain rows.

[0154] In another possible implementation, the core matrix of the base graph 80a may be used as the core matrix of the base graph, and the submatrix D of the base graph may be m of the matrix including rows 5 to 45 and columns 0 to 26 of the base graph shown in FIG. D It may contain rows.

[0155] It will be understood that in the present application, a quasi-orthogonal structure is not limited to only two adjacent rows, and a matrix satisfying the quasi-orthogonal structure may be designed to include multiple groups, each group including at least two rows, e.g., three rows or four rows, and the rows included in each group are quasi-orthogonal.

[0156] In the performance curve diagrams shown in FIG. 4 and FIG. 5, LDPC1 indicates that the LDPC code is obtained by encoding based on the basis matrix corresponding to the basis graph 30a, and LDPC2 indicates a common LDPC code for comparison. The horizontal coordinate indicates the length of the information bit sequence, and the unit of length is bits. The vertical coordinate is the symbol signal-to-noise ratio (Es / N0). The performance curves show the performance of the symbol signal-to-noise ratio for LDPC1 and LDPC2 for different information bit sequence lengths when the BLER is 0.01 and 0.0001, respectively. In FIG. 4, the coding rate R is 8 / 9, and in FIG. 5, the coding rate R is 1 / 3. It can be known that at the same BLER, the symbol signal-to-noise ratio of LDPC1 is less than that of LDPC2 for different information bit sequence lengths, that is, the performance of LDPC1 is higher than that of LDPC2.

[0157] In the encoding method provided in the embodiment of the present application, the encoder encodes the input sequence by using an LDPC matrix. The basis graph of the LDPC matrix can be any of the basis graphs in the above examples, and the basis matrix H Bmay be any of the basis matrices of the above examples. The input sequence of the encoder may be an information bit sequence or may be an information bit sequence obtained after at least one of the following processing: appending a CRC or inserting filler bits.

[0158] The method further includes determining a lifting factor Z. A value of the lifting factor Z may be determined based on a length K of the input sequence. The information bit sequence may also be referred to as a code block and may be obtained by performing code block partitioning on the transport block. If the length of the information bit sequence is Kc, a minimum value of the lifting factor that satisfies 22*Z≧Kc may be determined from a plurality of lifting factors defined in the system. If Kc = 3800 and the lifting factors defined in the system include 16, 18, 20, 22, 24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, and 384, then Z may be determined to be 176. Note that merely examples are provided herein and the examples do not constitute a limitation.

[0159] A possible design is that the input sequence has length K = K b Z, i.e., Z = K / K b Filling may be performed on the information bit sequence to obtain an input sequence such that: . For example, the values ​​of the fill bits may be null, 0, or other values ​​agreed upon in the system. After encoding, these fill bits are identifiable and are not transmitted, which is not a limitation in this application.

[0160] The encoder's encoding of the input sequence by using the LDPC matrix H may be encoding the input sequence by using an LDPC matrix corresponding to the lifting factor Z.

[0161] In a possible implementation, the input sequence is c = {c0, c1, c2, ..., c K-1}, the length of the input sequence c is K, and the output sequence obtained after the encoder encodes the input sequence c is d = {d0, d1, d2, ..., d N-1}, where K is an integer greater than 0, and K may be an integer multiple of the lifting factor Z.

[0162] The output sequence d contains K0 bits of the input sequence c and parity bits of the parity sequence w, where K0 is an integer greater than 0 and less than or equal to K, and the length of the parity sequence w is N - K0, and w = {w0, w1, w2, ..., w N-K0-1}.

[0163] The parity sequence w and the input sequence c satisfy equation (1).

[0164]

number

[0165] In the formula, c T = [c0, c1, c2, ..., c K-1 ] T and c T is the transpose vector of the vector containing the bits of the input sequence, and w T = [w0, w1, w2, ..., w N-K0-1 ] T and w T is the transpose vector of the vector containing the bits of the parity sequence, and is 0 T is a column vector, 0 T The value of all elements of is 0.

[0166] H is an LDPC matrix obtained according to any of the basis graphs described in the above embodiments, where the basis graph of H has m rows and n columns and may be any of the basis graphs described in the above embodiments, e.g., 30a, 80a, 170a, and the basis graph shown in FIG. 12.

[0167] In the design, the basis graph of H contains p columns of embedded puncture bits, where p is an integer greater than or equal to 0, and information bits corresponding to the p columns of embedded puncture bits are not output, and the output sequence does not contain information bits corresponding to the p columns of embedded puncture bits. In this case, K0 = K - p·Z. For example, if p = 2, then K0 = K - 2·Z, and the length of the parity sequence w is N + 2·Z - K. If p columns of embedded puncture bits are involved in the coding, then K0 = K, and the length of the parity sequence w is N - K.

[0168] Correspondingly, H may have M rows and (N + p·Z) columns or M rows and N columns, and a ground graph of H may have M / Z rows and

[0169]

number

[0170] It has columns.

[0171] The basis graph of an LDPC matrix H is [H BG H BG,EXT ],

[0172]

number

[0173] and

[0174]

number

[0175] is size m c ×n c represents the all-zero matrix of

[0176]

number

[0177] is the size n c ×n c Represents the unit matrix of .

[0178] A possible design would be:

[0179]

number

[0180] is the submatrix C of the base graph in the above embodiment,

[0181]

number

[0182] is the submatrix E of the above embodiment,

[0183]

number

[0184] where A, B, and D are the submatrix A, submatrix B, and submatrix D of the base graph in the above embodiment, respectively, and m c = 5, 0 ≤ n c ≦41, and H BG The number of rows in is less than or equal to 46 and greater than or equal to 5, and H BG The number of columns is equal to 27.

[0185] In another possible design, column 26 is a weight 1 matrix column, and the non-zero elements of column 26 are in row 5, so that

[0186]

number

[0187] may include the first four rows of column 26 of the base graph of the above embodiment and the first four rows of the submatrix C of the above embodiment,

[0188]

number

[0189] may include the submatrix E of the base graph in the above embodiment, rows 5 to 46 of column 26, and the last row of the submatrix C, and m c = 4, 0 ≤ n c ≦42, and H BG is the matrix obtained after the last column is deleted from the part including submatrix A, submatrix B, and submatrix D of the base graph in the above embodiment, and H BG The number of rows in is less than or equal to 46 and greater than or equal to 5, and H BG The number of columns of H is equal to 26. Optionally, if the coding rate needs to be further increased, BG may have four rows, namely row 0 through row 3.

[0190] Correspondingly, the LDPC matrix H may be represented as H = [H1H2].

[0191] H1 is H BG Each zero element of is replaced by an all-zero matrix of size Z*Z, and each non-zero element of is replaced by a cyclic permutation matrix h i,j can be obtained after replacing the cyclic permutation matrix h i,j is a unit matrix of size Z*Z on the right i,j is obtained by circular shifting, I(P i,j), where i is the row index and j is the column index. In a possible design, P i,j = mod(V i,j , Z) and V i,j is the nonzero element in row i and column j of the basis matrix that corresponds to the index of the set of lifting factors corresponding to Z.

[0192] H2 is H BG,EXT may be obtained after each zero element of Z*Z is replaced by an all-zero matrix of Z*Z and each non-zero element is replaced by an identity matrix of Z*Z.

[0193] The encoder may perform the encoding and output in multiple ways. Either one of the basis graphs shown in FIG. 12 described in the above embodiment, the basis graph 80a, or the basis graph 170a is used as an example for explanation below. The basis graph has a maximum of 46 rows and a maximum of 68 columns, and includes two columns of embedded puncture bits. For ease of explanation, the basis graph with the most rows and the most columns may be referred to as the complete basis graph in this application.

[0194] Method 1:

[0195] The encoding is performed based on the complete basis graph to obtain as many parity bits as possible, where m = 46 and n = 68, which corresponds to rows 0 to 45 and columns 0 to 67 of any one of the basis graphs mentioned above.

[0196] Correspondingly, M = 46·Z for the LDPC matrix H. N = 68·Z if the output sequence contains information bits corresponding to the sequence of embedded puncture bits, or N = 66·Z if the output sequence does not contain 2·Z information bits corresponding to the sequence of embedded puncture bits.

[0197] During subsequent processing, one or more information bits and one or more parity bits that need to be transmitted may be determined from the output sequence generated by the encoder.

[0198] Method 2:

[0199] The encoding is performed based on some rows and some columns of the complete basis graph. Rows and columns may be selected from the complete basis graph for encoding based on the code rate, the amount of information bits and the amount of parity bits that need to be transmitted, etc.

[0200] For example, the coding rate is 8 / 9, m = 5, and n = 27, i.e., the coding is performed based on rows 0 to 4 and columns 0 to 26 of any one of the base graphs mentioned above.

[0201] Correspondingly, M = 5·Z for the LDPC matrix H. N = 27·Z if the output sequence contains information bits corresponding to the columns of embedded puncture bits, or N = 25·Z if the output sequence does not contain information bits corresponding to the columns of embedded puncture bits.

[0202] As another example, the code rate is 1 / 3, m=46, and n=68.

[0203] In this method, it may be known that the size of the basis graph of H satisfies 5≦m≦46 and 27≦n≦68, and correspondingly, for the LDPC matrix H, 5·Z≦M≦46·Z and 27·Z≦N≦68·Z.

[0204] In a possible design, the 26th column of any of the above base graphs is a weight 1 matrix column, and puncturing may be performed on the weight 1 matrix column of the core matrix, so that the core matrix is ​​accordingly reduced by one row and one column, and m = 4 and n = 26, that is, encoding is performed based on rows 0 to 3 and columns 0 to 25 of any of the above base graphs. In this manner, a higher coding rate can be obtained. Thus, the size of the base graph satisfies 4≦m≦46 and 26≦n≦68, and correspondingly, for the LDPC matrix H, 4·Z≦M≦46·Z and 26·Z≦N≦68·Z.

[0205] In the above implementation, the basis matrix H of the LDPC matrix H is B may be any of the basis matrices described in the above embodiments, or a basis matrix obtained by performing row permutation, or column permutation, or row permutation and column permutation on any of the above basis matrices. B The basis graph of includes at least submatrix A and submatrix B, and may further include submatrix C, submatrix D, and submatrix E. For the submatrix, reference shall be made to the description of the above embodiment, and the details will not be described again in this specification. Indeed, the basis matrix H B may be another basis matrix whose basis graph conforms to the basis graph shown in the above embodiment, and the basis matrix H B are not limited thereto in this application.

[0206] In a possible implementation, the basis matrix H of the LDPC code B may be stored in a memory, and the encoder derives an LDPC matrix corresponding to the lifting factor Z for encoding the input sequence.

[0207] In another possible implementation, multiple basis matrices H B exists and the basis matrix H BSince a relatively large storage space is occupied when is stored based on a matrix structure, a basis graph of the LDPC code may be stored in a memory, and the shift values ​​of the non-zero elements of each basis matrix may be stored row by row or column by column, and then an LDPC matrix may be obtained based on the basis graph and the shift values ​​of the basis matrix corresponding to the lifting factor Z.

[0208] The basis graph may indicate the positions of the non-zero elements of each basis matrix. In another possible implementation, storing the basis graph may be storing the positions of the non-zero elements of the basis graph. The positions of the non-zero elements may be indicated by the rows and columns with the non-zero elements, for example, the positions of the columns with the non-zero elements of each row, or the positions of the rows with the non-zero elements of each column. In another possible implementation, storing the basis graph may be storing the positions of the zero elements of the basis graph. Similarly, the positions of the zero elements may also be indicated by the rows and columns with the zero elements, for example, the positions of the columns with the zero elements of each row, or the positions of the rows with the zero elements of each column, and the corresponding positions of the non-zero elements may be obtained by excluding the positions of the zero elements. It should be noted that merely examples are provided herein, and examples do not constitute a limitation in this application.

[0209] In the design, the parameters related to the basis graph or the basis matrix may be represented in a table. For example, the related parameters or the table may be stored in one or more memories. The related parameters, such as the row index of the basis graph or the basis matrix, or the column with the non-zero elements, are read from the memory to obtain the basis graph or the basis matrix. Optionally, the weight of each row and the shift value of the non-zero elements of each row may be further stored.

[0210] Figure 11a is used as an example for explanation below. For other basis graphs or basis matrices provided in this application, please refer to similar designs.

[0211] For example, the core matrix of base graph 80a, base graph 170a, or the base graph shown in FIG.

[0212] [Table 3]

[0213] For example, the base graph of the LDPC matrix may include a portion of the core matrix shown in Table 3. Another portion of the base graph of the LDPC matrix may be shown in base graph 80a, base graph 170a, or the base graph shown in FIG. 12, or another structure described in this application, or another matrix structure, which is not limited in this application.

[0214] Basis graph 170a is used as another example. Parameters associated with the first 24 rows of the basis graph may be shown in Table 4. Parameters associated with the other rows are similar and are not listed in Table 4 due to space limitations.

[0215] [Table 4]

[0216] Please note that only examples are provided herein, and examples are not limiting. Related parameters of other basis graphs or basis matrices provided in this application can also be represented in similar tables. It will be understood that the basis graph 170a, Table 3, and Table 4 are intended to help understand the design of the basis graphs and basis matrices. The representation format is not limited to the representation format of the basis graph 170a or Table 3 or Table 4. It may include other possible variations.

[0217] In implementation, the format of column index, column weight, and rows with non-zero elements or rows with zero elements, for example, Table 5, may be used.

[0218] [Table 5]

[0219] In implementation, the parameter "row weight" or "column weight" in Table 3, Table 4, or Table 5 may be omitted. The amount of non-zero elements in a row or column may be known from the column or row in which there are non-zero elements. Thus, the row weight or column weight is also known.

[0220] In an implementation, the parameter values ​​of the "column index of the nonzero element in the row" in Table 3 or Table 4 or the parameter values ​​of the "row index of the nonzero element in the column" in Table 5 cannot be sorted in ascending order if a column with nonzero elements or a row with nonzero elements can be retrieved among the parameter values.

[0221] In an implementation, Table 3 or Table 4 may further include a column of "shift value of non-zero element", where the parameter values ​​of the column of "shift value of non-zero element" correspond one-to-one with the parameter values ​​of the column index of non-zero element in row. Table 5 may further include a column of "shift value of non-zero element", where the parameter values ​​of the column of "shift value of non-zero element" correspond one-to-one with the parameter values ​​of the column index of non-zero element in row.

[0222] In the design, to save storage space, the positions of nonzero elements in a portion of the base graph that has a relatively fixed structure may be calculated based on row or column indexes without the positions being stored. For example, the submatrix E is a diagonal matrix and contains nonzero elements only on the diagonal of the matrix. The positions of columns with nonzero elements in the submatrix E may be calculated based on row indexes, or the positions of rows with nonzero elements may be calculated based on column indexes. In the example of any one of the base graphs 80a, 170a, or FIG. 12, the positions of the rows m e The column indices of the nonzero elements of m e +K band m e ≧4, and K b = 22. For example, the column with the nonzero element in row 7 is column 29. As another example, the bidiagonal structure B' of submatrix B is in rows 0 to 3 and columns 23 to 25 of base graph 80a, base graph 170a, or any one of the base graphs shown in FIG. 12. The column indexes of the columns with the nonzero elements of the bidiagonal structure B' may be calculated based on the row indexes, or the row indexes of the rows with the nonzero elements may be calculated based on the column indexes. B The location of the nonzero elements in B +K b and column m B +K b Including +1, 0 <m B <3. Row m B The location of the nonzero elements in B +K b and m B = 0 or m B As another example, for a weight 1 matrix column of submatrix B, i.e., column 26 of any one of base graph 80a, base graph 170a, or the base graphs of FIG. 12, row m B The location of the nonzero elements in B +K b and m B = 4.

[0223] Table 6 shows the parameters associated with the rows of FIG. 12. The positions of columns with non-zero elements in columns 0 through 25 may be stored, while the positions of columns with non-zero elements in columns 26 through 68 are not stored, i.e., the positions of non-zero elements of weight 1 matrix columns of submatrix E and submatrix B are not stored. Table 6 shows the parameters associated with the rows of FIG. 12. BG can be used to represent

[0224] [Table 6]

[0225] Table 7 shows the parameters associated with the rows of FIG. 12. The positions of columns with non-zero elements in columns 0 through 26 may be stored, while the positions of columns with non-zero elements in columns 27 through 68 are not stored, i.e., the columns with non-zero elements of submatrix E are not stored. Table 7 shows the parameters associated with the rows of FIG. 12. BG can be used to represent

[0226] [Table 7]

[0227] In the above design, the "row weight" column is optional. In a possible design, the ones and zeros in each row or column of the basis graph can be considered as binary numbers, and storing the binary numbers in decimal or hexadecimal can save storage space. Any one of the above basis graphs is used as an example. The positions of the non-zero elements in the first 26 columns or the first 27 columns can be stored in four hexadecimal numbers in each row. For example, if the first 26 columns of row 0 are 11110110 01111101 10111111 00, the positions of the non-zero elements in row 0 can be written as 0xF6, 0x7D, 0xBF, and 0x00. Specifically, every eight columns form one hexadecimal number. The last two or three columns are filled with zeros to obtain eight digits, resulting in the corresponding hexadecimal number. This also applies to other rows, and the details will not be described again in this specification.

[0228] When the information bit sequence is to be encoded, the basis matrix H B can be lifted based on Z to obtain the LDPC matrix H used for encoding. i,j is the basis matrix H B For each non-zero element P i,j is determined with respect to h i,j Let P be the unit matrix. i,j To obtain the parity check matrix H, we use the nonzero elements P i,j h i,jis replaced by the basis matrix H B are replaced by an all-zero matrix of size Z*Z.

[0229] In a possible design, the basis matrix H B Element P in row i and column j of i,j can satisfy the relationship shown in (2).

[0230]

number

[0231] In the formula, V i,j may be the shift value of the element in row i and column j of the basis matrix of the set of lifting factors that includes lifting factor Z, or the shift value of the non-zero element in row i and column j of the basis matrix that corresponds to the largest lifting factor in the set of lifting factors that includes lifting factor Z.

[0232] The correspondence between the indices of the basis matrices and the set of lifting factors Z shown in Table 2 is used as an example. Z = 13, and the element P i,j satisfies (2).

[0233] V i,j is the shift value of the non-zero element in row i and column j of the basis matrix denoted by PCM7. For Z = 13, the shift value V i,j Modulo arithmetic is performed by taking modulo Z, where Z = 13, and V i,j is the shift value of the non-zero element in row i and column j of the basis matrix indicated by PCM7.

[0234] It should be noted that merely examples are provided herein and that the examples do not constitute limitations on this application.

[0235] The basis graph 80a or the basis graph 170a is used as an example.B After H is determined, one or more parity bits corresponding to columns 22 to 25 of the basis matrix are added to the input sequence and rows 0 to 3 and columns 0 to 25, i.e., H core-dual and one or more parity bits corresponding to column 26, i.e., the weight 1 matrix column, may be obtained by first using the input sequence and H core-dual Then, encoding can be performed based on the input sequence, one or more parity bits corresponding to columns 22 to 26, and submatrix D to obtain one or more parity bits corresponding to submatrix E. In this way, encoding is completed. For the encoding process of the LDPC code, please refer to the above implementation description, and the details will not be described again in this specification.

[0236] In a communication system, an LDPC code can be obtained after encoding is performed in the above-mentioned manner. After the LDPC code is obtained, the communication device can further perform one or more of the following operations: performing rate matching on the LDPC code, performing interleaving on the LDPC code obtained after rate matching according to an interleaving scheme, modulating the LDPC code obtained after interleaving according to a modulation scheme to obtain a bit sequence X, or transmitting the bit sequence X.

[0237] In a decoding method provided in another embodiment of the present application, a decoder decodes an input sequence by using an LDPC matrix. The basis graph of the LDPC matrix can be any of the basis graphs in the above examples, and the basis matrix H B may be any of the basis matrices in the above examples. The input sequence of the decoder may be a sequence of soft decision values ​​of the LDPC code.

[0238] The method further includes determining a lifting factor Z. A communication device at a receiving end may receive a signal including an LDPC code, obtain a soft value sequence of the LDPC code in the signal, and determine a corresponding lifting factor Z.

[0239] The decoder's decoding of the input sequence by using the LDPC matrix H may be decoding a soft-decision value sequence of the LDPC code by using the LDPC matrix H corresponding to the lifting factor Z.

[0240] Since decoding is the inverse process of encoding, please refer to the encoding embodiment above for the description of the LDPC matrix H and the basis graph of the LDPC matrix H. Decoding can be performed based on the complete basis graph, or decoding can be performed based on some rows or some columns of the complete basis graph.

[0241] Basis matrix H of LDPC matrix H B may be any of the basis matrices described in the above embodiments, or a basis matrix obtained by performing row permutation, or column permutation, or row permutation and column permutation on any of the above basis matrices. B The basis graph of includes at least submatrix A and submatrix B, and may further include submatrix C, submatrix D, and submatrix E. For the submatrix, reference shall be made to the description of the above embodiment, and the details will not be described again in this specification. Indeed, the basis matrix H B may be another basis matrix whose basis graph conforms to the basis graph shown in the above embodiment, and the basis matrix H B are not limited thereto in this application.

[0242] In a possible design, the basis matrix H B may be stored in a memory, and after the LDPC matrix corresponding to the lifting factor Z is obtained, the soft decision values ​​of the LDPC code may be decoded.

[0243] In another possible implementation, since there are multiple basis matrices of an LDPC code, and when the basis matrices are stored based on a matrix structure, a relatively large storage space is occupied, a basis graph of the LDPC code may be stored in a memory, and the shift values ​​of the non-zero elements of each basis matrix may be stored row by row or column by column, and then an LDPC matrix may be obtained based on the basis graph and the shift values ​​of the basis matrix corresponding to the lifting factor Z.

[0244] The basis graph can be stored in a variety of ways as described in the encoding embodiments above.

[0245] It should be noted that only examples are provided herein and that the examples are not limiting.

[0246] Decoding is the inverse process of encoding, and the basis matrix H used during decoding is B has the same characteristics as the basis matrix of the embodiment of the encoding method. B For lifting, please also refer to the encoding method embodiment.

[0247] In a communication system, prior to the decoding method, the communication device may further perform one or more of the following operations: receiving a signal including an LDPC code, or performing demodulation, deinterleaving, or rate dematching on the signal to obtain a soft decision value of the LDPC code.

[0248] In a possible implementation, one or more of the following may be stored: (a) Any of the basis matrices H described in the implementation above B The parameters used to obtain the basis matrix H Bmay be obtained based on parameters, for example, the parameters including one or more of the following: row index, row weight, column index, or column weight of the basis graph and / or basis matrix, position of a non-zero element of the basis graph and / or basis matrix, shift value of the basis matrix, shift value of a non-zero element and corresponding position, compensation value, lifting factor, set of lifting factors, basis graph of the basis matrix, or code rate; (b) any of the basis matrices H described in the implementation above B , (c) Basis matrix H B The matrix lifted from (d) any of the basis matrices H described in the implementation above B a basis matrix obtained by performing row / column permutations on (e) Lifted matrix from the basis matrices obtained by performing row / column permutations.

[0249] In a possible implementation, the input sequence may be encoded or decoded by using a low density parity check LDPC matrix in one or more of the following ways during encoding or decoding:

[0250] Based on the parameters described in (a) above, the basis matrix H B and the obtained basis matrix H B or performs encoding or decoding based on the obtained basis matrix H B and performing row / column permutation based on the matrix obtained by performing the row / column permutation, the encoding or decoding being performed based on the matrix of the present specification, and optionally, the encoding or decoding may be performed based on a lifted matrix of the matrix of the present specification. The basis matrix stored in (b) or (d) (the stored basis matrix H B Or the basis matrix H Bor performing encoding or decoding based on a basis matrix obtained by performing row / column permutation on the stored basis matrix, the encoding or decoding being performed based on a basis matrix herein, and optionally, the encoding or decoding may be performed based on a lifted matrix of the basis matrix; or performing row / column permutation on the stored basis matrix, the encoding or decoding being performed based on a basis matrix obtained by performing row / column permutation on the stored basis matrix, the encoding or decoding being performed based on a basis matrix herein, and optionally, the encoding or decoding may be performed based on a lifted matrix of the basis matrix; Perform encoding or decoding based on (c) or (e).

[0251] The lifting in this application may be to obtain a lifted matrix after the matrix is ​​transformed or processed, and the lifting method is not limited in this application. In an implementation, the lifting may be to perform a compensation process on the matrix. For example, each shift value of 0 or more of the basis matrix is ​​increased or decreased by a compensation value to obtain a compensated matrix. In another implementation, the lifting may be to lift rows and columns of the matrix to obtain a lifted matrix. In another implementation, the lifting may be to transform non-zero values ​​of the matrix.

[0252] Storing in this application may be storing in one or more memories. The one or more memories may be located separately or integrated into an encoder, a decoder, a processor, a chip, a communication device, or a terminal. Some of the one or more memories may be located separately and other memories may be integrated into a decoder, a processor, a chip, a communication device, or a terminal. The type of memory may be any form of storage medium, and the type is not limited in this application.

[0253] 6 is a schematic structural diagram of a communication device 600. The device 600 is configured to implement the method described in the above method embodiment. Please refer to the description of the above method embodiment. The communication device 600 may be a chip, a base station, a terminal, or another network device.

[0254] The communication device 600 includes one or more processors 601. The processor 601 may be a general-purpose processor, a special-purpose processor, etc. For example, the processor 601 may be a baseband processor or a central processing unit. The baseband processor may be configured to perform processing related to communication protocols and communication data. The central processing unit may be configured to control the communication device (such as a base station, a terminal, or a chip), execute software programs, and process data of the software programs.

[0255] In one possible design, the communications device 600 includes one or more processors 601. The one or more processors 601 may implement the functionality of the encoder described above. In another possible design, the encoder may be part of the processor 601, and the processor 601 may implement other functionality in addition to the functionality of the encoder.

[0256] The communication device 600 encodes the input sequence by using an LDPC matrix. The basis graph of the LDPC matrix may be any of the example basis graphs described above, or a basis graph obtained by performing row permutation, or column permutation, or row permutation and column permutation on any of the above basis graphs. The basis matrix H of the LDPC matrix may be B may be a basis matrix of any of the above-mentioned embodiments, or a basis matrix obtained by performing row permutation, or column permutation, or row permutation and column permutation on any of the above-mentioned basis matrices. The input sequence of the encoder may be an information bit sequence.

[0257] In one possible design, one or more processors 601 may implement the functionality of the decoder described above. In another possible design, the decoder may be part of the processor 601.

[0258] The communication device 600 is configured to decode the input sequence by using the LDPC matrix. The basis graph of the LDPC matrix may be any of the basis graphs in the above examples, or a basis graph obtained by performing row permutation, or column permutation, or row permutation and column permutation on any of the above basis graphs. The basis matrix H B may be any of the basis matrices in the above examples, or a basis matrix obtained by performing row permutations, or column permutations, or row and column permutations on any of the above basis matrices. The input sequence of the decoder may be a sequence of soft decision values.

[0259] Optionally, in a design, the processor 601 may also include instructions 603. The instructions may be executed on the processor to cause the communications device 600 to perform the methods described in the method embodiments above.

[0260] In another possible design, the communications device 600 may also include circuitry that may implement the functionality of the encoder, decoder, or encoder and decoder of the above-mentioned method embodiments.

[0261] Optionally, the communication device 600 may include one or more memories 602. The memory may store instructions 604, which may be executed on the processor to cause the communication device 600 to perform the method described in the above method embodiment. Optionally, the memory may further store data. Optionally, the processor may also store instructions and / or data. The processor and memory may be located separately or integrated together. Optionally, the one or more memories 602 may store parameters related to the basis matrix, such as shift values, basis graphs, matrices lifted from the basis graphs, rows of the basis matrix, or lifting factors. Optionally, the one or more memories 602 may store the basis matrix or matrices lifted from the basis matrix.

[0262] Optionally, the communication device 600 may further include a transceiver 605 and an antenna 606. The processor 601 may also be called a processing unit and controls the communication device (terminal or base station). The transceiver 605 may also be called a transceiver unit or transceiver circuit and is configured to implement the transmission and reception functions of the communication device by using the antenna 606.

[0263] Optionally, the communication device 600 may further include a component configured to generate a CRC of a transport block, a component used for segmentation and CRC checking of code blocks, an interleaver used for interleaving, a modulator used for modulation processing, etc. The functionality of these components may be implemented by one or more processors 601.

[0264] Optionally, the communications device 600 may further include a demodulator used for demodulation, a deinterleaver used for deinterleaving, components used for rate dematching, etc. The functionality of these components may be implemented by one or more processors 601.

[0265] 7 is a schematic diagram of a communication system 700. The communication system 700 includes a communication device 70 and a communication device 71. The communication device 70 and the communication device 71 receive information data from each other and transmit information data to each other. The communication device 70 and the communication device 71 may be communication apparatuses 600, or the communication device 70 and the communication device 71 include communication apparatuses 600 and receive and transmit information data, respectively. For example, the communication device 70 may be a terminal, and the communication device 71 may be a base station, correspondingly. As another example, the communication device 70 may be a base station, and the communication device 71 may be a terminal, correspondingly.

[0266] Those skilled in the art will further understand that various illustrative logical blocks and steps listed in the embodiments of the present application can be implemented by using electronic hardware, computer software, or a combination thereof. Whether a function is implemented by using hardware or software depends on the requirements of a specific application and the overall system design. Those skilled in the art may use various methods to implement the described functions for each specific application, but the implementation should not be considered to be outside the scope of the embodiments of the present application.

[0267] The various exemplary logic units and circuits described in the embodiments of the present application may implement or operate the described functions by using a design of a general-purpose processor, a digital signal processor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or another programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general-purpose processor may be a microprocessor. Optionally, the general-purpose processor may be any conventional processor, controller, microcontroller, or state machine. The processor may be implemented by a combination of computing devices such as a digital signal processor and a microprocessor, multiple microprocessors, one or more microprocessors with a digital signal processor core, or any other similar configuration.

[0268] The steps of the method or algorithm described in the embodiments of the present application may be directly embedded in hardware, instructions executed by a processor, or a combination thereof. The memory may be a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable magnetic disk, a CD-ROM, or any other form of storage medium in the art. For example, the memory may be connected to the processor such that the processor can read information from the memory and write information to the memory. Optionally, the memory may be integrated into the processor. The processor and the memory may be located in an ASIC, and the ASIC may be located in a communication device (such as a base station or a terminal). Optionally, the processor and the memory may be located in different components of the communication device.

[0269] Through the above description of implementation, those skilled in the art will clearly understand that the present application can be implemented by hardware, firmware, or a combination thereof. When the present application is implemented by a software program, the present application can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded into a computer and executed, the procedure or function according to the embodiment of the present application is generated in whole or in part. When the present application is implemented by a software program, the above-mentioned functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes in a computer-readable medium. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or another programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. The computer-readable medium includes computer storage media and communication media, and the communication medium includes any medium that allows a computer program to be transmitted from one place to another. The storage medium can be any available medium that can be accessed by a computer. The following provides examples but does not impose limitations. The computer-readable medium may include RAM, ROM, EEPROM, CD-ROM, or other optical or disk storage medium, or other magnetic storage device, or any other medium that can carry or store expected program code in the form of instructions or data structures and that can be accessed by a computer. Additionally, any connection may be properly defined as a computer-readable medium.For example, if the software is transmitted from a website, server, or another remote source by using coaxial cable, optical fiber / cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio wave, and microwave, the coaxial cable, optical fiber / cable, twisted pair, DSL, or wireless technologies such as infrared, radio wave, and microwave are included in the definition of the medium to which they belong. For example, Disk or disc as used by this application includes compact disc (CD), laser disc (registered trademark), optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disk generally copies data by magnetic means, and disc copies data optically by means of laser. Combinations of the above should also be included in the scope of protection of computer-readable medium.

[0270] In this application, " / " denotes and / or, for example, encoding / decoding denotes encoding, decoding, or encoding and decoding.

[0271] In summary, what has been described above is only an embodiment of the technical solution of the present application, and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, or improvement made without departing from the principle of the present application falls within the protection scope of the present application. [Explanation of symbols]

[0272] 10a Ground Graphs 10b basis matrix 11a All-zero matrix 11b Identity matrix 11d cyclic permutation matrix 30a Ground Graph 30b-1 Basis matrix 30b-2 Basis matrix 30b-3 Basis matrix 30b-4 Basis matrix 30b-5 Basis matrix 30b-6 Basis matrix 30b-7 Basis matrix 30b-8 Basis matrix 30b-9 Basis matrix 30b-10 Basis matrix 30c basis matrix 30c-1 matrix 30c-2 matrix 30c-3 matrix 30c-4 matrix 30c-5 matrix 30c-6 matrix 30c-7 matrix 30c-8 matrix 30c-9 matrix 30c-10 matrix 70 Communication Devices 71 Communication Devices 80a Ground Graph 80b-1 basis matrix 80b-2 basis matrix 80b-3 basis matrix 80b-4 basis matrix 80b-5 basis matrix 80b-6 basis matrix 80b-7 basis matrix 80b-8 basis matrix 80b-9 Basis matrix 80c-1 matrix 80c-2 matrix 80c-3 matrix 80c-4 matrix 80c-5 matrix 80c-6 matrix 80c-7 matrix 80c-8 matrix 80c-9 matrix 170a Ground Graph 170b-1 Basis matrix 180a Ground Graph 200 Column weights (column weights) 600 Communication Equipment 601 Processor 602 Memory 603 Instructions 604 Instructions 605 Transceiver 606 Antenna 700 Communication Systems A, B, B', C, D, E submatrix c input series c T , w T Transposed Vector d output series F matrix H LDPC matrix H' LDPC matrix H B basis matrix H core , H core-dual , H BG matrix h i,j cyclic permutation matrix i row, row index j column, column index 0 T Column vector p is the amount of bits, the amount of columns R m Encoding rate, minimum encoding rate P i,j Shift value, nonzero elements, elements P e Vector PCM1~PCM8 basis matrix S, S' input series s0 the amount of bits shortened [SP e ] T Transpose matrix V i,j Shift Value w Parity sequence X bit sequence Z Lifting Factor

Claims

1. 1. An encoding method comprising: determining a lifting factor Z, where Z is a positive integer; encoding an input sequence based on a basis matrix corresponding to the lifting factor Z to obtain a low-density parity-check (LDPC) code; Equipped with The basis matrix is ​​represented by a matrix with m rows and n columns, where m is an integer of 5 or more, and n is an integer of 27 or more; the basis matrix comprises at least a submatrix A and a submatrix B; The submatrix A is a matrix with 5 rows and 22 columns, The submatrix B is a matrix with 5 rows and 5 columns, In a matrix formed by the submatrix A and the submatrix B, one row has a weight between 1 and 5, and the other four rows have weights between 17 and 21. An encoding method characterized by:

2. A decoding method comprising: determining a lifting factor Z, where Z is a positive integer; decoding an input sequence of a low-density parity-check (LDPC) code based on a basis matrix corresponding to the lifting factor Z; Equipped with The basis matrix is ​​represented by a matrix with m rows and n columns, where m is an integer of 5 or more, and n is an integer of 27 or more; the basis matrix comprises at least a submatrix A and a submatrix B; The submatrix A is a matrix with 5 rows and 22 columns, The submatrix B is a matrix with 5 rows and 5 columns, In a matrix formed by the submatrix A and the submatrix B, one row has a weight between 1 and 5, and the other four rows have weights between 17 and 21. A decoding method comprising:

3. 3. The method according to claim 1, wherein in the matrix formed by the submatrix A and the submatrix B, one row has a weight of 3 and the other four rows have a weight of 19.

4. In the matrix formed by the submatrix A and the submatrix B, one row is [Equation 1] and The other four lines are: [Equation 2] The method according to any one of claims 1 to 3, wherein

5. The matrix formed by the submatrix A and the submatrix B is expressed as follows: [Equation 3] 5. The method according to any one of claims 1 to 4.

6. the basis matrix further comprises submatrix C, submatrix D, and submatrix E; The submatrix C has 5 rows and m D is a column-all-zero matrix, The submatrix D is m D is a matrix with 27 rows and 27 columns, The submatrix E is m D row m D is the column identity matrix, m D is an integer, and 0≦m D 6. The method of claim 1, wherein the β-amino acid is ≦41.

7. The method of claim 1 , wherein the basis matrix comprises 46 rows and 68 columns.

8. The method of claim 1 , wherein the basis matrix comprises two columns of embedded puncture bits.

9. 9. The method of claim 1, wherein each element of the basis matrix corresponds to either an all-zero matrix of size Z*Z or a cyclic permutation matrix of size Z*Z.

10. The circulant permutation matrix is ​​a unit matrix P i,j 10. The method of claim 9, wherein the matrix is ​​obtained by circular shifting the matrix.

11. A communication device comprising a module adapted to carry out any one of claims 1 and 3 to 10.

12. A communication device comprising a module adapted to carry out any one of claims 2 to 10.

13. A computer readable storage medium comprising a program, which when executed causes a computer to carry out the method according to any one of claims 1 to 10.

14. A program that causes a computer to execute the method according to any one of claims 1 to 10.

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