Communication device

Abstract

To suppress jitter in a multichannel communication device.SOLUTION: A communication device includes an oscillator, a signal generation circuit, an insulation element, and an output circuit. The oscillator is configured to output a carrier signal when an input signal externally input is at a first logic level. The signal generation circuit includes: a delay circuit; a first logic circuit having a first input end to receive an input signal and a second input end to receive an input signal via the delay circuit; a second logic circuit having a first input end connected to an output end of the first logic circuit and having a second input end to receive a carrier signal; a third logic circuit having a first input end to receive an input signal and a second input end connected to an output end of the second logic circuit; and a driving circuit to amplify a voltage output by the third logic circuit. The insulation element is connected to an output of the driving circuit. The output circuit receives a signal based on the output signal of the driving circuit via the insulation element and outputs the signal to the outside.SELECTED DRAWING: Figure 23

Description

[Technical field]

[0001] The embodiment relates to a communication device. [Background technology]

[0002] Galvanic isolation elements are known as elements included in communication devices that connect high-voltage equipment and low-voltage equipment. Galvanic isolation elements are used to prevent noise leakage and electric shock between high-voltage equipment and low-voltage equipment, and can transmit only signals while ensuring electrical insulation between input and output. Examples of media that galvanic isolation elements use to transmit signals include light, electric fields, and magnetic fields.

[0003] For example, a photocoupler that includes a light-emitting diode (LED) as a light generating element and a photodiode (PD) as a light receiving element is known as a galvanic isolation element that uses an optical signal as a signal transmission medium. Photocouplers ensure electrical insulation by a resin provided between the LED and the PD. For this reason, photocouplers have high reliability in terms of their isolation function.

[0004] However, when a communication device transmits multiple signals, the photocoupler needs to have the same number of LED and PD pairs as the number of signals to be transmitted. If multiple LEDs and PDs are implemented in one photocoupler, crosstalk may occur between the multiple signals to be transmitted. Furthermore, implementing multiple LEDs and multiple PDs in a photocoupler may result in reduced reliability and increased costs due to complex assembly.

[0005] In contrast, a galvanic isolation element that uses an electric field or a magnetic field as a signal transmission medium can eliminate the above-mentioned concerns of photocouplers. A galvanic isolation element that uses an electric field or a magnetic field as a signal transmission medium is also called a digital isolator. When an electric field is used as a signal transmission medium, for example, an insulating capacitance in which a metal plate is formed on both ends of an insulating layer is used. When a magnetic field is used as a signal transmission medium, for example, an insulating transformer in which a coil is formed on both ends of an insulating layer is used. It is easy to mount a plurality of insulating capacitances and insulating transformers on the same semiconductor substrate. Therefore, a communication device that transmits a plurality of signals can reduce costs by using a digital isolator as a galvanic isolation element compared to using a photocoupler. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Pat. No. 5,952,849 [Patent Document 2] U.S. Patent No. 7,302,247 [Patent Document 3] U.S. Pat. No. 9,660,848 [Patent Document 4] U.S. Patent No. 7,376,212 Summary of the Invention [Problem to be solved by the invention]

[0007] To suppress jitter in a multi-channel communication device. [Means for solving the problem]

[0008] A communication device according to an embodiment includes an oscillator, a first signal generating circuit, a second signal generating circuit, a first insulating element, a second insulating element, a first output circuit, and a second output circuit. The oscillator outputs a first carrier signal and a second carrier signal when at least one of a first input signal and a second input signal input from outside is at a first logic level. The first signal generating circuit includes a first delay circuit, a first logic circuit having a first input terminal to which the first input signal is input and a second input terminal to which the first input signal via the first delay circuit is input, a second logic circuit having a first input terminal connected to an output terminal of the first logic circuit and a second input terminal to which the first carrier signal is input, a third logic circuit having a first input terminal to which the first input signal is input and a second input terminal connected to an output terminal of the second logic circuit, and a first drive circuit that amplifies a voltage output by the third logic circuit. The second signal generating circuit includes a second delay circuit, a fourth logic circuit having a first input terminal to which the second input signal is input and a second input terminal to which the second input signal via the second delay circuit is input, a fifth logic circuit having a first input terminal connected to the output terminal of the fourth logic circuit and a second input terminal to which the second carrier signal is input, a sixth logic circuit having a first input terminal to which the second input signal is input and a second input terminal connected to the output terminal of the fifth logic circuit, and a second drive circuit that amplifies a voltage output by the sixth logic circuit. The first insulating element is connected to the output of the first drive circuit. The second insulating element is connected to the output of the second drive circuit. The first output circuit receives a signal based on the output signal of the first drive circuit via the first insulating element and outputs it to the outside. The second output circuit receives a signal based on the output signal of the second drive circuit via the second insulating element and outputs it to the outside. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a communication device according to a first embodiment. [Diagram 2] 2 is a circuit diagram showing an example of a circuit configuration of an RF generator included in the communication device according to the first embodiment. [Diagram 3] 2 is a circuit diagram showing an example of a circuit configuration of a signal generating circuit included in the communication device according to the first embodiment. [Figure 4]FIG. 2 is a circuit diagram showing an example of a circuit configuration of an insulating element included in the communication device according to the first embodiment. [Diagram 5] 4 is a timing chart showing an example of a modulation operation of an input signal. [Figure 6] 5 is a timing chart showing an example of an operation of the communication device according to the first embodiment. [Figure 7] 6 is a timing chart showing an example of an operation of a communication device according to a comparative example of the first embodiment. [Figure 8] FIG. 11 is a block diagram showing an example of a configuration of a communication device according to a first modified example of the first embodiment. [Figure 9] FIG. 11 is a block diagram showing an example of the configuration of a communication device according to a second modification of the first embodiment. [Figure 10] FIG. 13 is a block diagram showing an example of the configuration of a communication device according to a third modified example of the first embodiment. [Figure 11] FIG. 11 is a circuit diagram showing an example of a circuit configuration of a signal generating circuit included in a communication device according to a second embodiment. [Figure 12] FIG. 11 is a circuit diagram showing an example of a circuit configuration of an insulating element included in a communication device according to a second embodiment. [Figure 13] 10 is a timing chart showing an example of an operation of a communication device according to the second embodiment. [Figure 14] FIG. 11 is a circuit diagram showing an example of a circuit configuration of an insulating element included in a communication device according to a modified example of the second embodiment. [Figure 15] FIG. 11 is a circuit diagram showing an example of a circuit configuration of a signal generating circuit included in a communication device according to a modified example of the second embodiment. [Figure 16] FIG. 13 is a block diagram showing an example of the configuration of a communication device according to a third embodiment. [Figure 17] FIG. 13 is a circuit diagram showing an example of a circuit configuration of an RF generator included in a communication device according to a first modified example of the third embodiment. [Figure 18] FIG. 13 is a block diagram showing an example of the configuration of a communication device according to a first modified example of the third embodiment. [Figure 19] FIG. 13 is a circuit diagram showing an example of a circuit configuration of an RF generator included in a communication device according to a second modified example of the third embodiment. [Figure 20]FIG. 13 is a block diagram showing an example of the configuration of a communication device according to a second modification of the third embodiment. [Figure 21] FIG. 13 is a circuit diagram showing an example of a circuit configuration of an RF generator included in a communication device according to a second modified example of the third embodiment. [Figure 22] FIG. 13 is a circuit diagram showing an example of a circuit configuration of an RF generator included in a communication device according to a third modified example of the third embodiment. [Diagram 23] FIG. 13 is a circuit diagram showing an example of a circuit configuration of a signal generating circuit included in a communication device according to a fourth embodiment. [Figure 24] 13 is a timing chart showing an example of an operation of a communication device according to the fourth embodiment. [Diagram 25] 13 is a timing chart showing an example of an operation of a communication device according to the fourth embodiment. [Figure 26] 13 is a timing chart showing an example of an operation of a communication device according to the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiments will be described with reference to the drawings. Each embodiment illustrates an apparatus or method for embodying the technical idea of ​​the invention. The drawings are schematic or conceptual, and the dimensions and ratios of each drawing are not necessarily the same as those in reality. The technical idea of ​​the present invention is not specified by the shape, structure, arrangement, etc. of the components.

[0011] In the following description, components having substantially the same functions and configurations are given the same reference numerals. The numerals following the letters of the reference numerals are used to distinguish between elements that are referred to by the reference numerals containing the same letters and that have similar configurations. Similarly, the numerals following the letters of the reference numerals are used to distinguish between elements that are referred to by the reference numerals containing the same numbers and that have similar configurations.

[0012] [1] First embodiment The first embodiment relates to a communication device that transmits two signals using a galvanic isolation element, i.e., a multi-channel communication device. A communication device 1 according to the first embodiment will be described below by taking as an example a case where an isolation transformer is used as the galvanic isolation element.

[0013] [1-1] Configuration [1-1-1] Overall configuration of communication device 1 Fig. 1 shows an example of the configuration of a communication device 1 according to the first embodiment. As shown in Fig. 1, the communication device 1 according to the first embodiment includes, for example, input circuits 10A and 10B, an RF (Radio Frequency) generator 20, signal generating circuits 30A and 30B, isolation elements 40A and 40B, receiving circuits 50A and 50B, and output circuits 60A and 60B.

[0014] The input circuit 10 is used to input a signal from an external device to the communication device 1, and includes, for example, a buffer circuit. Input signals IN1 and IN2 are input to the input circuits 10A and 10B, respectively, from the external device. The input circuit 10A outputs an input signal Vin1 based on the input signal IN1 to the RF generator 20 and the signal generating circuit 30A. The input circuit 10B outputs an input signal Vin2 based on the input signal IN2 to the RF generator 20 and the signal generating circuit 30B.

[0015] The RF generator 20 is a signal generator such as a ring oscillator circuit. The RF generator 20 generates and outputs a carrier signal CS based on an input signal Vin1 input from an input circuit 10A and an input signal Vin2 input from an input circuit 10B. The carrier signal CS is input to signal generating circuits 30A and 30B.

[0016] The signal generation circuit 30 modulates the input signal Vin (modulated signal) input from the input circuit 10 using the carrier signal CS. Then, the signal generation circuit 30 outputs the modulated electrical signal (modulated signal) to the isolation element 40. Specifically, the signal generation circuit 30A modulates the input signal Vin1 and outputs it to the isolation element 40A. The signal generation circuit 30B modulates the input signal Vin2 and outputs it to the isolation element 40B.

[0017] The isolation element 40 is a galvanic isolation element used in an OOK (On-Off Keying) system, and includes, for example, an isolation transformer. In the first embodiment, the isolation element 40 transmits a signal by utilizing magnetic field coupling. The isolation element 40A transmits an electric signal input from the signal generating circuit 30A to the receiving circuit 50A. The isolation element 40B transmits an electric signal input from the signal generating circuit 30B to the receiving circuit 50B.

[0018] The receiving circuit 50 includes a demodulation circuit. The receiving circuit 50A detects and demodulates the electrical signal transmitted from the isolation element 40A, and outputs the signal to the output circuit 60A. The receiving circuit 50B detects and demodulates the electrical signal transmitted from the isolation element 40B, and outputs the signal to the output circuit 60B.

[0019] The output circuit 60 is used to output to the outside the signal transmitted through the isolation element 40 in the communication device 1, and includes, for example, a buffer circuit. The output circuit 60A outputs an output signal OUT1 to an external device based on the signal input from the receiving circuit 50A. The output circuit 60B outputs an output signal OUT2 to an external device based on the signal input from the receiving circuit 50B.

[0020] In the configuration of the communication device 1 described above, a set of the input circuit 10A, the signal generating circuit 30A, the isolation element 40A, the receiving circuit 50A, and the output circuit 60A corresponds to a first channel of the communication device 1. Similarly, a set of the input circuit 10B, the signal generating circuit 30B, the isolation element 40B, the receiving circuit 50B, and the output circuit 60B corresponds to a second channel of the communication device 1. In this way, the communication device 1 according to the first embodiment is a two-channel communication device capable of transmitting two types of signals.

[0021] In the communication device 1 according to the first embodiment, for example, the set of the input circuits 10A and 10B, the RF generator 20, and the signal generating circuits 30A and 30B are configured by semiconductor elements mounted on a first substrate. On the other hand, the set of the insulating elements 40A and 40B, the receiving circuits 50A and 50B, and the output circuits 60A and 60B are configured by semiconductor elements mounted on a second substrate different from the first substrate. The circuits provided on the first substrate and the circuits provided on the second substrate are electrically connected by using, for example, bonding wires.

[0022] Hereinafter, the set of the circuit mounted on the first substrate and the first substrate will be referred to as chip CP1, and the set of the circuit mounted on the second substrate and the second substrate will be referred to as chip CP2. For example, the circuit in chip CP1 is connected to ground GND1, and a power supply voltage VDD1 is applied to the circuit in chip CP1. The circuit in chip CP2 is connected to ground GND2, and a power supply voltage VDD2 is applied to the circuit in chip CP2. For example, one of the power supply voltages VDD1 and VDD2 corresponds to a high voltage system, and the other corresponds to a low voltage system.

[0023] [1-1-2] Circuit configuration of communication device 1 An example of the circuit configuration of each of the RF generator 20, the signal generating circuit 30, and the insulating element 40 in the communication device 1 according to the first embodiment will be described below in order.

[0024] (Circuit configuration of RF generator 20) 2 shows an example of a circuit configuration of the RF generator 20 included in the communication device 1 according to the first embodiment. As shown in FIG. 2, the RF generator 20 in the first embodiment includes, for example, an OR circuit 21, a NAND circuit 22, and inverters 23, 24, and 25.

[0025] The input signal Vin1 output from the input circuit 10A is input to a first input terminal of the OR circuit 21. The input signal Vin2 output from the input circuit 10B is input to a second input terminal of the OR circuit 21. The output terminal of the OR circuit 21 is connected to a first input terminal of the NAND circuit 22. The output terminal of the NAND circuit 22 is connected to an input terminal of the inverter 23. The output terminal of the inverter 23 is connected to an input terminal of the inverter 24. The output terminal of the inverter 24 is connected to an input terminal of the inverter 25 and a second input terminal of the NAND circuit 22. The signal output from the inverter 25 corresponds to the carrier signal CS.

[0026] Here, a method for generating the carrier signal CS by the RF generator 20 will be briefly described. In the following, the node corresponding to the output terminal of the NAND circuit 22 is called "N1." The node corresponding to the output terminal of the inverter 23 is called "N2." The node corresponding to the output terminal of the inverter 24 is called "N3."

[0027] When both the input signals Vin1 and Vin2 are at the "L" level, the OR circuit 21 outputs a voltage at the "L" level. The NAND circuit 22, to which the "L" level voltage is input at its first input terminal, outputs a voltage at the "H" level. As a result, the voltages at the nodes N1, N2, and N3 become "H", "L", and "H" levels, respectively, and the inverter 25 outputs a voltage at the "L" level. Also, when the voltage at the node N3 is at the "H" level, the input voltages at the first input terminal and the second input terminal of the NAND circuit 22 are different, so that the output of the NAND circuit 22 is maintained at the "H" level. As a result, when both the input signals Vin1 and Vin2 are at the "L" level, the carrier signal CS is maintained at the "L" level.

[0028] On the other hand, when at least one of the input signals Vin1 and Vin2 is at the "H" level, the OR circuit 21 outputs a "H" level voltage. Then, the NAND circuit 22, to which a "H" level voltage is input at its first input terminal, outputs a "L" level voltage when, for example, the voltage at its second input terminal is at the "H" level. As a result, the voltages at the nodes N1, N2, and N3 become "L", "H", and "L" levels, respectively, and the inverter 25 outputs a "H" level voltage.

[0029] Furthermore, when the voltage of node N3 becomes "L" level, a "H" level voltage is input to the first input terminal of NAND circuit 22, and a "L" level voltage is input to the second input terminal, so that the output voltage of NAND circuit 22 changes from "L" level to "H" level. As a result, the voltages of nodes N1, N2, and N3 become "H", "L", and "H" levels, respectively, and inverter 25 outputs a "L" level voltage. When at least one of input signals Vin1 and Vin2 is at "H" level, these operations are repeated, and the output of carrier signal CS oscillates.

[0030] As described above, the RF generator 20 in the first embodiment can generate the carrier signal CS by using the OR signal of the input signal Vin1 and the input signal Vin2. Note that the circuit configuration of the RF generator 20 described above is merely an example. The RF generator 20 may have another circuit configuration as long as it is capable of generating the carrier signal CS based on at least one of the input signals Vin1 and Vin2 becoming the "H" level.

[0031] (Circuit configuration of signal generating circuit 30) Fig. 3 shows an example of a circuit configuration of the signal generating circuit 30 included in the communication device 1 according to the first embodiment. As shown in Fig. 3, the signal generating circuit 30 in the first embodiment includes, for example, a signal generating unit 31 and a driving unit 32. The signal generating circuit 30 includes, for example, an AND circuit 311, a delay circuit 312, a NAND circuit 313, and an AND circuit 314. The driving unit 32 includes, for example, a driving circuit 321 .

[0032] An input signal Vin (modulation signal) is input to a first input terminal of the AND circuit 311. An input signal Vind corresponding to the input signal Vin delayed via a delay circuit 312 is input to a second input terminal of the AND circuit 311. The delay circuit 312 is, for example, an even number of inverters connected in series. Other circuits may be used as the delay circuit 312.

[0033] An output terminal of the AND circuit 311 is connected to a first input terminal of the NAND circuit 313. A carrier signal CS is input to a second input terminal of the NAND circuit 313. An input signal Vin is input to a first input terminal of the AND circuit 314. An output terminal of the NAND circuit 313 is connected to a second input terminal of the AND circuit 314. The AND circuit 314 outputs a modulated signal MS. The drive circuit 321 amplifies the modulated signal MS and outputs an output voltage Vout.

[0034] The signal generating circuit 30 in the first embodiment described above can modulate the input signal Vin based on the carrier signal CS. For example, the output voltage Vout of the signal generating circuit 30 becomes a voltage of the "L" level when the input signal Vin is at the "L" level, and becomes a voltage based on the carrier signal CS generated by the RF generator 20 when the input signal Vin is at the "H" level. Note that the circuit configuration of the signal generating circuit 30 described above is merely an example. The signal generating circuit 30 may have another circuit configuration as long as it is capable of modulating the input signal Vin based on the carrier signal CS.

[0035] (Circuit configuration of the insulating element 40) 4 shows an example of a circuit configuration of the insulating element 40 included in the communication device 1 according to the first embodiment. As shown in FIG. 4, the insulating element 40 in the first embodiment includes coils 41 and 42, for example.

[0036] The coil 41 and the coil 42 face each other via an insulator layer ISO. An oxide film or polyimide may be used as the insulator layer ISO. An output voltage Vout is applied to one end of the coil 41 by a signal generating circuit 30 in the chip CP1. The other end of the coil 41 is grounded, for example, at the chip CP1. One end of the coil 42 is connected to a receiving circuit 50. The other end of the coil 42 is grounded, for example, at the chip CP2.

[0037] In the isolation element 40 in the first embodiment described above, magnetic field coupling is formed between the coil 41 and the coil 42. As a result, the output voltage Vout applied to the coil 41 is transmitted to the coil 42 by magnetic field coupling, and the transmitted output voltage Vout is applied to the receiving circuit 50. Note that the circuit configuration of the isolation element 40 described above is merely an example. The isolation element 40 may have another circuit configuration as long as it is possible to transmit the output voltage Vout using magnetic field coupling.

[0038] [1-2] Operation [1-2-1] Input signal modulation A communication method using an insulating transformer or insulating capacitance can improve efficiency by modulating an input signal to a high frequency band. Known modulation methods for digital isolators include an edge encoding method and an OOK (On Off Keying) method. From the viewpoint of current consumption during low-speed communication, the edge encoding method is advantageous, while from the viewpoint of current consumption and transmission delay time during high-speed communication, the OOK method is advantageous. The communication device 1 according to the first embodiment uses the OOK method.

[0039] FIG. 5 shows an example of a basic modulation operation of an input signal. As shown in FIG. 5, the input signal is a voltage of "L" level or "H" level, and contains one bit of information. When the input signal becomes "H" level, the RF generator 20 is turned on, and when the input signal becomes "L" level, the RF generator 20 is turned off. Since the RF generator 20 operates based on the input signal becoming "H" level, the carrier signal oscillates during the period when the input signal is at "H" level. The modulated signal is a signal generated based on the carrier signal during the period when the input signal is at "H" level. Therefore, the modulated signal oscillates in the same manner as, for example, the carrier signal during the period when the input signal is at "H" level.

[0040] [1-2-2] Operation of communication device 1 6 shows an example of a timing chart of the operation of the communication device 1 according to the first embodiment. "MSA" indicates a modulated signal corresponding to the input signal Vin1. "MSB" indicates a modulated signal corresponding to the input signal Vin2. (1) to (4) indicate the phase of the carrier signal CS when the input signal Vin transitions from the "L" level to the "H" level.

[0041] 6(1), when the input signal Vin1 becomes "H" level while the input signal Vin2 is at "L" level, the RF generator 20 turns on and the carrier signal CS oscillates. At this time, in the signal generating circuit 30A, the voltage of the first input terminal of the AND circuit 314 becomes "H" level based on the input signal Vin1, and the voltage of the second input terminal of the AND circuit 314 becomes a level based on the carrier signal CS, the AND circuit 311, the delay circuit 312, and the NAND circuit 313.

[0042] Specifically, the AND circuit 311 outputs a "L" level signal because a "H" level voltage is applied to the first input terminal and a "L" level voltage is applied to the second input terminal until the delay time td by the delay circuit 312 has elapsed. This causes the voltage of the first input terminal of the NAND circuit 313 to become "L" level, so that the NAND circuit 313 inputs a "H" level voltage to the second input terminal of the AND circuit 314 regardless of the state of the carrier signal CS. As a result, the output of the AND circuit 314 is maintained at the "H" level.

[0043] On the other hand, after the delay time td has elapsed, a voltage of the "H" level is applied to each of the first input terminal and the second input terminal of the AND circuit 311. As a result, the AND circuit 311 outputs a signal of the "H" level, and the voltage of the first input terminal of the NAND circuit 313 becomes the "H" level. Since the carrier signal CS is oscillating, the NAND circuit 313 inputs an inverted signal of the carrier signal CS to the second input terminal of the AND circuit 314. As a result, the output of the AND circuit 314 oscillates based on the carrier signal CS.

[0044] As described above, the output of the AND circuit 314, i.e., the modulated signal MSA, becomes "H" level when, for example, the input signal Vin1 becomes "H" level, and then maintains the "H" level until the delay time td has elapsed. Then, when the delay time td has elapsed, the modulated signal MSA oscillates based on the carrier signal CS. Then, when the input signal Vin1 becomes "L" level, the RF generator 20 is turned off, and the oscillation of the carrier signal CS and the oscillation of the modulated signal MSA stop.

[0045] As shown in Fig. 6(2), when the input signal Vin2 goes to "H" level while the input signal Vin1 is at "L" level, the RF generator 20 turns on and the carrier signal CS oscillates. The operation of the signal generating circuit 30B at this time is the same as that of the signal generating circuit 30A in Fig. 6(1). In each of Figs. 6(1) and (2), the carrier signal CS oscillates based on the input signal Vin going to "H" level. That is, since the input signal Vin and the carrier signal CS are synchronized, the phase of the carrier signal CS becomes 0° when the input signal Vin transitions from "L" level to "H" level.

[0046] As shown in Fig. 6(3), when the input signal Vin1 becomes "H" level while the input signal Vin2 is at "H" level, the input signal Vin1 is modulated based on the carrier signal CS that is already oscillating. In other words, the carrier signal CS of the RF generator 20 and the input signal Vin1 of the input circuit 10A are in an asynchronous relationship. For this reason, a shift may occur between the timing at which the input signal Vin1 transitions from "L" level to "H" level and the phase of the carrier signal CS. Fig. 6(3) shows a case where the phase of the carrier signal CS is 90° when the input signal Vin1 is input.

[0047] Even in such a case, in the signal generating circuit 30A, the AND circuit 314 immediately outputs a voltage of the "H" level when the input signal Vin1 becomes the "H" level. That is, the modulated signal MSA becomes the "H" level when the input signal Vin1 becomes the "H" level. Then, after the delay time td has elapsed, the modulated signal MSA oscillates based on the carrier signal CS.

[0048] Then, after both the input signals Vin1 and Vin2 become "H" level, only the input signal Vin2 changes to "L" level. In this case, the oscillation of the modulated signal MSB stops based on the transition of the input signal Vin2 from "H" level to "L" level. Meanwhile, since the input signal Vin1 maintains the "H" level, the RF generator 20 maintains the on state. In other words, while any of the input signals Vin is at the "H" level, the RF generator 20 maintains the carrier signal CS in an oscillating state.

[0049] As shown in Fig. 6(4), when the input signal Vin2 goes to "H" level while the input signal Vin1 is at "H" level, the input signal Vin2 is modulated based on the carrier signal CS that is already oscillating. In other words, the carrier signal CS of the RF generator 20 and the input signal Vin2 of the input circuit 10B are in an asynchronous relationship. Fig. 6(4) shows a case where the phase of the carrier signal CS is 90° when the input signal Vin2 is input, similar to Fig. 6(3).

[0050] Even in such a case, in the signal generating circuit 30B, the AND circuit 314 immediately outputs a voltage of the "H" level when the input signal Vin2 becomes the "H" level. That is, the modulated signal MSB becomes the "H" level when the input signal Vin2 becomes the "H" level. Then, after the delay time td has elapsed, the modulated signal MSB oscillates based on the carrier signal CS.

[0051] Then, after the input signals Vin1 and Vin2 each become "H" level again, only the input signal Vin1 changes to "L" level. In this case, the oscillation of the modulated signal MSA stops based on the input signal Vin1's transition from "H" level to "L" level. Meanwhile, since the input signal Vin2 maintains the "H" level, the RF generator 20 maintains the ON state. Then, when the input signal Vin2 becomes "L" level, the oscillation of the modulated signal MSB stops. Furthermore, when the input signals Vin1 and Vin2 each become "L" level, the RF generator 20 is turned off, and the carrier signal CS becomes "L" level.

[0052] As described above, in the communication device 1 according to the first embodiment, when the input signal Vin becomes “H” level, the corresponding modulated signal MS immediately becomes “H” level. Then, after the delay time td has elapsed, that is, after a pulse for the delay time td has been applied, the modulated signal MS becomes a pulse based on the carrier signal CS.

[0053] [1-3] Effects of the first embodiment According to the communication device 1 according to the first embodiment described above, it is possible to suppress jitter in a communication device using one RF generator. The effects of the communication device 1 according to the first embodiment will be described in detail below.

[0054] A known modulation method for a communication device using the OOK method is to use an AND signal of an RF carrier (e.g., carrier signal CS) and an input signal. When the communication device is multi-channel, it is preferable that an RF generator that generates an RF carrier is provided for each channel. However, providing multiple RF generators can lead to increased power consumption and an increase in chip area. Therefore, in order to reduce power consumption in a multi-channel communication device, a method has been devised in which one RF generator is shared by multiple channels.

[0055] Here, as a comparative example of the first embodiment, a case will be described in which a communication device having multiple inputs uses one RF generator 20 and uses a signal obtained by ANDing an input signal Vin and a carrier signal CS as a modulated signal MS. Briefly, a communication device according to the comparative example of the first embodiment has a configuration in which, for example, the AND circuit 311, the delay circuit 312, and the NAND circuit 313 are omitted from the signal generating circuit 30 described in FIG. 3, and the RF generator 20 is directly connected to the second input terminal of the AND circuit 314.

[0056] Fig. 7 shows an example of a timing chart of the operation of a communication device according to a comparative example of the first embodiment, illustrating a case where the input signals Vin1 and Vin2 become "H" level at the same timing as in Fig. 6. When the RF generator 20 operates using the AND signal of the input signals Vin1 and Vin2, modulated signals MSA and MSB as shown in Fig. 7 are obtained.

[0057] As shown in Fig. 7, when either of the input signals Vin1 and Vin2 changes from a state in which both are at "L" level to a state in which the input signals Vin1 and Vin2 change to a "H" level, for example, the modulated signal MSA or MSB oscillates in the same manner as the carrier signal CS. Also, as shown in Fig. 7(1) and (2), when the input signal Vin and the carrier signal CS are synchronized, the phase of the carrier signal CS at the timing when the input signal Vin changes from a "L" level to a "H" level is 0°.

[0058] On the other hand, as shown in Figures 7(3) and (4), when one input signal Vin transitions from "L" level to "H" level while the other input signal Vin is at "H" level, the input signal Vin and the carrier signal CS become asynchronous. In this case, a shift may occur between the timing at which the input signal Vin transitions from "L" level to "H" level and the phase of the carrier signal CS. Figure 7(3) shows a case where the phase of the carrier signal CS is 90° when the input signal Vin1 is input, and Figure 7(4) shows a case where the phase of the carrier signal CS is 90° when the input signal Vin2 is input.

[0059] In the communication device 1 according to the comparative example of the first embodiment, when the transition timing of the input signal Vin is synchronized with the carrier signal CS, that is, when the input signal Vin is input while the RF generator 20 is in the off state, the rising waveform of the carrier signal CS and the rising waveform of the modulated signal MS can be made substantially the same. In this case, the communication device 1 can make the waveforms of the output signals OUT1 and OUT2 substantially the same.

[0060] On the other hand, in the communication device 1 according to the comparative example of the first embodiment, when the input signal Vin is input while the RF generator 20 is in the on state, the transition timing of the input signal Vin cannot be synchronized with the carrier signal CS, so that a deviation may occur between the rising edge of the input signal Vin and the phase of the carrier signal CS. When the rising edge of the input signal Vin is out of phase with the carrier signal CS, the voltage value of the carrier signal CS input to the AND circuit 314 varies, and the shape of the waveform of the rising edge of the modulated signal MS becomes random. Such a variation in the shape of the waveform of the rising edge of the modulated signal MS is reflected in the variation in the waveforms of the output signals OUT1 and OUT2. The change in the waveform of the rising edge of the modulated signal MS based on the operation timing of the input signal Vin and the carrier signal CS causes jitter and a decrease in the operational stability of the receiving circuit 50.

[0061] In contrast, the communication device 1 according to the first embodiment uses a signal generating circuit 30 having a delay circuit 312 to modulate the input signal Vin. Briefly, the communication device 1 according to the first embodiment includes an AND circuit 311 having a first input terminal to which the input signal Vin is input and a second input terminal to which the input signal Vin via the delay circuit 312 is input, and a NAND circuit 313 having a first input terminal connected to the output of the AND circuit 311, a second input terminal connected to the output of the RF generator 20, and an output terminal connected to the second input terminal of the AND circuit 314.

[0062] In the signal generating circuit 30 in the first embodiment, when the input signal Vin becomes "H" level, the AND circuit 314 sets the modulated signal MS to "H" level regardless of the state of the carrier signal CS. In addition, the RF generator 20 is turned on in response to the input of the input signal Vin. Meanwhile, the AND circuit 311, the delay circuit 312, and the NAND circuit 313 delay the input of the signal oscillated based on the carrier signal CS to the AND circuit 314. Therefore, the modulated signal MS is maintained at "H" level until the delay time td by the delay circuit 312 has elapsed since the input signal Vin became "H" level. Then, when the delay time td has elapsed, the output of the AND circuit 311 becomes "H" level, and the NAND circuit 313 outputs a signal oscillated based on the carrier signal CS. As a result, when the delay time td has elapsed since the input signal Vin became "H" level, the input signal Vin is modulated based on the carrier signal CS.

[0063] As described above, the communication device 1 according to the first embodiment sets the modulated signal MS to the “H” level based on the input signal Vin, regardless of whether the RF generator 20 is on or not. That is, unlike the comparative example, the communication device 1 according to the first embodiment has the same rising waveform of the modulated signal MS when the input signal Vin and the carrier signal CS are synchronous and when they are asynchronous.

[0064] As a result, in the communication device 1 according to the first embodiment, the variation in the rising edge of the modulated signal MS is suppressed, and therefore the variation in the waveforms of the output signals OUT1 and OUT2 is suppressed. Furthermore, the communication device 1 according to the first embodiment can input a signal oscillated based on the carrier signal CS to the AND circuit 314 after the delay time td by the delay circuit 312 has elapsed, and therefore can perform communication in the OOK method as in the comparative example.

[0065] As a result, the communication device 1 according to the first embodiment can suppress jitter in the output signal OUT and stabilize the operation of the receiving circuit 50. Therefore, the communication device 1 according to the first embodiment can transmit a high-quality signal using one RF carrier generation circuit in a digital isolator that transmits signals using the OOK method in a multi-channel configuration. Furthermore, the communication device 1 according to the first embodiment can operate multiple channels with only one RF generator 20, thereby suppressing power consumption and reducing the chip area.

[0066] As described above, the communication device 1 according to the first embodiment uses the carrier signals CS associated with each isolated device in a synchronized manner. Therefore, in the communication device 1 according to the first embodiment, the phase of each isolated device may be adjusted. The communication device 1 according to the first embodiment can suppress EMI (Electro Magnetic Interference) by adjusting the phase of each isolated device.

[0067] [1-4] Modification of the first embodiment The communication device 1 according to the first embodiment described above can be modified in various ways. Below, the first, second, and third modifications of the first embodiment will be described with respect to differences from the first embodiment.

[0068] [1-4-1] First modified example of the first embodiment Fig. 8 shows an example of the configuration of a communication device 1 according to a first modified example of the first embodiment. As shown in Fig. 8, the communication device 1 according to the first modified example of the first embodiment is different from the first embodiment in the combination of circuits included in the chip CP1 and circuits included in the chip CP2.

[0069] Specifically, in the communication device 1 according to the first modification of the first embodiment, a set of the input circuits 10A and 10B, the RF generator 20, the signal generating circuits 30A and 30B, and the isolation elements 40A and 40B are implemented on a chip CP1, while a set of the receiving circuits 50A and 50B and the output circuits 60A and 60B are implemented on a chip CP2.

[0070] In this way, in the communication device 1, the isolation elements 40A and 40B may be mounted on the chip CP1 instead of the chip CP2. The communication device 1 can obtain the same effects as the first embodiment regardless of whether the isolation elements 40A and 40B are mounted on the chip CP1 or CP2. In this way, the system of the communication device 1 in which one isolation element 40 is provided for each channel and one isolation element 40 is mounted on either the chip CP1 or CP2 is also called a single isolation system.

[0071] [1-4-2] Second Modification of the First Embodiment Fig. 9 shows an example of the configuration of a communication device 1 according to a second modified example of the first embodiment. As shown in Fig. 9, the isolation elements 40A and 40B may be mounted on both the chips CP1 and CP2.

[0072] Specifically, in the communication device 1 according to the second modification of the first embodiment, the set of the input circuits 10A and 10B, the RF generator 20, the signal generating circuits 30A and 30B, and the isolation elements 40A-1 and 40B-1 are implemented on a chip CP1, while the set of the isolation elements 40A-2 and 40B-2, the receiving circuits 50A and 50B, and the output circuits 60A and 60B are implemented on a chip CP2.

[0073] Then, the isolation elements 40A-1 and 40B-2 are connected in series between the signal generating circuit 30A and the receiving circuit 50A. The isolation elements 40B-1 and 40B-2 are connected in series between the signal generating circuit 30B and the receiving circuit 50B. In other words, the isolation element 40 of the chip CP1 and the isolation element 40 of the chip CP2 are connected in series between the signal generating circuit 30 in the chip CP1 and the receiving circuit 50 in the chip CP2. In this way, the system of the communication device 1 in which two isolation elements 40 are provided for each channel and the isolation elements 40 are mounted on both the chips CP1 and CP2 is also called a double isolation system.

[0074] [1-4-3] Third Modification of the First Embodiment Fig. 10 shows an example of the configuration of a communication device 1 according to a third modified example of the first embodiment. As shown in Fig. 10, the communication device 1 according to the third modified example of the first embodiment has a configuration in which input circuits 10C and 10D, signal generating circuits 30C and 30D, insulating elements 40C and 40D, receiving circuits 50C and 50D, and output circuits 60C and 60D are added to the communication device 1 according to the first embodiment.

[0075] Input signals IN3 and IN4 are input to the input circuits 10C and 10D, respectively, from an external device. The input circuits 10C and 10D then output input signals Vin3 and Vin4, respectively. The input signal Vin3 is input to the RF generator 20 and the signal generating circuit 30C. The input signal Vin4 is input to the RF generator 20 and the signal generating circuit 30D.

[0076] In the RF generator 20 in the third modified example of the first embodiment, although not shown in the figure, input signals Vin1, Vin2, Vin3, and Vin4 are input to a first input terminal, a second input terminal, a third input terminal, and a fourth input terminal of an OR circuit 21, respectively. Then, the RF generator 20 in the third modified example of the first embodiment generates and outputs a carrier signal CS based on the input signals Vin1, Vin2, Vin3, and Vin4. Other configurations and operations of the RF generator 20 in the third modified example of the first embodiment are similar to those of the first embodiment.

[0077] The signal generation circuit 30C modulates the input signal Vin3 and outputs it to the isolation element 40C. The signal generation circuit 30D modulates the input signal Vin4 and outputs it to the isolation element 40D. The isolation element 40C transmits the electrical signal input from the signal generation circuit 30C to the receiving circuit 50C. The isolation element 40D transmits the electrical signal input from the signal generation circuit 30D to the receiving circuit 50D.

[0078] The receiving circuit 50C demodulates the electrical signal transmitted from the isolation element 40C and outputs it to the output circuit 60C. The receiving circuit 50D demodulates the electrical signal transmitted from the isolation element 40D and outputs it to the output circuit 60D. The output circuit 60C outputs an output signal OUT3 to an external device based on the signal input from the receiving circuit 50C. The output circuit 60D outputs an output signal OUT4 to an external device based on the signal input from the receiving circuit 50D. The other configurations of the communication device 1 according to the third modification of the first embodiment are similar to those of the first embodiment.

[0079] As described above, the communication device 1 according to the third modification of the first embodiment includes four sets (channels) of the input circuit 10, the signal generating circuit 30, the isolation element 40, the receiving circuit 50, and the output circuit 60. One RF generator 20 is shared by the signal generating circuits 30 included in each channel. In this manner, the RF generator 20 in the first embodiment may be shared by four channels, or may be shared by N channels (N is an integer equal to or greater than 3). The communication device 1 can obtain the same effect as the first embodiment by operating the RF generator 20 based on the OR signal of N input signals.

[0080] [2] Second embodiment The communication device 2 according to the second embodiment has a configuration in which a signal generating circuit 30 generates and outputs a differential signal. The following describes the communication device 2 according to the second embodiment and the differences from the first embodiment.

[0081] [2-1] Configuration Fig. 11 shows an example of a circuit configuration of the signal generating circuit 30 included in the communication device 2 according to the second embodiment. As shown in Fig. 11, the signal generating circuit 30 in the second embodiment has a configuration in which an inverter 315 and an AND circuit 316 are added to the signal generating unit 31, and the driving circuit 321 of the driving unit 32 is replaced with transistors 322, 323, 324, and 325, and a current source 326, compared to the signal generating circuit 30 in the first embodiment.

[0082] An input terminal of the inverter 315 is connected to an output terminal of the NAND circuit 313. An input signal Vin is input to a first input terminal of the AND circuit 316. An output terminal of the inverter 315 is connected to a second input terminal of the AND circuit 316. The AND circuits 314 and 316 output modulated signals MS1 and MS2, respectively. The modulated signals MS1 and MS2 are in a complementary relationship and correspond to, for example, positive and negative phase signals, respectively.

[0083] The transistors 322 and 323 are, for example, P-type MOS transistors. A power supply voltage VDD1 is applied to the sources of the transistors 322 and 323. The gate of the transistor 322 is connected to the output terminal of the AND circuit 316. The gate of the transistor 323 is connected to the output terminal of the AND circuit 314.

[0084] The transistors 324 and 325 are, for example, N-type MOS transistors. The drain of the transistor 324 is connected to the drain of the transistor 322. The drain of the transistor 325 is connected to the drain of the transistor 323. The gate of the transistor 324 is connected to the output terminal of the AND circuit 316. The gate of the transistor 325 is connected to the output terminal of the AND circuit 314.

[0085] The input terminal of the current source 326 is connected to the sources of the transistors 324 and 325. The output terminal of the current source 326 is connected to the ground GND1. In this way, the current source 326 maintains the sum of the currents through the transistors 322 and 324 and the currents through the transistors 323 and 325 constant.

[0086] In the signal generating circuit 30 in the second embodiment described above, the output current Iout1 is output from the node between the transistors 323 and 325, and the output current Iout2 is output from the node between the transistors 322 and 324. The output currents Iout1 and Iout2 correspond to a differential signal, and the differential signal is input to the isolation element 40.

[0087] In other words, the signal generating unit 31 of the signal generating circuit 30 outputs a differential output voltage based on the input signal Vin from the input circuit 10 and the carrier signal CS from the RF generator 20. Then, the driving unit 32 of the signal generating circuit 30 transmits the differential output voltage to the isolation element 40. In the second embodiment, as a typical example for driving an isolation transformer, a case is illustrated in which the driving unit 32 of the signal generating circuit 30 is an H-bridge type with a current limiter.

[0088] Fig. 12 shows an example of a circuit configuration of an insulating element 40 included in a communication device 2 according to the second embodiment. As shown in Fig. 12, the insulating element 40 in the second embodiment is different from the first embodiment in connection of the coils 41 and 42, etc.

[0089] Specifically, an output current Iout1 is supplied to one end of the coil 41 by the signal generating circuit 30 in the chip CP1. An output current Iout2 is supplied to the other end of the coil 41 by the signal generating circuit 30 in the chip CP1. One and the other ends of the coil 42 are connected to the receiving circuit 50.

[0090] In the insulating element 40 in the second embodiment described above, similarly to the first embodiment, magnetic field coupling is formed between the coil 41 and the coil 42. Specifically, such an insulating transformer generates a magnetic field by inputting a current. The direction of this magnetic field changes by switching between a path through which a current flows when the transistors 323 and 324 in the signal generating circuit 30 are turned on and a path through which a current flows when the transistors 322 and 325 in the signal generating circuit 30 are turned on.

[0091] As a result, a voltage based on the output currents Iout1 and Iout2 applied to the coil 41 is transmitted to the coil 42 by magnetic field coupling, and the transmitted voltage is applied to the receiving circuit 50. In other words, the insulating element 40 can transmit a modulated signal based on the principle of electromagnetic induction between the coils 41 and 42 and apply a voltage to the receiving circuit 50. Then, the receiving circuit 50 demodulates a voltage based on the voltages at one end and the other end of the coil 42, and outputs it to the output circuit 60. The other configurations of the communication device 2 according to the second embodiment are similar to those of the first embodiment.

[0092] [2-2] Operation Fig. 13 shows an example of a timing chart of the operation of the communication device 2 according to the second embodiment, illustrating a case where the input signals Vin1 and Vin2 become "H" level at the same timing as in Fig. 6. "MS1A" and "MS2A" respectively indicate the positive-phase modulated signal MS and the negative-phase modulated signal MS with respect to the input signal Vin1. "MS1B" and "MS2B" respectively indicate the positive-phase modulated signal MS and the negative-phase modulated signal MS with respect to the input signal Vin2.

[0093] 13, in the second embodiment, the positive-phase modulated signal MS1A for the input signal Vin1 and the positive-phase modulated signal MS1B for the input signal Vin2 change in the same manner as the modulated signals MSA and MSB described in the first embodiment. On the other hand, the negative-phase modulated signal MS2A for the input signal Vin1 and the negative-phase modulated signal MS2B for the input signal Vin2 become inverted signals of the modulated signals MS1A and MS1B, respectively.

[0094] In short, the AND circuit 314 corresponding to the positive phase operates in the same manner as the AND circuit 314 of the first embodiment. The AND circuit 316 corresponding to the negative phase receives the input signal Vin at its first input terminal, and receives a signal obtained by inverting the output of the NAND circuit 313 by the inverter 315 at its second input terminal. That is, the same signal is input to the first input terminal of the AND circuit 314 and the first input terminal of the AND circuit 316. On the other hand, an inverted signal is input to the second input terminal of the AND circuit 314 and the second input terminal of the AND circuit 316. As a result, the AND circuit 316 outputs the inverted signal of the AND circuit 314.

[0095] Furthermore, in the communication device 2 according to the second embodiment, when the input signal Vin is at the "L" level, each of the AND circuits 314 and 316 outputs an "L" level signal. Then, in the drive unit 32 of the signal generation circuit 30, the current path between the power supply and the ground is cut off. As a result, the drive unit 32 of the signal generation circuit 30 stops applying a voltage to the insulating element 40. Other operations of the communication device 2 according to the second embodiment are similar to those of the first embodiment.

[0096] [2-3] Effects of the second embodiment When the isolation element 40 is driven by an H-bridge circuit as in the communication device 2 according to the second embodiment, a differential signal is necessary. However, when the input signal Vin is at the “L” level, applying a current and a voltage to the isolation element 40 is not preferable because it increases power consumption and causes noise.

[0097] In contrast, the communication device 2 according to the second embodiment sets both the positive-phase voltage of the modulated signal (i.e., the modulated signal MS1) and the negative-phase voltage of the modulated signal (i.e., the modulated signal MS2) to the "L" level when the input signal Vin is at the "L" level. This allows the communication device 2 according to the second embodiment to suppress power consumption and noise when the isolation element 40 is driven by an H-bridge circuit.

[0098] Furthermore, the communication device 2 according to the second embodiment can make the rising waveform of the positive-phase modulated signal MS1 constant, regardless of whether the input signal Vin and the carrier signal CS are synchronized, as in the first embodiment. Moreover, the modulated signal MS2 for driving the H-bridge circuit is an inverted signal of the modulated signal MS1, and is therefore at the "L" level when the input signal Vin becomes the "H" level. Therefore, the occurrence of noise can also be suppressed in the modulated signal MS2. As a result, the communication device 2 according to the second embodiment can suppress the jitter of the output signal by the signal generating circuit 30, and can improve the stability of the operation.

[0099] [2-4] Modification of the second embodiment The communication device 2 according to the second embodiment can be modified in various ways. For example, the signal generating circuit 30 may have a circuit configuration that sets the modulated signals MS1 and MS2 to the "H" level when the input signal Vin is at the "L" level. In this case, for example, each of the AND circuits 314 and 316 is replaced with a NAND circuit. Even in such a case, the communication device 2 can obtain the same effects as those of the second embodiment.

[0100] Moreover, the communication device 2 according to the second embodiment can be combined with the third modified example of the first embodiment. Fig. 14 shows an example of a circuit configuration of an insulating element 40 included in the communication device 2 according to the modified example of the second embodiment. As shown in Fig. 14, the insulating element 40 in the modified example of the second embodiment has a configuration in which the coils 41 and 42 in the second embodiment are replaced with capacitors 43 and 44.

[0101] Specifically, an output current Iout1 is applied to one electrode of the capacitor 43 by the signal generating circuit 30 in the chip CP1. The other electrode of the capacitor 43 is connected to one end of the receiving circuit 50. An output current Iout2 is supplied to one electrode of the capacitor 44 by the signal generating circuit 30 in the chip CP1. The other electrode of the capacitor 44 is connected to the other end of the receiving circuit 50. In this case, the insulator provided between the one electrode and the other electrode of the capacitor 43 and the insulator provided between the one electrode and the other electrode of the capacitor 44 each correspond to the insulator layer ISO.

[0102] In the insulating element 40 in the modified example of the second embodiment, electric field coupling is formed between one electrode and the other electrode of the capacitor 43 and between one electrode and the other electrode of the capacitor 44. As a result, a voltage based on the output current Iout1 supplied to one electrode of the capacitor 43 is transmitted to the other electrode of the capacitor 43 by electric field coupling, and the transmitted output voltage Vout is applied to one end of the receiving circuit 50. Similarly, a voltage based on the output current Iout2 supplied to one electrode of the capacitor 44 is transmitted to the other electrode of the capacitor 44 by electric field coupling, and the transmitted output voltage Vout is applied to the other end of the receiving circuit 50.

[0103] In this way, the isolation element 40 used in the communication device 2 according to the second embodiment may be an isolation capacitor instead of an isolation transformer. Even when an isolation capacitor is used as the isolation element 40, the communication device 2 can obtain the same effects as those of the second embodiment. Note that the circuit configuration of the isolation element 40 described above is merely an example. The isolation element 40 may have another circuit configuration as long as it is possible to transmit the output currents Iout1 and Iout2 using electric field coupling.

[0104] Fig. 15 shows an example of a circuit configuration of the signal generating circuit 30 included in the communication device 2 according to the modification of the second embodiment. As shown in Fig. 15, the signal generating circuit 30 according to the modification of the second embodiment has a configuration in which the current source 326 is omitted from the signal generating circuit 30 according to the second embodiment, since the insulating element 40 uses capacitive coupling. Specifically, the sources of the transistors 324 and 325 are each connected to the ground GND1.

[0105] In this way, when an insulating capacitance is used as an insulating device, for example, an inverter circuit is used in the drive section 32 of the signal generating circuit 30. Then, the insulating capacitance (capacitors 43 and 44) ​​in the insulating element 40 is driven by the voltage from the inverter circuit. The other configurations and operations of the communication device 2 according to the modified example of the second embodiment are similar to those of the second embodiment. As a result, the communication device 2 according to the modified example of the second embodiment can obtain the same effects as those of the second embodiment.

[0106] [3] Third embodiment The communication device 3 according to the third embodiment has a configuration in which an RF generator 20 generates and outputs a plurality of types of carrier signals CS. The following describes the communication device 3 according to the third embodiment in terms of differences from the first and second embodiments.

[0107] [3-1] Configuration Fig. 16 shows an example of the configuration of a communication device 3 according to the third embodiment. As shown in Fig. 16, the communication device 3 according to the third embodiment has four channels, similar to the third modification of the first embodiment. Moreover, the communication device 3 according to the third embodiment differs from the third modification of the first embodiment in that the RF generator 20 outputs four types of carrier signals CS.

[0108] Specifically, the RF generator 20 in the third embodiment generates and outputs carrier signals CS1, CS2, CS3, and CS4 based on an input signal Vin1 input from an input circuit 10A, an input signal Vin2 input from an input circuit 10B, an input signal Vin3 input from an input circuit 10C, and an input signal Vin4 input from an input circuit 10D. The carrier signals CS1, CS2, CS3, and CS4 are input to signal generating circuits 30A, 30B, 30C, and 30D, respectively.

[0109] Fig. 17 shows an example of a circuit configuration of an RF generator 20 included in a communication device 3 according to the third embodiment. As shown in Fig. 17, for example, the signal output from node N1 corresponds to carrier signal CS4. The signal output from node N2 corresponds to carrier signal CS2. The signal output from node N3 corresponds to carrier signal CS1. The signal output from inverter 25 corresponds to carrier signal CS3.

[0110] In the RF generator 20 described above, the phases of the carrier signals CS1 to CS4 are different from one another. In the third embodiment, the allocation of the carrier signal CS to the nodes N1, N2, and N3 and the output end of the inverter can be changed arbitrarily. The other configurations of the communication device 3 according to the third embodiment are similar to those of the third modified example of the first embodiment.

[0111] [3-2] Effects of the third embodiment In a communication device capable of inputting an N-bit signal, N signal generating circuits 30 operate in synchronization, and a synchronized carrier signal flows through N isolation elements 40. As a result, the EMI radiated from the signal generating circuits 30 and isolation elements 40 also increases by N times. In the first and second embodiments, the signal (pulse) output by each signal generating circuit 30 is completely synchronized with the carrier signal CS. As a method for improving EMI, it is considered to change the driving phase between the multiple isolation elements 40.

[0112] Therefore, the communication device 3 according to the third embodiment includes an RF generator 20 capable of generating a plurality of types of carrier signals CS. Briefly, in the RF generator 20 according to the third embodiment, four types of carrier signals CS1 to CS4 are extracted from four different nodes among a plurality of nodes connected to any of the inverters 23 to 25 connected in series. Then, the signal generating circuits 30A, 30B, 30C, and 30D modulate the input signal Vin using the carrier signals CS1, CS2, CS3, and CS4, respectively, to drive the corresponding isolation elements 40.

[0113] Here, the carrier signal flowing through isolation element x (corresponding to isolation element 40, where x is an integer from 1 to 4) is defined as Ax·sin(ω0·t+φx). In this case, the EMI signals radiated from the four isolation elements are expressed by the following equation (1). Note that ω0 corresponds to the oscillation angular frequency of the RF generator 20. Ax corresponds to the amplitude of one side of the carrier signal flowing through isolation element x.

[0114]

number

[0115] In equation (1), when φ1 = 0 [rad], φ2 = 2π / 3 [rad], φ3 = π [rad], and φ4 = 4π / 3 [rad]. The composite amplitude A in equation (1) is expressed as in equation (2A) below, and the phase φ in equation (1) is expressed as in equation (2B) below.

[0116]

number

[0117]

number

[0118] When φ1=0 [rad], φ2=2π / 3 [rad], φ3=π [rad], and φ4=4π / 3 [rad], the maximum composite amplitude A=2 is obtained when A1=0 and A2=A3=A4=1. On the other hand, when φ1=φ2=φ3=φ4=0 [rad], the maximum composite amplitude A=4 is obtained when A1=A2=A3=A4=1. Comparing these cases, the communication device 3 according to the third embodiment can halve the composite amplitude A by setting φ1=0 [rad], φ2=2π / 3 [rad], φ3=π [rad], and φ4=4π / 3 [rad], thereby improving EMI by 6 dB.

[0119] A similar argument can also be used to discuss EMI of double waves. When considering EMI of harmonics, for example, equation (1) can be rewritten as the following equation (3A).

[0120]

number

[0121] That is, in the case of a double wave, ω = 2ω0. Therefore, the phase for the double wave is twice as long as that for the fundamental wave. When the Nth harmonic, ω = nω0, is taken into consideration, the carrier signal flowing through the isolation element x is expressed by the following equation (3B).

[0122]

number

[0123] Moreover, the composite amplitude A of equation (3B) is expressed as in the following equation (4A), and the phase φ of equation (3B) is expressed as in the following equation (4B).

[0124]

number

[0125]

number

[0126] When φ1=0 [rad], φ2=2π / 3 [rad], φ3=π [rad], and φ4=4π / 3 [rad], the maximum composite amplitude A=2 is obtained when A1=A3=1 and A2=A4=1. On the other hand, when φ1=φ2=φ3=φ4=0 [rad], the maximum composite amplitude A=4 is obtained when A1=A2=A3=A4=1. Comparing these cases, the communication device 3 according to the third embodiment can halve the composite amplitude A by setting φ1=0 [rad], φ2=2π / 3 [rad], φ3=π [rad], and φ4=4π / 3 [rad], as in the case of the fundamental wave, and can improve the EMI of the harmonic by 6 dB.

[0127] [3-3] Modification of the third embodiment The communication device 3 according to the third embodiment described above can be modified in various ways. For example, the third embodiment has been described with reference to a case where four types of carrier signals with different phases, φ1=0 [rad], φ2=2π / 3 [rad], φ3=π [rad], and φ4=4π / 3 [rad], are used, but the present invention is not limited to this. The communication device 3 can also improve harmonic EMI in cases where the types of carrier signals are other than four. Below, the first and second modifications of the third embodiment will be described with reference to the differences from the third embodiment.

[0128] [3-3-1] First modified example of the third embodiment Fig. 18 shows an example of the configuration of a communication device 3 according to a first modified example of the third embodiment. As shown in Fig. 18, the communication device 3 according to the first modified example of the third embodiment differs from the third embodiment in that the RF generator 20 outputs three types of carrier signals CS.

[0129] Specifically, the RF generator 20 in the first modified example of the third embodiment generates and outputs carrier signals CS1, CS2, and CS3 based on an input signal Vin1 input from an input circuit 10A, an input signal Vin2 input from an input circuit 10B, an input signal Vin3 input from an input circuit 10C, and an input signal Vin4 input from an input circuit 10D. For example, the carrier signal CS1 is input to signal generating circuits 30A and 30B. The carrier signals CS2 and CS3 are input to signal generating circuits 30C and 30D, respectively.

[0130] Fig. 19 shows an example of a circuit configuration of an RF generator 20 included in a communication device 3 according to a first modification of the third embodiment. As shown in Fig. 19, the RF generator 20 in the first modification of the third embodiment has a configuration in which the inverter 25 is omitted from the RF generator 20 in the first embodiment, and a plurality of carrier signals CS are output from a plurality of nodes.

[0131] Specifically, in the first modified example of the third embodiment, for example, the signal output from node N1 corresponds to carrier signal CS3. The signal output from node N2 corresponds to carrier signal CS2. The signal output from node N3 corresponds to carrier signal CS1. Note that in the first modified example of the third embodiment, the allocation of carrier signals CS to nodes N1, N2, and N3 can be changed arbitrarily. The other configurations of the communication device 3 according to the first modified example of the third embodiment are similar to those of the third embodiment.

[0132] In the communication device 3 according to the first modified example of the third embodiment described above, φ1=φ2=0 [rad], φ3=2π / 3 [rad], and φ4=4π / 3 [rad]. As a result, the communication device 3 according to the first modified example of the third embodiment can improve the EMI performance of the fundamental wave and the second harmonic by 6 dB compared to the case where φ1=φ2=φ3=φ4=0 [rad], similar to the third embodiment.

[0133] In the first modification of the third embodiment, the case where the carrier signal CS1 is input to the two signal generating circuits 30A and 30B is illustrated, but other carrier signals CS may be input to the two signal generating circuits 30A and 30B. When the carrier signal CS2 is input to the signal generating circuits 30A and 30B, φ1=0 [rad], φ2=φ3=2π / 3 [rad], and φ4=4π / 3 [rad]. When the carrier signal CS3 is input to the signal generating circuits 30A and 30B, φ1=0 [rad], φ2=2π / 3 [rad], and φ3=φ4=4π / 3 [rad]. In either case, the communication device 3 can improve the EMI performance of the fundamental wave and the second harmonic wave by 6 dB, as in the third embodiment.

[0134] [3-3-2] Second Modification of the Third Embodiment Fig. 20 shows an example of the configuration of a communication device 3 according to a second modified example of the third embodiment. As shown in Fig. 20, the communication device 3 according to the second modified example of the third embodiment differs from the third embodiment in that the RF generator 20 outputs two types of carrier signals CS.

[0135] Specifically, the RF generator 20 in the second modification of the third embodiment generates and outputs carrier signals CS1 and CS2 based on an input signal Vin1 input from an input circuit 10A, an input signal Vin2 input from an input circuit 10B, an input signal Vin3 input from an input circuit 10C, and an input signal Vin4 input from an input circuit 10D. For example, the carrier signal CS1 is input to signal generating circuits 30A and 30B. The carrier signal CS2 is input to signal generating circuits 30C and 30D.

[0136] Fig. 21 shows an example of a circuit configuration of an RF generator 20 included in a communication device 3 according to a second modified example of the third embodiment. As shown in Fig. 21, the RF generator 20 in the second modified example of the third embodiment has a configuration in which the output of the carrier signal CS from the node N2 is omitted, compared to the RF generator 20 in the first modified example of the third embodiment.

[0137] In the second modification of the third embodiment, for example, the signal output from node N1 corresponds to carrier signal CS2. The signal output from node N3 corresponds to carrier signal CS1. In addition, in the second modification of the third embodiment, the allocation of carrier signals CS to nodes N1 and N3 can be changed arbitrarily. The other configurations of the communication device 3 according to the second modification of the third embodiment are similar to those of the first modification of the third embodiment.

[0138] In the communication device 3 according to the second modified example of the third embodiment described above, φ1=φ2=0 [rad] and φ3=φ4=2π / 3 [rad]. As a result, the communication device 3 according to the second modified example of the third embodiment can improve the EMI performance of the fundamental wave and the second harmonic wave by 6 dB compared to the case where φ1=φ2=φ3=φ4=0 [rad], similar to the third embodiment.

[0139] [3-3-3] Third modified example of the third embodiment Fig. 22 shows an example of a circuit configuration of an RF generator 20 included in a communication device 3 according to a third modified example of the third embodiment. As shown in Fig. 22, the RF generator 20 in the third modified example of the third embodiment has a configuration in which the output of the carrier signal CS from the node N1 is omitted, compared to the RF generator 20 in the first modified example of the third embodiment.

[0140] In the third modification of the third embodiment, for example, the signal output from node N2 corresponds to carrier signal CS1. The signal output from node N3 corresponds to carrier signal CS2. In addition, in the third modification of the third embodiment, the allocation of carrier signals CS to nodes N2 and N3 can be changed arbitrarily. The other configurations of the communication device 3 according to the third modification of the third embodiment are similar to those of the first modification of the third embodiment.

[0141] In the communication device 3 according to the third modified example of the third embodiment described above, φ1=φ2=0 [rad] and φ3=φ4=4π / 3 [rad]. As a result, the communication device 3 according to the third modified example of the third embodiment can improve the EMI performance of the fundamental wave and the second harmonic by 6 dB compared to the case where φ1=φ2=φ3=φ4=0 [rad], similar to the third embodiment.

[0142] [4] Fourth embodiment The communication device 4 according to the fourth embodiment is a modified example of the signal generating circuit 30 using the positive-phase and negative-phase modulated signals described in the second embodiment. The following describes the differences between the communication device 4 according to the fourth embodiment and the second embodiment.

[0143] [4-1] Configuration Fig. 23 shows an example of a circuit configuration of a signal generating circuit 30 included in a communication device 4 according to the fourth embodiment. As shown in Fig. 23, the signal generating circuit 30 in the fourth embodiment includes a signal generating unit 31 having a different circuit configuration from that in the second embodiment. The signal generating unit 31 in the fourth embodiment includes, for example, a first delay circuit 330, a second delay circuit 331, a clock transition detection circuit 332, a pulse generating circuit 333, a NAND circuit 334, a phase detection circuit 335, a selector circuit 336, an OR circuit 337, and a NOR circuit 338.

[0144] An input signal Vin is input to the first delay circuit 330. Then, the first delay circuit 330 inputs the delayed input signal Vin to the pulse generating circuit 333. The delay amount of the first delay circuit is designed to be equal to the delay amount of the signal via the clock transition detection circuit 332, for example. Hereinafter, the input signal Vin delayed by the first delay circuit is referred to as a delayed input signal VinD.

[0145] The carrier signal CS is input to the second delay circuit 331. Then, the second delay circuit 331 inputs the delayed carrier signal CS to the selector circuit 336. The delay amount of the second delay circuit is designed to be equal to the sum of the delay amount of the signal via the clock transition detection circuit 332 and the delay amount of the signal via the phase detection circuit 335, for example. Hereinafter, the carrier signal CS delayed by the second delay circuit is referred to as a delayed carrier signal CSd.

[0146] The clock transition detection circuit 332 receives the input signal Vin and the carrier signal CS, and generates the clock transition signals CT1 and CT2 based on the input signal Vin and the carrier signal CS. The clock transition detection circuit 332 then inputs the generated clock transition signals CT1 and CT2 to the pulse generation circuit 333, the NAND circuit 334, and the phase detection circuit 335, respectively.

[0147] The pulse generating circuit 333 generates a positive phase input signal VinNP based on the input delayed input signal VinD and the clock transition signals CT1 and CT2. The pulse generating circuit 333 then inputs the generated positive phase input signal VinNP to the OR circuit 337.

[0148] The NAND circuit 334 performs a NAND operation on the input clock transition signals CT1 and CT2. Then, the NAND circuit 334 inputs the operation result to the NOR circuit 338 as a reverse phase input signal VinRP.

[0149] The phase detection circuit 335 generates phase detection signals PD1 and PD2 based on the input clock transition signals CT1 and CT2. Then, the phase detection circuit 335 inputs the generated phase detection signals PD1 and PD2 to the selector circuit 336.

[0150] The selector circuit 336 generates an internal carrier signal Vcs based on the input phase detection signals PD1 and PD2 and the delayed carrier signal CSd. The selector circuit 336 then inputs the generated internal carrier signal Vcs to an OR circuit 337 and a NOR circuit 338.

[0151] The OR circuit 337 corresponds to the positive-phase output of the signal generating circuit 30. Specifically, the OR circuit 337 performs an OR operation on the input positive-phase input signal VinNP and the internal carrier signal Vcs. Then, the OR circuit 337 outputs the operation result to the driving unit 32 as the positive-phase modulated signal MS1.

[0152] The NOR circuit 338 corresponds to the negative-phase output of the signal generating circuit 30. Specifically, the NOR circuit 338 performs a NOR operation on the input negative-phase input signal VinRP and the internal carrier signal Vcs. The NOR circuit 338 then outputs the operation result to the driving unit 32 as the negative-phase modulated signal MS2.

[0153] Other configurations of the communication device 4 according to the fourth embodiment are similar to those of the second embodiment. That is, modulated signals MS1 and MS2 generated by a signal generating unit 31 are input to a driving unit 32 (not shown). Then, the driving unit 32 differentially amplifies the modulated signals MS1 and MS2, and outputs the amplified voltage to the insulating element 40. Note that the signal generating circuit 30 in the fourth embodiment may have other circuit configurations as long as it is capable of executing the operations described below.

[0154] [4-2] Operation The operation of the communication device 4 according to the fourth embodiment may change depending on the state of the RF generator 20 and the timing at which the input signal Vin rises. Specific examples of the operation of the communication device 4 according to the fourth embodiment will be described below with reference to Figs. 24 to 26. Each of Figs. 24 to 26 shows an example of a timing chart of the operation of the communication device 4 according to the fourth embodiment, and shows the voltage of each signal corresponding to one signal generating circuit 30.

[0155] In the following description, when the RF generator 20 is in the on state, it means that at least one of the input signals Vin corresponding to the other signal generating circuits 30 is rising and the carrier signal CS is already oscillating. On the other hand, when the RF generator 20 is in the off state, it means that all of the input signals Vin corresponding to the other signal generating circuits 30 are falling and the carrier signal CS is not oscillating.

[0156] Also, the initial voltages of the input signal Vin, the delayed input signal VinD, the clock transition signals CT1 and CT2, the phase detection signals PD1 and PD2, the internal carrier signal Vcs, and the positive-phase input signal VinNP are set to the "L" level. At this time, the NAND circuit 334 outputs the negative-phase input signal VinRP at the "H" level. The OR circuit 337 outputs the modulated signal MS1 at the "L" level. The NOR circuit 338 outputs the modulated signal MS2 at the "L" level.

[0157] (When the RF generator 20 is on and CS is at the low level, Vin rises.) Fig. 24 corresponds to the operation when the input signal Vin rises while the RF generator 20 is in the on state and the carrier signal CS is at the "L" level (RF: on, "L" → "H" detection). As shown in Fig. 24, in the initial state of this example, the carrier signal CS is oscillating, and the delayed carrier signal CSd is oscillating with a delay with respect to the carrier signal CS.

[0158] When the input signal Vin rises, the first delay circuit 330 delays the delayed input signal VinD with respect to the input signal Vin, and causes it to transition from the "L" level to the "H" level (FIG. 24(1)). Then, based on the delayed input signal VinD becoming the "H" level, the pulse generating circuit 333 transitions the positive phase input signal VinNP from the "L" level to the "H" level. As a result, the positive phase input signal VinNP at the "H" level is input to the OR circuit 337, and the OR circuit 337 sets the modulated signal MS1 to the "H" level.

[0159] Also, when the input signal Vin rises, the clock transition detection circuit 332 starts monitoring the state of the carrier signal CS. At this time, the clock transition detection circuit 332 first transitions the clock transition signal CT1 from the "L" level to the "H" level based on the rising of the carrier signal CS (FIG. 24(2)). Next, the clock transition detection circuit 332 transitions the clock transition signal CT2 from the "L" level to the "H" level based on the falling of the carrier signal CS (FIG. 24(3)). When both the clock transition signals CT1 and CT2 become "H" level, the pulse generation circuit 333 transitions the positive phase input signal VinNP from the "H" level to the "L" level, and the NAND circuit 334 transitions the negative phase input signal VinRP from the "H" level to the "L" level. In addition, the phase detection circuit 335 transitions the phase detection signal PD1 from the “L” level to the “H” level based on the fact that the clock transition signal CT1 transitions to the “H” level before the clock transition signal CT2 (Figure 24 (4)).

[0160] Then, based on the phase detection signal PD1 being at "H" level, the selector circuit 336 outputs a signal having the same phase as the delayed carrier signal CSd as the internal carrier signal Vcs (FIG. 24(5)). When the positive-phase input signal VinNP at "L" level is input to the OR circuit 337, the OR circuit 337 goes into a state where it sets the modulated signal MS1 to "L" level and then outputs the modulated signal MS1 having a phase that maintains the phase of the internal carrier signal Vcs. When the negative-phase input signal VinRP at "L" level is input to the NOR circuit 338, the NOR circuit 338 goes into a state where it outputs the modulated signal MS2 having a phase that is the inverse of the phase of the internal carrier signal Vcs.

[0161] As described above, in this example, when the input signal Vin rises, the first pulse signal of the modulated signal MS1 is immediately generated by the pulse generating circuit 333, and the second and subsequent pulse signals are generated based on the internal carrier signal Vcs corresponding to the same phase as the carrier signal CS. After that, when the input signal Vin falls, the first delay circuit 330 transitions the delayed input signal VinD from the “H” level to the “L” level, and the clock transition detection circuit 332 transitions the clock transition signals CT1 and CT2 from the “H” level to the “L” level (FIG. 24(6)). Based on the clock transition signals CT1 and CT2 both becoming the “L” level, the NAND circuit 334 outputs the inverse phase input signal VinRP at the “H” level, the phase detection circuit 335 transitions the phase detection signal PD1 from the “H” level to the “L” level, and the selector circuit 336 maintains the internal carrier signal Vcs at the “L” level. As a result, the signal generating circuit 30 returns to the initial state.

[0162] (When the RF generator 20 is on and CS is at “H” level, Vin rises.) Fig. 25 corresponds to the operation when the input signal Vin rises while the RF generator 20 is in the on state and the carrier signal CS is at the "H" level (RF: on, "H" → "L" detection). As shown in Fig. 25, in the initial state of this example, the carrier signal CS is oscillating, and the delayed carrier signal CSd is oscillating with a delay with respect to the carrier signal CS.

[0163] When the input signal Vin rises, the first delay circuit 330 delays the delayed input signal VinD with respect to the input signal Vin, and causes it to transition from the "L" level to the "H" level (FIG. 25(1)). Then, based on the delayed input signal VinD becoming the "H" level, the pulse generating circuit 333 causes the positive phase input signal VinNP to transition from the "L" level to the "H" level. As a result, the positive phase input signal VinNP at the "H" level is input to the OR circuit 337, and the OR circuit 337 sets the modulated signal MS1 to the "H" level.

[0164] Also, when the input signal Vin rises, the clock transition detection circuit 332 starts monitoring the state of the carrier signal CS. At this time, the clock transition detection circuit 332 first transitions the clock transition signal CT2 from the "L" level to the "H" level based on the falling edge of the carrier signal CS (FIG. 25(2)). Next, the clock transition detection circuit 332 transitions the clock transition signal CT1 from the "L" level to the "H" level based on the rising edge of the carrier signal CS (FIG. 25(3)). When both the clock transition signals CT1 and CT2 become "H" level, the pulse generation circuit 333 transitions the positive phase input signal VinNP from the "H" level to the "L" level, and the NAND circuit 334 transitions the negative phase input signal VinRP from the "H" level to the "L" level. In addition, the phase detection circuit 335 transitions the phase detection signal PD2 from the “L” level to the “H” level based on the fact that the clock transition signal CT2 transitions to the “H” level before the clock transition signal CT1 (Figure 25 (4)).

[0165] Then, based on the phase detection signal PD2 being at "H" level, the selector circuit 336 outputs a signal having a phase obtained by inverting the phase of the delayed carrier signal CSd as the internal carrier signal Vcs (FIG. 25(5)). When the positive-phase input signal VinNP at "L" level is input to the OR circuit 337, the OR circuit 337 goes into a state in which it sets the modulated signal MS1 to "L" level and then outputs the modulated signal MS1 having the same phase as the internal carrier signal Vcs. When the negative-phase input signal VinRP at "L" level is input to the NOR circuit 338, the NOR circuit 338 goes into a state in which it outputs the modulated signal MS2 having a phase obtained by inverting the phase of the internal carrier signal Vcs.

[0166] As described above, in this example, when the input signal Vin rises, the first pulse signal of the modulated signal MS1 is immediately generated by the pulse generating circuit 333, and the second and subsequent pulse signals are generated based on the internal carrier signal Vcs corresponding to the inverted output of the carrier signal CS. After that, when the input signal Vin falls, the first delay circuit 330 transitions the delayed input signal VinD from the “H” level to the “L” level, and the clock transition detection circuit 332 transitions the clock transition signals CT1 and CT2 from the “H” level to the “L” level (FIG. 25(6)). Based on the fact that both the clock transition signals CT1 and CT2 have become the “L” level, the NAND circuit 334 outputs the inverse phase input signal VinRP at the “H” level, the phase detection circuit 335 transitions the phase detection signal PD2 from the “H” level to the “L” level, and the selector circuit 336 maintains the internal carrier signal Vcs at the “L” level. As a result, the signal generating circuit 30 returns to the initial state.

[0167] (When Vin rises while RF generator 20 is off) Fig. 26 corresponds to the operation when the input signal Vin rises when the RF generator 20 is in the off state (RF: off → on). As shown in Fig. 26, in the initial state of this example, the carrier signal CS is in the off state ("L" level).

[0168] When the input signal Vin rises, the RF generator 20 is turned on and the carrier signal CS starts oscillating (RF on). In this case, the clock transition detection circuit 332 detects the rising edge of the carrier signal CS first and detects the falling edge of the carrier signal CS later. That is, in this example, after the input signal Vin rises, the clock transition signal CT1 becomes the “H” level first, and the clock transition signal CT2 becomes the “H” level later. Other operations shown in FIG. 26 are the same as those described with reference to FIG. 24. Note that, if the other input signal Vin is maintained at the “L” level, when the input signal Vin falls, the RF generator 20 is turned off (RF off).

[0169] [4-3] Effects of the fourth embodiment As described above, the signal generating circuit 30 included in the communication device 4 according to the fourth embodiment includes the signal generating section 31 that changes the phase of the internal carrier signal Vcs in response to the rising timing of the input signal Vin.

[0170] In short, when the signal generating unit 31 in the fourth embodiment detects the rising edge of the input signal Vin, it generates a first pulse signal (modulated signal MS1) regardless of whether the RF generator 20 is in an on state or an off state. The pulse width of this first pulse signal is 0.5 to 1.0 times the period of the carrier signal CS depending on the rising edge timing of the input signal Vin. Then, when the signal generating unit 31 in the fourth embodiment detects the rising edge of the input signal Vin while the carrier signal CS is at the "L" level, it generates an internal carrier signal Vcs based on the phase of the delayed carrier signal CS. On the other hand, when the signal generating unit 31 in the fourth embodiment detects the rising edge of the input signal Vin while the carrier signal CS is at the "H" level, it generates an internal carrier signal Vcs based on the inverted phase of the delayed carrier signal CS.

[0171] As described above, the first pulse signal is generated regardless of the state of the RF generator 20, so that the waveform of the rising edge of the positive-phase modulated signal MS1 is constant regardless of whether the input signal Vin and the carrier signal CS are synchronized. In other words, even if the input signal Vin and the carrier signal CS are operated asynchronously, the leading edge waveform of the modulated signal MS used in the OOK system is aligned. As a result, the communication device 4 according to the fourth embodiment can stabilize the rising time of the detection circuit, and can suppress jitter in the output signal by the signal generating circuit 30, as in the first and second embodiments.

[0172] Furthermore, the second and subsequent pulse signals are generated based on an inverted or non-inverted internal carrier signal Vcs according to the rising timing of the input signal Vin, so that the falling edge of the first pulse signal and the rising edge of the second and subsequent pulse signals are smoothly connected. In other words, the signal generating unit 31 in the fourth embodiment can stably generate the second and subsequent pulses. As a result, the communication device 4 according to the fourth embodiment can suppress the generation of high-frequency pulses such as glitches. Therefore, the communication device 4 according to the fourth embodiment can improve the stability of operation compared to the second embodiment.

[0173] In the fourth embodiment, the signal generating circuit 30 uses the positive-phase modulated signal MS1 and the negative-phase modulated signal MS2, but the present invention is not limited to this. For example, the signal generating circuit 30 may handle one modulated signal MS, as in the first embodiment. In this case, the signal generating unit 31 has a configuration in which the NAND circuit 334 and the NOR circuit 338 are omitted from the configuration shown in FIG. 23. A communication device having such a signal generating circuit 30 can obtain the same effects as the fourth embodiment and can improve the stability of operation compared to the first embodiment.

[0174] [5] Other The above embodiments can be combined. For example, the second embodiment may be combined with any of the first to fourth modified examples of the first embodiment. The third embodiment may be combined with any of the first embodiment, the first and second modified examples of the first embodiment, the second embodiment, and the modified examples of the second embodiment. The fourth embodiment may be combined with any of the third embodiment and the first to third modified examples of the third embodiment. The signal generating circuit 30 of the fourth embodiment may be applied to each of the N channels, as in the third modified example of the first embodiment. A communication device 1 in which a plurality of embodiments and modified examples are combined can obtain the respective effects of the combined embodiments and modified examples. As in the third embodiment, adjusting the phase of each isolation element 40 to suppress EMI can also be applied to the first and second embodiments. In other words, the third embodiment can be applied regardless of the configuration of the signal generating circuit 30, the number of channels provided in the communication device 1, and the type of isolation element used.

[0175] In this specification, a voltage at the "H" level is a voltage at which an N-type transistor having the voltage applied to its gate is turned on and a P-type transistor having the voltage applied to its gate is turned off. A voltage at the "L" level is a voltage at which an N-type transistor having the voltage applied to its gate is turned off and a P-type transistor having the voltage applied to its gate is turned on. The "first logic level" and the "second logic level" correspond to either the "H" level or the "L" level. The oscillating signal output by the RF generator 20 may be called an "RF signal" or a "clock signal". The RF generator 20 may be called an "oscillator". The set of the receiving circuit 50 and the output circuit 60 may be called an "output circuit".

[0176] In this specification, "connection" means that the two are electrically connected, and does not exclude, for example, the presence of another element between them. In addition, in this specification, "on state" means that a voltage equal to or greater than the threshold voltage of the corresponding transistor is applied to the gate of the corresponding transistor. "Off state" means that a voltage less than the threshold voltage of the corresponding transistor is applied to the gate of the corresponding transistor, and does not exclude, for example, the flow of a minute current such as a transistor's leakage current. "A signal rises" means that the voltage of the corresponding signal changes from an "L" level to an "H" level. "A signal falls" means that the voltage of the corresponding signal changes from an "H" level to an "L" level. "A state in which the signal rises" corresponds to an "H" level. "A state in which the signal falls" corresponds to an "L" level. "One pulse signal" corresponds, for example, to the portion where the signal transitions from an "L" level to an "H" level to an "L" level. "Pulse width" corresponds, for example, to the period where the signal transitions from an "L" level to an "H" level to an "L" level.

[0177] The proposed claims of this specification are set forth below.

[0178] <1> The communication device includes an oscillator, a first signal generating circuit, a second signal generating circuit, a first insulating element, a second insulating element, a first output circuit, and a second output circuit. The oscillator outputs a carrier signal when at least one of a first signal and a second signal input from outside is at a first logic level. The first signal generating circuit includes a first signal generating unit and a first driving circuit. The first signal generating unit generates a first pulse signal when it detects a rising edge of the first signal, outputs a signal having the same phase as the carrier signal as a second or subsequent pulse signal when the carrier signal is at a second logic level different from the first logic level when the rising edge of the first signal is detected, and outputs a signal having an inverted phase of the carrier signal as a second or subsequent pulse signal when the carrier signal is at the first logic level when the rising edge of the first signal is detected. The first driving circuit amplifies the output signal of the first signal generating unit. The second signal generating circuit includes a second signal generating unit and a second driving circuit. The second signal generating unit generates a first pulse signal when it detects a rising edge of the second signal, and outputs a signal having the same phase as the carrier signal as the second and subsequent pulse signals if the carrier signal is at the second logic level when the rising edge of the second signal is detected, and outputs a signal having an inverted phase of the carrier signal as the second and subsequent pulse signals if the carrier signal is at the first logic level when the rising edge of the first signal is detected. The second driving circuit amplifies the output signal of the second signal generating unit. The first insulating element is connected to the output of the first driving circuit. The second insulating element is connected to the output of the second driving circuit. The first output circuit receives a signal based on the output signal of the first driving circuit via the first insulating element and outputs it to the outside. The second output circuit receives a signal based on the output signal of the second driving circuit via the second insulating element and outputs it to the outside.

[0179] <2> <1> The communication device described in has the following configuration. The first signal generating unit includes a clock transition detection circuit, a pulse generation circuit, a phase detection circuit, a selector circuit, and a first logical OR circuit. The clock transition detection circuit receives the first signal and the carrier signal, and generates a first control signal and a second control signal based on the input first signal and the carrier signal. The pulse generation circuit generates a first input signal based on the first signal, the first control signal, and the second control signal. The phase detection circuit generates a third control signal and a fourth control signal based on the first control signal and the second control signal. The selector circuit generates an internal carrier signal based on the third control signal, the fourth control signal, and the carrier signal. The first logical OR circuit performs a logical OR operation on the first input signal and the internal carrier signal, and the operation result is output by the first driving circuit. The clock transition detection circuit transitions the first control signal from the second logic level to the first logic level when it detects a rising edge of the carrier signal after the first signal rises, and transitions the second control signal from the second logic level to the first logic level when it detects a falling edge of the carrier signal. The pulse generation circuit transitions the first input signal from the second logic level to the first logic level when it detects a rising edge of the first signal, and transitions the first input signal from the first logic level to the second logic level in response to both the first control signal and the second control signal becoming the first logic level after detecting the rising edge of the first signal. The phase detection circuit generates an internal carrier signal with the same phase as the carrier signal if the third control signal transitions to the first logic level before the fourth control signal when both the third control signal and the fourth control signal become the first logic level, and generates an internal carrier signal with an inverted phase of the carrier signal if the fourth control signal transitions to the first logic level before the third control signal.

[0180] <3> <2> The communication device described in has the following configuration. The first signal generating unit further includes a first delay circuit and a second delay circuit. The first delay circuit generates a delay equivalent to the delay amount of the clock transition detection circuit. The second delay circuit generates a delay equivalent to the total delay amount of the clock transition detection circuit and the phase detection circuit. The first signal is input to the pulse generating circuit via the first delay circuit, and the pulse generating circuit generates a first input signal based on the delayed first signal. The carrier signal is input to the selector circuit via the second delay circuit, and the selector circuit generates an internal carrier signal based on the delayed carrier signal.

[0181] <4> <2> or <3> The communication device described in has the configuration described subsequently. The first signal generating unit further includes a first NAND circuit and a first NOR circuit. The first NAND circuit executes a NAND operation between the first control signal and the second control signal, and outputs the operation result as a second input signal. The first NOR circuit executes a NOR operation between the second input signal and an internal carrier signal, and the operation result is output by the first driving circuit. The first driving circuit differentially amplifies the output of the first OR circuit and the output of the first NOR circuit.

[0182] <5> <1> ~ <4> The communication device according to any one of claims 1 to 5 has the following configuration: when the first signal generating unit detects a rising edge of the first signal and then a falling edge of the first signal, the first signal generating unit outputs a signal of a second logic level to the first driving circuit.

[0183] <6> The communication device includes an oscillator, a first signal generating circuit, a second signal generating circuit, a first insulating element, a second insulating element, a first output circuit, and a second output circuit. The oscillator outputs a carrier signal when at least one of a first signal and a second signal input from outside is at a first logic level. The first signal generating circuit includes a first delay circuit, a first logic circuit, a second logic circuit, a third logic circuit, and a first drive circuit. The first logic circuit receives the first signal at a first input terminal and receives the first signal via the first delay circuit at a second input terminal. The second logic circuit has an output terminal of the first logic circuit connected to a first input terminal and receives the carrier signal at a second input terminal. The third logic circuit receives the first signal at a first input terminal and receives an output terminal of the second logic circuit connected to a second input terminal. The first drive circuit amplifies the voltage output by the third logic circuit. The second signal generating circuit includes a second delay circuit, a fourth logic circuit, a fifth logic circuit, a sixth logic circuit, and a second driving circuit. The fourth logic circuit receives the second signal at its first input terminal, and receives the second signal via the second delay circuit at its second input terminal. The fifth logic circuit has a first input terminal connected to the output terminal of the fourth logic circuit, and receives a carrier signal at its second input terminal. The sixth logic circuit receives the second signal at its first input terminal, and receives the output terminal of the fifth logic circuit at its second input terminal. The second driving circuit amplifies the voltage output by the sixth logic circuit. The first insulating element is connected to the output of the first driving circuit. The second insulating element is connected to the output of the second driving circuit. The first output circuit receives a signal based on the output signal of the first driving circuit via the first insulating element, and outputs the signal to the outside. The second output circuit receives a signal based on the output signal of the second driving circuit via the second insulating element, and outputs the signal to the outside.

[0184] <7> <6> In the communication device described in the above, the first logic circuit, the third logic circuit, the fourth logic circuit, and the sixth logic circuit are AND circuits, and the second logic circuit and the fifth logic circuit are NAND circuits.

[0185] <8> <6> or <7> The communication device described in has the following configuration. The first signal generating circuit further includes a fourth inverter and a thirteenth logic circuit. The fourth inverter has an input terminal connected to the output terminal of the second logic circuit. The thirteenth logic circuit has a first input terminal to which the first signal is input and a second input terminal to which the output terminal of the fourth inverter is connected. The second signal generating circuit further includes a fifth inverter and a fourteenth logic circuit. The second signal generating circuit has an input terminal to which the output terminal of the fifth logic circuit is connected. The fourteenth logic circuit has a first input terminal to which the second signal is input and a second input terminal to which the output terminal of the fifth inverter is connected. The first driving circuit differentially amplifies the output of the third logic circuit and the output of the thirteenth logic circuit. The second driving circuit differentially amplifies the output of the sixth logic circuit and the output of the fourteenth logic circuit.

[0186] <9> <1> ~ <8> The communication device according to any one of the above has the following configuration: The first insulating element includes a first coil and a second coil. The first coil is connected to the output of the first drive circuit. The second coil faces the first coil via an insulating layer and is connected to the first output circuit. The second insulating element includes a third coil and a fourth coil. The third coil is connected to the output of the second drive circuit. The fourth coil faces the third coil via an insulating layer and is connected to the second output circuit.

[0187] <10> <1> ~ <8> The communication device according to any one of the above has the following configuration: the first insulating element includes a first capacitor, one electrode of which is connected to the output of the first drive circuit and the other electrode of which is connected to the first output circuit; the second insulating element includes a second capacitor, one electrode of which is connected to the output of the second drive circuit and the other electrode of which is connected to the second output circuit.

[0188] <11> <1> ~ <10> The communication device according to any one of claims 1 to 5 further includes a first substrate and a second substrate. An oscillator, a first signal generating circuit, and a second signal generating circuit are mounted on the first substrate. A first output circuit and a second output circuit are mounted on the second substrate. The first isolation element and the second isolation element are mounted on either the first substrate or the second substrate.

[0189] <12> <1> or <6> In the communication device described in , a phase of a carrier signal input to the first signal generating circuit is different from a phase of a carrier signal input to the second signal generating circuit.

[0190] <13> <12> In the communication device described in , the oscillator includes a second OR circuit, a second NAND circuit, a first inverter, and a second inverter. The second OR circuit has a first input terminal to which a first signal is input, and a second input terminal to which a second signal is input. The second NAND circuit has a first input terminal to which an output terminal of the second OR circuit is connected. The first inverter has an input terminal to which an output terminal of the second NAND circuit is connected. The second inverter has an input terminal to which an output terminal of the first inverter is connected, and an output terminal to which a second input terminal of the second NAND circuit is connected. The output terminal of the second NAND circuit is connected to the second signal generating circuit. The output terminal of the second inverter is connected to the first signal generating circuit.

[0191] <14> <12> In the communication device described in , the oscillator includes a second OR circuit, a second NAND circuit, a first inverter, and a second inverter. The second OR circuit has a first input terminal to which a first signal is input, and a second input terminal to which a second signal is input. The second NAND circuit has a first input terminal to which an output terminal of the second OR circuit is connected. The first inverter has an input terminal to which an output terminal of the second NAND circuit is connected. The second inverter has an input terminal to which an output terminal of the first inverter is connected, and an output terminal to which a second input terminal of the second NAND circuit is connected. The output terminal of the first inverter is connected to the second signal generating circuit. The output terminal of the second inverter is connected to the first signal generating circuit.

[0192] <15> <6> The communication device described in further includes a third signal generating circuit, a third insulating element, and a third output circuit. The third signal generating circuit includes a third delay circuit, a seventh logic circuit, an eighth logic circuit, a ninth logic circuit, and a third driving circuit. The seventh logic circuit receives a third signal from outside the communication device at a first input terminal, and receives a third signal via the third delay circuit at a second input terminal. The eighth logic circuit has an output terminal of the seventh logic circuit connected to a first input terminal, and receives a carrier signal at a second input terminal. The ninth logic circuit receives the third signal at a first input terminal, and receives an output terminal of the eighth logic circuit connected to a second input terminal. The third driving circuit amplifies the voltage output by the ninth logic circuit. The third insulating element is connected to the output of the third driving circuit. The third output circuit receives a signal based on the output signal of the third driving circuit via the third insulating element, and outputs the signal to the outside.

[0193] <16> <15> The communication device described in has the following configuration. The oscillator outputs a carrier signal when at least one of the first signal, the second signal, and the third signal is at a first logic level. The phase of the carrier signal input to the first signal generating circuit, the phase of the carrier signal input to the second signal generating circuit, and the phase of the carrier signal input to the third signal generating circuit are different from each other.

[0194] <17> <16> The communication device described in has the configuration described subsequently. The oscillator includes a second OR circuit, a second NAND circuit, a first inverter, and a second inverter. The second OR circuit has a first input terminal to which a first signal is input, a second input terminal to which a second signal is input, and a third input terminal to which a third signal is input. The second NAND circuit has a first input terminal to which an output terminal of the second OR circuit is connected. The first inverter has an input terminal to which an output terminal of the second NAND circuit is connected. The second inverter has an input terminal to which an output terminal of the first inverter is connected, and an output terminal to which a second input terminal of the second NAND circuit is connected. The output terminal of the second NAND circuit is connected to a third signal generating circuit. The output terminal of the first inverter is connected to the second signal generating circuit. The output terminal of the second inverter is connected to the first signal generating circuit.

[0195] <18> <15> The communication device described in further includes a fourth signal generating circuit, a fourth insulating element, and a fourth output circuit. The fourth signal generating circuit includes a fourth delay circuit, a tenth logic circuit, an eleventh logic circuit, a twelfth logic circuit, and a fourth driving circuit. The tenth logic circuit receives a fourth signal from outside the communication device at a first input terminal, and receives a fourth signal via the fourth delay circuit at a second input terminal. The eleventh logic circuit has an output terminal of the tenth logic circuit connected to a first input terminal, and receives a carrier signal at a second input terminal. The twelfth logic circuit receives the fourth signal at a first input terminal, and receives an output terminal of the eleventh logic circuit connected to a second input terminal. The fourth driving circuit amplifies the voltage output by the twelfth logic circuit. The fourth insulating element is connected to the output of the fourth driving circuit. The fourth output circuit receives a signal based on the output signal of the fourth driving circuit via the fourth insulating element, and outputs the signal to the outside.

[0196] <19> <18> The communication device described in has the following configuration. The oscillator outputs a carrier signal when at least one of the first signal, the second signal, the third signal, and the fourth signal is at a first logic level. The phase of the carrier signal input to the first signal generating circuit, the phase of the carrier signal input to the second signal generating circuit, the phase of the carrier signal input to the third signal generating circuit, and the phase of the carrier signal input to the fourth signal generating circuit are different from each other.

[0197] <20> <19> The communication device described in has the configuration described subsequently. The oscillator includes a second OR circuit, a second NAND circuit, a first inverter, a second inverter, and a third inverter. The second OR circuit has a first input terminal to which a first signal is input, a second input terminal to which a second signal is input, a third input terminal to which a third signal is input, and a fourth input terminal to which a fourth signal is input. The second NAND circuit has a first input terminal to which an output terminal of the second OR circuit is connected. The first inverter has an input terminal to which an output terminal of the second NAND circuit is connected. The second inverter has an input terminal to which an output terminal of the first inverter is connected, and an output terminal to which a second input terminal of the second NAND circuit is connected. The third inverter has an input terminal to which an output terminal of the second inverter is connected. The output terminal of the second NAND circuit is connected to the fourth signal generating circuit. The output terminal of the first inverter is connected to the second signal generating circuit. The output terminal of the second inverter is connected to the first signal generating circuit. The output terminal of the third inverter is connected to the third signal generating circuit.

[0198] <21> The communication device includes an oscillator, an Nth signal generating circuit, an Nth isolation element, an Nth receiving circuit, and an Nth output circuit. The oscillator outputs a carrier signal when at least one of a first signal and a second signal input from outside is at a first logic level. The Nth signal generating unit generates a first pulse signal when it detects a first logic level of an Nth signal (N is an integer equal to or greater than 1) among a plurality of signals, and outputs a pulse signal in which the first pulse signal is followed by a carrier signal and the carrier signal stops when the Nth signal becomes at a second logic level. The Nth driving circuit amplifies the output signal of the Nth signal generating unit. The Nth isolation element is connected to the output of the Nth driving circuit. The Nth receiving circuit receives a signal based on the output signal of the Nth driving circuit via the Nth isolation element, and demodulates the received signal. The Nth output circuit outputs a signal based on the output signal of the Nth receiving circuit to the outside.

[0199] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0200] 1...communication device, 10...input circuit, 20...RF generator, 21...OR circuit, 22...NAND circuit, 23-25...inverter, 30...signal generating circuit, 31...signal generating unit, 32...driving unit, 40...insulating element, 41, 42...coil, 43, 44...capacitor, 50...receiving circuit, 60...output circuit, 311, 314, 316...AND circuit, 312...delay circuit, 313...NAND circuit, 315...inverter, 321...driving circuit, 322-325...transistor, 326...current source, 330...first delay circuit, 331...second delay circuit, 332...clock transition detection circuit, 333...pulse generating circuit, 334...NAND circuit, 335...phase detection circuit, 336...selector circuit, 337...OR circuit, 338...NOR circuit, CP1, CP2...chip, CS...carrier signal

Claims

1. an oscillator that outputs a first carrier signal and a second carrier signal when at least one of a first input signal and a second input signal input from outside is at a first logic level; a first signal generating circuit including a first delay circuit, a first logic circuit having a first input terminal to which the first input signal is input and a second input terminal to which the first input signal via the first delay circuit is input, a second logic circuit having a first input terminal connected to an output terminal of the first logic circuit and having a second input terminal to which the first carrier signal is input, a third logic circuit having a first input terminal to which the first input signal is input and having a second input terminal connected to an output terminal of the second logic circuit, and a first drive circuit for amplifying a voltage output by the third logic circuit; a second signal generating circuit including a second delay circuit, a fourth logic circuit having a first input terminal to which the second input signal is input and a second input terminal to which the second input signal via the second delay circuit is input, a fifth logic circuit having a first input terminal connected to an output terminal of the fourth logic circuit and having a second input terminal to which the second carrier signal is input, a sixth logic circuit having a first input terminal to which the second input signal is input and an output terminal of the fifth logic circuit connected to a second input terminal, and a second drive circuit for amplifying a voltage output by the sixth logic circuit; a first isolation element connected to an output of the first driver circuit; a second isolation element connected to an output of the second driver circuit; a first output circuit that receives a signal based on an output signal of the first drive circuit via the first isolation element and outputs the signal to an outside; a second output circuit that receives a signal based on an output signal of the second drive circuit via the second isolation element and outputs the signal to an outside; A communication device comprising:

2. the first logic circuit, the third logic circuit, the fourth logic circuit, and the sixth logic circuit are AND circuits, the second logic circuit and the fifth logic circuit are NAND circuits; The communication device according to claim 1 .

3. the first signal generating circuit further includes a first inverter having an input terminal connected to the output terminal of the second logic circuit, and a seventh logic circuit having a first input terminal to which the first input signal is input and a second input terminal to which the output terminal of the first inverter is connected, the second signal generating circuit further includes a second inverter having an input terminal connected to the output terminal of the fifth logic circuit, and an eighth logic circuit having a first input terminal to which the second input signal is input and a second input terminal to which the output terminal of the second inverter is connected, the first drive circuit differentially amplifies an output of the third logic circuit and an output of the seventh logic circuit; the second drive circuit differentially amplifies an output of the sixth logic circuit and an output of the eighth logic circuit; The communication device according to claim 1 or 2.

4. The first carrier signal and the second carrier signal have different phases. A communication device according to any one of claims 1 to 3.

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