Systems and methods for controlling quantum components

Abstract

A programmable component of a quantum processor can be selectively programmed using a digital-to-analog converter (DAC). A DAC having a first stage and a second stage and first and second quantum flux parametron (OFF) loops galvanically coupled to and extending from respective ones of the first and second stages are described. The first stage has a first storage loop interrupted by a first Josephson junction and an interface for communicating with an external component. The second stage has a second storage loop interrupted by a second Josephson junction, the second storage loop being galvanically coupled to the first storage loop, and the first and second Josephson junctions being coupled in series to a first control line. A method of loading flux quanta into a target DAC stage is also described.

Description

[Technical field]

[0001] Field The present disclosure relates generally to quantum computing, and more particularly to the design and operation of components used to program and operate other quantum components. [Background technology]

[0002] background Quantum Computing A quantum computer is a system that directly exploits at least one quantum-mechanical phenomenon, such as superposition, tunneling, or entanglement, to perform operations on data. The elements of a quantum computer are quantum binary digits called qubits. One model of quantum computing is adiabatic quantum computing. Adiabatic quantum computing may be suitable, for example, for solving difficult optimization problems. Further details regarding adiabatic quantum computing systems, methods, and apparatus are described, for example, in U.S. Pat. Nos. 7,135,701 and 7,418,283.

[0003] Quantum Annealing Quantum annealing is a computational method that can be used to find a low-energy state of a system, usually preferably the ground state of the system. Conceptually similar to traditional simulated annealing, this method relies on the underlying principle that natural systems have a tendency toward relatively low energy states because lower energy states are relatively stable. While traditional annealing uses traditional thermal fluctuations to guide the system to a low energy state, quantum annealing may use quantum effects such as quantum tunneling as a source of delocalization to reach the energy minimum more accurately and / or quickly than traditional annealing. In quantum annealing, thermal effects and other noise may be present. The final low energy state may not be the global energy minimum.

[0004] Adiabatic quantum computing can be considered a special case of quantum annealing. In adiabatic quantum computing, the system ideally begins and remains in its ground state throughout the adiabatic evolution. Thus, those skilled in the art will understand that quantum annealing systems and methods can generally be implemented on adiabatic quantum computers. Throughout this application, any reference to quantum annealing is intended to encompass adiabatic quantum computing, unless the context requires otherwise.

[0005] Quantum Components Quantum components are structures in which quantum mechanical effects are observable. Quantum components may also be referred to as quantum devices. Quantum components include circuits in which current transport is governed by quantum mechanical effects. Such components include spintronics, in which electron spin is used as a resource, and superconducting circuits. Superconducting circuits are circuits that include superconducting devices. Superconducting devices are devices that include superconducting materials. Superconducting materials are materials that have no electrical resistance below critical levels of electric current, magnetic field, and temperature. Both spin and superconductivity are quantum mechanical phenomena. Quantum components can be used for metrology instruments in computing devices and the like.

[0006] Quantum Processor The quantum processor may have the form of a superconducting quantum processor, which may include a number of superconducting qubits and associated components that provide local biasing, and may also include coupling devices (also referred to as couplers) that selectively provide communicative coupling between the qubits.

[0007] The quantum processor may be a superconducting quantum processor that includes superconducting qubits. "SUPERCONDUCTING QUANTUM CIRCUITS, QUBITS AND COMPUTING" (arXiv:cond-mat / 0508729v1, 2005) by Wendin G. and Shumeiko VS provides an overview of the physics and operating principles of quantized superconducting electrical circuits for quantum information processing.

[0008] A superconducting qubit is a solid-state quantum bit based on a circuit of superconducting material. The operation of a superconducting qubit is based on the underlying principles of flux quantization and Josephson tunneling. The superconducting effect can exist in a variety of configurations, resulting in different types of superconducting qubits, including flux, phase, charge, and hybrid qubits. The various configurations can vary in the topology of the loop, the arrangement of the Josephson junctions, and the physical parameters of the elements of the superconducting circuit, such as the inductance, capacitance, and Josephson junction critical current.

[0009] In one implementation, a superconducting qubit includes a superconducting loop interrupted by a Josephson junction. The ratio of the inductance of the Josephson junction to the geometric inductance of the superconducting loop is 2πLI C / Φ0, where L is the geometric inductance and I C (where Φ is the critical current of the Josephson junction and Φ is the magnetic flux quantum). The inductance and critical current can be selected, adjusted, or tuned to increase the ratio of the inductance of the Josephson junction to the geometric inductance of the superconducting loop and to enable the qubit to operate as a bistable device. In some implementations, the ratio of the inductance of the Josephson junction to the geometric inductance of the superconducting loop of the qubit is equal to about 3.

[0010] In one implementation, the superconducting coupler includes a superconducting loop interrupted by a Josephson junction. The inductance and critical current can be selected, adjusted, or tuned to reduce the ratio of the inductance of the Josephson junction to the geometric inductance of the superconducting loop and to enable the coupler to operate as a monostable device. In some implementations, the ratio of the inductance of the Josephson junction to the geometric inductance of the superconducting loop of the coupler is approximately equal to 1 or less.

[0011] Further details and implementations of example quantum processors that may be used in connection with the present systems and components are described in, for example, U.S. Pat. Nos. 7,533,068, 8,008,942, 8,195,596, 8,190,548, and 8,421,053.

[0012] The above examples of related technologies and limitations associated therewith are intended to be illustrative and not exhaustive. Other limitations of the related technologies will become apparent to those of ordinary skill in the art upon review of this specification and drawings. Summary of the Invention [Means for solving the problem]

[0013] A quick overview According to one aspect, a digital-to-analog converter (DAC) is provided that includes a first stage having a first storage loop interrupted by a first Josephson junction, the first storage loop having an interface operable to communicate with an external component; a second stage having a second storage loop interrupted by a second Josephson junction, the second storage loop being galvanically coupled to the first storage loop, the first Josephson junction and the second Josephson junction being coupled in series to a first control line; and a first quantum flux parametron (QFP) loop and a second quantum QFP loop, the first and second QFP loops being galvanically coupled to and extending from respective ones of the first and second stages.

[0014] According to another aspect, the DAC may further include a third stage galvanically coupled to the second stage and a fourth stage galvanically coupled to the third stage, the third and fourth stages having third and fourth storage loops interrupted by third and fourth Josephson junctions, respectively, the third and fourth Josephson junctions coupled in series to the first control line and the third and fourth QFP loops, the third and fourth QFP loops galvanically coupled to and extending from respective ones of the third and fourth stages. Each QFP loop may have an individual Josephson junction, each individual Josephson junction of each QFP loop may have an individual compound Josephson junction, the first and second Josephson junctions may each have a compound Josephson junction, the first and second QFP loops may be symmetrically connected to respective ones of the first and second stages, and the first QFP loop may be isolated from the second QFP loop. The first control line may bisect each of the first and second storage loops, each of the first and second storage loops may have a respective Josephson junction on each of a respective first side and a respective second side of the respective storage loop, and each of the first and QFP loops may be coupled to extend from the respective first side of the respective storage loop to the respective second side of the respective storage loop.Each of the first and second QFP loops may be galvanically coupled to one or more further QFP loops, the DAC may further include a second control line extending at least approximately perpendicular to the first control line, the second control line may be positioned so as to be inductively coupled to each of the first and second storage loops, the first and second QFP loops may be galvanically coupled along the first control line, the first, second, third, and fourth QFP loops may be galvanically coupled along the first control line, the DAC may further include a flux bias line communicatively coupleable to the first QFP loop, the flux bias line may comprise a QFP stage of a QFP shift register, and the flux bias line may comprise a signal line.

[0015] According to one aspect, a method of selectively programming a programmable component of a quantum processor is provided, the method including: loading a first persistent current into a first digital-to-analog converter quantum flux parametron (DAC-QFP) loop, the first DAC-QFP loop being galvanically coupled to a first digital-to-analog converter (DAC) storage loop, the first persistent current corresponding to an intended state of the first DAC storage loop; loading a second persistent current into a second DAC-QFP loop, the second DAC-QFP loop being galvanically coupled to the second DAC storage loop, the second DAC storage loop being galvanically coupled to the first DAC storage loop, the second persistent current corresponding to an intended state of the second DAC storage loop; and loading a first intervening gyroscope into the first intervening gyroscope. applying a signal to one or more control lines in communication with the first DAC-QFP loop to induce a first amount of magnetic flux in the first DAC storage loop based on a first persistent current in the first DAC-QFP loop via a Josephson junction; applying a signal to one or more control lines in communication with the second DAC-QFP loop to induce a second amount of magnetic flux in the second DAC storage loop based on a second persistent current in the second DAC-QFP loop via a second intervening Josephson junction; and transferring a flux bias to the programmable component based on a combined flux having the first amount of magnetic flux in the first DAC storage loop and the second amount of magnetic flux in the second DAC storage loop through an interface carried by the first DAC storage loop in communication with the programmable component.

[0016] According to other aspects, loading the first persistent current into the first DAC-QFP loop may include applying a current bias to a first quantum flux parametron (QFP) of a QFP shift register to provide the first current and shifting the first current through at least one first intervening QFP of the QFP shift register to reach the first DAC-QFP loop, and loading the second persistent current into the second DAC-QFP loop may include applying a current bias to a second QFP of the QFP shift register electrically isolated from the first QFP of the QFP shift register to provide the second current and shifting the first current through at least one first intervening QFP of the QFP shift register to reach the first DAC-QFP loop. and shifting a second current through at least one second intervening QFP of the QFP shift register to reach the DAC-QFP loop, and loading the persistent current into the second QFP loop may include loading a second persistent current into the first QFP loop and shifting the second persistent current into the second QFP loop through one or more intermediate QFP loops, the intermediate QFP loop being galvanically coupled to the intermediate DAC storage loop, where the first DAC storage loop, the intermediate DAC storage loop, and the second DAC storage loop are galvanically connected. Transferring the flux bias to the programmable component may include transferring the flux bias to one of a qubit, a coupler, a programming component, or a readout component.

[0017] According to one aspect, a quantum processor is provided that includes one or more programmable superconducting components; a shift register having two or more rows extending in a first direction and formed of a plurality of quantum flux parametron (QFP)-based shift register stages, each QFP-based shift register stage in each row being coupled to at least one other QFP-based shift register stage of the plurality of QFP-based shift register stages; and individual digital-to-analog converter quantum flux parametrons (DAC-QFPs) coupled to one QFP-based shift register stage in each row in the shift register, each digital-to-analog converter (DAC) storage loop being galvanically coupled to each DAC-QFP by a galvanic coupler, the galvanic coupler including a Josephson junction, each of the individual DAC storage loops being galvanically coupled along a second direction perpendicular to the first direction, each of the individual DAC storage loops being in communication with one of the one or more programmable superconducting components.

[0018] According to other aspects, the DAC-QFP may be configured as an array, power lines may extend in a second direction between the QFPs in a column extending in the first direction, global signal lines may extend perpendicular to the power lines in the first direction and along a first row of the QFPs, the DAC storage loop may have a compound Josephson junction (CJJ), and the DAC-QFP may be galvanically coupled symmetrically to both sides of the CJJ.

[0019] According to one aspect, a method for programming a target stage of a DAC is provided that includes applying a bias current to a first QFP stage, shifting the bias current through an intermediate QFP stage to the target QFP stage, and applying a current through one or more control lines to introduce a magnetic flux in the target DAC storage loop.

[0020] According to another aspect, shifting a bias current through the intermediate QFP stage to the target QFP stage and applying a current through one or more control lines to transfer magnetic flux into the target DAC storage loop includes applying a magnetic flux bias to a first Josephson junction carried by the first QFP stage, applying a magnetic flux bias to an intermediate Josephson junction carried by the intermediate QFP stage, suppressing the first Josephson junction of the first QFP stage, and loading a pulse into the target DAC storage loop through the target QFP stage, wherein applying a magnetic flux bias to the target Josephson junction of the target QFP stage, The method may include injecting a current into a first control line in communication with the AC storage loop, injecting a current into a second control line in communication with the DAC Josephson junction to increase a current through the DAC Josephson junction above a threshold so that a bias current is transferred from the target QFP stage into the galvanically coupled target DAC storage loop, removing current from the first and second control lines, suppressing a flux bias of the target QFP stage, and repeatedly loading flux into the target DAC storage loop via the target QFP stage until an intended number of flux quanta have been introduced into the target DAC storage loop.

[0021] In other embodiments, the above-described features may be combined together in any reasonable combination, as will be appreciated by those skilled in the art.

[0022] A brief description of some of the figures of the drawing In the drawings, the same reference numbers identify similar elements or acts. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes and angles of various elements are not necessarily drawn to scale, and some of these elements may be arbitrarily enlarged and positioned to improve the readability of the drawings. Furthermore, the specific shapes of the elements as drawn are not necessarily intended to convey any information regarding the actual shape of the particular elements, but may only be selected for ease of recognition in the drawings. [Brief description of the drawings]

[0023] [Figure 1] 1 is a schematic diagram of a hybrid computing system including a digital computer coupled to an analog computer in accordance with present systems, components, and methods; [Diagram 2] 1 is a schematic diagram of a portion of an example superconducting quantum processor. [Diagram 3] FIG. 1 is a schematic diagram of an implementation of a digital-to-analog converter (DAC) having a single stage. [Figure 4] FIG. 1 is a schematic diagram of one implementation of a DAC having a shift register and three stages. [Diagram 5] FIG. 1 is a schematic diagram of one implementation of a series of three DACs, each having four stages. [Figure 6A] FIG. 2 is a schematic diagram of another implementation of a DAC having four stages. [Figure 6B] FIG. 2 is a schematic diagram of an array of multiple DACs having four stages. [Figure 7] 1 is a flowchart of a method for selectively programming programmable components of a quantum processor. [Figure 8] 1 is a flowchart of a method for programming a target stage of a DAC. [Figure 9]1 is a representation of an example implementation of a quantum processor having an array of DACs programmed by a QFP shift register. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Detailed Description In the following description, certain specific details are set forth to provide a thorough understanding of various disclosed implementations. However, those skilled in the art will recognize that implementations can be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures associated with computer systems, server computers, and / or communication networks have not been shown or described in detail to avoid unnecessarily obscuring the description of implementations.

[0025] Unless the context requires otherwise, throughout this specification and the appended claims, the term "comprising" is synonymous with "including" and is inclusive or open-ended (i.e., does not exclude additional, unrecited elements or method acts).

[0026] References throughout this specification to "one implementation" or "an implementation" mean that a particular feature, structure, or characteristic described in connection with that implementation is included in at least one implementation. Thus, the appearances of the phrase "in one implementation" or "in an implementation" in various places throughout this specification are not necessarily all referring to the same implementation. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more implementations.

[0027] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. It should also be noted that the term "or" is generally utilized in its sense including "and / or" unless the context clearly dictates otherwise.

[0028] The headings and "Abstract" of the disclosure provided herein are for convenience only and do not interpret the scope or meaning of the implementations.

[0029] Example Computing System 1 illustrates a computing system 100 having a digital computer 102. The exemplary digital computer 102 includes one or more digital processors 106 that may be used to perform conventional digital processing tasks. The digital computer 102 may further include at least one system memory 122 and at least one system bus 120 that couples various system components including the system memory 122 to the one or more digital processors 106. The system memory 122 may store a set of modules 124.

[0030] The one or more digital processors 106 may be any logical processing unit or circuit (e.g., integrated circuit), such as one or more central processing units ("CPUs"), graphical processing units ("GPUs"), digital signal processors ("DSPs"), application specific integrated circuits ("ASICs"), programmable gate arrays ("FPGAs"), programmable logic controllers ("PLCs"), or the like, and / or combinations thereof.

[0031] In some implementations, the computing system 100 includes an analog computer 104, which may include one or more quantum processors 126. The quantum processor 126 may include at least one superconducting integrated circuit using the systems and methods described herein. The digital computer 102 may communicate with the analog computer 104, for example, via a controller 118. As described in more detail herein, certain operations may be performed by the analog computer 104 under the direction of the digital computer 102.

[0032] The digital computer 102 may include a user input / output subsystem 108. In some implementations, the user input / output subsystem includes one or more user input / output components, such as a display 110, a mouse 112, and / or a keyboard 114.

[0033] The system bus 120 may utilize any known bus structure or architecture, including a memory bus with a memory controller, a peripheral bus, and a local bus. The system memory 122 may include read only memory ("ROM"), static random access memory ("SRAM"), non-volatile memory such as Flash NAND, and volatile memory such as random access memory ("RAM") (not shown).

[0034] The digital computer 102 may also include other non-transitory computer or processor readable storage media or non-volatile memory 116. The non-volatile memory 116 may have various forms including a hard disk drive for reading and writing to a hard disk (e.g., a magnetic disk), an optical disk drive for reading and writing to a removable optical disk, and / or a solid-state drive (SSD) for reading and writing to a semiconductor medium (e.g., a NAND-based flash memory). The non-volatile memory 116 may communicate with one or more digital processors via a system bus 120 and may include a suitable interface or controller 118 coupled to the system bus 120. The non-volatile memory 116 may serve as long-term storage for processor or computer readable instructions, data structures, or other data (often referred to as program modules) for the digital computer 102.

[0035] Although the digital computer 102 is described as utilizing hard disks, optical disks, and / or semiconductor storage media, those skilled in the art will appreciate that other types of non-transitory and non-volatile computer readable media may be utilized. Those skilled in the art will appreciate that some computer architectures utilize non-transitory volatile memory and non-transitory non-volatile memory. For example, data in volatile memory may be cached to non-volatile memory or semiconductor disks utilizing integrated circuits to provide the non-volatile memory.

[0036] Various processor or computer readable instructions, data structures, or other data can be stored in the system memory 122. For example, the system memory 122 can store instructions for communicating with remote clients and for scheduling the use of resources, including resources on the digital computer 102 and the analog computer 104. Also, for example, the system memory 122 can store at least one of processor executable instructions or data that, when executed by the at least one processor, causes the at least one processor to execute various algorithms and / or instructions. In some implementations, the system memory 122 can store processor or computer readable computational instructions and / or data for performing pre-processing, contemporaneous processing, and post-processing on the analog computer 104. The system memory 122 can store a set of analog computer interface instructions for interacting with the analog computer 104.

[0037] Analog computer 104 may include at least one analog processor, such as quantum processor 126. Analog computer 104 may be provided in an isolated environment, such as, for example, in an isolated environment that shields the internal elements of the quantum computer from heat, magnetic fields, and other external noise. The isolated environment may include a refrigerator, such as, for example, a dilution refrigerator, operable to cryogenically cool the analog processor, for example, to a temperature below about 1 K.

[0038] Analog computer 104 may include programmable elements such as qubits, couplers, and other components. The qubits may be read out via readout control system 128. The readout results may be sent to other computer or processor readable instructions of digital computer 102. The qubits may be controlled via qubit control system 130. The qubit control system 130 may include an on-chip digital-to-analog converter (DAC) and an analog line operable to apply a bias to a target device. The couplers coupling the qubits may be controlled via coupler control system 132. The coupler control system 132 may include tuning elements such as on-chip DACs and analog lines. The qubit control system 130 and coupler control system 132 may be used to implement a quantum annealing schedule as described herein on analog processor 104. The program elements may be included in quantum processor 126 in the form of an integrated circuit. The qubits and couplers may be positioned in a layer of an integrated circuit having a first material. Other components, such as the readout control system 128, may be located in other layers of the integrated circuit comprising the second material.

[0039] Superconducting Flux Storage Components The superconducting flux storage component is also referred to in this application as a superconducting digital-to-analog converter (DAC) or flux DAC.

[0040] A quantum processor can have multiple programmable devices (also referred to herein as programmable components) for performing operations through quantum effects. The programmable devices can include qubits, couplers (which couple the qubits in a programmable manner), as well as these components. The programmable devices are programmed via signals applied to them to affect their operation, for example, a bias signal can be applied to a flux qubit to affect its magnetic flux during an operation. On-chip control circuitry can be used to selectively apply a static magnetic flux bias to the superconducting loop to achieve the control parameters.

[0041] Such signals may require conversion and / or storage before being applied to the programmable component. For example, a conventional computer may generate digital signals for a quantum processor, and those digital signals may be converted to analog form via one or more digital-to-analog converters (DACs). The converted analog signals may be applied to the programmable component. As another example, a signal (which may be digital or analog) may be received by the quantum processor at a point in time before or during an operation, and stored via a DAC until the signal is required to be applied to the programmable component at a later point in time. DACs have many uses and may be used for one or more of these purposes (i.e., conversion and / or memory) and / or for other purposes. Examples of the use of DACs for these and other purposes are described in more detail, for example, in U.S. Pat. Nos. 7,876,248 and 8,098,179.

[0042] Although the term DAC is used throughout, it should be understood that the components described may be used for a variety of purposes not necessarily limited to converting digital signals to analog signals (and in some implementations may not involve such conversion at all). For example, as discussed above, superconducting DACs may be used by quantum processors to store signals for a period of time (e.g., thereby acting as a form of memory).

[0043] Quantum Flux Parametron Quantum Flux Parametrons (QFPs) are superconducting Josephson junction devices similar in some aspects to compound RF-SQUIDs. A particular potential energy curve can be generated by a QFP device. This potential energy curve may resemble a "W" where a central peak or "barrier" is adjustable in height along with the independent depths of the two wells on either side of the central barrier. Although the term "quantum" appears in the names of QFP devices, the devices are generally operated in a conventional manner. In essence, it is conventionally believed that if the height of the central barrier is rapidly increased, the energy makeup of the system will be significantly disrupted. QFP devices, such as QFP shift registers, are further described in U.S. Pat. No. 10,528,886.

[0044] An exemplary superconducting quantum processor Figure 2 is a schematic diagram of a portion 200 of an example superconducting quantum processor according to at least one implementation. The portion 200 of the superconducting quantum processor shown in Figure 2 includes two superconducting qubits 201 and 202. Also shown is a tunable coupling (i.e., providing two-local interaction) between the qubits 201 and 202 (diagonal coupling) via coupler 210. Although the portion 200 of the quantum processor shown in Figure 2 includes only two qubits 201, 202 and one coupler 210, one skilled in the art will understand that the quantum processor 200 may include any number of qubits and any number of couplers that couple information therebetween.

[0045] Quantum processor 200 includes a number of interfaces 221-225 that are used to configure and control the state of quantum processor 200. Each of interfaces 221-225 may be implemented by a respective inductive coupling structure as shown, as part of the programming and / or development subsystems. Alternatively or additionally, interfaces 221-225 may be implemented by a galvanic coupling structure. Galvanic coupling herein refers to a coupling implemented through one or more elements (e.g., wires) that are physically shared between the coupled circuits. Galvanic coupling may also be referred to as a direct conductive connection. A direct conductive connection is formed between circuits through a supplied element, thereby providing a direct electrical connection to couple the circuits. In contrast, inductive coupling refers to a coupling implemented through the interaction of magnetic fields between the circuits without a direct electrical connection. A current through a portion of a first circuit generates a magnetic field around the first circuit, thereby inducing a current in the second circuit. In some implementations, one or more of interfaces 221-225 may be driven by one or more DACs. Such programming and / or evolution subsystems may be separate from quantum processor 200 or may be included locally (i.e., on-chip with quantum processor 200).

[0046] During operation of quantum processor 200, interfaces 221 and 224 can be used to couple flux signals into respective compound Josephson junctions (CJJs) 231 and 232 of qubits 201 and 202, respectively, thereby realizing tunable tunneling terms in the Hamiltonian function. This coupling is achieved by the off-diagonal σ x These magnetic flux signals are examples of "delocalized signals."

[0047] Similarly, interfaces 222 and 223 apply flux signals into the individual qubit loops of qubits 201 and 202, respectively, which in turn apply the h i can be used to realize the diagonal σ z Additionally, interface 225 couples the magnetic flux signal into coupler 210, thereby providing one or more J terms in the Hamiltonian function. ij can be used to realize the term (a dimensionless local field for the coupler). This coupling is the diagonal σ i z , σ j z Examples of Hamiltonian functions (and their terms) used in quantum computing are described in further detail, for example, in U.S. Patent Application Publication No. 20140344322.

[0048] Throughout this specification and the appended claims, the term "quantum processor" is used to generally describe a collection of physical qubits (e.g., qubits 201 and 202) and couplers (e.g., coupler 210). Physical qubits 201 and 202 and coupler 210 are referred to as "programmable components" of quantum processor 200, and their corresponding parameters (e.g., qubit h i Value and coupler J ij The programmable parameters (values) are referred to as the "programmable parameters" of the quantum processor. In the context of quantum processors, the term "programming subsystem" is used to generally describe the interfaces (e.g., programming interfaces 222, 223, and 225) used to apply the programmable parameters to the programmable components of quantum processor 200 and other associated control circuitry and / or instructions.

[0049] To control quantum devices (also referred to herein as programmable components), such as qubits 201, 202 and coupler 210 as described above, DACs can be used to couple magnetic flux into individual devices. These DACs can be addressed or programmed, in some implementations, using an XYZ scheme, as described in U.S. Pat. No. 10,528,886. However, this type of programming requires lines to uniquely address each DAC, and can result in the use of a large number of lines. Managing these devices generally requires control over some parameters through communication with external circuitry, i.e., from outside the processor architecture. As processor sizes increase, providing sufficient control lines can become difficult. It can therefore be beneficial to provide DACs that can be programmed using a relatively small number of lines.

[0050] As mentioned above, the programming interface of the programming subsystem can communicate with other subsystems that may be separate from the quantum processor or may be included locally on the processor. The programming subsystem can be configured to receive programming instructions in a machine language of the quantum processor and to execute the programming instructions to program the programmable components in accordance with the programming instructions. Similarly, in the context of a quantum processor, the term "evolution subsystem" generally includes interfaces (e.g., "evolution interfaces" 221 and 224) used to evolve the programmable components of the quantum processor 200 and other associated control circuitry and / or instructions. For example, the evolution subsystem can include annealing signal lines and their corresponding interfaces (221, 224) to the qubits (201, 202).

[0051] Quantum processor 200 also includes readout devices 251 and 252, where readout device 251 is associated with qubit 201 and readout device 252 is associated with qubit 202. In some implementations, such as that shown in FIG. 2, each of readout devices 251 and 252 includes a direct current superconducting quantum interference device (DC-SQUID) inductively coupled to a corresponding qubit. In the context of quantum processor 200, the term "readout subsystem" is used to generally describe readout devices 251, 252 used to read out the final states of qubits (e.g., qubits 201 and 202) within the quantum processor to generate a bit string. The readout subsystem may also include other elements, such as routing circuitry (e.g., latch elements, shift registers, or multiplexer circuitry) and / or may be configured in alternative configurations (e.g., XY-addressable array, XYZ-addressable array, etc.), any of which may include a DAC. Qubit readout can also be performed using alternative circuits such as those described in International Patent Application Publication No. WO2012064974.

[0052] 2 shows two physical qubits 201, 202, one coupler 210, and two readout devices 251, 252, a quantum processor (e.g., processor 200) may utilize any number of qubits, couplers, and / or readout devices, including a relatively large number (e.g., hundreds, thousands, or more) of qubits, couplers, and / or readout devices. Application of the teachings herein to processors having a different (e.g., relatively large) number of computational components will be readily apparent to one of ordinary skill in the art.

[0053] Examples of superconducting qubits include superconducting flux qubits, superconducting charge qubits, and the like. In superconducting flux qubits, the Josephson energy dominates or is equal to the charge energy. In charge qubits, the energy relationship is the opposite. Examples of flux qubits that can be used include radio frequency superconducting quantum interference devices (RF-SQUIDs), which include a superconducting loop interrupted by one Josephson junction, persistent current qubits, which include a superconducting loop interrupted by three Josephson junctions, and the like.

[0054] A programming interface such as 222, 223, and 225 in the example implementation of FIG. 2 can be connected to a superconducting DAC. A superconducting DAC can function as a flux memory or flux storage device and can convert a digital amount of flux to flux stored in an analog device. In some implementations, the DAC includes a loop of material that is superconducting within a predetermined temperature range, where the loop is interrupted by one or more Josephson junctions. In one implementation, the DAC includes an RF-SQUID and includes a superconducting loop interrupted by a single Josephson junction. In another implementation, the DAC includes a superconducting loop interrupted by a compound Josephson junction (CJJ). The DAC-CJJ can act as a summing element for the flux.

[0055] Storing magnetic flux in a DAC includes adding magnetic flux into the storage loop of the DAC (i.e., into the superconducting loop of the DAC) through the CJJ of the DAC. Magnetic flux can be added to the storage loop of the superconducting DAC through the CJJ by using one or more control signals or biases. Multiple magnetic flux quanta can be stored in a superconducting DAC implemented using CJJs. See, for example, Johnson MWet al. "A scalable control system for a superconducting adiabatic quantum optimization processor", arXiv:0907.3757v2, 24 March 2010, for a description of a flux DAC operable to control a superconducting device in an integrated circuit. Further details regarding programmable DAC implementations can be found in U.S. Patent Application Serial No. 16 / 098,801.

[0056] Quantum Flux Parametron Digital-to-Analog Converter Referring to FIG. 3, a superconducting integrated circuit 300 is shown with one implementation of a digital-to-analog converter (DAC) 302. It should be understood that the material of the superconducting integrated circuit 300 is generally a superconducting material, where a barrier material is present in any Josephson junctions. A superconducting material is generally superconducting below a critical temperature characteristic of a given material. The DAC 302 has a storage loop 304 galvanically coupled to a quantum flux parametron (QFP) loop 308. For purposes of clarity and to aid in distinguishing the loops, the storage loop 304 is shown with an example current path 307, and the QFP loop 308 is shown with an example current path 309. It should be understood that these paths are added only as examples, and that the current paths may change (e.g., may reverse, but only occur in one of the loops at a given time). In the implementation of FIG. 3, the storage loop 304 includes a compound Josephson junction (CJJ) and a storage inductor 305. The CJJ is formed by first and second Josephson junctions 306a and 306b that interrupt the loop 304. The circuit 300 includes a first control line 310 that crosses the storage loop 304 and a second control line 312 that extends perpendicular to the first control line 310 and is inductively coupled to the storage loop 304. As used herein, "perpendicularly" means at an angle that is approximately 90 degrees, but it should be understood that it may not be exactly 90 degrees. For example, in some implementations, the first control line 310 and the second control line 312 may extend at an angle of 90 degrees ±10 degrees relative to each other. It should also be understood that the perpendicular direction may only be within the region of the circuit 300, and the control lines may bend in a different direction away from the region of the circuit 300 and may no longer be perpendicular.

[0057] The QFP loop 308 extends from the storage loop 304 and has a body 314 interrupted by a CJJ 316 coupled to a third control line 318. When a current is introduced into the CJJ 316 by the third control line, a magnetic flux quantum can be introduced into the QFP loop 308. A CJJ, as used herein, generally includes two electrically parallel current paths, each interrupted by a Josephson junction. The first control line 310 and the second control line 312 can then have a current introduced to introduce magnetic flux into the DAC storage loop 304 based on the current in the QFP loop 308. This series of control pulses formed by the currents introduced into the signal lines can be repeated to program a selected number of magnetic flux quanta into the DAC storage loop 304. As will be further described below, the DAC storage loop 304 may be coupled to other DAC storage loops, to a programmable component, and / or to other DAC stages collectively coupled to a programmable component. In the implementation shown in FIG. 3, the QFP loop 308 is symmetrically connected to the DAC storage loop 304. The control line 310 bisects the storage loop 304 such that Josephson junctions 306a, 306b are found on both sides of the DAC storage loop 304 and the QFP loop 308 extends from a first side of the DAC storage loop 304 to a second side of the DAC storage loop 304. This symmetrical connection between the QFP loop 308 and the DAC storage loop 304 can beneficially reduce or eliminate feedback currents in the QFP loop 308 due to flux quanta stored in the DAC storage loop 304, thereby increasing the programming range. In some implementations, the current flowing inside the DAC storage loop 304 can be spread evenly through both sides of the DAC storage loop 304. This configuration can result in the currents communicating with the QFP loop 308 being equal and opposite on both sides of the DAC storage loop 304.This equal and opposite current flow may therefore cancel any effects in the QFP loop 308 as the amount of magnetic flux in the DAC storage loop 304 increases, resulting in less or no current being transferred back to the QFP loop 308.

[0058] The circuit 300 may be formed from a combination of low inductance and high inductance materials, as defined in more detail above. In some implementations, the QFP loop 308 and the DAC storage loop 304 may be low inductance materials, high inductance materials, or a combination thereof. In some implementations, the QFP loop 308 may be formed primarily from a low inductance superconducting material, while the DAC storage loop 304 may be formed primarily from a high inductance superconducting material. In some implementations, the low inductance superconducting material may be one of Ta, Nb, and Al, while the high inductance superconducting material may be one of WSi, MoN, NbN, NbTiN, and granular aluminum.

[0059] The example implementation of FIG. 4 shows a portion 400 of a quantum processor. A programmable superconducting component 402, such as a qubit or coupler, is inductively coupled to be programmed. The multiple superconducting components can be programmed as further described in connection with FIG. 5. The quantum processor 400 includes a shift register 404 having two or more rows formed from multiple QFPs (only one shown for clarity) based on shift register stages 406. Each QFP shift register stage 406 in each row is magnetically or galvanically coupled to its neighbors and extends in a first direction. Within each row of the shift register 404, one QFP based register stage 406 has each adjacent DAC-QFP 408 of the magnetically or galvanically coupled multi-stage 414 as shown in column 410. The DAC-QFP 408 is galvanically coupled to individual DAC storage loops 412 to form a multi-stage DAC 414, where the coupling between the DAC-QFP 408 and the DAC storage loops 412 includes a Josephson junction 416. As shown, the Josephson junction 416 may be a CJJ. The multi-stage DAC 414 has individual DAC storage loops 412a, 412b, 412c galvanically coupled along a second direction that is perpendicular to the first direction. As used herein, "perpendicular" refers to the general configuration of the rows of the QFP shift register 404 and the columns of the multi-stage DAC 414, and not necessarily an exact 90 degree angle. In some implementations, the angle of intersection may be 90 degrees ±10 degrees. One of the DAC storage loops, the first storage loop 412a in the implementation of FIG. 4, is in communication with one of the one or more programmable superconducting components 402.

[0060] The DAC-QFP 408 can be used in combination with a power line 418 (shown by a long dashed line for clarity) in communication with a respective DAC storage loop 412 and a global signal line 420 (shown by a short dashed line for clarity) that runs along a row of the QFP 406. In some implementations, the DAC storage loop 412 has a CJJ 416 and the power line 418 is in communication with the CJJ 416. In some implementations, the DAC-QFP 408 is symmetrically coupled to both sides of the CJJ 416. It should be understood that while the implementation of FIG. 4 shows three stages, more stages may be included for greater control precision in programming the programmable component 402. The state communicated to the DAC-QFP 408 will determine whether the corresponding DAC storage loop 412 will be programmed by a flux quantum when the global signal line 420 and the power line 418 are increased. For example, in some implementations, when the flux bias provided by the DAC-QFP 408 of an individual stage has the same polarity as the flux from the global signal line, the DAC storage loop 412 will be programmed with a flux quantum when the control line is increased. Conversely, if the DAC-QFP 408 is programmed with a flux bias having the opposite polarity, the DAC storage loop 412 will not be programmed when the signal line is increased. In some implementations, the direction of the current provided by the power line 418 can be used to determine whether a positive or negative pulse will be stored in the DAC storage loop 412 when the control line is increased.

[0061] In some implementations, the multi-stage DAC 414 can be programmed by several flux quanta provided to the respective DAC storage loops 412 to provide the intended value to be sent to the programmable component 402. Once the programmable component 402 has been programmed, it may be desirable to reset the multi-stage DAC 414. This can be done by unloading flux quanta from the respective DAC storage loops 412 by loading several pulses in the opposite sense of the loading pulse through switching the direction of the current provided by the power lines 418 and repeating a procedure similar to that described for programming the multi-stage DAC 414. For example, if a stage of the DAC is loaded with a positive flux quantum, it can be unloaded with a negative pulse and vice versa. In some implementations, such as a four-stage DAC, different stages of the DAC can be loaded with pulses in opposite directions (e.g., four stages loaded as (-4 +2 -1 0)) and therefore unloaded with pulses having the opposite direction of each stage. In other implementations, the reset can be accomplished by applying a varying signal to the global signal line 420 and / or the power line 418.

[0062] As mentioned above, the circuit 400 can be formed from a combination of low inductance and high inductance materials. In some implementations, the DAC-QFP 408 can be formed primarily from low inductance superconducting material, while the DAC storage loop 412 can be formed primarily from high inductance superconducting material. In some implementations, the links connecting adjacent QFP stages (e.g., 406 and 408) can be formed from high inductance material. In some implementations, the low inductance superconducting material can be one of Ta, Nb, and Al, while the high inductance superconducting material can be one of WSi, MoN, NbN, NbTiN, TiN, and granular aluminum.

[0063] Referring to FIG. 5, an example implementation of a portion 500 of a quantum processor having an array of multi-stage DACs is shown. FIG. 5 utilizes notation similar to that used in FIG. 4 (i.e., the two least significant digits are the same) to denote, for example, programmable superconducting component 402 and programmable superconducting component 502 as similar devices. In the implementation of FIG. 5, a QFP loop (referred to as a DAC-QFP) that is part of a QFP-DAC as described herein is configured as an array as part of multiple multi-stage DACs, allowing programming of multiple programmable superconducting components 502. The DAC-QFP 508 may have a column magnetically or galvanically coupled to a shift register as described in connection with FIG. 4, or the DAC-QFP 508 may be addressed by address lines or other control schemes. Each individual DAC-QFP 508 is magnetically or galvanically coupled to the other DAC-QFPs 508 in a row, and each DAC-QFP 508 is also galvanically coupled to an individual DAC storage loop 512. The coupling between the DAC-QFP 508 and the DAC storage loop 512 includes a Josephson junction 516, which may be a CJJ. The individual DAC storage loops 512a, 512b, 512c, 512d are connected in columns to form four-stage DACs 522a, 522b, 522c (collectively 522) in communication with the programmable component 502. For each section within a portion of the quantum processor 500, the DAC-QFPs 508 are magnetically or galvanically coupled in a first direction within the rows of the DAC-QFPs 508, and the DAC storage loops 512 are galvanically coupled in a second direction within the columns of the DAC storage loops 512. The first and second directions are perpendicular, which means approximately 90 degrees, as discussed above, but not necessarily an exact 90 degree angle.The programmable superconducting components 502 are connected to respective columns of DAC storage loops 512, which form a single four-stage DAC 522 for programming the programmable components 502. Power lines 518a, 518b, 518c (collectively 518 and shown by long dashed lines for clarity) extend in a second direction in communication with the respective DAC storage loops 512 forming the four-stage DAC 522, while a global signal line 520 (shown by short dashed lines for clarity) extends perpendicular to the power lines 518 and is inductively connected to the CJJs of the respective DAC storage loops 512 in a given row. It should be understood that the control line DAC storage loops 512 may be galvanically coupled along the power lines 518. It should further be understood that "perpendicular" as used herein means approximately a 90 degree angle, not exactly a 90 degree angle as described above. Also, it should be understood that "vertical" refers to the portion of the quantum processor 500 where the power lines 518 and global signal lines 520 cross the DAC-QFP 508 and DAC storage loops 512, and that the control lines can bend in different directions away from this portion and not be vertical in those regions. In the example implementation of FIG. 5, the global signal lines 520 are parallel to the power lines 518 at the edge of the circuit, where the global signal lines 520 bend in the opposite direction along the next row. As shown, the global signal lines 520 can reverse direction to address all DAC storage loops 512 in the array. It should be understood that in some implementations, multiple global signal lines can be used to provide a global bias signal, while in other implementations, a current provided by a single wire can provide a global flux bias signal to all of the DACs in the array.As used herein, the terms "power lines" and "global signal lines" refer to control lines that introduce current to individual components to introduce flux quanta into DAC storage loops 512 when the individual DAC storage loops 512 are selected by programming of DAC-QFP 508. As mentioned above, circuit 500 can be formed from a combination of low inductance and high inductance materials. In some implementations, it can be beneficial to have high inductance materials in the links between devices.

[0064] In some implementations, the DAC storage loop 512 has a CJJ 516, and the DAC-QFP 508 is symmetrically coupled to either side of the CJJ 516. As shown, the rows of the DAC-QFP 508 are electrically isolated from communication between each other, and the columns of the DAC storage loop 512 are electrically isolated from communication between each other. It should be understood that the portion of the quantum processor 500 is not limited to the three columns of four-stage DACs 522 shown in the implementation of FIG. 5, and each DAC-QFP 508 may have galvanic coupling to one or more additional DAC-QFP loops, to shift registers, or to other devices. It should also be understood that in some implementations, while the columns of the DAC storage loops 512 are not directly connected to each other and thus are considered to be electrically isolated from communication between each other, they may share a power line 518. For example, in one implementation, the portion 500 of the quantum processor shown in FIG. 5 may be repeated multiple times in an array. The three DACs 522 can be addressed by independent power lines 518a, 518b, 518c, respectively, and further DACs 522 can be connected in parallel such that the power line signal is applied to all third DACs 522a through power line 518a, the power line signal is applied to all third DACs 522b connected in the next DAC-QFP in the array through power line 518b, and the power line signal is applied to the remaining DACs 522c through power line 518c. It should be understood that a different number of repeated power lines, referred to as "colors," can be used in different implementations, such as four or five colors instead of the three colors described above. It should also be understood that similar addressing schemes can be applied to other implementations described herein.

[0065] DAC programming can be accomplished in a number of ways, such as the XYZ addressing described above. As the processor size increases and the number of DACs to be controlled within the processor increases accordingly, the number of lines required for programming also increases. It may be beneficial to introduce other programming schemes that require a relatively small number of control lines to allow for an increased number of devices. The DACs incorporating the QFP stages described herein may allow for DAC programming with a relatively small number of lines in a beneficial manner, and may also allow for parallel programming of multiple DACs with a relatively small number of control lines in a beneficial manner.

[0066] Referring to FIG. 6A, a superconducting integrated circuit 600a is shown with one implementation of a DAC 602. The DAC 602 includes a first stage 604 having a first storage loop 606 interrupted by a first Josephson junction 608. The first storage loop 606 carries or has an interface 610 for communicating with an external component 612, which may be a programmable device such as a qubit or a coupler. The DAC 602 includes a second stage 614 having a second storage loop 616 interrupted by a second Josephson junction 618. The second storage loop 616 is galvanically coupled to the first storage loop 606. The first Josephson junction 608 and the second Josephson junction 618 are coupled in series to a first control line 620. The superconducting integrated circuit 600a further includes first and second QFP loops 622 and 624 galvanically coupled to and extending from the respective ones of the first stage 604 and the second stage 614. In some implementations, the first and second Josephson junctions 608, 618 may be CJJs.

[0067] 6A, in some implementations, the DAC may include a third stage 626 galvanically coupled to the second stage 614 and a fourth stage 628 galvanically coupled to the third stage 626. The third and fourth stages 626, 628 have third and fourth storage loops 630, 632 interrupted by third and fourth Josephson junctions 634, 636, respectively, where the fourth and fourth Josephson junctions 634, 636 are coupled in series to the first control line 620. The third and fourth stages 626, 628 also have third and fourth QFP loops 638, 640 galvanically coupled to and extending from respective ones of the third stage 626 and the fourth stage 628. In the implementation of FIG. 6A, each QFP loop 622, 624, 638, 640 has a Josephson junction, in this case CJJs 642a, 642b, 642c, 642d.

[0068] Although the exemplary implementation of FIG. 6A is asymmetric, it should be understood that a similar circuit can be designed with two DJJs per each stage that are relatively symmetric. Additional control lines can be provided, such as flux bias line 650, Josephson junction annealing lines 652a, 652b, 642c, 652d, and trigger lines 654a, 654b, 654c, 654d. In some implementations, the QFP loops 622, 624, 638, and 640 can be formed from low inductance superconducting material, while the DAC storage loops 606, 616, 630, and 632 can be formed from high inductance superconducting material. In some implementations, the low inductance superconducting material can be one of Ta, Nb, and Al, while the high inductance superconducting material can be WSi, MoN, NbN, NbTiN, TiN, and granular aluminum. To address a particular DAC stage (604, 614, 626, 628), the persistent currents in the QFP loop (622) and the control lines in communication with the respective stages (e.g., 654a and 620 in communication with stage 604) have currents that sum positively to load a flux quantum into the respective DAC storage loop (606).

[0069] In some implementations, such as the example implementation of FIG. 6B, the superconducting integrated circuit 600b may include an array of DACs 602 in communication with a plurality of programmable components 612. In FIG. 6B, the same reference numbers used in FIG. 6A indicate the associated components. In some implementations, the plurality of DACs 602 (two shown as 602a and 602b for clarity) may be spaced apart along the first control line 620. The superconducting integrated circuit 600b may include an intervening QFP stage 656. In the example implementation of FIG. 6B, the superconducting integrated circuit 600b includes two intervening QFP stages 656 that separate the DACs 602a and 602b. Similar intervening QFP stages are found within each column 658 of the DACs 602. In other implementations, there may be no intervening QFP stages or there may be a different number of QFP stages. In some implementations, it may be beneficial to have an even number of intervening QFP stages 656 so that the direction of current flow is preserved as current is transferred between DACs 602. Each column 658 may have a single flux bias line 650 that transfers the flux that is shifted into the QFP stages of the DACs 602 and the intervening QFP stages 656.

[0070] 7 is a flow chart illustrating an example method 700 for selectively programming a programmable component of a quantum processor according to the present disclosure. The programmable component may be one of, for example, a qubit, a coupler, a programming component such as a shift register or a separate DAC in communication with a further programmable device, and a readout component such as a shift register or a readout QFP in communication with a readout line. Method 700 may be implemented by a programming system such as the system described in connection with FIG.

[0071] Method 700 includes acts 702-708, and one of ordinary skill in the art will appreciate that in alternative implementations, certain acts may be omitted and / or acts may be added. One of ordinary skill in the art will appreciate that the illustrated order of the acts is presented for illustrative purposes only and may vary in alternative embodiments.

[0072] Method 700 begins, for example, in response to the initiation of programming. At 702, a first persistent current is loaded into a first DAC-QFP loop that is galvanically coupled to the first DAC storage loop. The persistent current can be loaded by a flux bias line or a signal line or through a shift register, as described above. The persistent current corresponds to the intended state (or number of flux quanta) of the first DAC storage loop after receiving the current loaded into the first DAC-QFP loop. For example, if it is desired to load flux quanta into the individual DAC storage loop, the persistent current in the DAC-QFP loop can be in a first direction (e.g., clockwise), while if it is not desired to load flux quanta into the individual DAC storage loop, the persistent current in the DAC-QFP loop can be in a second direction (e.g., counterclockwise).

[0073] At 704, a second persistent current is loaded into the second DAC-QFP loop, which is galvanically coupled to the second DAC storage loop, which is galvanically coupled to the first DAC storage loop, and as described above, the second persistent current corresponds to an intended state of the second DAC storage loop.

[0074] In some implementations where a QFP shift register is connected to the DAC-QFP loop (see FIG. 5 for one implementation), a first persistent current is loaded into the first DAC-QFP loop by applying a current bias to a first QFP of the QFP shift register and shifting the current through at least one second intervening QFP of the QFP shift register to reach the first DAC-QFP loop. A second persistent current is also loaded into the second DAC-QFP by applying a current bias to a second QFP of the QFP shift register. The second QFP of the QFP shift register is isolated from the first QFP of the QFP shift register, and the current is shifted through at least one second intervening QFP of the QFP shift register to reach the second DAC-QFP loop. In some implementations, loading the persistent current into the second QFP loop may involve loading a second persistent current into the first QFP loop and then shifting the second persistent current into the second QFP loop. This may be accomplished through one or more intermediate QFP loops galvanically coupled to the intermediate storage loop, where the first storage loop, the intermediate storage loop, and the second storage loop are galvanically connected.

[0075] At 706, a signal is applied to one or more control lines in communication with the first DAC-QFP loop to shift a predetermined amount of magnetic flux in the first DAC storage loop based on the persistent current of the first DAC-QFP loop through the first intervening Josephson junction. For example, if the persistent current in the DAC-QFP loop was clockwise, the combined contribution of the DAC-QFP loop and the one or more control lines is sufficient to push magnetic flux through the JJ and introduce a magnetic flux quantum into the DAC storage loop. The required power level is selected so that the combined contribution of the DAC-QFP and the one or more control lines adds a magnetic flux quantum into the intervening Josephson junction when an upper threshold is exceeded. As mentioned above, in some implementations, this can be accomplished by two control lines in communication with the respective stages.

[0076] Also, in some implementations, the signal applied to one or more control lines in communication with the first DAC-QFP loop applies a signal to one or more control lines in communication with the second DAC-QFP loop to shift a predetermined amount of magnetic flux in the second DAC storage loop based on a persistent current in the second DAC-QFP loop through a second intervening Josephson junction, while in other implementations this signal may be applied in a separate act.

[0077] Loading one or more flux quanta into the DAC storage loop is also referred to in this application as programming the DAC. Programming the DAC may also include removing one or more flux quanta from the DAC storage loop. In one implementation, removing one or more flux quanta from the DAC storage loop includes inverting a signal on an address line. It should be understood that programming may require both increasing and decreasing a signal on a control line, such as an address line, to cause a flux quanta to move into the DAC storage loop.

[0078] At 708, a flux bias is transferred to the programmable component based on the combined flux in the first DAC storage loop and the second DAC storage loop through an interface carried by the first DAC storage loop in communication with the programmable component.

[0079] The method may then end, at which point it may begin again, or the method may be repeated in an iterative manner or in parallel to program multiple programmable components.

[0080] 8 is a flow chart illustrating an example method 800 for loading a pulse into a target stage of a DAC according to the present disclosure. Method 800 can be implemented by a programming system, such as the system described in connection with FIG.

[0081] Although method 800 includes acts 802-806, one skilled in the art will understand that in alternative implementations, certain acts may be omitted and / or additional acts may be added. One skilled in the art will understand that the illustrated order of the acts is presented for illustrative purposes only and may vary in alternative implementations.

[0082] The method 800 begins, for example, in response to the initiation of programming. At 802, a bias current is applied to a first QFP stage.

[0083] At 804, a bias current is shifted through the intermediate QFP stage to the target QFP stage. In some implementations, this can include applying a flux bias to a first Josephson junction carried by the first QFP stage, applying a flux bias to an intermediate Josephson junction carried by the intermediate QFP stage, and then suppressing the first Josephson junction of the first QFP stage such that the state of the first QFP stage is transferred to the intermediate QFP stage. A pulse can then be loaded through the target QFP stage into the target DAC storage loop by applying a flux bias to a target Josephson junction of the target QFP stage to replicate the state of the intermediate QFP stage in the target QFP stage.

[0084] At 806, a current is applied through one or more control lines to transfer magnetic flux into the target DAC storage loop. In some implementations, this can include introducing a current into a first control line in communication with the target DAC storage loop and introducing a current into a second control line in communication with the DAC Josephson junction to increase the current through the DAC Josephson junction above a threshold so that bias current is transferred from the target QFP stage into the galvanically coupled target DAC storage loop. The current can then be removed from the first and second control lines and the magnetic flux bias of the target QFP stage can be suppressed. With the state remaining at the intermediate QFP stage, these acts can be repeated to iteratively load pulses into the target DAC storage loop via the target QFP stage until the intended number of pulses have been introduced into the target DAC storage loop.

[0085] The method may then end, at which point it may begin again, or the method may be repeated in an iterative manner or in parallel to load multiple DAC storage loops.

[0086] In some implementations, the reversal of direction that occurs when transferring pulses between QFP stages results in the need for an odd number of QFP stages in-line to send states to the target QFP stage. The first QFP stage receives the state intended for the target QFP stage and transfers it to an intermediate QFP stage, in this case in the reverse direction. The intermediate QFP stage then transfers the state to the target QFP stage, in this case back to the original direction. As a result, an array of QFP stages can be used to program one-third of the DAC storage loops for each programming act. This can advantageously allow for parallel programming of multiple DAC storage loops in a quantum processor. Additionally, in some implementations, the QFP state can be preloaded into a shift register in communication with the array of QFP stages and the DAC storage loops.

[0087] With reference to FIG. 6A, one implementation of a method 800 in which a pulse is loaded into the third stage of the DAC 602 will be described. A bias is applied to the first QFP stage 622 through a flux bias line 650 to induce a current in the QFP loop 622. It should be understood that this bias can also be applied by a stage in the QFP shift register or through another connected QFP stage of the DAC. A signal is injected into the Josephson junction annealing line 652a and then into the Josephson junction annealing line 652b, after which the signal to line 652a is suppressed or set to zero. As a result, the current injected in the first QFP loop 622 is transferred into the second QFP loop 624. It should be understood that the direction of the current can be reversed during the transfer. A signal is then injected into the Josephson junction annealing line 652c, so that a current is injected into the third QFP loop 638 in the direction of the original signal. Then, to introduce a pulse into DAC storage loop 630, control line 620 and control line 654c are turned on to overcome the threshold of JJ 634. Then, control lines 620 and 654c can be turned off and annealing line 652c can be suppressed. To introduce another pulse, a signal can be introduced again into annealing line 652c and control lines 620 and 654c can be turned on again. This action can be repeated until the intended number of pulses have been loaded. In some implementations, loading DAC storage loop 630 destroys the state held in QFP loop 638 and thus is copied from QFP loop 624 for each state loaded into DAC storage loop 630.

[0088] With reference to FIG. 9, a representation of an example implementation of a quantum processor 900 (also referred to herein as a memory array) having an array of DACs 902 programmed by a QFP shift register 904 will be described. Each QFP-DAC component 906 is represented by a circle in the array of DACs 902 (only one is shown for clarity) and will be described herein. Power lines 908 are in communication with the QFP-DAC components and global signal lines 910 pass through the array of DACs 902. It should be understood that in some implementations, a different number of QFP-DACs 906 with a different number of stages may be used. In the example implementation of FIG. 9, a four-stage QFP-DAC 906 is shown. Data may be transferred into the memory array 904 through a data path 912, where the data is communicated horizontally into the array of QFP-DACs 902 through the QFP stages 914 of the QFP shift register. Once the QFP stages of the QFP-DAC 906 receive the data, the power lines 908 and global signal lines 910 can be increased and magnetic flux can be transmitted into selected DAC stages to program the QFP-DAC 906. This process can be repeated until all DACs are programmed. Magnetic flux can then be sent to programmable components in the quantum processor to program those components using the QFP-DAC 906. Although the QFP stages 914 and the QFP-DAC 906 are shown using similar circles, it should be understood that the QFP shift register 904 acts as a memory and transmits data horizontally into the array of DACs 902. The array of DACs 902 does not contain a separate QFP component to transmit data.Instead, the array of DACs 902 contains QFP-DACs 906, as described herein, which may advantageously allow data to be sent through the QFP stages of the QFP-DACs 906 and also allow programming into the storage loop stages of the QFP-DACs 906 based on data contained within the QFP stages of the QFP-DACs 906. In some implementations, the QFP-DACs can be programmed to address each DAC without requiring individual combinations of outer signal lines. The QFP-DACs can also be advantageously programmed in parallel, such as by addressing one-third of the DAC storage loop with each programming act.

[0089] The above-described methods, processes, or techniques may be implemented by a series of processor-readable instructions stored on one or more non-transitory processor-readable media. Some examples of the above-described methods, processes, or techniques are performed in part by specialized apparatus, such as an adiabatic quantum computer or quantum annealer or system, for programming or otherwise controlling the operation of an adiabatic quantum computer or quantum annealer, such as a computer including at least one digital processor. The above-described methods, processes, or techniques may include various acts, but those skilled in the art will understand that in alternative examples, certain acts may be omitted and / or additional acts may be added. Those skilled in the art will understand that the illustrated order of acts is shown for illustrative purposes only and may be changed in alternative examples. Some of the example acts or operations of the above-described methods, processes, or techniques are performed iteratively. Some acts of the above-described methods, processes, or techniques may be performed during each iteration, after multiple iterations, or at the end of all iterations.

[0090] The above description of illustrated implementations, including those described in the "Summary", is not intended to be exhaustive or to limit the implementations to the precise forms disclosed. While specific implementations and examples are described herein for illustrative purposes, those skilled in the art will recognize that various equivalent modifications can be made without departing from the spirit and scope of the disclosure. The teachings of the various implementations provided herein may also be applied to other methods of quantum operations, not necessarily the exemplary methods for quantum operations generally described above.

[0091] The various implementations described above can be combined to provide further implementations. All commonly assigned U.S. patent application publications, U.S. patent applications, foreign patents, and foreign patent applications cited herein and / or listed within the Applicant Data Sheets, including, without limitation, U.S. Patent Application Serial No. 16 / 098,801, 63 / 136,987, U.S. Patent Nos. 7,135,701, 7,418,283, 7,533,068, 7,876,248, 8,008,942, 8,098,179, 8,195,596, 8,190,548, 8,421,053, 10,528,886, and International Patent Application Publication No. 2012064974, are hereby incorporated by reference in their entirety.

[0092] These and other changes can be made to the implementations in light of the above description. Generally, in the appended claims, the terms used should not be construed to limit the claims to the specific implementations disclosed in the specification and claims, but should be construed to include all possible implementations, with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by this disclosure.

Claims

1. 1. A digital-to-analog converter (DAC), comprising: a first stage having a first storage loop interrupted by a first Josephson junction, said first storage loop having an interface operable to communicate with an external component; a second stage having a second storage loop interrupted by a second Josephson junction, the second storage loop being galvanically coupled to the first storage loop, the first Josephson junction and the second Josephson junction being coupled in series to a first control line; a first quantum flux parametron (QFP) loop and a second quantum QFP loop, the first and second QFP loops being galvanically coupled to and extending from respective ones of the first stage and the second stage; A DAC having

2. a third stage galvanically coupled to the second stage and a fourth stage galvanically coupled to the third stage, the third and fourth stages having third and fourth storage loops interrupted by third and fourth Josephson junctions, respectively, the third and fourth Josephson junctions coupled in series to the first control line; a third QFP loop and a fourth QFP loop, the third QFP loop and the fourth QFP loop being galvanically coupled to and extending from respective ones of the third stage and the fourth stage; The DAC of claim 1 further comprising:

3. 3. A DAC as claimed in claim 1 or 2, wherein each QFP loop comprises an individual Josephson junction.

4. 4. The DAC of claim 3, wherein the individual Josephson junctions of each QFP loop comprise individual compound Josephson junctions.

5. 2. The DAC of claim 1, wherein the first and second Josephson junctions each comprise a compound Josephson junction.

6. 2. The DAC of claim 1, wherein the first and second QFP loops are symmetrically connected to the respective ones of the first stage and the second stage, and the first QFP loop is isolated from the second QFP loop.

7. the first control line bisects each of the first storage loop and the second storage loop; each of the first storage loop and the second storage loop having a respective Josephson junction on each of a respective first side and a respective second side of the respective storage loop; 7. The DAC of claim 6, wherein each of the first and second QFP loops is coupled to extend from the respective first side of the respective storage loop to the respective second side of the respective storage loop.

8. 7. The DAC of claim 6, wherein each of the first and second QFP loops is galvanically coupled to one or more further QFP loops.

9. 2. The DAC of claim 1, further comprising a second control line extending at least approximately perpendicular to the first control line, the second control line positioned so as to be inductively coupled to each of the first storage loop and the second storage loop.

10. The DAC of claim 1 , wherein the first and second QFP loops are galvanically coupled along the first control line.

11. The DAC of claim 2 , wherein the first, second, third, and fourth QFP loops are galvanically coupled along the first control line.

12. 12. The DAC of claim 10 or 11, further comprising a flux bias line communicatively coupleable to the first QFP loop.

13. The DAC of claim 12 , wherein the flux bias line comprises a QFP stage of a QFP shift register.

14. The DAC of claim 12 wherein the flux bias line comprises a signal line.

15. 1. A method of selectively programming programmable components of a quantum processor, comprising: loading a first persistent current into a first digital-to-analog converter quantum flux parametron (DAC-QFP) loop, the first DAC-QFP loop being galvanically coupled to a first digital-to-analog converter (DAC) storage loop, the first persistent current corresponding to an intended state of the first DAC storage loop; loading a second persistent current into a second DAC-QFP loop, the second DAC-QFP loop being galvanically coupled to a second DAC storage loop, the second DAC storage loop being galvanically coupled to the first DAC storage loop, the second persistent current corresponding to an intended state of the second DAC storage loop; applying a signal to one or more control lines in communication with the first DAC-QFP loop to induce a first amount of magnetic flux in the first DAC storage loop based on the first persistent current of the first DAC-QFP loop through a first intervening Josephson junction; applying a signal to one or more control lines in communication with the second DAC-QFP loop to induce a second amount of magnetic flux in the second DAC storage loop based on the second persistent current of the second DAC-QFP loop through a second intervening Josephson junction; transferring a flux bias to the programmable component based on a combined flux having the first amount of flux in the first DAC storage loop and the second amount of flux in the second DAC storage loop through an interface carried by the first DAC storage loop in communication with the programmable component; The method according to claim 1,

16. 16. The method of claim 15, wherein loading a first persistent current into a first DAC-QFP loop comprises applying a current bias to a first quantum flux parametron (QFP) of a QFP shift register to provide a first current, and shifting the first current through at least one first intervening QFP of the QFP shift register to reach the first DAC-QFP loop.

17. 17. The method of claim 16, wherein loading a second persistent current into a second DAC-QFP loop comprises applying a current bias to a second QFP of the QFP shift register that is electrically isolated from the first QFP of the QFP shift register to provide a second current, and shifting the second current through at least one second intervening QFP of the QFP shift register to reach the second DAC-QFP loop.

18. Loading a persistent current into the second QFP loop loading the second persistent current into the first QFP loop; shifting the second persistent current through one or more intermediate QFP loops into the second QFP loop, the intermediate QFP loops being galvanically coupled to an intermediate DAC storage loop, the first DAC storage loop, the intermediate DAC storage loop, and the second DAC storage loop being galvanically connected; 16. The method of claim 15, having the following structure:

19. 16. The method of claim 15, wherein transferring a flux bias to the programmable component comprises transferring a flux bias to one of a qubit, a coupler, a programming component, or a readout component.

20. 1. A quantum processor, comprising: one or more programmable superconducting components; a shift register having two or more rows extending in a first direction and formed from a plurality of quantum flux parametron (QFP)-based shift register stages, each QFP-based shift register stage in each row being coupled to at least one other QFP-based shift register stage of the plurality of QFP-based shift register stages; an individual digital-to-analog converter quantum flux parametron (DAC-QFP) coupled to one QFP-based shift register stage in each row of the shift register; individual digital-to-analog converter (DAC) storage loops galvanically coupled to respective DAC-QFPs by galvanic couplers, the galvanic couplers including Josephson junctions; each of the individual DAC storage loops is galvanically coupled along a second direction perpendicular to the first direction; one of the individual DAC storage loops is in communication with one of the one or more programmable superconducting components; a digital-to-analog converter (DAC) storage loop; A quantum processor having

21. The quantum processor of claim 20 , wherein the DAC-QFPs are arranged in an array.

22. 22. A quantum processor as claimed in claim 20 or 21, wherein power lines extend in the second direction between QFPs in columns extending along the first direction.

23. 23. The quantum processor of claim 22, wherein a global signal line extends perpendicular to the power lines in the first direction and along a first row of the QFP.

24. 21. The quantum processor of claim 20, wherein the DAC storage loop comprises a compound Josephson junction (CJJ), and the DAC-QFP is galvanically coupled symmetrically to either side of the CJJ.

25. 1. A method for programming a target stage of a DAC, comprising the steps of: applying a bias current to a first QFP stage; shifting the bias current through an intermediate QFP stage to a target QFP stage; applying a current through one or more control lines to induce a magnetic flux in a target DAC storage loop; The method according to claim 1,

26. applying current through one or more control lines to shift the bias current through an intermediate QFP stage to a target QFP stage and transfer magnetic flux into a target DAC storage loop; applying a flux bias to a first Josephson junction carried by the first QFP stage; applying a flux bias to an intermediate Josephson junction carried by the intermediate QFP stage; suppressing the first Josephson junction of the first QFP stage; loading a pulse into the target DAC storage loop via the target QFP stage; applying a magnetic flux bias to a target Josephson junction of the target QFP stage; injecting a current into a first control line in communication with the target DAC storage loop; injecting a current into a second control line in communication with a DAC Josephson junction to increase the current through the DAC Josephson junction above a threshold so that the bias current is transferred from the target QFP stage into a galvanically coupled target DAC storage loop; removing the current from the first and second control lines; suppressing the flux bias of the target QFP stage; and repeatedly loading flux into the target DAC storage loop through the target QFP stage until an intended number of flux quanta have been introduced into the target DAC storage loop; 26. The method of claim 25, having the following structure: