ASSEMBLY USED FOR EMBEDDING INTEGRATED CIRCUIT ASSEMBLY, ITS USE AND MANUFACTURING METHOD - Patent application

Abstract

Assemblies and laminates for use in the manufacture of integrated circuits and methods of making and using same are described, the assemblies may include closely packed components held in place by a release layer or a vacuum applied to a porous substrate, and at least one potting material deposited to encapsulate the components while leaving uncoated sides of the components, including pads, thereby forming a laminate of the components and the potting material.

Description

[Technical field]

[0001] INCORPORATION BY REFERENCE TO PRIORITY APPLICATIONS Any application in which a foreign or domestic priority claim is identified in an Application Data Sheet or Request filed with this application is incorporated by reference herein under 37 CFR § 1.57 and PCT Rules 4.18 and 20.6. U.S. Provisional Application No. 63 / 169,658, filed April 1, 2021, is incorporated by reference herein in its entirety.

[0002] The present invention is directed to forming assemblies of microelectronic components. [Background technology]

[0003] Components such as packaged integrated circuits, capacitors, resistors, and inductors are typically arranged on a printed circuit board ("PCB"). The printed circuit board has multiple layers of preformed traces that terminate in landing pads, with each layer being connected to the components by solder. Typically, the solder balls or bumps on the input / output ("I / O") terminals of an integrated circuit ("IC") package are aligned and placed onto solder paste printed on the PCB. The assembly is then passed through an oven, called a reflow oven, where the solder melts and the joints are formed. Passive components have relatively large metal plated terminals that are also aligned and placed onto screen printed solder paste patterns on the PCB.

[0004] This method has several drawbacks: The assembly must be heated to a temperature of about 250-260°C to melt the solder (e.g., solder such as "SAC" with a typical composition of 96.5% tin (Sn), 3% silver (Ag), and 0.5% copper (Cu)), and then temperatures above 220°C must be applied for a minute or more to allow the solder to flow freely over the pads. As the board cools, severe stresses tend to develop due to the large differences in the coefficients of thermal expansion (CTE) of the various materials (especially the solder, the polymer in the PCB, copper (Cu), and silicon (Si)). At near ambient temperatures (which can be substantially higher above the glass transition temperature), the CTE is 2.7 ppm / °C for silicon (Si), 17 ppm / °C for copper (Cu), about 23 ppm / °C for SAC, about 14-16 ppm / °C for FR4 (the name for a series of silica-filled epoxy composites used in PCB construction), and about 15-30+ ppm / °C for underfill polymers and / or various epoxies. These stresses can and often do cause failure of the circuit by fracture of solder joints and delamination of solder from component (e.g., IC) pads. Further opportunities for failure arise during thermal cycling during use. For example, heat generation during operation can raise the temperature of an IC to 85°C or higher.

[0005] Therefore, architectures and manufacturing methods that do not mitigate such shortcomings and failures may be beneficial. Summary of the Invention

[0006] For purposes of summarizing the disclosure and the advantages achieved over the prior art, certain objects and advantages of the disclosure are described herein. Not all such objects or advantages may be achieved in any particular embodiment. Thus, for example, one of ordinary skill in the art may realize that the invention achieves all of the objects or advantages taught herein without necessarily achieving other objects or advantages that may be taught or suggested herein. It will be recognized that the present invention may be embodied or carried out in a manner to achieve or optimize any one advantage or group of advantages.

[0007] In one aspect, an assembly for use in integrated circuit manufacturing is disclosed that includes a substrate, a release layer disposed on the substrate, a plurality of components disposed on the release layer, each of the plurality of components having an active surface in contact with the release layer, and a potting material layer encapsulating the plurality of components.

[0008] In some embodiments, each of the active surfaces of the component is substantially free of contact with the embedment material. In some embodiments, the embedment material layer comprises a plurality of embedment material sublayers. In some embodiments, the embedment material layer comprises an amalgam. In some embodiments, the amalgam is a low CTE amalgam having a coefficient of thermal expansion (CTE) of about -5 ppm / °C to about 5 ppm / °C. In some embodiments, the amalgam comprises a matrix metal, an alloying metal, and a low CTE material. In some embodiments, the matrix metal comprises gallium (Ga). In some embodiments, the alloying metal is selected from the group consisting of copper (Cu), nickel (Ni), silver (Ag), cerium (Ce), and combinations thereof. In some embodiments, the low CTE material is selected from the group consisting of ZrW2O8 (zirconium tungstate), HfW2O8, Sc2W3O 12 , and combinations thereof. In some embodiments, the amalgam further comprises an element selected from the group consisting of an additional low CTE material, a passivation material, a liquid, a reducing agent, and combinations thereof. In some embodiments, the release layer comprises an undercut region located between the release layer and at least one component of the plurality of components. In some embodiments, the undercut region comprises a deposition material. In some embodiments, the substrate has pores.

[0009] In another aspect, a method of manufacturing the assembly is described, the method including depositing a plurality of components on a release layer, the release layer being disposed on a substrate, and encapsulating the plurality of components with a layer of embedding material.

[0010] In some embodiments, encasing the plurality of components with the layer of potting material is performed by spraying.

[0011] In another aspect, a method of integrating an assembly into an integrated circuit is described, the method including separating a release layer from a plurality of components encapsulated by a layer of embedded material of the assembly to form a stack, and depositing an interconnect material onto each of the exposed surfaces of the plurality of components to form a wired stack.

[0012] In some embodiments, the method further comprises placing the wired stack within a device and electrically connecting the wired stack to the device.

[0013] In another aspect, a laminate for integration into a circuit device is described, the laminate including a plurality of components, each component including a plurality of encapsulating surfaces and an exposed surface, and an embedding material encapsulating the plurality of encapsulating surfaces of the plurality of components.

[0014] In some embodiments, each of the exposed surfaces comprises a pad. In some embodiments, each of the exposed surfaces are substantially coplanar with one another. In some embodiments, the stack further comprises an interconnect material disposed on each of the exposed surfaces. In some embodiments, the potting material comprises an amalgam. In some embodiments, the potting material comprises a porcelain amalgam. In embodiments, the amalgam includes a matrix metal, an alloying metal, and a low CTE material, hi some embodiments, the amalgam is a low CTE amalgam having a coefficient of thermal expansion (CTE) of about -5 ppm / °C to about 5 ppm / °C. [Brief description of the drawings]

[0015] These and other features, aspects, and advantages of the present disclosure will be described with reference to drawings of specific embodiments, which are intended to illustrate particular embodiments and are not intended to limit the invention.

[0016] [Figure 1] FIG. 1 is a line graph showing the hardening reaction rate of gallium amalgam at various temperatures. [Diagram 2] FIG. 2 illustrates a nebulizer system and method of use for spray deposition of amalgams. [Diagram 3] FIG. 3 illustrates a nebulizer that may be used for spray deposition of amalgam. [Figure 4] FIG. 4 illustrates an assembly with potting material encapsulating components, according to some embodiments. [Diagram 5] FIG. 5 illustrates an assembly with multiple potting materials encapsulating components, according to some embodiments. [Figure 6] FIG. 6 illustrates an assembly with potting material deposited in the undercut area beneath a component, according to some embodiments. [Figure 7] FIG. 7 illustrates an assembly with a component and potting material deposited on a porous substrate with a vacuum applied to the porous substrate, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Although specific embodiments and examples are described below, those skilled in the art will recognize that the invention extends beyond the specifically disclosed embodiments and / or uses, and obvious modifications and equivalents thereof, and therefore it is not intended that the scope of the invention disclosed herein should be limited by any specific embodiments described below.

[0018] Assemblies and laminates including components, as well as methods of their use and manufacture, are provided. The assemblies may include closely packed components held in place by a vacuum applied to a release layer or porous substrate, and at least one embedding material deposited to encapsulate the components while leaving the sides of the components, including the pads, uncoated, thereby forming a laminate of the components and the embedding material. Once the laminate is formed, it may be separated from the substrate and release layer for further processing, such as adding interconnects and / or integrating into a device. The embedding material may be selected to have favorable CTE, electrically insulating / conductive, and / or thermally conductive properties. Such assemblies may also include deposited materials that insulate one component from another.

[0019] Placing components on a pre-routed PCB with landing pads sized for screen printing of solder is relatively difficult to print at resolutions below about 50 μm. Furthermore, such processes, using traces typically patterned from rolled copper foil (e.g., 17 μm or 35 μm thick), typically result in separation of I / O terminals between components of at least 1 millimeter. Even when chip-scale packages (CSPs) are used, where the package is up to 1.3 times larger than the bare die, the separation of the nearest components (e.g., bypass capacitors) from the I / O transistor terminals is often very small. The distance between the terminals of two ICs is likely to be at least 1 mm. More typically, the distance between the terminals of two ICs can be several centimeters. These separation distances between components come with unwanted inductance near the ICs, as well as resistive losses.

[0020] Additionally, the size of the interconnects may be affected by the patterning technique used. Methods used to pattern copper (Cu) layers that utilize relatively large aspect ratios typically force the traces to be wider than they are tall, forcing interconnect traces to be tens of microns wide (e.g., often at least a few thousandths of an inch or more) in width in order to achieve satisfactory shapes with isotropic wet etching. Such interconnect limitations increase areal density and therefore the number of interconnect layers required.

[0021] In addition to being relatively large laterally, the resulting structures are thick and rigid (e.g., PCBs are typically about 1 mm thick, while packaged ICs are about 0.5 mm or thicker), and heat dissipation through the IC packaging material and PCB is relatively poor due to the use of organic polymers with thermal conductivity on the order of 0.01% of that of silicon (Si).

[0022] Similar problems occur in the process of packaging integrated circuits. Traditionally, after singulation of a processed wafer, a bare die (Si) is placed on a package substrate by a pick-and-place machine. The package substrate, like a PCB, may have pre-formed traces to connect the IC's I / O pads to the package's I / O pads, which are typically larger and more widely spaced than the IC's I / O pads. After forming the interconnects (e.g., by solder reflow, wire bonding, or another technique), the die and its substrate and traces may be encapsulated in a protective polymer by injection molding. These processes have many of the same problems, such as mismatched CTE of materials and excess length of interconnects.

[0023] Attempts to solve some of these problems include the use of reconfigured wafers, where silicon dice from various source wafers are placed on a temporary substrate using a release layer type adhesive and embedded in an epoxy molding compound in wafer form. Such "reconfigured wafers" are then peeled off the substrate and further processed to add interconnects before forming the final packaged multi-die product. Several variations of this concept have been created, including those by STATSChipPAC, Amkor, ASE, and others. However, epoxy packages still have a large CTE mismatch, making the structure susceptible to significant warpage due to these factors. Heat removal is also an issue. Packaged multi-die systems must be placed on a PCB along with other packaged ICs and components, creating similar problems to those discussed above.

[0024] A desirable architecture is one in which all ICs and other components required for the circuit, regardless of their size, are located as close together as possible in exposed (bare) form (e.g., preferably with a few μm or less spacing between them), and are surrounded on all but one surface (e.g., the bottom surface) by a thermally conductive embedding medium or material whose CTE is similar to silicon (Si) and whose surface is flush with the IC. If the IC is thin (e.g., less than 50 μm), the product will be thin and, in some embodiments, flexible. Such thinness can facilitate the creation of a continuous embedding or encapsulation layer, since it is difficult to uniformly flow a solidifiable material in a space that is a few μm wide and 250 μm high. Thinness also minimizes stress normal to the IC, in part due to the mismatch in the CTE of the materials, and allows efficient heat removal through a thin yet highly thermally conductive embedding medium.

[0025] When ICs are placed within micrometers of each other, the final interconnects within each IC Interconnection traces of approximately the same size as the layers may be advantageously formed by fabricating them directly on the flat surface of the embedding medium. Two or more such ICs, or an IC with several relatively small passive components, effectively function as one large IC. Such architectures are difficult or impossible to fabricate using lithography due to yield losses and size limitations of lithography equipment. Depending on the specific electrical requirements, the width and thickness of a trace connecting two I / O pads that are not directly adjacent may be larger than one connecting adjacent pads. However, such a trace for two I / O pads is likely still relatively smaller than a typical PCB trace due to the short distance over which the current must flow. For example, the interconnects on the top layer of an IC are on the order of about 2 μm thick and 4-5 μm wide, so that the traces between these components are more than an order of magnitude smaller than in conventional techniques, allowing for more compact routing, improved electrical performance due to shorter traces, and further savings in circuit area.

[0026] Once the required number of interconnect layers (separated by dielectric layers) have been fabricated, the stack is encapsulated with one or more protective layers to make it ready for use in a product. These layers are typically selected according to specific requirements and may be formed using materials known in the art, such as metals (e.g., aluminum or copper), ceramics (e.g., oxides and nitrides), polyimides, polyesters (polyethylene or polyethylene terephthalate), polyurethanes, etc. Connections to other components may be made, as needed, by metal traces that terminate at the edges of the substrate and are not covered in the final package, or through vias formed through the protective encapsulation. Since, according to the present invention, a complete functional circuit may be fabricated in one unit, relatively few I / O connections are likely to be required.

[0027] Such structures can be used for any degree of integration, from circuits traditionally contained within a single chip to circuits that currently occupy large PCBs. One application is so-called "multi-die packages" or "system-in-package" devices, which may contain several or more IC dies in a single package, but are still intended to be placed on a traditional PCB with other chips to form a final functional system. Another application is for relatively large and complex chips, such as high-end microprocessors, field programmable gate arrays, etc. These may be fabricated from "chiplets," which are subunits of a functional IC and therefore do not function on their own, and are appropriately combined to form a self-supporting circuit. For example, such subunits could be elements of a microprocessor block diagram (e.g., cores, I / O sections, direct memory access ("DMA") controllers, timing sections, etc.). Advantages of such architectures include the ability to easily upgrade a system with improvements to specific subsystems without creating completely new masks for the entire chip, the ability to rapidly design new systems, and / or the ability to reduce power consumption and signal degradation due to long interconnect traces.

[0028] In some embodiments, an embedding material fluid can be coated onto a set of components disposed on a temporary release layer, such that the fluid penetrates into the micron-scale gaps between the components and cures at low temperature into a solid (e.g., pliable-solid) embedding material, encapsulating the components. The fluid and solid compositions can be selected to have thermal conductivity and CTE that are comparable or nearly matched to silicon, and can be either conductive or insulating.

[0029] Release layers and methods of use thereof are discussed in U.S. Patent Nos. 6,946,178 and 7,141,348, which are incorporated herein by reference for all purposes. A trigger process may be used to separate the components from the release layer. As described in U.S. Patent No. 6,946,178, the trigger process includes the step of releasing the release layer in a single step. The process includes exposing the release layer to heat and light to degrade the release layer. Irradiation with light (e.g., actinic light) can be used to selectively activate the release layer compound (e.g., polymer) under the component that the user wants to transfer while leaving other components on the same substrate inactive. Heating the release layer compound (also called a digital release material (e.g., digital release adhesive ("DRA")) to an appropriate temperature (e.g., less than about 150°C) can evaporate the release layer and release the component while leaving the inactive device attached to the donor substrate. By this method, the parts may be held in close position by the release layer while the embedding material encapsulates the component on all sides except the side facing the release layer, and the release layer may then be decomposed to transfer the assembly and / or expose the unencapsulated side of the component for application of interconnects. In some embodiments, transfer methods include photopolymer component assembly ("PCA") and light-induced forward transfer ("LIFT").

[0030] In some embodiments, the potting material comprises an amalgam mixture of gallium and particles of another metal (e.g., copper and / or nickel). Such an amalgam may be a fluid when first mixed, but forms a high melting point solid as the elements interdiffuse. For example, an alloy of about 65% gallium (Ga), 30% copper (Cu), and 5% nickel (Ni) melts above 500° C., but solidifies from the fluid mixture at ambient temperatures (e.g., about 25° C. or about 30° C.). Such amalgams are described, for example, in U.S. Pat. No. 5,053,195 and in “Amalgams for Improved Electronics Interconnection” (IEEE Micro, pp. 46-58, 1993), which are incorporated by reference in their entireties for all purposes.

[0031] Some fluid amalgams may take several days to fully harden without heating. Figure 1 shows the hardening kinetics of gallium amalgam (5% nickel (Ni), 30% copper (Cu)). However, gallium amalgams with hardening results similar to those shown in Figure 1 have typically utilized powders with average particle sizes in the range of microns to tens of microns. Although there is published evidence that liquid metal atoms diffuse relatively quickly along grain boundaries in amalgams (e.g., T. Okabe and RJ Mitchell, in “Setting Reactions In Dental Amalgam Part 2. The Kinetics Of Amalgamation”, Critical Reviews of Oral and Biological Medicine, vol. 7, pp. 23-35), it has been demonstrated that smaller particles result in more uniform mixing (e.g., AB Shubin, et al. “The Diffusion of Gallium into Copper-Tin Alloy Particles”, Defect and Diffusion Forum Vols. 283-286 (2009) pp 238-242). Such small particles have not been used in some cases because the mixture tends to harden quickly and is difficult to transfer from the mortar and pestle or from the amalgamator capsule in which these amalgam precursors were formed, making them difficult to handle.

[0032] To avoid premature curing and to allow for the use of submicron particles (e.g., nanoscale particles), in some embodiments, the particles may be mixed in an ultrasonic mixer or jetting device. In ultrasonic spray coaters (e.g., coaters manufactured by Sono-tek Corporation, Milton, NY), the liquid feedstock is converted to an aerosol by an ultrasonic atomizer just prior to coating. FIG. 2 shows such a spray coating apparatus (i.e., nebulizer) for spray deposition as described in U.S. Pat. No. 6,358,567, which is incorporated by reference in its entirety for all purposes. The system includes a liquid 2 pumped from a liquid pump 4 to an ultrasonic transducer 6, which is then pumped to an ultrasonic transducer 7, which is then pumped to an ultrasonic transducer 8. An acoustic transducer 6 is used to create vibrations in the liquid to break the atomized liquid into small (e.g., sub-micron sized) droplets of aerosol that are sprayed onto a substrate 8 that is placed on the heater. There are many alternatives for creating an aerosol spray of multiple particle types. In some embodiments, the liquid may include metal particles present in a mixture (e.g., solution). For example, most metals (e.g., copper (Cu) and nickel (Ni)) are less reactive with each other than they are with themselves. Thus, metal particles can be combined in a single solution or dispersion to deliver the desired aerosol particle stream if they are stabilized against agglomeration. In some embodiments, the liquid includes a passivation material. In some embodiments, the metal particles include a passivation layer.

[0033] In some embodiments, the different liquid streams may be combined as they enter the nebulizer to minimize the time that different particles are exposed to each other. FIG. 3 shows a schematic of a commercially available nebulizer 300 from Sono-Tek Corporation in which two input streams are combined. The nebulizer 300 includes a Liquid A feed channel 302 with a microbore tube 304 and a Liquid B feed channel 306 that surrounds the Liquid A feed channel 302 and the microbore tube 304 and is contained within a housing 314. At the distal end of the nebulizer 300, Liquid A 306 and Liquid B 310 are combined at an atomizing surface 312 and sprayed out of the nebulizer 300. In some embodiments, a gas stream may be used to mix the aerosol particle streams from the separate liquid streams toward each other. Such shaped streams have been used, for example, by Sono-tek in some spray coating nozzles, and some aspects of shaped streams are disclosed in U.S. Patent Application Publication No. 2010 / 0078496, which is incorporated by reference in its entirety. Other jetting systems, such as those manufactured by Optomec (Albuquerque, NM), nScrypt (Orlando, FL), and others, may be used to form a stream of nanoparticles for mixing and deposition. In some embodiments, the fluids or liquids may include different amounts of solvents. In some embodiments, the solvent may be a low boiling point solvent so that it evaporates quickly upon deposition from the surface. In some embodiments, the solvent may help to generate a uniform, densely packed distribution of particles on the deposited surface. In some embodiments, when the droplet speed in such systems is on the order of a few, tens, or hundreds of m / s (e.g., 1-900 m / s), the distance between the dispenser tip and the substrate is on the order of a few millimeters, and the movement takes at most a few milliseconds, allowing the use of relatively small metal particles without hardening the amalgam formed prior to deposition.

[0034] Metal (e.g., gallium) nanoparticles can be synthesized in a variety of ways. One example of a method for synthesizing gallium nanoparticles is described in MF Melen'ndrez, et al. (The Journal of Colloid and Interface Science, vol. 346, pp. 279-287 (2010)), which is incorporated by reference in its entirety for all purposes. The melting point of gallium (Ga) is about 29°C, so the particles can be maintained in solid form or delivered as a liquid. In some embodiments, gallium (Ga) can be mixed with the nanoparticle metal by an ultrasonic nebulizer as described herein, which allows deposition within milliseconds after mixing. In some embodiments, alternating thin layers of gallium (Ga) and other nanoparticles can be deposited. In some embodiments, the resulting film of alternating thin layers of gallium (Ga) and other nanoparticles is heated to melt the gallium (Ga) and promote the formation of a uniform distribution of particles within the fluid matrix or interstitial fluid.

[0035] In some embodiments, the metal nanoparticles are stabilized against agglomeration because many bare metal surfaces are reactive and tend to adhere to other similar surfaces. Examples of thin, low-temperature removable passivation coatings are known and commercially available. For example, copper (Cu) passivation coatings are available in Passivating coatings are manufactured by Zerovalent NanoMetals, Inc., Rochester, NY, or the outer surface of the metal particles may be oxidized to form a passivating coating. In some embodiments, a reducing agent may be used to remove oxides formed on the metal particle surface. In some embodiments, a forming gas (e.g., 4% hydrogen (H2) in nitrogen (N2) and / or formic acid) may be used in the gas stream of the application device (e.g., nebulizer) or applied to the deposition surface in a separate stream.

[0036] Although an ultrasonic aerosol generator and associated spray deposition have been described, other methods of forming and depositing nanoparticle mixtures may be utilized. For example, suitable passivation of the particle surface may be achieved by the formation of oxides and / or the attachment of relatively labile organic ligands. In some embodiments, a solution or suspension of relatively non-reactive particles may be mixed with a solution or suspension of gallium (Ga) particles in an apparatus (e.g., a rapid mixer) and then deposited by one of a variety of techniques (e.g., spray coating, slot-die (i.e., meniscus) coating, and ultrasonic coating, as well as jetting under pressure (e.g., inkjet printing)). The protective passivation may be removed by heat, chemical treatment (e.g., forming gas, formic acid, etc.), and / or photolysis.

[0037] Although FIG. 1 shows that the high melting point solid can be formed without heating the object above ambient temperature (about 25° C.), it may be advantageous to heat the amalgam mixture (e.g., to about 85° C. or 100° C.) to complete the hardening more quickly. Such temperatures are often experienced by electronic products as a result of normal operation, and therefore deviations from these values ​​may occur in the circuit anyway. In some embodiments, the CTE of the amalgam is matched or substantially matched to the circuit material (e.g., silicon (Si)) to mitigate or prevent these deviations from causing damage to typical architectures.

[0038] In some embodiments, a low CTE amalgam is used. In some embodiments, the amalgam (e.g., low CTE amalgam) comprises a matrix metal and an alloying metal. In some embodiments, the amalgam (e.g., low CTE amalgam) further comprises a low CTE material. In some embodiments, the amalgam (e.g., low CTE amalgam) comprises a matrix metal in an amount of net, about, at least, or at least about 40 wt%, 45 wt%, 50 wt%, 55 wt%, 60 wt%, 65 wt%, 70 wt%, 75 wt%, 80 wt%, 85 wt%, 90 wt%, 92 wt%, or 95 wt%, or any range of values ​​therebetween. In some embodiments, the matrix metal comprises gallium (Ga). In some embodiments, the alloying metal is selected from copper (Cu), nickel (Ni), silver (Ag), cerium (Ce), and combinations thereof. In some embodiments, the low CTE material is ZrW2O8 (zirconium tungstate), HfW2O8, and / or Sc2W3O 12 In some embodiments, the low CTE amalgam further comprises an additional low CTE material. In some embodiments, the additional low CTE material is selected from silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), silicon (Si), non-stoichiometric versions thereof, and combinations thereof. In some embodiments, the amalgam (e.g., low CTE amalgam) further comprises a passivation material. In some embodiments, the amalgam (e.g., low CTE amalgam) further comprises a liquid (e.g., a solvent). In some embodiments, the liquid is a low viscosity liquid. In some embodiments, the amalgam (e.g., low CTE amalgam) further comprises a reducing agent.

[0039] In some embodiments, the CTE of the amalgam (e.g., gallium (Ga) amalgam) is about 15-20 ppm / °C, and may vary depending on the specific composition of the amalgam. In some embodiments, lower CTE values ​​may be desirable. Depending on the material, , the CTE is very close to zero (i.e., less than that of silicon (Si)), and in some cases may even be negative. For example, silicon dioxide (SiO2) has a CTE of about 0.5 ppm / °C. Thus, in some embodiments, mixing silicon dioxide with an amalgam in the appropriate proportions can bring the CTE close to a desired value. Although the CTE of a mixture will not usually be exactly the mass-weighted average of the components, the relationship between mass fraction and CTE over a wide range of compositions is often close to or nearly linear. In some embodiments, the amalgam has a pH of about -25 ppm / °C, -20 ppm / °C, -19 ppm / °C, -18 ppm / °C, -17 ppm / °C, -16 ppm / °C, -15 ppm / °C, -14 ppm / °C, -13 ppm / °C, -12 ppm / °C, -11 ppm / °C, -10 ppm / °C, -9 ppm / °C, -8 ppm / °C, -7 ppm / °C, -6 ppm / °C, -5 ppm / °C, -4 ppm / °C, -3 ppm / °C, -2 ppm / °C, -1 ppm / °C, -0.75 ppm / °C, -0.5 ppm / °C, -0.25 ppm / °C, -0.1 ppm / °C, 0 ppm m / °C, 0.1 ppm / °C, 0.25 ppm / °C, 0.5 ppm / °C, 0.75 ppm / °C, 1 ppm / °C, 1.5 ppm / °C, 2 ppm / °C, 2.5 ppm / °C, 3 ppm / °C, 4 ppm / °C, 5 ppm / °C, 6 ppm / °C, 7 ppm / °C, 8 ppm / °C, 9 ppm / °C, 10 ppm / °C, 11 ppm / °C, 12 ppm / °C, 13 ppm / °C, 14 ppm / °C, 15 ppm / °C, 16 ppm / °C, 17 ppm / °C, 18 ppm / °C, 19 ppm / °C, 20 ppm / °C, or 25 ppm / °C, or any range of values ​​therebetween.

[0040] An example of a negative CTE is that of ZrW2O8, which is about -7.2 ppm / °C. In order for a mixture of materials with negative and positive CTEs to have a net value between the CTEs of the two individual compounds without undesirable stresses, the particles of the compounds must be as small as possible (e.g., nanoparticles). Nanoparticles of ZrW2O8 have been synthesized (see, for example, H. Wu, “Physical and Thermal Properties of Zirconium Tungstate Nanoparticles with Different Morphologies from Hydrothermal Synthesis”, MS thesis, Iowa State University, 2012 and “Optical and Dielectric studies in zirconium(IV) tungstate nanoparticles prepared by chemical co-precipitation method”, J. Iranian Chem. Res. 5 (2) (2012) 109-118).

[0041] To be useful as a fill material layer in microcircuits, composite amalgam materials preferably form a uniform solid at temperatures that the circuit components can withstand. ZrW2O8 sinters at temperatures above 1000°C, so it may not be practical to use it alone or in combination with other heat-resistant materials. As described in U.S. Pat. No. 6,132,676, this problem actually prevents the use of low or zero CTE materials in many applications. However, by mixing an appropriate amount of ZrW2O8 into a gallium (Ga) amalgam precursor, a uniform solid may be formed at low temperatures and pressures (e.g., atmospheric pressure and temperatures below 150°C or below 100°C). Other compositional materials can be added similarly, provided that the amalgam composition contains enough initial liquid gallium (Ga) to fill the voids between the solid particles. The free volume of spherical particles of the same size when uniformly arranged is about 33% of the total, depending on the packing. However, by combining a multimodal dispersion, the free volume can be significantly reduced. For example, for three particle sizes, the remaining free volume may be approximately 4-5%.

[0042] The thermal conductivity of the ceramic material ZrW2O8 is not as high as that of typical metals or single crystals such as silicon. CA Kennedy, et al.(Solid State Communications vol. 134, pp 271-276 (2005)), it is about 1 W / m·K, compared to 149 W / m·K for silicon (Si) and 401 W / m·K for copper (Cu). However, amalgams (e.g., gallium (Ga) amalgams) can significantly exceed the thermal conductivity of the matrix metal (e.g., gallium (Ga)) alone, depending on the specific composition. The thermal conductivity of gallium (Ga) is 40.6 W / m·K. By compressing a 1:1 volumetric mixture of ZrW2O8 and copper (Cu) to 3 GPa and then heating it to 500 °C, X. Li, et al. were able to obtain a thermal conductivity of 165 W / m·K for gallium (Ga) amalgam ("High-pressure and high-temperature synthesis and study of the thermal properties of ZrW2O8 / Cu composites"; Physica B: Physics of Condensed Matter, vol. 487, pp. 27-41 (2016)). Thus, it is possible to achieve both a CTE and thermal conductivity close to that of silicon in a matrix using the closer interfacial contact available through the use of an amalgam (e.g., gallium (Ga) amalgam). In some embodiments, the gallium (Ga) amalgam comprises Ga-M (where "M" represents one or more metal atoms) and a negative CTE material (e.g., ZrW2O8). In some embodiments, M is selected from copper (Cu), nickel (Ni), silver (Ag), cerium (Ce), and combinations thereof. In some embodiments, the negative CTE material is selected from ZrW2O8 (zirconium tungstate), HfW2O8, and / or Sc2W3O 12 In some embodiments, the gallium (Ga) amalgam further comprises a low CTE material, in some embodiments, the low CTE material is selected from silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), silicon (Si), non-stoichiometric versions thereof, and combinations thereof.

[0043] Matrix metals (e.g., gallium (Ga)) usually form alloys with many other elements, but matrix metals may not be miscible with all other elements. For example, the solubility of silicon (Si) in gallium (Ga) is about 10 -7% atomic percent. In some embodiments, the interface between the different crystallites needs to be as strong as possible to obtain the desired mechanical properties. In some cases, the alloy of the matrix metal (e.g., gallium (Ga)) may not form a clear and strong bond with the oxide (e.g., ZrW2O8). However, the nanoparticles may be coated using atomic layer deposition to enhance the alloying compatibility between the nanoparticles. This is a technique that is particularly suitable for forming specific bonds between many metals and oxygen. In some embodiments, the matrix metal has a net D50 average particle size of a particle size distribution defined by about, at most, or at most about 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, or 1000 nm, or any range value therebetween. In some embodiments, the alloying metal has a net D50 average particle size of a particle size distribution defined by about, at most, or at most about 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, or 1000 nm, or any range of values ​​therebetween. In some embodiments, the low CTE material has a D50 average particle size of a particle size distribution defined by a value of, net, about, at most, or at most about 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, or 1000 nm, or any range therebetween. In some embodiments, the additional low CTE material has a D50 average particle size of, net, about, at most, or at most about 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, or 1000 nm, or any range therebetween. The amalgam has a D50 mean particle size of a particle size distribution defined by 5 nm, 30 nm, 35 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, or 1000 nm, or any range of values ​​therebetween, hi some embodiments, the amalgam comprises a multimodal particle size distribution of particles.

[0044] In some embodiments, thin layers of pure metals can also be deposited by atomic layer deposition ("ALD"), which strongly adhere to the substrate via bonding (e.g., chemical bonding). In this way, metals can be bonded to the surface of certain types of nanoparticles that are more compatible with gallium (Ga) alloys, so that stronger bonds can be formed thereafter. For example, copper (Cu) is a metal that is highly compatible with gallium (Ga) layers deposited by ALD, but other metals are known, including, for example, tungsten (W), platinum (Pt), cobalt (Co), iron (Fe), silver (Ag), and nickel (Ni). These coatings can be applied onto the nanoparticles using fluidized bed techniques (e.g., as practiced by ALD Nanosolutions, Inc., Broomfield, Colorado).

[0045] In some embodiments, the amalgam is conductive, for example an amalgam with a majority of its volume being a matrix metal (e.g., gallium (Ga)). In some embodiments, the amalgam is insulating, for example an amalgam with a majority of its volume being a ceramic material (e.g., ZrW2O8). In some embodiments, an advantage of a conductive amalgam is that it acts as a ground plane for an integrated circuit, eliminating the need for a layer in the interconnect portion of the circuit. In such embodiments, components may be electrically isolated from one another by depositing an insulating layer (e.g., an insulating fill material) prior to applying the fill material having the conductive amalgam composition. In some embodiments, the insulating layer may be a thin layer (e.g., up to about 1 μm) of oxide, for example a layer of silicon dioxide (SiO2). In some embodiments, the insulating layer is formed by plasma enhanced chemical vapor deposition (PECVD) or other deposition techniques. In some embodiments, the insulating material and / or insulating amalgam material comprises a dielectric material selected from ZrW2O8, silicon dioxide (SiO2), aluminum oxide (Al2O3), silicon nitride (Si3N4), polymeric materials (e.g., polyimides, liquid crystal polymers, and benzocyclobutene-based polymers), non-stoichiometric ratios thereof, and combinations thereof.

[0046] FIG. 4 illustrates an assembly 400 that includes multiple components 406 positioned and held in place by a release layer 404 disposed on a temporary substrate 402, where the components 406 are encapsulated by a single layer of potting material 408. In some embodiments, the potting material 408 is an amalgam as described herein. In some embodiments, the potting material 408 is deposited to encapsulate the components 406 by methods described herein (e.g., spray deposition or multi-layer deposition). FIG. 4 is not drawn to scale, but the relative height and width of the assembly 400 are intended to illustrate that in some embodiments, a large assembly aspect ratio may exist. As illustrated in FIG. 4, each of the multiple components may be the same, similar, and / or different height, width, or shape as the other components. In some embodiments, the components may have a height of about, at most, or at most about 2 μm, 3 μm, 5 μm, 8 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 150 μm, 200 μm, 300 μm, 400 μm, 500 μm, 600 μm, 700 μm, 800 μm, or 1000 μm, or any range of values ​​therebetween. For example, in some embodiments, the thinnest component in terms of height may have a height of about 2 μm, 3 μm, 5 μm, 8 μm, 10 μm, 150 μm, 200 μm, 300 μm, 400 μm, 500 μm, 600 μm, 700 μm, 800 μm, or 1000 μm, or any range of values ​​therebetween. The components may be as small as 25 μm in height or less. In some embodiments, the spacing between two adjacent components is net, about, at most, or at most about 0.1 μm, 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 12 μm, 15 μm, or 20 μm, or any range of values ​​therebetween. For example, in some embodiments, the spacing between two adjacent components may be 5-10 μm or less. In some embodiments, the components may have a width that is approximately, at least, or at least about 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 12 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 150 μm, 200 μm, 300 μm, 400 μm, 500 μm, 600 μm, 700 μm, 800 μm, 900 μm, 1 mm, 2 mm, 3 mm, 4 mm, or 5 mm, or any range of values ​​therebetween. For example, in some embodiments, the width of a component may be between about 25 μm and several mm. As shown, the components 406 are placed upside down with their active surfaces or sides (e.g., pads) in contact with the release layer 404, so that the active surfaces are not in contact with the embedding material 408. In some embodiments, once the embedding material 408 is deposited, it is cured. In some embodiments, curing is performed by heating the embedding material and / or allowing it to harden. In some embodiments, following deposition and / or curing of the embedding material, the laminate including the components 406 and the embedding material is separated from the release layer 404 and the substrate 402. In some embodiments, the laminate is peeled from the release layer. In some embodiments, the release layer is decomposed (e.g., by light and / or heat) to separate the laminate from the substrate 402. In some embodiments, the components may be passive components. In some embodiments, the passive components are capacitors or resistors.In some embodiments, the height (i.e., thickness) of the components is about 150 μm or more. In some embodiments, the width (i.e., thickness) of the components is about twice their height. In some embodiments, microelectromechanical systems ("MEMS") components with primary packaging that protects sensitive internal structures may be as high as 100 μm or more in height (e.g., thickness) and / or as wide as hundreds to hundreds of μm. In some embodiments, the potting material is applied from an amalgam containing liquid. In some embodiments, the liquid is a low viscosity precursor liquid, which may completely fill narrow cracks between tall components with the potting material. In some embodiments, the assembly further comprises a temporary border or dam that may be used to contain the amalgam at the edges of the assembly (e.g., while the material hardens). In some embodiments, the release layer has a thickness of about 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 12 μm, 15 μm, 20 μm, or 25 μm, or any range of values ​​therebetween. For example, in some embodiments, the release layer has a thickness of about 1-2 μm, which may be sufficient to hold a component on a flat surface. In some embodiments, the substrate surface has a mean surface height variation of about, at most, or at most about 0.01 μm, 0.05 μm, 0.1 μm, 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm, or any range of values ​​therebetween.

[0047] 5 illustrates an assembly 500 comprising a plurality of components 506 positioned and held in place by a release layer 504 disposed on a temporary substrate 502, the components 506 being encapsulated by a first layer of embedding material 508 and a second layer of embedding material 510. In some embodiments, the first layer of embedding material 508 may have pits and / or cracks where the surface is only partially planarized by flow. In some embodiments, any number of layers of embedding material may be used, for example, at least 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10 layers, or any range therebetween. A value within can be used to encapsulate the component. In some embodiments, a layer may include two or more sublayers of the same or different composition. In some embodiments, each potting material layer may have the same, similar, or different relative heights (i.e., thicknesses). In some embodiments, the potting material of the first and / or second layers may include an insulating material, an amalgam material, or a combination thereof. In some embodiments, at least one of the potting materials of the layers includes an amalgam material. The elements of assembly 500 of FIG. 5 and its processes may be similar to those described herein and with respect to FIG. 4.

[0048] In some embodiments, the encapsulation of the component occurs after forming interconnects on the active surface of the component. In some embodiments, the encapsulation of the component occurs before forming interconnects on the active surface of the component. In some embodiments, potting materials of various compositions can be applied to encapsulate the component. In some embodiments, the first layer may be applied to the component first and at least partially solidified. In some embodiments, the composition of the first layer may be selected to match as closely as possible the CTE of silicon so that stresses in and around the silicon IC are minimized during thermal cycling. In some embodiments, such a composition may enhance the reliability of contact between metal interconnect lines and I / O pads of the IC. In some embodiments, a second layer having a second composition may then be applied over the first layer of the component. In some embodiments, the composition of the second layer is selected to provide a high thermal conductivity. In some embodiments, a slight mismatch in the CTE of the first layer relative to silicon may be tolerated, for example, if at least some components exceed the height of the first layer. Such a slight CTE mismatch may be tolerated. For example, when all critical components of a first layer are on a layer and are not completely encapsulated by the first layer, the critical components are therefore more or less equally affected by the thermal expansion and contraction of the second layer. In some embodiments, wider or larger components such as passive devices (e.g., resistors and ceramic capacitors) that contact both the first and second layers may be less susceptible to CTE mismatch because their larger contact area provides a larger total bond area to the interconnects, making them less susceptible to failure.

[0049] In some embodiments, two different embedding material compositions are used in the two layers. In some embodiments, the two different embedding material compositions are configured to simultaneously optimize the thermal expansion match and thermal conductivity of the device (e.g., circuit). In some embodiments, the thickness of each embedding material layer can be selected and configured for flexibility. In some embodiments, the layers can have the same, similar, or different relative thicknesses. In some embodiments, the embedding material of the first layer can be an insulator material (e.g., an insulating amalgam material), which can eliminate the need for a dielectric layer, as an example. In some embodiments, the embedding material of the second layer and subsequent layers can be a conductor, as an example, forming a ground plane and possibly contacting some of the passive components, such as bypass capacitors, all connected to ground.

[0050] In some embodiments, the stacks and assemblies described herein may be suitable for use with very thin components, or may be suitable for use with thicker components that are not thinned. For example, components having a thickness of about 250 μm or 500 μm may be utilized, which are examples of silicon wafer thicknesses found in commercially available products. Any component placement process may be used, such as a conventional pick-and-place process as disclosed in U.S. Patent Nos. 6,946,178 and 7,141,348, which are incorporated herein by reference in their entirety for all purposes.

[0051] In some embodiments, one objective is to provide a buried layer whose surface is flush with the component surface, as shown, for example, in FIG. 4. This allows high resolution interconnects to be produced with minimal surface preparation. For example, one problem that arises with conventional injection molding embedding is that after the component is pressed into a temporary release layer and then a molding or embedding compound is applied and released, there can be a height discontinuity between the chip and the embedding material, called mold flash. This is described, for example, in U.S. Pat. No. 8,922,021, which is incorporated by reference in its entirety for all purposes. U.S. Pat. No. 8,922,021 describes a remedy to the problem by covering the surface with an insulating layer and then forming vias to the I / O pads. This does planarize the surface, but at a significant expense and adds process complexity.

[0052] In some embodiments, the release layer (e.g., a temporary adhesive polymer) has a thickness as described herein (e.g., about 1-2 μm). The thickness of the release layer can be configured to be sufficient to temporarily hold a component as described herein (e.g., a typical surface mount component) to a substrate. In some embodiments, the substrate is flat or substantially flat (i.e., has low variation in average surface height) as described herein (e.g., within less than about ±1 μm). In some embodiments, unlike some injection molding processes, the process of applying the potting material involves strong lateral forces. In some embodiments, the components of the release layer (e.g., a polymer film) penetrate the thickness of the release layer net about, at most, or at most about 1%, 5%, 10%, 20%, 30%, 40%, 50%, 60%, or 70%, or any range therebetween. In some embodiments, the discontinuities in the release layer at the edges of the deposited components are about, at most, or at most about 0.01 μm, 0.05 μm, 0.1 μm, 0.2 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.2 μm, 1.5 μm, or 2 μm, or any range of values ​​therebetween. In some embodiments, the discontinuities in the release layer at the edges of the deposited components are comparable to the shape variations typically present in a finished IC. In some embodiments, the assemblies and processes described herein advantageously reduce the disturbing forces present during molding, thereby reducing the need for thick release layers (e.g., temporary adhesive layers) where extensive component penetration may occur.

[0053] In some embodiments, the release layer (e.g., temporary adhesive polymer) is a photoresist that loses a portion of its mass as a result of exposure to light and / or thermal development. In some embodiments, such photoresists are common in the microlithography industry and are based on the loss of t-butoxycarbonyl moieties, which can result in a loss of approximately 15% of the film thickness. In some embodiments, this decomposition produces gaseous products that reduce adhesion (e.g., temporarily or permanently) to the surface attached to the film. In some embodiments, decomposition can result in delamination (e.g., pulling apart) of the substrate and laminate including the component. In some embodiments, decomposition of the release layer separates the substrate and laminate including the component.

[0054] In some embodiments, the release layer material (e.g., a photoresist polymer) may be etched (e.g., imaged and developed) to create small recesses between the components and the release layer. FIG. 6 shows an assembly 600 having a deposition material 612 deposited on and within the walls of undercut regions 606A and 606B of the release layer 604, directly beneath components 608 and 610, respectively. In some embodiments, the deposition material is a fill material as described herein. In some embodiments, the deposition material is an insulating and / or dielectric material. The release layer 604 is disposed on a substrate 602; Components 608 and 610 are disposed on the release layer 604. In some embodiments, the substrate 602 (e.g., a temporary substrate) is a porous material. In some embodiments, the undercut regions 606A and 606B may be formed by exposure and / or thermal development of the material (e.g., a polymer) of the release layer 604. In some embodiments, the distance that the components overhang the undercut regions of the release layer (e.g., a polymer) may be several micrometers. In some embodiments, the distance that the components overhang the undercut regions of the release layer (e.g., a polymer) is net, about, at most, or at most about 0.1 μm, 0.2 μm, 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 12 μm, 15 μm, or 20 μm, or any range of values ​​therebetween (e.g., about 2-10 μm). 6 illustrates that the thickness of the undercut region 606A is less than the thickness of the undercut region 606B, and the thickness of the release layer 604 directly under the component 608 is less than the thickness of the release layer 604 directly under the component 610. In some embodiments, the thickness of the undercut region and / or release layer region may be reduced relative to another undercut region and / or release layer region directly under two components because one of the components is located deeper (e.g., depressed or pressed) into the release layer (e.g., polymer). In some embodiments, the depth of the components depressed into the release layer is about, at most, or at most about 25 nm, 50 nm, 75 nm, 100 nm, 125 nm, 150 nm, 200 nm, 250 nm, 300 nm, 400 nm, 500 nm, 600 nm, 800 nm, or 1000 nm, or any range therebetween (e.g., about 150-300 nm if the original release layer is about 1-2 μm thick, or a relatively deeper recess if the original release layer is about 2-10 μm thick). In some embodiments, the release layer is irradiated with light prior to placing the components on the release layer and undercut regions.In some embodiments, the irradiation of the release layer forms a photosensitive release layer. In some embodiments, the photosensitive release layer decomposes when sufficient heat is applied. In some embodiments, the release layer is deposited on the substrate as a photosensitive release layer. In some embodiments, the release layer is irradiated with light after placing a component on the release layer and the undercut region. In some embodiments, once the component is placed on the release layer and the undercut region, a deposition material (e.g., a dielectric film) is deposited on the walls of the component and in the undercut region. In some embodiments, the deposition of the deposition material is performed by sputtering or PECVD. In some embodiments, the mean free path of the reactive molecules of the deposition material is small enough that at least some of them diffuse under the overhang before deposition, resulting in a thin layer with a tapered thickness in the undercut region, as shown in FIG. 4.

[0055] In some embodiments, the deposition material provides a smooth transition across the edges of the components. In some embodiments, the deposition material covers edges of components that may be sharp and therefore difficult to fabricate interconnects later. In some embodiments, the deposition material may insulate the component (e.g., chip) from interconnects that are deposited later, e.g., regardless of what metal structures are part of the IC near the edge. In some embodiments, this smooth transition of the deposition material may offset height differences that may exist due to differences in the penetration of components (e.g., polymers) in the release layer. In some embodiments, the assembly 600 may be further processed to encapsulate the components 608 and 610 with a potting material and / or release the components from the release layer 604 and substrate 602. In some embodiments, after deposition of the deposition material (e.g., dielectric), the release layer (e.g., photoresist film) is heated to decompose the release material (e.g., t-butoxycarbonyl) and reduce adhesion. In some embodiments, if the deposition material is a dielectric, a thicker graded deposition is formed that helps to cover some edge defects and component structures. will be done.

[0056] In some embodiments, the release layer is a thermally decomposable polymer as disclosed in U.S. Patent Nos. 7,300,824 and 7,863,762, which are incorporated by reference in their entirety for all purposes. In some embodiments, the release layer (e.g., a polymer film with or without a photosensitizer) can be formed on a porous substrate that can function as a porous vacuum chuck. In some embodiments, for example, after all components of a circuit are placed on the release layer and at least a deposition material (e.g., a dielectric layer) is deposited, the release layer is heated to a decomposition temperature while applying a vacuum to the porous vacuum chuck, so that decomposition products of the release layer are evacuated through the pores of the porous vacuum chuck while the porous vacuum chuck holds the component stack in place. In some embodiments, the potting material can be applied before or after decomposition of the release layer.

[0057] In some embodiments, the release layer may be decomposed prior to deposition of a release material (e.g., a dielectric). In some embodiments, the vacuum from the porous vacuum chuck holds the individual components in place even if there are undercut areas because this is a small fraction of the total area and an appropriate pressure differential can be maintained across the components despite the open areas. In some embodiments, the deposition material (e.g., a dielectric film) is then deposited using an atmospheric pressure process (e.g., atmospheric pressure PECVD). In some embodiments, the surface of the components is in direct contact with the surface of the substrate (e.g., the porous vacuum chuck). In some embodiments, the porous vacuum chuck defines a flat or substantially flat plane regardless of the extent to which the components have penetrated the release layer (e.g., a polymer). The structure of such an assembly 700 is shown in FIG. 7. FIG. 7 shows components 704 and 706 disposed on a substrate 702 (e.g., a temporary substrate) after removal of a release layer (e.g., a temporary adhesive layer) and deposition of a deposition material (e.g., an insulating dielectric). In some embodiments, the insulating material is deposited before or after removal of a release layer (e.g., adhesive). In some embodiments, the contact (e.g., adhesion) between the deposited material (e.g., dielectric film) and the substrate 702 may separate (e.g., break) during peeling due to the component stack (e.g., circuit stack) being only a small percentage of the total area. In some embodiments, the substrate may be treated with a low surface energy coating (e.g., a thin coating) to facilitate separation of the components from the substrate. In some embodiments, the low surface energy coating is selected from a plasma deposited fluorocarbon film, a self-assembled monolayer of a fluorocarbon, and combinations thereof. In some embodiments, the assembly 700 may be further processed to encapsulate the components 704 and 706 with an embedding material and / or release the components from the substrate 702. In some embodiments, the separated component stack may be further processed to add interconnects to the active faces of the components.

[0058] In some embodiments, the porous vacuum chuck comprises a plurality of pores. In some embodiments, the pores have nanometer-scale diameters and / or micron-scale diameters. In some embodiments, the pores have a net average diameter of about, at most, or at most about 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 75 nm, 100 nm, 150 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 800 nm, 1 μm, 1.5 μm, 2 μm, 3 μm, 5 μm, or 10 μm, or any range of values ​​therebetween. In some embodiments, the substrate (e.g., porous vacuum chuck) comprises silicon.

[0059] In some embodiments, the release layer is deposited on the porous vacuum chuck prior to component deposition. In some embodiments, a vacuum chuck may not be used to hold the component during the component placement process, for example because initially all areas are exposed and would not provide sufficient retention for the initially placed component. In some embodiments, a vacuum can be applied once the release layer and the component are placed on the substrate, and the vacuum is sufficient to hold the component due to the reduced exposed area (e.g., exposed spaces between closely packed components) on the porous vacuum chuck before or after decomposition of the release layer (e.g., temporary adhesive).

[0060] Although specific embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions, and modifications may be made in the systems and methods described herein without departing from the spirit of the present disclosure. The appended claims and their equivalents are intended to cover such forms or modifications as are within the scope and spirit of the present disclosure.

[0061] It should be understood that a feature, material, characteristic, or group described in connection with a particular aspect, embodiment, or example may be applied to any other aspect, embodiment, or example described in this section or elsewhere in this specification, unless incompatible therewith. All features disclosed in this specification (including the accompanying claims, abstract, and drawings), and / or all steps of any method or process so disclosed, may be combined in any combination, except combinations in which at least some of such features and / or steps are mutually exclusive. This protection is not limited to the details of the foregoing embodiments. This protection extends to any novel feature or novel combination of features disclosed in this specification (including the accompanying claims, abstract, and drawings), or to any novel step or novel combination of steps of any method or process so disclosed.

[0062] Moreover, certain features that are described in the disclosure in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although the features described above may be described as functioning in a particular combination, in some cases one or more features can be deleted from a claimed combination, and the combination may be claimed as a subcombination or a variation of the subcombination.

[0063] Additionally, although operations may be shown in the figures or described in the specification in a particular order, it is not necessary that such operations be performed in the particular order shown or sequential order, or that all of the operations be performed, to achieve desirable results. Other operations not shown or described may be incorporated into the exemplary methods and processes. For example, one or more additional operations may be performed before, after, simultaneously with, or between any of the described operations. Additionally, operations may be rearranged or reordered in other implementations. Those skilled in the art will appreciate that in some embodiments, the actual steps performed in the illustrated and / or disclosed processes may differ from those shown in the figures. Depending on the embodiment, certain of the above-described steps may be omitted and other steps may be added. Additionally, the features and characteristics of certain embodiments disclosed above may be combined in various ways to form additional embodiments, all of which are within the scope of the present disclosure. Additionally, it is to be understood that the separation of various system components in the above implementations should not be understood as requiring such separation in all implementations, and that the components and systems described may typically be integrated together in a single product or packaged together in multiple products. For example, the components of the energy storage systems described herein may be integrated in a single product or packaged together in multiple products. Any of the components may be provided separately or may be integrated together (eg, packaged together or mounted together) to form an energy storage system.

[0064] For purposes of this disclosure, certain aspects, advantages, and novel features are described herein. Not necessarily all such advantages are achieved in accordance with a particular embodiment. Thus, for example, one skilled in the art will recognize that the present disclosure may be embodied or carried out in a manner that achieves one advantage or group of advantages taught herein without necessarily achieving other advantages that may be taught or suggested herein.

[0065] Conditional language such as "can," "could," "might," or "may" is generally intended to convey that certain features, elements, and / or steps are included in certain embodiments but not in other embodiments, unless otherwise specified or understood within the context in which it is used. Thus, such conditional language is generally not intended to suggest in any way that the features, elements, and / or steps are required for one or more embodiments, or that one or more embodiments necessarily include logic for determining whether those features, elements, and / or steps should be included or performed in a particular embodiment, with or without user input or prompting.

[0066] Conjunctions such as "at least one of X, Y, and Z," unless otherwise noted, are typically understood in the context in which they are used to convey that an item, term, etc. can be either X, Y, or Z. Thus, such conjunctions are typically not intended to imply that a particular embodiment requires the presence of at least one of X, at least one of Y, and at least one of Z.

[0067] As used herein, terms indicating degree, such as "approximately," "about," "generally," and "substantially," refer to a value, amount, or characteristic that is close to a stated value, amount, or characteristic that performs a desired function or achieves a desired result. For example, the terms "approximately," "about," "generally," and "substantially" refer to an amount that is within less than 10%, within less than 5%, within less than 1%, within less than 0.1%, and within less than 0.01% of the stated amount, depending on the desired function or result.

[0068] The scope of the present disclosure is not intended to be limited by the specific disclosure of preferred embodiments in this section or elsewhere herein, but may be defined by the claims presented in this section or elsewhere herein, or presented in the future. The language of the claims is to be interpreted broadly based on the language used in the claims, and is not limited to the examples described herein or during the prosecution of this application, which examples are to be construed as non-exclusive. The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the devices and methods disclosed herein.

Claims

1. 1. An assembly for use in the manufacture of an integrated circuit, comprising: substrate, a release layer disposed on the substrate; a plurality of components disposed on the release layer, each of the plurality of components having an active surface in contact with the release layer; and a potting material layer encapsulating the plurality of components.

2. The assembly of claim 1 , wherein each of the active surfaces of the components is substantially free of contact with potting material.

3. The assembly of claim 1 , wherein the fill material layer comprises a plurality of fill material sublayers.

4. The assembly of any one of claims 1 to 3, wherein the potting material layer comprises an amalgam.

5. The assembly of claim 4, wherein the amalgam is a low coefficient of thermal expansion (CTE) amalgam having a CTE of between -5 ppm / °C and 5 ppm / °C.

6. The assembly of claim 4 , wherein the amalgam comprises a matrix metal, an alloying metal, and a low CTE material.

7. The assembly of claim 6 , wherein the matrix metal comprises gallium (Ga).

8. 7. The assembly of claim 6, wherein the alloying metal is selected from the group consisting of copper (Cu), nickel (Ni), silver (Ag), cerium (Ce), and combinations thereof.

9. The low CTE material is ZrW ２ O ８ (zirconium tungstate), HfW ２ O ８ , Sc ２ W ３ O １２ 7. The assembly of claim 6, wherein the at least one conductor is selected from the group consisting of:

10. The assembly of claim 4 , wherein the amalgam further comprises a member selected from the group consisting of an additional low CTE material, a passivation material, a liquid, a reducing agent, and combinations thereof.

11. The assembly of any one of claims 1 to 3, wherein the release layer comprises an undercut region located between the release layer and at least one component of the plurality of components.

12. The assembly of claim 11 , wherein the undercut area comprises a deposited material.

13. The assembly according to any one of claims 1 to 3, wherein the substrate has pores.

14. A method for producing an assembly according to any one of claims 1 to 3, comprising the steps of: depositing the plurality of components on the release layer, the release layer being disposed on the substrate; and encapsulating the plurality of components with the layer of potting material; A manufacturing method comprising:

15. The method of claim 14 , wherein the step of encasing the plurality of components with the layer of potting material is performed by a spraying method.

16. A method of integrating an assembly into an integrated circuit, comprising the steps of: Separating the release layer from the components encapsulated by the embedding material layer of the assembly of any one of claims 1 to 3 to form a laminate; and depositing an interconnect material onto each of the exposed surfaces of the plurality of components to form a wired stack; A method comprising:

17. placing the wired stack into a device; and electrically connecting the wired stack to the device.

20. The method of claim 16, further comprising:

18. 1. A laminate for integration into a circuit device, comprising: a plurality of components, each of the components including a plurality of encapsulating surfaces and an exposed surface; and an embedding material encapsulating the encapsulation surfaces of the components; A laminate comprising:

19. The laminate of claim 18 , wherein each of the exposed surfaces comprises a pad.

20. 20. The laminate of claim 18, wherein each of the exposed surfaces are substantially coplanar with one another.

21. The laminate of any one of claims 18 to 20, further comprising an interconnect material disposed on each of the exposed surfaces.

22. The laminate of any one of claims 18 to 20, wherein the potting material comprises an amalgam.

23. 23. The laminate of claim 22, wherein the amalgam comprises a matrix metal, an alloying metal, and a low CTE material.

24. 23. The laminate of claim 22, wherein the amalgam is a low coefficient of thermal expansion (CTE) amalgam having a CTE of between -5 ppm / °C and 5 ppm / °C.

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