Direct bonding and delamination of carriers

Abstract

A method for processing a semiconductor device is disclosed. The method can include providing a semiconductor device having a first non-conductive material. The first non-conductive material is disposed on a device portion of the semiconductor device. The method can include providing a transparent carrier. The method can include providing an intervening structure in which a second non-conductive material, a photolysis layer, and an opaque layer are stacked on top of each other. The method can include forming a bonding structure such that the second non-conductive material is bonded to the first non-conductive material or directly to the transparent carrier. The intervening structure is disposed between the semiconductor device and the transparent carrier. The method can include separating the transparent carrier from the semiconductor device by exposing the photolysis layer to light through the transparent carrier such that the light decomposes the photolysis layer.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 169,029, entitled “Direct Bonding and Debonding of Carriers,” filed March 31, 2021, the entire contents of each of which are hereby incorporated by reference herein.

[0002] The field of the invention relates to direct bonding of a semiconductor element to a carrier and removal of the carrier after direct bonding. [Background technology]

[0003] Semiconductor devices, such as semiconductor wafers, can be stacked and directly bonded to one another without adhesives. For example, in some direct bonding structures, non-conductive field regions of the devices can be directly bonded to one another. In some structures, corresponding conductive contact structures can also be directly bonded to one another. In some applications, it can be difficult to form thinned dies and wafers and / or perform backside processing. Thus, there remains a need for improved methods and structures for direct bonding. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Pat. No. 9,564,414 [Patent Document 2] U.S. Pat. No. 9,391,143 [Patent Document 3] U.S. Pat. No. 10,434,749 [Patent Document 4] U.S. Patent No. 11,056,390 [Patent Document 5] U.S. Patent No. 9,716,033 [Patent Document 6] U.S. Pat. No. 9,852,988 [Patent Document 7] U.S. Pat. No. 11,195,748 [Patent Document 8] U.S. Patent Application Serial No. 17 / 206,725

[0005] Reference will now be made to the following drawings, in which specific implementations are given by way of example and not by way of limitation. [Brief description of the drawings]

[0006] [Figure 1A] FIG. 2 is a schematic cross-sectional side view of two elements prior to bonding. [Figure 1B] FIG. 1B is a schematic cross-sectional side view of the two elements shown in FIG. 1A after bonding. [Diagram 2] 1 is a schematic cross-sectional view of a semiconductor device coupled to a carrier structure according to an embodiment. [Figure 3A] 1A-1C illustrate various stages of a manufacturing process for producing a bonded structure according to an embodiment. [Figure 3B] 1A-1C illustrate various stages of a manufacturing process for producing a bonded structure according to an embodiment. [Figure 3C] 1A-1C illustrate various stages of a manufacturing process for producing a bonded structure according to an embodiment. [Figure 3D] 1A-1C illustrate various stages of a manufacturing process for producing a bonded structure according to an embodiment. [Figure 3E] 1A-1C illustrate various stages of a manufacturing process for producing a bonded structure according to an embodiment. [Figure 3F] 1A-1C illustrate various stages of a manufacturing process for producing a bonded structure according to an embodiment. [Figure 3G] 1A-1C illustrate various stages of a manufacturing process for producing a bonded structure according to an embodiment. [Figure 3H] 1A-1C illustrate various stages of a manufacturing process for producing a bonded structure according to an embodiment. [Figure 4A] FIG. 1 illustrates a general process for bonding multiple devices according to an embodiment. [Figure 4B]FIG. 1 illustrates a general process for bonding multiple devices according to an embodiment. [Figure 4C] FIG. 1 illustrates a general process for bonding multiple devices according to an embodiment. [Figure 4D] FIG. 1 illustrates a general process for bonding multiple devices according to an embodiment. [Figure 4E] FIG. 1 illustrates a general process for bonding multiple devices according to an embodiment. [Figure 4F] FIG. 1 illustrates a general process for bonding multiple devices according to an embodiment. [Figure 5A] 1A-1C illustrate various stages in a manufacturing process for making a singulated die according to an embodiment. [Figure 5B] 1A-1C illustrate various stages in a manufacturing process for making a singulated die according to an embodiment. [Figure 5C] 1A-1C illustrate various stages in a manufacturing process for making a singulated die according to an embodiment. [Figure 5D] 1A-1C illustrate various stages in a manufacturing process for making a singulated die according to an embodiment. [Figure 6A] 1A-1C illustrate various stages in a manufacturing process for producing a reconstructed wafer according to an embodiment. [Figure 6B] 1A-1C illustrate various stages in a manufacturing process for producing a reconstructed wafer according to an embodiment. [Figure 6C] 1A-1C illustrate various stages in a manufacturing process for producing a reconstructed wafer according to an embodiment. [Figure 6D] 1A-1C illustrate various stages in a manufacturing process for producing a reconstructed wafer according to an embodiment. [Figure 7A] 10A-10C illustrate various stages in a manufacturing process for making a singulated die according to another embodiment. [Figure 7B] 10A-10C illustrate various stages in a manufacturing process for making a singulated die according to another embodiment. [Figure 7C] 10A-10C illustrate various stages in a manufacturing process for making a singulated die according to another embodiment. [Figure 7D]11A-11C illustrate various stages in a manufacturing process for making a singulated die according to another embodiment. [Figure 7E] 11A-11C illustrate various stages in a manufacturing process for making a singulated die according to another embodiment. [Figure 7F] 11A-11C illustrate various stages in a manufacturing process for making a singulated die according to another embodiment. [Figure 7G] 11A-11C illustrate various stages in a manufacturing process for making a singulated die according to another embodiment. [Figure 7H] 11A-11C illustrate various stages in a manufacturing process for making a singulated die according to another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] In various microelectronic devices, two or more elements 2, 3 can be directly bonded to each other without adhesive to form a bonded structure. The elements 2, 3 in FIG. 1A and FIG. 1B can comprise semiconductor elements in some embodiments. For example, in various embodiments, the first and second elements 2, 3 can comprise semiconductor wafers. In some embodiments, the first and second elements 2, 3 can comprise semiconductor device dies. In some embodiments, one of the first and second elements can comprise a semiconductor wafer and the other of the first and second elements can comprise a semiconductor device die. In various embodiments disclosed herein, the second element 3 can comprise a carrier that can be temporarily directly bonded to the first element 2 and subsequently removed (e.g., after thinning and / or other processing). For example, in some embodiments, the first element 2 can comprise a semiconductor element (e.g., a singulated integrated device die or a non-singulated wafer) having a device portion 5 and a first non-conductive bonding material 4a on the device portion 5. The device portion 5 can comprise a semiconductor material having active circuitry formed thereon. The second element 3 may comprise a substrate 6 and a second non-conductive bonding material 4b on the substrate 6. In some embodiments, the substrate 6 may comprise glass or a semiconductor (such as silicon).

[0008] In various embodiments, as shown in Figures 1A-1B, the non-conductive (e.g., semiconductive or inorganic dielectric) bonding material 4a of the first element 2 can be directly bonded to the corresponding non-conductive (e.g., semiconductive or inorganic dielectric) bonding material 4b of the second element 3 without an adhesive. In some embodiments (not shown), the conductive regions (e.g., metal pads or contact structures) of the first element 2 can be directly bonded to the corresponding conductive regions (e.g., metal pads or contact structures) of the second element 3 without an adhesive. In some embodiments, the non-conductive material 4a of the first element 2 can be directly bonded to the corresponding non-conductive material 4b of the second element 3 using adhesive-free bonding techniques using direct bonding techniques disclosed in at least U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, the contents of each of which are incorporated herein by reference in their entirety for all purposes. Additional examples of hybrid bonding can be found throughout U.S. Patent No. 11,056,390, the contents of which are incorporated herein by reference in their entirety for all purposes. In other applications, in a bonded structure 1, the non-conductive material of the first element 2 can be directly bonded to the conductive material of the second element 3, so that the conductive material of the first element 2 is intimately interdigitated with the non-conductive material of the second element 3. Dielectric bonding surfaces or materials suitable for direct bonding include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, or silicon oxynitride, or can include silicon carbide, silicon oxycarbonitride, low-K dielectrics, SICOH, silicon carbonitride, or diamond-like carbon, or materials with diamond surfaces. Such carbon-containing ceramic materials can be considered inorganic, despite the carbon content.

[0009] In various embodiments, the direct bond can be formed without an intervening adhesive. For example, the semiconductor or dielectric bonding surface can be polished to a high degree of smoothness. The bonding surface can be cleaned and exposed to a plasma and / or an etchant to activate the bonding surface. In some embodiments, the bonding surface can be terminated with a chemical species after or during activation (e.g., during the plasma and / or etch step). Without being limited by theory, in some embodiments, an activation step can be performed to break chemical bonds at the bonding surface, and a termination step can provide the bonding surface with additional chemical species that improve the bond energy during direct bonding. In some embodiments, the activation and termination treatments are provided in the same step, such as, for example, a plasma or wet etchant that activates and terminates the bonding surface. In other embodiments, the bonding surface can be terminated in a separate process to provide additional chemical species for direct bonding. In various embodiments, the termination chemical species can comprise nitrogen. For example, in some embodiments, the bonding surface can be exposed to a nitrogen-containing plasma. Additionally, in some embodiments, the bonding surface can be exposed to fluorine. For example, there may be one or more fluorine peaks near the layer and / or bond interfaces, particularly the dielectric bond interfaces. Thus, in a direct bond structure, the bond interface between two non-conductive materials may have a very smooth interface with higher nitrogen content and / or fluorine peaks at the bond interface. Additional examples of activation and / or termination treatments may be found throughout U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, the contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0010] In various embodiments, the conductive contact pads of a first element can be directly bonded to corresponding conductive contact pads of a second element (e.g., in a configuration where both elements have contact pads). For example, direct hybrid bonding techniques can be used to provide conductor-conductor direct bonds along bond interfaces comprising covalently directly bonded dielectric-dielectric surfaces prepared as described above. In various embodiments, conductor-conductor (e.g., contact pad-contact pad) direct bonds and dielectric-dielectric hybrid bonds can be formed using direct bonding techniques disclosed at least in U.S. Pat. Nos. 9,716,033 and 9,852,988, the contents of each of which are incorporated herein by reference in their entirety for all purposes. The bond structures described herein may also be useful for direct metal bonding or other bonding techniques that do not involve bonding of non-conductive regions.

[0011] In some embodiments, inorganic dielectric bonding surfaces can be prepared and bonded directly to each other without an adhesive as described above. In a direct bond structure with contact pads, the conductive contact pads (which may be surrounded by non-conductive dielectric field regions) can also be bonded directly to each other without an adhesive. In some embodiments, each contact pad can be recessed below the outer surface (e.g., top surface) of the dielectric field region or non-conductive bonding region by, for example, less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, in the range of 2 nm to 20 nm or in the range of 4 nm to 10 nm. The coefficient of thermal expansion (CTE) of the dielectric can be, for example, in the range of 0.1 ppm / °C to 5 ppm / °C, and the CTE of the conductive material can be in the range of 6 ppm / °C to 40 ppm / °C or 8 ppm / °C to 30 ppm / °C. The difference between the CTE of the dielectric and the CTE of the conductive material inhibits the lateral expansion of the conductive material during subsequent thermal processing operations. The non-conductive bonding regions may in some embodiments be directly bonded to each other without adhesive at room temperature, after which the bonded structure may be annealed. Upon annealing, the contact pads may expand against the non-conductive bonding regions and contact each other to form a direct metal-metal bond. Advantageously, hybrid bonding techniques such as Direct Bond Interconnect, or DBI®, available from Xperi, Inc., San Jose, Calif., allow for a high density of pads (e.g., small or fine pitch for a regular array) connected across the direct bond interface. In various embodiments, the contact pads may comprise copper, although other metals may be suitable. In arrangements where the first and second elements 2, 3 do not have contact pads on their bonding surfaces, the non-conductive materials may be directly bonded at room temperature, achieving metal contact without subsequent annealing.

[0012] Thus, in a direct bonding process, a first element may be directly bonded to a second element without an intervening adhesive. In some arrangements, the first element may comprise a singulated element, such as a singulated integrated device die. In other arrangements, the first element may comprise a carrier or substrate (e.g., a wafer) comprising a plurality (e.g., tens to hundreds or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element may comprise a singulated element, such as a singulated integrated device die. In other arrangements, the second element may comprise a carrier or substrate (e.g., a wafer). In some embodiments, multiple dies with different CTEs may be bonded onto the same carrier. In some embodiments, the CTE of the substrate of the bonded die may be similar to the CTE of the substrate of the carrier. In other embodiments, the CTE of the substrate of the bonded die may be different from the CTE of the substrate of the carrier. The difference in CTE between the bonded dies or between the bonded die and the carrier may range from 1 ppm / °C to 70 ppm / °C, and may be less than 30 ppm / °C, for example less than 12 ppm / °C.

[0013] As described herein, the first and second elements can be directly bonded to each other without an adhesive, which is different from a deposition process. Thus, the first and second elements can comprise non-deposited elements. Furthermore, the direct bond structure, unlike a deposited layer, can comprise defect regions in which nano-voids exist along the bond interface. The nano-voids can form due to activation (e.g., exposure to plasma) of the bonding surface. As described above, the bond interface can include concentrations of material from the activation and / or final chemical processing steps. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen peak can form at the bond interface. In embodiments utilizing oxygen plasma for activation, an oxygen peak or oxygen-rich layer can form at the bond interface. In some embodiments, the bond interface can comprise an inorganic non-conductive material such as nitrogen-terminated silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, or silicon carbonitride, and the level of nitrogen present at the bond interface represents a nitrogen termination for at least one of the elements prior to direct bonding. Except for nitrogen-containing dielectrics, the nitrogen content of non-conductive materials typically has a gradient that peaks at or near the surface. In some embodiments, nitrogen and nitrogen-related moieties may be absent from the bond interface. As described herein, direct bonding can comprise covalent bonds that are stronger than van der Waals bonds. The bonding layer can also comprise a polished surface that is planarized to a high degree of smoothness.

[0014] In various embodiments where the elements 2, 3 have directly bonded metallic contact pads, the metal-metal bond between the contact pads may be bonded such that the metal grains (e.g., copper grains) grow into each other across the bond interface. In some embodiments, the copper may have grains oriented perpendicularly along the (111) crystal plane to improve diffusion of the copper across the bond interface. However, in some embodiments, other crystal planes of the copper may be oriented perpendicularly to the contact pad surface. The non-conductive bond interface may extend substantially completely to at least a portion of the bonded contact pads, such that there is substantially no gap between the non-conductive bonding regions at or near the bonded contact pads. In some embodiments, a barrier layer may be provided under the contact pads (which may comprise, for example, copper). However, in other embodiments, there may be no barrier layer under the contact pads, as described, for example, in U.S. Pat. No. 11,195,748, the entirety of which is incorporated herein by reference for all purposes.

[0015] In some applications, for example, in a multi-element device stack such as a memory device, it may be desirable to utilize a thinned semiconductor element. For example, the semiconductor element (such as a semiconductor element wafer) can be temporarily bonded to a carrier (e.g., a glass or silicon carrier wafer) through an adhesive, such as a thermally curable or UV-curable adhesive (e.g., an organic adhesive). The backside of the semiconductor element can be thinned, for example, by grinding and / or chemical mechanical polishing (CMP). Furthermore, additional backside processing can be performed on the backside of the semiconductor element while it is attached to the carrier. For example, a metallization or interconnect line (BEOL) layer or thin film can be deposited or otherwise provided over the thinned semiconductor element.

[0016] However, the use of adhesives for temporary bonding can be challenging in many ways. For example, when a device wafer is thinned, the die size may grow laterally due to residual stresses from the BEOL thin films because the organic adhesive may not provide sufficient bond strength to suppress the lateral growth of the device wafer. Furthermore, the mechanical stability of the adhesive bond between the device wafer and the carrier wafer during the thinning process (e.g., grinding process) may be degraded or unreliable due to the forces applied during thinning. In some cases, the thinning process may cause the thickness of the device wafer to vary significantly, even exceeding the desired total thickness variation (TTV). For example, the temporary adhesive interposed between the device wafer and the carrier wafer may have non-uniformities, resulting in excessive thickness variation during thinning. Furthermore, the temporary adhesive bond may not have sufficient thermal and / or chemical stability when exposed to different processes. For example, the temporary adhesive may degrade when exposed to chemicals used in wafer cleaning, electrochemical deposition (ECD), and / or CMP. Alternatively or additionally, the adhesive may decompose during deposition and / or etching processes (such as chemical vapor deposition (CVD), plasma enhanced CVD, physical vapor deposition, etc.). In addition, when the carrier and adhesive are removed from the device wafer, the device wafer may contain residues from the adhesive, which may require additional cleaning steps. Thus, there remains a need for improved methods and structures for thinning semiconductor devices.

[0017] FIG. 2 is a schematic cross-sectional view of a semiconductor device 10 bonded to a carrier structure 12 according to an embodiment. The carrier structure 12 can serve as a temporary support for the semiconductor device 10 during different processing stages, such as thinning, backside metallization, and / or other processing. The carrier structure 12 can comprise a transparent carrier 14 (e.g., glass), a non-conductive layer 16, a photolysis layer 18, and an opaque blocking layer 20 (e.g., in some embodiments, a metal). The non-conductive layer 16, the photolysis layer 18, and the opaque layer 20 can together define an intervening or intermediate structure 21. The transparent carrier 14 and the non-conductive layer 16 can be bonded along a bonding interface 22. The opaque layer 20 can comprise, for example, titanium and / or tungsten. In some embodiments, an adhesion layer (see FIG. 7A) can be provided between the non-conductive layer 16 and the photolysis layer 18 of the carrier structure 12. For example, a nitride adhesion layer can be disposed between the non-conductive layer 16 and the photolysis layer 18. In the illustrated embodiment, the semiconductor device 10 comprises a silicon device wafer 24. However, the semiconductor device 10 may comprise semiconductor device elements in wafer form or as singulated integrated device die. The semiconductor device 10 may comprise non-conductive field regions 26 and conductive features 28.

[0018] In the illustrated embodiment, the transparent carrier 14 comprises a glass carrier. The transparent carrier 14 may comprise any suitable material that is transparent to the wavelength range of light incident on the transparent carrier 14. For example, the transparent carrier 14 may comprise an ultraviolet (UV) transparent carrier. In some embodiments, the transparent carrier 14 may be directly bonded to the non-conductive layer 16. Using direct bonding techniques to bond the transparent carrier 14 and the non-conductive layer 16 allows for reliable bonding while minimizing total thickness variation (TTV). In the illustrated embodiment, the non-conductive layer 16 comprises an inorganic dielectric layer such as silicon oxide, e.g., a low temperature oxide (LTO) layer. In some embodiments, the non-conductive layer 16 of the carrier structure 14 may comprise a dielectric bonding layer such as silicon oxide, silicon oxynitride, silicon nitride, silicon oxycarbonitride. The non-conductive layer 16 may be relatively thin, e.g., less than 300 nm.

[0019] In the illustrated embodiment, the photodecomposition layer 18 comprises a photodecomposition polymer layer and the opaque layer comprises a metal layer. The photodecomposition layer 18 can have a thickness ranging from 100 nm to 1 μm, or from 100 nm to 500 nm. The metal layer can have a thickness ranging from 20 nm to 100 nm. In some embodiments, the photodecomposition layer 18 can comprise any suitable photodecomposition material. As shown in FIG. 2, the photodecomposition layer 18 can be exposed to UV light (e.g., a UV laser) through the transparent carrier 14. The photodecomposition layer 18 can react with the UV light to separate the non-conductive layer 16 of the carrier structure 12 from the opaque layer 20. The photodecomposition material is a material that includes a compound that can be broken down or decomposed by photons. Sufficient photon energy can be provided to decompose the photodecomposition material. Light with an energy higher than that of visible light may be more suitable for providing sufficient photon energy than light with wavelengths below visible light. In various embodiments disclosed herein, UV light, X-rays, and gamma rays can be used to decompose the photodecomposition material. Separation of the non-conductive layer from the opaque layer 20 using a photodecomposable material can be accomplished without the application of external pressure or heat.

[0020] By removing the transparent carrier 14 after processing the semiconductor element 10, the semiconductor element 10 is free to expand laterally. For larger dies with very fine bonding pitch applications, appropriate dimensional compensation can be applied to precisely align the semiconductor element 10 to other semiconductor elements having different thicknesses. For example, dimensional compensation techniques disclosed throughout U.S. Patent Application No. 17 / 206,725, filed March 19, 2021, which is incorporated herein by reference in its entirety for all purposes, can be used to improve alignment.

[0021] 3A to 3H illustrate a manufacturing process for producing a bonded structure according to an embodiment. Unless otherwise noted, the components of FIGS. 3A to 3H may be the same or substantially similar to the analogous components disclosed herein, such as those shown in FIG. 2. The various bonding stages may utilize non-conductive-to-non-conductive direct bonding techniques described above. For example, such direct bonding may allow for minimal thickness variation, spontaneous bonding at room temperature for relatively high bonding machine throughput, and annealing at relatively low temperatures to achieve the desired bond strength for processing of the bonded wafers, such as mechanical grinding and CMP. The bonded structure may withstand relatively high process temperatures (e.g., 350° C. for PECVD oxide deposition). Room temperature bonding and low temperature annealing are advantageous for temperature sensitive components, such as dynamic random access memory (DRAM). For products with higher temperature resistance, high process temperature capability allows for deposition of relatively high quality dielectrics in the backside assembly process. As described below, the manufacturing process may include delamination using a photolytic layer, which allows for delamination of sensitive areas with minimal risk of damage.

[0022] In FIG. 3A, a structure having a photodecomposition layer 18 (e.g., a photodecomposition polymer layer), an opaque layer 20 (e.g., a metal layer), and a non-conductive layer 16 (e.g., a dielectric layer) can be provided. The structure of FIG. 3A can be referred to as an intervening structure or intermediate structure 21′. The structure of FIG. 3A can be disposed on a transparent carrier 14 (e.g., a glass carrier wafer) as shown in FIG. 3B. In some embodiments, the structure can be formed on a glass carrier wafer. In some embodiments, the structure can be formed layer by layer. For example, the photodecomposition layer 18 (e.g., a photodecomposition polymer layer) can be deposited on the surface of the transparent carrier 14 (e.g., a glass carrier wafer). Before depositing the photodecomposition layer 18, the transparent carrier 14 can be polished, for example, by chemical mechanical polishing (CMP). The photodecomposition layer 18 can be cured after the deposition process. The opaque layer 20 (e.g., a metal layer) can be deposited over the photodecomposition polymer layer 18. The non-conductive layer 16 (e.g., an oxide layer) can be deposited over the metal layer.

[0023] The photodecomposition layer 18 may comprise any suitable decomposition layer capable of decomposing in response to exposure to light. For example, the decomposition layer may decompose in response to ultraviolet (UV) light. The transparent carrier 14 may comprise any transparent support structure transparent to a range of wavelengths capable of decomposing the decomposition layer. The opaque layer 20 may comprise any suitable blocking layer capable of blocking at least a portion of the light. For example, the blocking layer may comprise a metallic opaque layer. In some embodiments, the non-conductive layer 16 may comprise any suitable non-conductive layer or bonding layer. For example, the non-conductive layer 16 may comprise an organic dielectric layer such as silicon oxide, e.g., a low temperature oxide (LTO) layer.

[0024] As shown in Figure 3B, the structure shown in Figure 3A and the transparent carrier 14 together can define a carrier structure 12'. The surface 16a of the non-conductive layer 16 can be prepared for bonding. For example, the surface 16a of the non-conductive layer 16 can be prepared for direct bonding. In some embodiments, the surface 16a can have a surface roughness of less than 15 Å (rms), less than 10 Å (rms), or less than 5 Å (rms).

[0025] In FIG. 3C, a semiconductor device 10 can be prepared. The semiconductor device 10 can include a device portion 24 and a non-conductive material 26 disposed on the device portion. The semiconductor device 10 can also include conductive features 28, which can include through-silicon vias (TSVs) 32 extending from the front side 24a through at least a portion of the device portion 24 and through at least a portion of the non-conductive material 26, a routing layer 34 in the non-conductive material, a via 36 in the non-conductive material, and a contact pad 38 in the non-conductive material. The TSVs 32, the routing layer 34, the via 36, ​​and the contact pad 38 can be electrically connected to each other. There can be additional TSVs (not shown) across the back side 24b opposite the front side 24a of the device portion 24.

[0026] The conductive features 28 may be formed by any suitable method. In some embodiments, the conductive features 28 may be formed by a multiple damascene process. For example, the routing layer 34 may be formed by a single damascene process, and the vias 36 and contact pads 38 may be formed by a dual damascene process. The conductive features 28 may comprise copper, in some embodiments. In some embodiments, the non-conductive material 26 may comprise a standard interconnect line (BEOL) dielectric. For example, the non-conductive material 26 may comprise tetraethoxysilane (TEOS), such as TEOS at 400° C. In some embodiments, the semiconductor device 10 may have a thickness in the range of 2 μm to 800 μm.

[0027] In FIG. 3D, a carrier structure 12′ comprising a transparent carrier 14 (e.g., a glass carrier wafer) and an intermediate structure (a photodecomposition layer 18 (e.g., a photodecomposition polymer layer), an opaque layer 20 (e.g., a metal layer), and a non-conductive layer 16 (e.g., an oxide layer)) and a semiconductor device 10 can be bonded together. In some embodiments, the oxide layer of the intermediate layer and the non-conductive material 26 of the semiconductor device 10 can be directly bonded together without an adhesive. The carrier structure 12′ and the semiconductor device 10 can be directly bonded together at room temperature. The bonded carrier structure 12′ and the semiconductor device 10 can be annealed at a low temperature, such as, for example, a temperature of 50° C. to 150° C., 100° C. to 200° C., 125° C. to 200° C., 100° C. to 175° C., or 125° C. to 175° C. After the carrier structure 12′ and the semiconductor device 10 are bonded together, at least a portion of the silicon wafer can be removed (e.g., thinned). For example, the silicon wafer can be thinned by grinding, CMP, and / or plasma etching to expose the TSVs 32. In some embodiments, after thinning the silicon wafer, the semiconductor device 10 can have a thickness of less than 100 μm, less than 50 μm, less than 10 μm, 5 μm or less, or 2 μm or less. In some embodiments, the silicon wafer can be thinned to have a total thickness variation (TTV) of 5 μm or less. In some embodiments, the silicon wafer can be thinned to have a total thickness variation (TTV) of 2 μm or less. The bonding surface between the semiconductor device 10 and the non-conductive layer 16 has a sub-nm roughness before bonding, and the thickness of the bonding interface is close to zero, minimizing thickness variation during backside processing. The TTV in this case is primarily affected by the grinding process, not the temporary bonding process.

[0028] In FIG. 3E, additional non-conductive material (non-conductive layer 46) may be formed over the thinned portion of the silicon wafer (backside 24b of device portion 24). In some embodiments, backside 24b of device portion 24 may be background, etched, and / or polished prior to forming non-conductive layer 46. Conductive features 48, such as electrical interconnect structures, may be formed in non-conductive layer 46. Conductive features 48 may include routing layers 54, vias 56, and contact pads 58 may be formed in non-conductive layer 46. Conductive features 48 may be formed by the same or similar methods as conductive features 28. In some embodiments, TSVs 32 may couple conductive features 28, 48.

[0029] In FIG. 3F, a structure including a semiconductor device 10 and a carrier structure 12′ shown in FIG. 3E and a structure including a semiconductor device 60 and a carrier structure 62 are bonded together to form a bonded structure. Unless otherwise noted, the components of the semiconductor device 60 and the carrier structure 62 can be the same or substantially similar to the similar components disclosed herein. The bonded semiconductor devices 10, 60 can define a bonded semiconductor structure. The semiconductor device 60 includes a device portion 74 having a front side 74a and a back side 74b, a non-conductive layer 76 on the front side 74a of the device portion 74, a conductive feature 78 formed in the non-conductive layer 76, a non-conductive layer 96 on the back side 74b of the device portion 74, a conductive feature 98 formed in the non-conductive layer 96, and a TSV 82 that can electrically couple the conductive features 78, 98. The conductive feature 78 can include a routing layer 84, a via 86, and a contact pad 88. The conductive features 98 may include a routing layer 104, vias 106, and contact pads 108. The carrier structure 62 may include a transparent carrier 64, a non-conductive layer 66, a photolytic layer 68, and an opaque layer 70.

[0030] In some embodiments, semiconductor device 10 and semiconductor device 60 may be bonded directly to one another without an intervening adhesive. For example, non-conductive layer 46 and corresponding portions of non-conductive layer 96 may be bonded directly to one another without an intervening adhesive, and contact pad 58 may be bonded directly to corresponding contact pad 108 without an intervening adhesive.

[0031] Similar to photodegradable layer 18, photodegradable layer 68 may comprise any suitable degradable layer capable of decomposing in response to exposure to light. For example, the degradable layer may decompose in response to ultraviolet (UV) light. Transparent carrier 64 may comprise any transparent support structure that is transparent to a range of wavelengths capable of decomposing the degradable layer. Opaque layer 70 may comprise any suitable blocking layer capable of blocking at least a portion of the light.

[0032] In Figures 3G and 3H, one of the glass carrier wafers can be removed by exposing the photolysis layer to light. For example, as shown in Figure 3G, the photolysis layer 68 can be exposed to light (e.g., UV light) through the transparent carrier 64. As shown in Figure 3H, the transparent carrier 64 can be removed. The non-conductive layer 66 and the opaque layer 70 can be removed. For example, the non-conductive layer 66 and the opaque layer 70 can be removed by CMP. In some embodiments, the front side 60a of the semiconductor device 60 can be prepared for direct bonding. For example, the front side 60a of the semiconductor device 60 can be polished by CMP to a surface roughness of less than 15 Å (rms), less than 10 Å (rms), or less than 5 Å (rms). In some embodiments, the transparent carrier 14 can be removed from the semiconductor device 10. Additional layers can be added to the bonded semiconductor devices 10 and 60 by repeating process steps 3F through 3H. Additionally, not shown, the carrier 14 can be removed by exposing the photolysis layer 18 to light (e.g., UV light).

[0033] 4A to 4F show a general process for bonding multiple devices (e.g., a first device 110 and a second device 114) according to embodiments. Various embodiments of the process disclosed herein can enable parallel processing, such as, for example, wafer thinning and backside assembly. In other words, in contrast to a sequential process that includes wafer thinning and backside assembly steps after bonding a wafer or die to another wafer or die, the process disclosed herein can perform separate wafer thinning and backside assembly steps on a wafer before bonding the wafer or die. Thus, in the case of die-to-wafer or die-to-die bonding, the process disclosed herein can select a qualified wafer or qualified die before bonding the die. The wafer thinning process disclosed herein can improve yields because if a wafer is damaged during the wafer thinning process disclosed herein, only the damaged wafer is discarded, in contrast to conventional processes that use a sequential wafer stacking process in which the entire stack of wafers is discarded if a wafer in the stack is damaged.

[0034] For example, as shown in FIG. 4A, a first device 110 can be bonded to a carrier structure 112. In FIG. 4B, the first device 110 can be processed (e.g., thinned) to define a first processed device 110'. In some embodiments, processing the first device 110 can include forming a bonding layer (or other back-end interconnect (BEOL) layer) on the thinned device. For example, in FIG. 4B, the bonding layer can be polished to prepare an exposed surface of the device 110' for direct hybrid bonding. In parallel or sequentially, as shown in FIG. 4C, a second device 114 can be bonded to a carrier structure 116. In FIG. 4D, the second device 114 can be processed (e.g., thinned and / or provided with a bonding layer or other BEOL layer) to define a second processed device 114'. In FIG. 4E, the first processed device 110' and the second processed device 114' can be bonded directly to each other. In Figure 4F, the carrier structures 112, 116 can be removed. Any of the principles and advantages disclosed herein, such as the use of a photolytic layer for release, a thinning process using CMP, and a direct bonding technique for bonding, can be implemented in one or more of the steps used in Figures 4A through 4F. Additional layers can be added by repeating the steps shown in Figures 3F through 3H.

[0035] 5A through 5D illustrate a manufacturing process for producing singulated die according to an embodiment. In some cases, the manufacturing process illustrated in FIGs. 5A through 5D can be utilized in die-to-wafer applications.

[0036] In FIG. 5A, a structure 120, the same as or similar to the structure shown in FIG. 3E, is bonded to an adapter plate 122. A dicing tape 124 can be provided between the structure and the adapter plate 122. A dicing frame 126 can be placed over the dicing tape 124. In some embodiments, the adapter plate 122, the dicing tape 124, and the dicing frame 126 can be bonded together with clamps (not shown). In FIG. 5B, the transparent carrier 14 (e.g., a glass carrier wafer) can be removed by any suitable method as disclosed herein. In FIG. 5C, the opaque layer 20 (e.g., a metal layer) and the non-conductive layer 16 (e.g., an oxide layer) can be removed. In some embodiments, the residue of the photolysis layer 18 (e.g., a photolysis polymer layer) can be removed by plasma ashing. In some embodiments, the opaque layer 20 can be removed by wet etching. In some embodiments, the opaque layer 20 and the non-conductive layer 16 can be removed by chemical mechanical polishing (CMP). Other materials such as adhesive residues present on or near the front side 10a of the semiconductor device 10 may be removed. For example, polymer residues remaining from adhesives for temporary bonding may be cleaned, for example, by CMP. Portions of the non-conductive material 26 and / or portions of the conductive features 28 may be polished by CMP for direct bonding. The adapter plate 122 may serve as a support for the polishing step. After CMP, the adapter plate 122 may be removed. In FIG. 5D, the semiconductor device 10 may be singulated into a plurality of device dies 130. In some embodiments, the semiconductor device 10 may be singulated into a plurality of device dies 130 by mechanical sawing, laser stealth die cutting, or plasma die cutting. In some embodiments, a protective coating may be added to the top surface of the non-conductive layer 26 and the contact pads 38 to prevent surface contamination during singulation. In some embodiments, the semiconductor device 10 may be singulated with the carrier structure 12′. In such embodiments, the singulation step may occur prior to FIG. 5D, for example, in FIG. 5A.

[0037] 6A-6C illustrate a manufacturing process for fabricating a reconstituted wafer according to an embodiment. In some cases, the manufacturing process illustrated in FIG. 6A-6D can be utilized for reconstituted wafer applications.

[0038] FIG. 6A shows a carrier structure 12′ comprising a transparent layer 14 (e.g., a glass carrier wafer), a photodecomposition layer 18 (e.g., a photodecomposition polymer layer), an opaque layer 20 (e.g., a metal layer), and a non-conductive layer 16 (e.g., an oxide layer), and a device die 132 mounted on the oxide layer of the carrier structure. For example, as shown in FIG. 6A, a first die 132a, a second die 132b, and a third die 132c can be mounted on the non-conductive layer 16. The first to third dies 132a to 132c can be directly bonded to the non-conductive layer 16 without an adhesive. A molding material 134 can be provided around the device dies 132a to 132c over the oxide layer. The device dies 132a to 132c can be bonded to the oxide layer to prevent or reduce the device dies 132a to 132c from moving during the molding process. The device dies 132a to 132c can comprise semiconductor elements comprising a non-conductive material disposed on a device portion. In FIG. 6B, the transparent carrier 14 (e.g., a glass carrier wafer) can be removed by any suitable method disclosed herein. In FIG. 6C, the non-conductive layer 16 (oxide layer), the opaque layer 20 (metal layer), and the residue of the photodecomposition layer 18 (photodecomposition polymer layer) can be removed by any suitable method disclosed herein. The structure shown in FIG. 6C can comprise a reconstituted wafer 131. As shown in FIG. 6D, a redistribution layer (RDL) 136 and electrical contact pads (e.g., which can be connected to solder balls 138) can be provided to the reconstituted wafer 131. The RDL 136 can comprise multiple layers having electrical routing structures (not shown). The RDL 136 can have lateral traces to provide electrical communication between any or all of the dies 132a to 132c and / or to provide electrical communication between the dies 132a to 132c and the solder balls 138. Reconstructed wafer 131 may be electrically connected to an external device, system, or substrate (not shown) through RDLs 136 and solder balls 138. In some embodiments, reconstructed wafer 131 may be diced. Any of the carrier structures disclosed herein, such as carrier structures 12, 12″, may be used in place of carrier structure 12′.

[0039] Figures 7A through 7H illustrate a manufacturing process for producing a singulated die according to an embodiment. The manufacturing process of Figures 7A through 7H may be substantially similar to the manufacturing process of Figures 3A through 3H. Unless otherwise noted, the components of Figures 7A through 7H may be the same or substantially similar to the analogous components disclosed herein as shown in Figures 3A through 3H.

[0040] In FIG. 7A, a semiconductor device 10 and an intermediate or intermediate structure 140 on the semiconductor device 10 may be provided. The semiconductor device 10 in FIG. 7A may be the same as or similar to the semiconductor device 10 shown in FIG. 3C. The intermediate structure 140 in FIG. 7A may comprise a non-conductive layer 16, a photolysis layer 18, an opaque blocking layer 20, and an adhesion layer 142. The opaque layer 20 may comprise a metal layer (e.g., a titanium layer or a tungsten layer), the photolysis layer 18 may comprise a photolysis polymer layer, and the non-conductive layer 16 may comprise a dielectric layer (e.g., a silicon oxide layer, such as a low temperature oxide (LTO) layer, a plasma enhanced chemical vapor deposition (PECVD) oxide layer). Using an LTO layer for the non-conductive layer 16 may be advantageous when the semiconductor device 10 comprises a temperature sensitive device, such as a dynamic random access memory (DRAM). The formation of the LTO layer may be performed at a temperature lower than 200° C. The intermediate structure 140 of FIG. 7A can have similar structure and / or materials as the intervening or intermediate structures disclosed herein.

[0041] In some embodiments, the intermediate structure 140 can be formed over the semiconductor device 10. For example, a metal layer can be deposited over the semiconductor device 10. A photodecomposed polymer layer can be deposited over the metal layer. An adhesion layer 142 (e.g., a nitride layer) can be deposited over the photodecomposed polymer layer. An LTO layer can be deposited over the adhesion layer 142.

[0042] In FIG. 7B, a transparent carrier 14 (e.g., a glass carrier wafer) can be bonded to a non-conductive layer 16 (e.g., an LTO layer). The intermediate structure 140 and the transparent carrier 14 together can define the carrier structure 12′. In some embodiments, the glass carrier wafer can be bonded directly to the LTO layer without an intervening adhesive. For example, the transparent carrier 14 and the non-conductive layer 16 can be bonded directly to each other at room temperature. The bonded transparent carrier 14 and the non-conductive layer 16 can be annealed at a low temperature, such as, for example, a temperature of 50° C. to 150° C., 100° C. to 200° C., 125° C. to 200° C., 100° C. to 175° C., or 125° C. to 175° C. In FIG. 7C, the semiconductor device 10 can be processed to expose the TSVs 32. In some embodiments, a non-conductive layer 46 can be formed over the backside 24b of the device portion 24 of the semiconductor device 10. The non-conductive layer 46 can be prepared for direct bonding. In Figure 7D, semiconductor device 10 may be processed to form routing layers 54, vias 56, and contact pads 58. The steps illustrated in Figures 7C and 7D may be similar to the steps described with respect to Figure 3E, for example.

[0043] In FIG. 7E, the semiconductor device 10 can be mounted on a dicing tape 124. In FIG. 7F, the transparent carrier 14 (e.g., glass carrier wafer) can be removed. The glass carrier wafer can be removed by any suitable method disclosed herein. In FIG. 7G, the residue of the photodecomposition layer 18 (e.g., photodecomposition polymer layer) and the opaque layer 20 (e.g., metal layer) can be removed. In some embodiments, the residue of the photodecomposition polymer layer can be removed by plasma ashing. In some embodiments, the metal layer can be removed by wet etching. In FIG. 7H, the semiconductor device 10 can be singulated into a plurality of device dies 150. In some embodiments, the semiconductor device 10 can be singulated into a plurality of device dies 150 by mechanical sawing, laser stealth dice cutting, or plasma dice cutting. In some embodiments, a protective coating can be added to the top surface of the non-conductive layer 26 and the contact pads 38 to prevent surface contamination during singulation.

[0044] In one aspect, a method for processing a semiconductor device is disclosed. The method can include providing a semiconductor device. The semiconductor device has a first non-conductive material. The first non-conductive material is disposed on a device portion of the semiconductor device. The method can include providing a transparent carrier. The method can include providing an intervening structure in which a second non-conductive material, a photodecomposition layer, and an opaque layer are stacked on top of each other. The method can include forming a bonding structure such that the second non-conductive material is directly bonded to the first non-conductive material or the transparent carrier. The intervening structure is disposed between the semiconductor device and the transparent carrier. The method can include separating the transparent carrier from the semiconductor device by exposing the photodecomposition layer to light through the transparent carrier such that the light decomposes the photodecomposition layer.

[0045] In one embodiment, the method further includes processing the semiconductor element after forming the bond structure and before separating the transparent carrier from the semiconductor element. The processing can include polishing a portion of the semiconductor element by chemical mechanical polishing. The processing can include forming a non-conductive layer such that a device portion of the semiconductor element is disposed between the first non-conductive material and the non-conductive layer, and forming conductive features in or with the non-conductive layer.

[0046] In one embodiment, the opaque layer is disposed between the second non-conductive material and the photodecomposition layer, and the method includes directly bonding the second non-conductive material to the first non-conductive material. The intervening structure can be disposed on a transparent carrier prior to bonding.

[0047] In one embodiment, the photodecomposition layer is disposed between the second non-conductive material and the opaque layer. The opaque layer can be deposited on the first non-conductive material of the semiconductor device prior to bonding. The intervening structure can further comprise an adhesive layer between the second non-conductive material and the photodecomposition layer.

[0048] In one embodiment, the light comprises UV light. The UV light may comprise a UV laser.

[0049] In one embodiment, the photodegradable layer comprises a photodegradable polymer layer.

[0050] In one embodiment, the opaque layer comprises a metal layer. A surface of the metal layer facing the transparent layer may comprise a reflective surface. The metal layer may comprise titanium. The metal layer may have a thickness in the range of 20 nm to 100 nm.

[0051] In one embodiment, the method further includes removing a portion of the semiconductor element from a side of the semiconductor element facing away from the transparent layer. The removing may include grinding, wet chemical etching, dry etching, plasma etching, or polishing. The removing may include thinning the semiconductor element to a thickness of less than 100 μm. The removing may include thinning the semiconductor element to a thickness of less than 50 μm. The removing may include thinning the semiconductor element to a thickness of less than 10 μm. The removing may include thinning the semiconductor element to have a total thickness variation of 5 μm or less. The removing may include thinning the semiconductor element to have a total thickness variation of 2 μm or less.

[0052] In one embodiment, the method further includes directly bonding the second semiconductor element to the semiconductor element such that the semiconductor element is disposed between the intermediate layer and the second semiconductor element. The directly bonding can include directly bonding a first non-conductive material to a third non-conductive material of the second semiconductor element and directly bonding a first conductive feature of the semiconductor element to a second conductive feature of the second semiconductor element. The method can further include directly bonding the second intermediate layer to the second semiconductor element and bonding the second transparent layer to the intermediate layer such that the intermediate layer is disposed between the second semiconductor element and the second transparent layer. The separating can be performed after directly bonding the second semiconductor element to the semiconductor element.

[0053] In one embodiment, the method further includes bonding the semiconductor device to the dicing frame such that the semiconductor device is disposed between the transparent carrier and the dicing frame. The method can further include singulating the semiconductor device into a plurality of singulated integrated device dies. The semiconductor device can include a semiconductor wafer.

[0054] In one embodiment, the first non-conductive material comprises a dielectric layer. The second non-conductive material may comprise a silicon oxide layer.

[0055] In one embodiment, the transparent layer comprises a glass carrier wafer.

[0056] In one embodiment, the method further comprises removing the opaque layer.

[0057] In one embodiment, the photodegradative layer has a thickness in the range of 100 nm to 1 μm. The photodegradative layer can have a thickness in the range of 100 nm to 500 nm.

[0058] In one embodiment, the method further includes coupling the semiconductor element to the adapter plate and removing the second non-conductive material. The semiconductor element and the adapter plate can be bonded after forming the bonded structure, and the second non-conductive material can be removed after separating the transparent carrier from the semiconductor element. The method can further include polishing the semiconductor element by chemical mechanical polishing for direct bonding after removing the second non-conductive material.

[0059] In one aspect, a carrier structure for temporary bonding is disclosed. The carrier can include a transparent carrier, a photolysis layer over the transparent carrier, an opaque layer over the photolysis layer, and a non-conductive layer having a first side and a second side. The first side is disposed over the opaque layer, and the second side is prepared for direct bonding to a semiconductor device.

[0060] In one embodiment, the transparent carrier comprises a glass carrier.

[0061] In one embodiment, the photodegradable layer comprises an ultraviolet (UV) photodegradable polymer layer.

[0062] In one embodiment, the photodegradable layer is a deposition layer.

[0063] In one embodiment, the photodegradable layer has a thickness in the range of 100 nm to 1 μm.The photodegradable layer has a thickness in the range of 100 nm to 500 nm.

[0064] In one embodiment, the opaque layer comprises a metal layer. A surface of the metal layer facing the transparent layer may comprise a reflective surface. The metal layer may comprise titanium. The metal layer may have a thickness in the range of 20 nm to 100 nm.

[0065] In one embodiment, the opaque layer is a deposited layer.

[0066] In one embodiment, the non-conductive layer comprises a silicon oxide layer.

[0067] In one embodiment, the non-conductive layer is a deposition layer.

[0068] In one embodiment, a method for manufacturing an electronic component is disclosed. The method can include providing a bonding structure on a diced tape. The bonding structure includes a semiconductor element having a device portion, a transparent carrier bonded to the semiconductor element, and an intermediate structure between the semiconductor element and the transparent carrier. The intermediate structure includes a photodecomposition layer. The semiconductor element has a first side facing the diced tape and a second side facing the transparent carrier. The method can include separating the transparent carrier from the semiconductor element by exposing the photodecomposition layer to light through the transparent carrier such that the light decomposes the photodecomposition layer. The method can include polishing the semiconductor element from the second side after the separating step.

[0069] In one embodiment, the semiconductor element is polished from the second side while the semiconductor element is adhered to the dicing tape.

[0070] In one embodiment, polishing the semiconductor device includes removing adhesion residues.

[0071] In one embodiment, the method further includes processing the semiconductor element prior to providing the bonding structure on the diced tape. Processing the semiconductor element can include bonding the semiconductor element to a transparent carrier and processing the semiconductor element to define a first side of the semiconductor element. Processing the semiconductor element can include thinning the semiconductor element and fabricating a conductive structure at or near the first side of the semiconductor element while the semiconductor element and the transparent carrier are bonded.

[0072] In one embodiment, the method further comprises singulating die from the semiconductor device. The singulating comprises sawing, stealth dice cutting, or plasma dice cutting.

[0073] In one embodiment, the method further comprises removing residues of the photolytic layer by plasma ashing after the step of removing the transparent carrier.

[0074] In one embodiment, the intermediate structure further comprises an opaque layer disposed between the semiconductor device and the photodecomposition layer. The method may further comprise removing the opaque layer by selective etching after the step of removing the transparent carrier.

[0075] In one embodiment, a bonding structure is disclosed. The bonding structure can include a semiconductor device having a first non-conductive material. The first non-conductive material is disposed on a device portion of the semiconductor device. The bonding structure can include an opaque layer over the first non-conductive material, a photolysis layer over the opaque layer, and a second non-conductive layer over the photolysis layer. The second non-conductive layer has a first side disposed over the photolysis layer and a second side opposite the first side. The second side is prepared for direct bonding to another device.

[0076] In one embodiment, the semiconductor device comprises a silicon device wafer.

[0077] In one embodiment, the semiconductor element has a thickness of less than 100 μm, less than 50 μm, or less than 10 μm.

[0078] In one embodiment, the bonding structure further comprises a transparent carrier bonded to the second side of the second non-conductive layer. The transparent carrier comprises a glass carrier.

[0079] In one embodiment, the photodegradable layer comprises an ultraviolet (UV) photodegradable polymer layer.

[0080] In one embodiment, the photodegradable layer is a deposition layer.

[0081] In one embodiment, the photodegradative layer has a thickness in the range of 100 nm to 1 μm.

[0082] In one embodiment, the opaque layer comprises a metal layer. A surface of the metal layer facing the transparent layer may comprise a reflective surface. The metal layer may comprise titanium.

[0083] In one embodiment, the metal layer has a thickness in the range of 20 nm to 100 nm.

[0084] In one embodiment, the opaque layer is a deposited layer.

[0085] In one embodiment, the second non-conductive layer comprises a silicon oxide layer.

[0086] In one embodiment, the second non-conductive layer is a deposition layer.

[0087] In one embodiment, the bonded structure further comprises an adhesive layer between the photodegradable layer and the second non-conductive layer.

[0088] In one aspect, a method of forming a peelable structure having a semiconductor element, a transparent carrier, and an intervening structure between the semiconductor element and the transparent carrier is disclosed. The semiconductor element has a first non-conductive material disposed on a device portion of the semiconductor element. The intervening structure includes a second non-conductive material, a photodecomposition layer, and an opaque layer. The method can include forming a bonding structure such that the second non-conductive material is directly bonded to the first non-conductive material or the transparent carrier. The intervening structure is disposed between the semiconductor element and the transparent carrier. The photodecomposition layer is configured to decompose in response to exposure to light.

[0089] In one embodiment, a method for fabricating a semiconductor device is disclosed. The method can include providing a carrier structure having a first side and a second side opposite the first side. The carrier structure includes a transparent carrier positioned closer to the first side than the second side. A photodecomposition layer is positioned between the transparent carrier and the second side. The method can include bonding a device die to the second side of the carrier structure, providing a molding material at least partially over the device die, and removing the transparent carrier by exposing the photodecomposition layer to light through the transparent carrier such that the light decomposes the photodecomposition layer.

[0090] In one embodiment, the carrier structure further comprises a non-conductive layer at least partially defining the second side. The device die can be directly bonded to the non-conductive layer without an intervening adhesive. The transparent carrier can at least partially define the first side of the carrier structure. The carrier structure further comprises an opaque layer between the photolysis layer and the non-conductive layer. The method can further comprise removing the opaque layer and the non-conductive layer after the step of removing the transparent carrier, thereby forming a reconstituted wafer. The method can further comprise forming a redistribution layer on the reconstituted wafer.

[0091] In one aspect, a method of processing a semiconductor device is disclosed. The method can include providing a first bonding structure having a first semiconductor device over a first carrier structure. The first semiconductor device has a first side on the first carrier structure and a second side opposite the first side. The method can include thinning the first semiconductor device from the second side of the first semiconductor device while the first semiconductor device is on the first carrier structure. The method can include providing a second bonding structure having a second semiconductor device over a second carrier structure. The second semiconductor device has a first side on the second carrier structure and a second side opposite the first side. The method can include directly bonding the second side of the first semiconductor device to the second side of the second semiconductor device while the first semiconductor device is on the first carrier structure and the second semiconductor device is on the second carrier structure to form a bonded semiconductor structure. The method may include, after the direct binding step, removing at least one of the first and second support structures from the binding structure.

[0092] In one embodiment, the method may further include thinning the second semiconductor device from a second side of the second semiconductor device while the second semiconductor device is on the second carrier structure.

[0093] In one embodiment, removing at least one of the first and second carrier structures comprises exposing the photolytic layer to light.

[0094] In one embodiment, the method may further include processing a second side of the first semiconductor element while the first semiconductor element is on the first carrier structure. Processing the second side of the first semiconductor element may include forming a bonding layer on the second side of the first semiconductor element after thinning the first semiconductor element. Forming the bonding layer may include forming a non-conductive bonding region and a plurality of contact pads at least partially embedded in the non-conductive bonding region.

[0095] In one embodiment, the first carrier structure includes a transparent carrier and an intermediate structure spanning the transparent carrier. The intermediate structure may include a non-conductive layer, a photodegradable layer, and an opaque layer.

[0096] In one aspect, a method for manufacturing an electronic device is disclosed. The method can include providing a semiconductor element on a dicing tape. The semiconductor element has a device portion and an adhesive residue from separating the carrier structure from the semiconductor element. The semiconductor element has a first side facing the dicing tape and a second side having the adhesive residue. The method can include polishing the semiconductor element from the second side while the semiconductor element is disposed on the dicing tape to remove the adhesive residue.

[0097] In one embodiment, the method further comprises bonding the semiconductor element to a carrier structure. The carrier structure may comprise a transparent carrier and an intermediate structure between the semiconductor element and the transparent carrier. The intermediate structure may comprise a photodecomposition layer. The intermediate structure may further comprise an opaque layer and a dielectric layer.

[0098] In one embodiment, the adhesive residue comprises a residue of a photodecomposition layer of a carrier structure.

[0099] Unless the context clearly indicates otherwise, the words "comprises," "comprising," "including," "including," and the like throughout this specification and claims are to be construed in an inclusive sense, i.e., "including but not limited to," as opposed to a restrictive or inclusive sense. As used generally herein, the word "coupled" refers to two or more elements that are either directly connected or connected through one or more intermediate elements. Similarly, as used generally herein, the word "connected" refers to two or more elements that are either directly connected or connected through one or more intermediate elements. In addition, the words "herein," "above," "below," and words of similar import, when used in this application, refer to this application as a whole and not to any particular portion of this application. Furthermore, as used herein, when a first element is described as being "on" or "over" a second element, the first element can be directly on or over the second element, such that the first and second elements are in direct contact, or the first element can be indirectly on or over the second element, such that there are one or more intervening elements between the first and second elements. Where the context permits, words using the singular or plural in the above detailed description can also include the plural or singular, respectively. The word "or" in connection with a list of two or more items covers all of the following interpretations for that word: any of the items in the list, all of the items in the list, and any and all combinations of the items in the list.

[0100] Additionally, conditional language used herein, such as, among others, "may," "could," "could," "may," "for example," "for example," and "such as," are generally intended to convey that certain embodiments include particular features, elements, and / or conditions, while other embodiments do not, unless specifically stated otherwise or understood otherwise within the context in which they are used. Thus, such conditional language is generally not intended to imply that a feature, element, and / or condition is in any way required for one or more embodiments.

[0101] Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in different other forms, and various omissions, substitutions, and modifications may be made to the forms of the methods and systems described herein without departing from the spirit of the present disclosure. For example, although blocks are presented in a given arrangement, alternative embodiments may perform similar functions using different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of the elements and operations of the various embodiments described above may provide further embodiments. The claims and their equivalents are intended to cover such forms or modifications as fall within the scope and spirit of the present disclosure.

Claims

1. 1. A method for processing a semiconductor device, comprising: providing a semiconductor device having a first non-conductive material disposed on a device portion of the semiconductor device; Providing a transparent carrier; providing an intervening structure in which a second non-conductive material, a photodecomposition layer, and an opaque layer are stacked together; forming a bonding structure such that the second non-conductive material is bonded to the first non-conductive material or directly to the transparent carrier, the intermediate structure being disposed between the semiconductor element and the transparent carrier; separating the transparent carrier from the semiconductor device by exposing the photodecomposition layer to light through the transparent carrier such that the light decomposes the photodecomposition layer; 23. A method comprising:

2. 10. The method of claim 1, further comprising processing the semiconductor device after forming the bond structure and before separating the transparent carrier from the semiconductor device.

3. 3. The method of claim 2, wherein the processing step includes polishing a portion of the semiconductor device by chemical mechanical polishing.

4. 3. The method of claim 2, wherein the processing step includes forming a non-conductive layer such that the device portion of the semiconductor device is disposed between the first non-conductive material and the non-conductive layer, and forming conductive features in or with the non-conductive layer.

5. the opaque layer is disposed between the second non-conductive material and the photodecomposition layer; The method is directly bonding the second non-conductive material to the first non-conductive material; Equipped with 2. The method of claim 1 .

6. The method of claim 5 , wherein the intervening structure is disposed on the transparent carrier prior to the bonding step.

7. The method of claim 1 , wherein the photolytic layer is disposed between the second non-conductive material and the opaque layer.

8. 8. The method of claim 7, wherein the opaque layer is disposed on the first non-conductive material of the semiconductor device prior to the bonding step.

9. 8. The method of claim 7, wherein the intervening structure further comprises an adhesive layer between the second non-conductive material and the photodecomposition layer.

10. The method of claim 1 , wherein the light comprises UV light.

11. The method of claim 10 , wherein the UV light comprises a UV laser.

12. The method of claim 1 , wherein the photodegradable layer comprises a photodegradable polymer layer.

13. The method of claim 1 , wherein the opaque layer comprises a metal layer.

14. 14. The method of claim 13, wherein a surface of the metal layer facing the transparent layer comprises a reflective surface.

15. The method of claim 13 , wherein the metal layer comprises titanium.

16. 14. The method of claim 13, wherein the metal layer has a thickness in the range of 20 nm to 100 nm.

17. 10. The method of claim 1, further comprising removing a portion of the semiconductor element from a side of the semiconductor element facing away from the transparent layer.

18. 20. The method of claim 17, wherein the removing step comprises grinding, wet chemical etching, dry etching, plasma etching, or polishing.

19. 20. The method of claim 17, wherein the removing step comprises thinning the semiconductor device to a thickness of less than 100 [mu]m.

20. 20. The method of claim 19, wherein the removing step comprises thinning the semiconductor device to a thickness of less than 50 [mu]m.

21. 21. The method of claim 20, wherein the removing step comprises thinning the semiconductor device to a thickness of less than 10 [mu]m.

22. 20. The method of claim 17, wherein the removing step comprises thinning the semiconductor device to have a total thickness variation of 5 μm or less.

23. 23. The method of claim 22, wherein the removing step comprises thinning the semiconductor device to have a total thickness variation of 2 μm or less.

24. 10. The method of claim 1, further comprising the step of directly bonding a second semiconductor device to the semiconductor device such that the second semiconductor device is disposed between the intervening layer and the second semiconductor device.

25. 25. The method of claim 24, wherein the directly bonding step comprises: directly bonding the first non-conductive material to a third non-conductive material of the second semiconductor element; and directly bonding a first conductive feature of the semiconductor element to a second conductive feature of the second semiconductor element.

26. 25. The method of claim 24, further comprising the steps of: bonding a second intervening layer directly to the second semiconductor device; and bonding a second transparent layer to the intervening layer such that the intervening layer is disposed between the second semiconductor device and the second transparent layer.

27. 25. The method of claim 24, wherein the step of separating is performed after the step of directly bonding the second semiconductor device to the semiconductor device.

28. 10. The method of claim 1, further comprising the step of coupling the semiconductor element to a dicing frame such that the semiconductor element is disposed between the transparent carrier and the dicing frame.

29. 30. The method of claim 28, further comprising singulating the semiconductor devices into a plurality of singulated integrated device dies.

30. 30. The method of claim 28, wherein the semiconductor device comprises a semiconductor wafer.

31. The method of claim 1 , wherein the first non-conductive material comprises a dielectric layer.

32. 10. The method of claim 1, wherein the second non-conductive material comprises a silicon oxide layer.

33. The method of claim 1 , wherein the transparent layer comprises a glass carrier wafer.

34. 10. The method of claim 1 further comprising removing the opaque layer.

35. 2. The method of claim 1, wherein the photodecomposition layer has a thickness in the range of 100 nm to 1 μm.

36. 36. The method of claim 35, wherein the photodecomposition layer has the thickness in the range of 100 nm to 500 nm.

37. 2. The method of claim 1, further comprising the steps of coupling the semiconductor device to an adapter plate and removing the second non-conductive material.

38. 38. The method of claim 37, wherein the semiconductor element and the adapter plate are joined after forming the bonding structure, and the second non-conductive material is removed after separating the transparent carrier from the semiconductor element.

39. 40. The method of claim 37, further comprising polishing the semiconductor device for direct bonding using chemical mechanical polishing after removing the second non-conductive material.

40. A carrier structure for temporary bonding, comprising: A transparent carrier; a photodecomposition layer over the transparent carrier; an opaque layer over the photodecomposition layer; a non-conductive layer having a first side disposed on the opaque layer and a second side prepared for direct bonding to a semiconductor device; A carrier structure comprising:

41. 41. The carrier structure of claim 40, wherein the transparent carrier comprises a glass carrier.

42. 41. The carrier structure of claim 40, wherein the photodegradable layer comprises an ultraviolet (UV) photodegradable polymer layer.

43. 41. The carrier structure according to claim 40, characterized in that the photodecomposition layer is a deposition layer.

44. 41. The carrier structure according to claim 40, wherein the photodecomposition layer has a thickness in the range of 100 nm to 1 μm.

45. 45. The carrier structure of claim 44, wherein the photodecomposition layer has the thickness in the range of 100 nm to 500 nm.

46. 41. The carrier structure of claim 40, wherein the opaque layer comprises a metal layer.

47. 47. The carrier structure of claim 46, wherein a surface of the metal layer facing the transparent layer comprises a reflective surface.

48. 47. The carrier structure of claim 46, wherein the metal layer comprises titanium.

49. 47. The carrier structure of claim 46, wherein the metal layer has a thickness in the range of 20 nm to 100 nm.

50. 41. The carrier structure of claim 40, wherein the opaque layer is a deposition layer.

51. 41. The carrier structure of claim 40, wherein the non-conductive layer comprises a silicon oxide layer.

52. 41. The carrier structure of claim 40, wherein the non-conductive layer is a deposition layer.

53. 1. A method of manufacturing an electronic component, comprising: providing a bonding structure on a dicing tape, the bonding structure including a semiconductor element having a device portion, a transparent carrier coupled to the semiconductor element, and an intermediate structure between the semiconductor element and the transparent carrier, the intermediate structure including a photodecomposition layer, and the semiconductor element having a first side facing the dicing tape and a second side facing the transparent carrier; separating the transparent carrier from the semiconductor device by directing light through the transparent carrier onto the photodecomposition layer such that the light decomposes the photodecomposition layer; polishing the semiconductor device from the second side after the separating step; 23. A method comprising:

54. 54. The method of claim 53, wherein the semiconductor element is polished from the second side while the semiconductor element is bonded to the diced tape.

55. 55. The method of claim 54, wherein polishing the semiconductor device includes removing adhesion residues.

56. The method further comprises the step of processing the semiconductor element before the step of providing the bonding structure on the die cut tape; The step of processing the semiconductor device includes: connecting the semiconductor device to the transparent carrier; processing the semiconductor device to define the first side of the semiconductor device; Equipped with 54. The method of claim 53.

57. 57. The method of claim 56, wherein processing the semiconductor element comprises thinning the semiconductor element while the semiconductor element and the transparent carrier are coupled together and fabricating a conductive structure at or near the first side of the semiconductor element.

58. 54. The method of claim 53, further comprising singulating a die from the semiconductor device.

59. 60. The method of claim 58, wherein the singulating step comprises sawing, stealth dicing, or plasma dicing.

60. 54. The method of claim 53, further comprising removing residue of the photolytic layer using plasma ashing after the transparent carrier is removed.

61. the intermediate structure further comprising an opaque layer disposed between the semiconductor device and the photolytic layer; The method is removing the opaque layer using selective etching after the transparent carrier is removed; Further comprising:

54. The method of claim 53.

62. a semiconductor device having a first non-conductive material disposed on a device portion of the semiconductor device; an opaque layer over the first non-conductive material; and a photodecomposition layer over said opaque layer; a second non-conductive layer over the photolytic layer, the second non-conductive layer having a first side disposed on the photolytic layer and a second side opposite the first side, the second side being prepared for direct bonding to another device; A bonding structure comprising:

63. 63. The structure of claim 62, wherein the semiconductor device comprises a silicon device wafer.

64. 63. The structure of claim 62, wherein the semiconductor element has a thickness of less than 100 μm, less than 50 μm, or less than 10 μm.

65. 63. The structure of claim 62, further comprising a transparent carrier bonded to the second side of the second non-conductive layer, the transparent carrier comprising a glass carrier.

66. 63. The bond of claim 62, wherein the photodegradable layer comprises an ultraviolet (UV) photodegradable polymer layer.

67. 63. The structure of claim 62, wherein the photodecomposition layer is a deposition layer.

68. 63. The structure of claim 62, wherein the photodecomposition layer has a thickness in the range of 100 nm to 1 μm.

69. 63. The structure of claim 62, wherein the opaque layer comprises a metal layer.

70. 70. The structure of claim 69, wherein a surface of the metal layer facing the transparent layer comprises a reflective surface.

71. 70. The bond of claim 69, wherein the metal layer comprises titanium.

72. 63. The structure of claim 62, wherein the metal layer has a thickness in the range of 20 nm to 100 nm.

73. 63. The bonded structure of claim 62, wherein the opaque layer is a deposition layer.

74. 63. The structure of claim 62, wherein the second non-conductive layer comprises a silicon oxide layer.

75. 63. The bond structure of claim 62, wherein the second non-conductive layer is a deposition layer.

76. 63. The bond of claim 62, further comprising an adhesive layer between said photodecomposition layer and said second non-conductive layer.

77. 1. A method for forming a peelable structure having a semiconductor element, a transparent carrier, and an intervening structure between the semiconductor element and the transparent carrier, the semiconductor element having a first non-conductive material disposed on a device portion of the semiconductor element, the intervening structure including a second non-conductive material, a photodecomposition layer, and an opaque layer, comprising: forming a bonding structure such that the second non-conductive material is bonded to the first non-conductive material or directly to the transparent carrier, and the interposer structure is disposed between the semiconductor element and the transparent carrier; Equipped with the photodegradable layer is configured to degrade in response to exposure to light; A method comprising:

78. 1. A method for processing a semiconductor device, comprising: providing a carrier structure having a first side and a second side opposite the first side, the carrier structure including a transparent carrier positioned closer to the first side than to the second side, and a photodecomposition layer positioned between the transparent carrier and the second side; coupling a device die to the second side of the carrier structure; applying a molding material at least partially over the device die; removing the transparent carrier by exposing the photodecomposition layer to light through the transparent carrier such that the light decomposes the photodecomposition layer; 23. A method comprising:

79. the carrier structure further includes a non-conductive layer at least partially defining the second side; the device die is bonded directly to the non-conductive layer without an intervening adhesive, and the transparent carrier at least partially defines the first side of the carrier structure.

79. The method of claim 78.

80. 80. The method of claim 79, wherein the carrier structure further comprises an opaque layer between the photodecomposition layer and the non-conductive layer.

81. 81. The method of claim 80, further comprising, after removing the transparent carrier, removing the opaque layer and the non-conductive layer, thereby forming a reconstituted wafer.

82. 82. The method of claim 81 further comprising forming a redistribution layer on the reconfigured wafer.

83. 1. A method for processing a semiconductor device, comprising: providing a first bonding structure having a first semiconductor element on a first carrier structure, the first semiconductor element having a first side on the first carrier structure and a second side opposite the first side; thinning the first semiconductor element from the second side of the first semiconductor element while the first semiconductor element is on the first carrier structure; providing a second bonding structure having a second semiconductor element on a second carrier structure, the second semiconductor element having a first side on the second carrier structure and a second side opposite the first side; while the first semiconductor device is on the first carrier structure and the second semiconductor device is on the second carrier structure, directly bonding the second side of the first semiconductor device to the second side of the second semiconductor device to form a bonded semiconductor structure; removing both the first and second support structures from the binding structure after the direct binding step; 23. A method comprising:

84. 84. The method of claim 83, further comprising thinning the second semiconductor device from the second side of the semiconductor device while the second semiconductor device is on the second carrier structure.

85. 84. The method of claim 83, wherein removing at least one of the first and second carrier structures comprises exposing a photolytic layer to light.

86. 84. The method of claim 83, further comprising processing the second side of the first semiconductor device while the first semiconductor device is on the first carrier structure.

87. 87. The method of claim 86, wherein processing the second side of the first semiconductor element comprises forming a bonding layer on the second side of the first semiconductor element after thinning the first semiconductor element.

88. 88. The method of claim 87, wherein forming the bonding layer comprises forming a non-conductive bonding region and a plurality of contact pads at least partially embedded in the non-conductive bonding region.

89. 84. The method of claim 83, wherein the first carrier structure comprises a transparent carrier and an intermediate structure spanning the transparent carrier, the intermediate structure comprising a non-conductive layer, a photodecomposition layer, and an opaque layer.

90. 1. A method of manufacturing an electronic component, comprising: providing a semiconductor element on a diced tape, the semiconductor element having a device portion and a first side facing the diced tape; bonding the semiconductor element to a carrier structure, the carrier structure including a transparent carrier and an intermediate structure between the semiconductor element and the transparent carrier, the intermediate structure including a photodecomposition layer; separating the transparent carrier from the semiconductor device, which step leaves an adhesive residue on a second side of the semiconductor device; polishing the semiconductor element from the second side to remove the residue while the semiconductor element is disposed on the dicing tape; 23. A method comprising:

91. 91. The method of claim 90, wherein the intermediate structure further comprises an opaque layer and a dielectric layer.

92. 91. The method of claim 90, wherein the adhesive residue comprises a residue of a photodecomposition layer of the carrier structure.

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