Method and process for using fingerprint-based semiconductor manufacturing process defect detection - Patents.com

Abstract

A sensitivity calculation of the process model through the rate of change of the model fingerprint to the process variables and defects is provided. A fingerprint sensitivity table is generated and the process variables are associated with a set of fingerprint sensitivities. The fingerprint of the input substrate is monitored throughout the production process by applying the same fingerprint methodology used in the process model. A calculation of the difference between the input substrate fingerprint and the process model predicted fingerprint is made. This difference fingerprint is compared against the table of fingerprint sensitivities to find the process variable that is most likely responsible for the difference. A spatial relationship between the process variables and the actual measurements on the substrate can be obtained. Correlation through fingerprint sensitivities improves the ability to pinpoint defective process tools. The difference fingerprint can also identify the formation of defects on the substrate.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of and priority to U.S. Patent Application Publication No. 17 / 484,204, entitled “Method and Process Using Fingerprint Based Semiconductor Manufacturing Process Fault Detection,” filed September 24, 2021, the contents of which are incorporated by reference in their entirety for all purposes.

[0002] SUMMARY OF THE DISCLOSURE The present disclosure relates to processing of substrates. In one embodiment, the present disclosure provides a novel method for processing substrates used to form microelectronic devices. [Background technology]

[0003] Microelectronic devices are individual electronic devices and components on the scale of a micrometer or less, or a collection of them. Individual microelectronic devices may include electronic components such as transistors, capacitors, inductors, resistors, diodes, etc. that may be connected according to a design to form combinations. The connections may be formed by integrating a multi-layer interconnection network of vertical and lateral conductors separated by insulators. The combinations may form electronic circuits that collectively perform complex functions such as data storage and retrieval, calculations, signal processing, and electronic image capture, or combinations thereof. An integrated circuit (IC), sometimes called a microchip, is one example of such a device. ICs are used in many electronic systems for industrial, military, and civilian applications.

[0004] Typically, microelectronic devices are formed on a substrate (e.g., a semiconductor wafer, etc.) and are produced as part of a stack of patterned layers of materials, e.g., semiconductors, insulators, and conductors, on the substrate. Substrate processing typically involves a series of process steps using various process tools to form, implant, process, pattern, etch, etc., various process layers through sequential use of the various process tools. With innovations in processing technology, minimum feature sizes have been periodically reduced to increase the packing density of components within microelectronic devices. With more components, the functionality of electronic circuits has increased, thereby enabling microelectronic devices to perform more complex tasks.

[0005] As the complexity of substrate processing increases with the increasing number of electronic components in each microelectronic device, and as the geometries in substrate processing continue to shrink, the technical challenges of forming structures on the substrate increase. Innovations in semiconductor wafer fabrication manufacturing systems, manufacturing methods, and manufacturing tools may be required to provide low-cost, electromechanically functional microelectronic devices produced by high-yield semiconductor fabrication methods.

[0006] Increasing complexity and decreasing geometries of substrate processing also require more precise manufacturing tools and control of those manufacturing tools. Defective tool parts can lead to poor performance of devices formed by substrate processing. Early detection of defective parts can save costs and prevent catastrophic failures. The traditional method of detecting defective parts is to inspect the processed wafers by setting uniform thresholds or by installing sensors to detect anomalies in the machine. Summary of the Invention [Problem to be solved by the invention]

[0007] It would be desirable to provide improved techniques for monitoring and controlling the various process steps and process tools utilized in substrate processing. [Means for solving the problem]

[0008] A sensitivity calculation of the process model through the rate of change of the model fingerprint to the process variables is provided. A table of fingerprint sensitivities is generated and the process variables are associated with a set of fingerprint sensitivities. The fingerprint of the input substrate is monitored throughout the production process by applying the same fingerprint methodology used in the process model. A calculation of the difference between the input substrate fingerprint and the predicted fingerprint calculated using the process model is performed. This difference fingerprint is compared against the table of fingerprint sensitivities to find the process variable that is most likely to be the cause of the difference. A chart ranking this likelihood can then be created and reported to the user. A spatial relationship between the process variables and the actual measurements on the substrate can be obtained. Direct correlation through fingerprint sensitivities improves the ability to pinpoint defective process tools. In another alternative, the fingerprint process can be utilized to detect defects formed on the substrate. For example, particulates that may be formed on the substrate in a particular process step can be detected through the use of the fingerprint comparison process described herein.

[0009] A defective process tool (or part of a process tool) can significantly impact the fingerprint of a processed substrate. Similarly, defects can significantly impact the fingerprint of a processed substrate. The disclosed method presents details of using fingerprint modeling to detect process variable related drifts to identify defective process tools and / or parts early and / or detect the formation of defects in a process step. The disclosed technique does not require sensor input to detect defective tools and / or defects. Thus, an alternative method of identifying the root cause of a substrate processing problem or defective tools and / or parts by isolating process variables having contributing fingerprint components and detecting based on process variable sensitivity is provided. Similarly, the disclosed method presents details of using fingerprint modeling to detect the formation of defects in a process step. The disclosed technique does not require sensor input to defects. Thus, the use of fingerprint techniques provides an alternative method of identifying substrate processing problems that form defects.

[0010] In one embodiment, a method for characterizing a fabrication process for manufacturing a semiconductor wafer is provided, the fabrication process including at least one process step, the at least one process step being associated with a plurality of process variables. The method includes performing an experimental design process for at least one process step, where a plurality of process variables are varied for a plurality of experimental design semiconductor wafers; acquiring experimental design wafer measurements of a first characteristic from the plurality of experimental design semiconductor wafers, where each of the experimental design wafer measurements is associated with a spatial location on the production semiconductor wafer where the measurement is acquired; creating an experimental design process step fingerprint from the acquired experimental design wafer measurements for each experimental design semiconductor wafer to provide a plurality of experimental design process step fingerprints; and creating a process model for the at least one process step using the plurality of experimental design process step fingerprints; performing the at least one process step on a production semiconductor wafer; acquiring production wafer measurements of the first characteristic of the production semiconductor wafers, where each of the production wafer measurements is associated with a spatial location on the production semiconductor wafer where the measurement is acquired; creating a production semiconductor wafer process step fingerprint from the acquired production semiconductor wafer measurements; and detecting a faulty process variable of the at least one process step using the production semiconductor wafer process step fingerprints and the process model.

[0011] The method may further include calculating a modeled fingerprint of the production semiconductor wafer utilizing the process model of the at least one process step.

[0012] The method may also include calculating a difference between the modeled fingerprint and the production semiconductor wafer process step fingerprint, and utilizing the calculated difference when detecting a faulty process variable of at least one process step. In one embodiment, the faulty process variable is detected by comparing the calculated difference against a process model sensitivity to facilitate determining whether the particular process variable is faulty. In one embodiment, the particular process variable is identified utilizing a probability determination. In one embodiment, the particular process variable is identified by analyzing a plurality of process model terms obtained by comparing the calculated difference against the process model sensitivity to identify process variables that exceed a predetermined fault probability level.

[0013] Another method is a method of characterizing a fabrication process for manufacturing semiconductor wafers, the fabrication process including a plurality of process steps, at least a first one of the plurality of process steps being associated with a plurality of process variables. The method may include performing an experimental design process. The experimental design process may include performing a first one of the plurality of process steps on a set of experimental design semiconductor wafers, where at least one or more of the values ​​of the plurality of process variables are changed for each of the set of experimental design semiconductor wafers, acquiring experimental design wafer measurements of a first characteristic from the set of experimental design semiconductor wafers, where each of the experimental design wafer measurements is associated with a spatial location on the experimental design semiconductor wafer where the experimental design wafer measurement is acquired, creating an experimental design process step fingerprint from the acquired experimental design wafer measurements for each experimental design semiconductor wafer to provide a plurality of experimental design process step fingerprints, and utilizing the plurality of experimental design process step fingerprints to create a process model for the first one of the plurality of process steps. The method further includes performing a first of the multiple process steps on at least one production semiconductor wafer; acquiring production wafer measurements of a first characteristic of the production semiconductor wafer, each of the production wafer measurements being associated with a spatial location on the production semiconductor wafer at which the measurement is acquired; creating a production wafer process step fingerprint from the acquired production wafer measurements; and detecting the faulty process variable using the production wafer process step fingerprint and the process model.

[0014] The method may further include calculating a modeled fingerprint of the production semiconductor wafer utilizing a process model of a first one of the plurality of process steps. The method may also include calculating a difference between the modeled fingerprint and the production wafer process step fingerprint. The method may also include calculating a difference between the modeled fingerprint and the production wafer process step fingerprint, and utilizing the calculated difference when detecting a faulty process variable of the first one of the plurality of process steps. In some embodiments, the faulty process variable is detected by comparing the calculated difference against a variable sensitivity level of the process model to facilitate determining that the particular process variable is a faulty process variable. In some embodiments, the faulty process variable is identified utilizing a probability determination. In some embodiments, the faulty process variable is identified by analyzing the plurality of process model terms obtained by comparing the calculated difference against the variable sensitivity level to identify process variables that exceed a predetermined fault probability level. In other embodiments, the faulty process variable is identified utilizing a probability determination.

[0015] In another embodiment, a method for characterizing a fabrication process for manufacturing semiconductor wafers is provided, the fabrication process including a plurality of process steps, at least a first one of the plurality of process steps being associated with a plurality of process variables. The method may include performing an experimental design process, the experimental design process including performing a first one of the plurality of process steps on a set of experimental design semiconductor wafers for a set of experimental design semiconductor wafers, where at least one or more of the values ​​of the plurality of process variables are varied for each of the set of experimental design semiconductor wafers, acquiring experimental design wafer measurements of a first characteristic from the set of experimental design semiconductor wafers, where each of the experimental design wafer measurements is associated with a spatial location on the experimental design semiconductor wafer at which the experimental design wafer measurement is acquired, creating an experimental design process step fingerprint from the acquired experimental design wafer measurements for each experimental design semiconductor wafer to provide a plurality of experimental design process step fingerprints, and utilizing the plurality of experimental design process step fingerprints to create a process model for the first one of the plurality of process steps. The method also includes performing a first of a plurality of process steps on the at least one production semiconductor wafer; acquiring production wafer measurements of a first characteristic of the at least one production semiconductor wafer, where each of the production wafer measurements is associated with a spatial location on the at least one production semiconductor wafer at which the measurement is acquired; calculating a modeling fingerprint of the production semiconductor wafer using a process model of the first of the plurality of process steps; and detecting defects on the at least one production semiconductor wafer using the calculated modeling fingerprint and the process model of the at least one production semiconductor wafer, where the process model is utilized to account for variations in process variables to improve accuracy of the defect detection.

[0016] In some embodiments, defects on the at least one production semiconductor wafer are determined by identifying spatially localized anomalies and removing false positive defect detections by accounting for variations in process variables. The method may further include calculating a difference between the acquired production wafer measurements and the calculated modeled fingerprint. The method may also include calculating a difference between the acquired production wafer measurements and the calculated modeled fingerprint and utilizing the calculated difference when detecting defects on the at least one production semiconductor wafer.

[0017] A more detailed understanding of the present invention and its advantages can be obtained by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals indicate like features, and in which it should be noted, however, that the accompanying drawings illustrate only exemplary embodiments of the disclosed concepts, and therefore should not be considered as limiting in scope, as the disclosed concepts may admit of other equally effective embodiments. [Brief description of the drawings]

[0018] [Figure 1A] 1 illustrates an example of measurable results of a process step of a wafer fabrication manufacturing system, according to one embodiment. [Figure 1B] 1B illustrates a fingerprint of one example of the measurable result illustrated in FIG. 1A. [Figure 1C] 1B illustrates a fingerprint of one example of the measurable result illustrated in FIG. 1A. [Diagram 2] 1 is a flow chart illustrating a portion of an example method in a wafer fabrication manufacturing system used to generate fingerprint models, transfer functions, and process models for process steps from in-line measurements of wafer fabrication metrology, according to one embodiment. [Figure 3A] 1 illustrates a portion of an example method in which an in-line measurement type measurement fingerprint is generated, according to one embodiment. [Figure 3B]1 illustrates a portion of an example method in which an in-line measurement type measurement fingerprint is generated, according to one embodiment. [Figure 3C] 1 illustrates a portion of an example method in which an in-line measurement type measurement fingerprint is generated, according to one embodiment. [Figure 4A] 1 illustrates a portion of an example method in which a process model for an in-line measurement type measurement fingerprint is generated, according to one embodiment. [Figure 4B] 1 illustrates a portion of an example method in which a process model for an in-line measurement type measurement fingerprint is generated, according to one embodiment. [Figure 4C] 1 illustrates a portion of an example method in which a process model for an in-line measurement type measurement fingerprint is generated, according to one embodiment. [Figure 4D] 1 illustrates a portion of an example method in which a process model for an in-line measurement type measurement fingerprint is generated, according to one embodiment. [Diagram 5] 1 is a flow chart illustrating a portion of an example method in a wafer fabrication manufacturing system used to generate fingerprint models, transfer functions, and process models for process modules from in-line measurements of wafer fabrication metrology, according to one embodiment. [Figure 6A] 1 illustrates an example method for generating a hierarchy of fingerprints from measurement fingerprints, according to one embodiment. [Figure 6B] 1 illustrates an example method for generating a hierarchy of fingerprints from measurement fingerprints, according to one embodiment. [Figure 6C] 1 illustrates an example method for generating a hierarchy of fingerprints from measurement fingerprints, according to one embodiment. [Figure 7] 1 is a generalized flowchart illustrating an example method for generating a model of a baseline process flow, according to one embodiment. [Figure 8]1 illustrates an example workflow diagram for implementing a fingerprint-based defect detection technique for use with semiconductor wafers. [Figure 9] 1 illustrates an exemplary table illustrating various process variables for a thin film formation process. [Figure 10] 1 illustrates raw film thickness data collected spatially across a grid of monitor wafers and corresponding coefficient intensities and coefficients provided by the fingerprint model. [Figure 11A] Illustrate some of the workflow steps of FIG. 8 for example film thicknesses for "good" and "bad" wafers. [Figure 11B] Illustrate some of the workflow steps of FIG. 8 for example film thicknesses for "good" and "bad" wafers. [Figure 12A] 1 illustrates a chart plotting process variables (process model terms) against defect probability for "good" and "bad" wafers. [Figure 12B] 1 illustrates a chart plotting process variables (process model terms) against defect probability for "good" and "bad" wafers. [Figure 13] 1 illustrates an example workflow diagram for implementing a fingerprint-based defect detection technique for use with semiconductor wafers. [Figure 14A] 1 illustrates an exemplary method utilizing the techniques disclosed herein. [Figure 14B] 1 illustrates an exemplary method utilizing the techniques disclosed herein. [Figure 15A] 1 illustrates an exemplary method utilizing the techniques disclosed herein. [Figure 15B] 1 illustrates an exemplary method utilizing the techniques disclosed herein. [Figure 16A] 1 illustrates an exemplary method utilizing the techniques disclosed herein. [Figure 16B] 1 illustrates an exemplary method utilizing the techniques disclosed herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] Existing techniques for preparing substrates such as semiconductor wafers use metrics that are single values ​​that apply or are assumed to apply across the entire substrate. Traditional application of these metrics is based on measurements of individual wafers or sample wafers.

[0020] These conventional approaches discard or ignore information related to or associated with each measurement. For example, such information may include spatial measurements or correlations between measurements. Such information is potentially valuable. Edge Placement Error (EPE) is an example of a combination of different measurements that forms a metric that can be correlated to yield.

[0021] Pending U.S. Patent Application Publication No. 16 / 666,087, filed October 28, 2019, entitled Systems and Methods for Manufacturing Microelectronic Devices by Fonseca and IP, the disclosure of which is expressly incorporated by reference in its entirety, describes a manufacturing system that employs a method in which a metric fingerprint (FP) that correlates to manufacturing yield is generated from one or more in-line measurements made at multiple spatial locations of one or more semiconductor wafers.

[0022] The technique described in U.S. Patent Application Publication No. 16 / 666,087, incorporated by reference, in various embodiments, preserves spatial information by generating process models that are built using much more available information. Additionally, the technique, in various embodiments, can be dynamically applied to semiconductor manufacturing and is suitable to be automated using feedback control loops.

[0023] The embodiments of the semiconductor wafer fabrication manufacturing system manufacturing methods and manufacturing tools described herein may improve the manufacturing yield and manufacturing costs of microelectronic devices produced by semiconductor wafer fabrication techniques. Semiconductor wafer fabrication may be described as the execution of a series of process modules, each process module including a series of unit process steps. Exemplary unit process steps include surface preparation, ion implantation, thermal steps (e.g., rapid thermal oxidation (RTO), rapid thermal anneal (RTA) and laser anneal), photolithography steps (e.g., resist coat, expose, develop and strip), electroplating, plasma deposition, plasma etching, wet etching, chemical mechanical polishing (CMP), etc., performed according to a sequential process flow to create layers, such as active layers, dummy gate layers, source-drain layers, metal gate layers, contact layers, etc. Each process module may be referred to as an active module, a dummy gate module, etc. The manufacturing yield of a semiconductor wafer fabrication line may be considered to be the percentage of completed microelectronic devices that have electrically testable metrics (e.g., transistor leakage, resistor resistance, circuit functionality, etc.) that comply with a set of specifications.

[0024] A metric fingerprint (FP) that correlates to manufacturing yield is generated from one or more in-line measurements made at multiple spatial locations of one or more semiconductor wafers. For each layer, an FP of the metric appropriate to the layer is generated as described in further detail below. For example, an FP of edge placement error (EPE) of a dummy gate layer may be generated. In some embodiments, each FP is a mathematical model of the respective metric that preserves the spatial information of the measurement. In some embodiments, the mathematical model is a mathematical function of the spatial coordinates of the location on the wafer where the in-line measurement was taken. The mathematical function may be expanded in a finite series of mathematical functions, called basis functions. The FP may then be represented by a coefficient vector that includes an ordered set of coefficients for each term of the series expansion of the model function. As described in further detail below, the FP of a layer metric may be a composite of a hierarchy of FPs. For example, the FP of the active layer EPE can be a composite mathematical model that includes contributions from several FPs, such as the height of the mandrel (used for sidewall image transfer (SIT)), pitch-walk (for multi-patterning techniques), overlay (e.g., alignment error between the active mask and the alignment mask), etc. These FPs (e.g., mandrel height, pitch-walk, and overlay) can then be derived from one or more FPs of in-line measurements, such as, for example, the mandrel deposited film thickness, the pitch of the multi-pattern of the sidewall hard mask, the dimensions of features in the overlay pattern, etc.

[0025] In-line measurements are designed to identify the results of a preceding process step that may ultimately affect manufacturing yield at the end of a wafer fabrication production line. As known to those skilled in the art, the results of a processing step may be adjusted by a set of adjustable process parameters. A process parameter is generally an equipment setting selected to perform one or more process steps. For example, a dummy gate resist EPE measurement after a resist development process step in a dummy gate process module may be adjusted by a wafer spin speed in a resist coat step, an exposure time during a photoresist exposure step, and a focal plane position. Thus, each coefficient of the FP of the dummy gate resist EPE may be adjusted by an adjustable process parameter, in this example, spin speed, exposure, and focus. The response of an FP coefficient (e.g., dummy gate resist EPE FP) to a set of process parameters (e.g., spin speed, exposure, and focus) may be modeled as a mathematical function of a set of independent variables, each variable being a numerical representation of a process parameter appropriately normalized to units of EPE (e.g., nanometers). These mathematical descriptions collectively form a process model of the dummy gate resist EPE.

[0026] In this example, the dummy gate resist EPE is a direct measurement, so its FP is one of the lowest level FPs in the hierarchy of FPs. It may be further noted that in this embodiment, the process model may retain spatial information in the dummy gate resist EPE measurement by accurately modeling the dummy gate resist EPE FP. In general, there may be more than one measurement type (e.g., EPE, line edge roughness (LER), overlay, critical dimension (CD), line width roughness (LWR), etc.). A lowest level FP with a respective process model may be generated for each measurement type of a process step. Measurements acquired in the current or previous process step may be combined with the in-line measurement FP and calculated (e.g., the difference between the two measurements) to create the next higher level FP of that process step.

[0027] Measurable results of a process step often depend on the state of the input wafer. For example, the EPE of a dummy gate resist pattern can be affected by the height of a fin formed protruding above a shallow trench isolation (STI) oxide at an active level in a process flow including the fabrication of a fin-shaped transistor structure called a FinFET. The fin height measured in an active process module can be accurately reproduced by the active fin height FP. The state of the input wafer is generally determined by both the previous process module and the completed process step of the current process module. Thus, the top level FP of the previous process module and the top level FP of the completed step in the current process module can be correlated to measurements in subsequent process steps and therefore to FPs generated therefrom. In this example, the active fin height FP can affect one or more FPs of in-line measurements in a dummy gate layer such as EPE, CD, LER, LWR, and overlay dummy gate resist FP. Such correlations between FP pairs (e.g., between active fin height FP and dummy gate resist EPE FP) are characterized for the process flow and fed forward from the previous process step as a transfer function suitable for use in generating a measured (lowest level) FP of a subsequent process step. In one embodiment, the transfer function may be implemented as a transformation matrix that maps a coefficient vector of a prior FP (e.g., active fin height FP) to a component vector that can be incorporated into the coefficient vector of the lowest level FP (e.g., dummy gate resist EPE FP) of the subsequent process step. In general, the transfer function may be implemented using any numerical model, such as a transformation matrix, a set of differential equations, a look-up table, a set of statistical correlation functions, or an iterative algorithm, that can be used to include the influence of a metric calculated from wafer characteristics of a previous process step on the FP of a metric derived from measurements made in a subsequent process step.Additionally, although we have formulated the impact of previous processing on wafer characteristics in a current process step as a transfer function that maps one or more FP models of a previous process step to at least a portion of the measured FP in the current process step, other formulations are contemplated. For example, a transfer function may be formulated to describe the mapping of process parameters in a previous step to at least a portion of the FP model of a metric derived from the combination / calculation of one or more in-line wafer fabrication metrology data in the current process step. Once the impact of previous processing is incorporated in the lowest level FP, correlations with previous process steps are naturally included in any higher level FPs subsequently formed using the lowest level FP.

[0028] After generating the FPs of the process steps of a process module, combination and calculation may be applied to generate the FPs of the next higher level, which may be FPs of a process module or layer, as further described below. For example, the FPs of some of the process steps in a dummy gate process module, such as dummy gate resist CD FP, dummy gate etch bias FP, and overlay, may be combined to generate a dummy gate CD FP for a dummy gate layer.

[0029] The embodiment of the method of using FP to generate a process model of FP coefficients that preserves and reproduces the spatial coordinates of raw measurement data is advantageous for monitoring and controlling semiconductor wafer fabrication production lines. A statistical process control (SPC) strategy using monitoring of FP coefficient vectors that provide spatial information facilitates identifying the cause of process excursions that may reduce the yield of wafer fabrication production lines. For example, if an increase in radial dependency is observed from an anomaly in the FP coefficients of a metric that may be influenced by several process parameters, one of which represents radial gas flow, it may suggest an abnormal gas flow. The process model of the FP coefficients that show outliers can be utilized in conjunction with the spatial information to simulate the anomaly in order to facilitate the rapid identification of equipment and equipment settings whose intervention may successfully restore the manufacturing yield.

[0030] Using a transfer function to generate an FP coefficient vector that incorporates correlation with previous process steps provides several unique advantages to wafer fabrication manufacturing systems. The transfer function method effectively splits the coefficient vector of the measurement FP into two component vectors: one that correlates with the previous processing, and one that correlates with the currently completed process step, called the current step vector. The component that correlates with the fingerprint of the previous step is predictable from the processing history and is called the transfer vector or transfer component of the measurement FP. Such a decomposition of the FP coefficient vector can be used to split the deviations observed at a given process step into the portion attributable to the input wafer state and the portion attributable to the current process step. Furthermore, the predictability can be used to feed forward corrective actions or make early decisions to terminate further processing.

[0031] The transfer function method increases the accuracy of the process model of the entire fabrication process flow by retaining the influence of all previous process steps on the FP of the metric in the subsequent process step. This capability can be advantageously used in computer-aided analysis to adjust process parameters to improve the yield of the production line, as described further below. In conjunction with the process model, the spatial information can aid in more targeted adjustments to optimize equipment settings to increase manufacturing yield. Furthermore, the analysis can identify specific equipment that is worthy of further investment due to its large impact on manufacturing yield, and can also identify specific equipment for which a less expensive alternative can be used with negligible impact on manufacturing yield.

[0032] The manufacturing system and method generally described above will now be illustrated in further detail with reference to FIGS.

[0033] The wafer map of FIG. 1A illustrates one example of a directly measurable result 100 of a process step of a wafer fabrication manufacturing system where the result is a collection of the same type of measurement repeated at multiple die locations on the wafer (e.g., EPE measurements of a resist patterning step). A data set that includes data values ​​associated with spatial locations (e.g., two-dimensional (2D) rectangular coordinates x and y or polar coordinates r and θ) on one sample wafer or a collection of such wafers may be displayed as a wafer map. In a wafer map, each data point is given an area according to its associated spatial coordinates in a two-dimensional image of the wafer. In wafer maps herein, such as the image of FIG. 1A, the data points are depicted as tessellated rectangles with values ​​indicated by a grayscale.

[0034] The raw data (e.g., directly measured EPE values ​​and their associated coordinates) may be processed to create a Fingerprint (FP) model. In particular, an analysis such as regression analysis may be performed to select and adjust parameters of the function for the best fit to the raw data values, e.g., the minimum error between the measured values ​​of EPE and the values ​​calculated by the FP model using the optimized parameters. The analysis involves selecting an appropriate mathematical function of 2D spatial coordinates that can reproduce the spatial pattern in the raw data with a manageable finite number of adjustable parameters. For example, in a measurement that may be subject to a process step in which, for example, liquid photoresist is introduced to the central region of a rotating wafer and distributed across the wafer surface by radial centrifugal forces, the model function may be selected to be a function of polar coordinates r and θ, mathematically expressed as a finite series of Zernike polynomials (or other functions such as Fourier series and Bessel functions). Each polynomial is weighted by a respective numerical coefficient. These coefficients are fitting parameters of the model whose values ​​may be optimized during analysis to obtain the best fit to the raw data. The ordered set of coefficients is called a coefficient vector, and each coefficient is a component of the coefficient vector. Collectively, the components (arranged in the same order as the Zernike polynomials) constitute an FP model of the raw data. The coefficient vector illustrated in FIG. 1B is an example of an FP model of the raw data depicted by the wafer map in FIG. 1A. The model function used for the FP model in FIG. 1B includes a series of the first 21 Zernike polynomials weighted by the 21 coefficients plotted in order in FIG. 1B. The wafer map 120 in FIG. 1C depicts modeled values ​​calculated using the optimized FP model illustrated in FIG. 1B. As can be observed from the two wafer maps (FIGS. 1A and 1C), the FP model in FIG. 1B can reproduce the raw data quite accurately.

[0035] In some cases, the initial FP model (e.g., the 21-dimensional coefficient vector of FIG. 1B) may be further simplified by expanding the analysis to include identifying dominant model parameters. If there are only a few principal components of the coefficient vector (e.g., five coefficients that significantly affect the calculated data values), then the initial FP model, including, for example, 21 coefficients, may be approximated by the identified few principal coefficients, e.g., five principal coefficients. In some embodiments, a lower-dimensional (e.g., five-dimensional) coefficient vector may replace the initial high-dimensional (e.g., 21-dimensional) FP model for further processing and calculations (the remaining coefficients are ignored).

[0036] 2 is a flow chart illustrating the execution flow of one process step in an example system 200 implementing the techniques described above. The example system 200 works in conjunction with the fabrication of semiconductor wafers. In some cases, the collaboration may include the example system 200 being an integral part of the fabrication itself. As described in more detail below, in addition to a baseline wafer fabrication process, processing steps may be performed, measurements may be taken, and model parameters may be extracted with high reliability and accuracy.

[0037] An example process is described herein for simplicity and not for any limitation as being performed by system 200. Figures 3 and 4, in conjunction with the flow chart of Figure 2, aid in the description of some of the steps in system 200. Figure 3 is used to illustrate the generation of measurements FP as a function of coordinates of measurement locations on a wafer. Figure 4 is used to describe the method system 200 uses to generate a process model that calculates the response of the fingerprint model coefficients to changes in process parameters.

[0038] As indicated by block 210 in the flow chart of system 200 in FIG. 2, the first step in the step-by-step description of the method used in system 200 to create a predictive mathematical model of the outcome of a process step, including FP, transfer function, and process model, is to acquire in-line measurements of one or more characteristics (e.g., resist CD of lines in a pattern of dense lines) of semiconductor wafers processed according to a baseline fabrication process flow. Each acquired measurement is associated with the wafer spatial location at which the measurement is acquired, and each acquired measurement may be graphically depicted by a wafer map similar to that described with reference to FIG. 1A. Graph 300 in FIG. 3A is a wafer map of raw data of measurements, e.g., CD measurements, collected from a set of baseline processed wafers at the same set of locations on each wafer.

[0039] More generally, the operations of block 210 may be described as collecting in-line fabrication metrology data for a semiconductor wafer along with spatial information of that collected data. This in-line fabrication metrology data is generated from in-line measurements made of, on, within, and to the wafer of properties resulting from a process step of a baseline fabrication process flow. The measurements may be made during a process step or after the process step is completed. That is, the in-line fabrication metrology data is a measurement of a property of a wafer formed in a process step of a baseline semiconductor fabrication process flow.

[0040] In-line fabrication metrology data for a process step may be derived from measurements of a thin film of material processed in a process step (e.g., thickness of a deposited thin film), a pattern in a processed thin film (e.g., resist linewidth in a resist development step), a completed device processed in a process step (e.g., by metal CMP at an interconnect level), a partially completed device exposed by etching of a material (e.g., alignment marks), etc. As used herein, a process step may be the processing of a thin film of material that is the focus of fabrication at that moment. In many cases, the thin film is the top or uppermost film. For example, the thin film may be a thin film that is being deposited, cleaned, or etched, or a thin film that has just been deposited, cleaned, or etched.

[0041] In some cases, for example, in-line fabrication metrology data may be derived from measurements on a thin film immediately adjacent to the thin film currently at the focus of fabrication, patterns in that adjacent layer, devices completed by the adjacent layer, partially completed devices exposed by the adjacent layer, etc. In many cases, the current adjacent layer is the layer immediately below the top thin film.

[0042] In still other cases, for example, in-line fabrication metrology data may be derived from measurements on multiple adjacent layers of a wafer, or on the wafer itself, e.g., multiple adjacent layers of a wafer may contain internal electrically and / or mechanically interacting microelectronic devices.

[0043] Typically, in-line fabrication metrology data includes measurements (calculations based on measurements from semiconductor wafers) from multiple semiconductor wafers that use a common stack of patterns of materials during semiconductor fabrication. Examples of different types of in-line fabrication metrology data include measured and / or calculated data such as EPE, grid CD measurements, block LWR measurements, grid LWR measurements, block CD measurements, edge profile, selective deposition and / or selective etch selectivity, electrical characteristics of formed microelectronic devices, contact hole CD, contact hole edge roughness (CER) and ellipticity, tip-to-tip distance of short and long lines and trenches, overlay error measurements between two patterned layers, thin film thickness and thickness uniformity, measured and / or calculated in-line fabrication metrology data selected from the group consisting of measurements made after a single tool operation, measurements made after all tools of a single process module, measurements made after multiple process modules, and combinations thereof.

[0044] In block 220, the system selects a mathematical function of the 2D spatial coordinates (x,y) or (r,□) appropriate for modeling the data. In one embodiment, the model function is a finite series of basis functions, and as discussed above, the numerical coefficients that weight each term in the series are called the coefficient vector or FP of the data. The basis functions are typically orthogonal functions such as Zernike polynomials, Legendre polynomials, or Bessel functions, and are selected to accurately model the in-line measurement type of interest without the need to use very long series that require long computation times, and the characteristics of the model correspond to some physical component of the in-line measurement step (e.g., radial characteristics of a spin-coating process).

[0045] In the next block 230, the system 200 performs calculations to optimize a finite set of coefficients that best fit the acquired spatial measurements of the measurement type according to an optimization algorithm to obtain the respective FP models. An FP model may be generated for each measurement type of the in-line fabrication metrology data acquired in the process step. These measurement FPs are the first (lowest) level FPs.

[0046] The generation of in-line measurements and their respective FPs is illustrated in Figures 3A-3C. Figure 3A shows raw in-line fabrication metrology data of measurement types acquired from one or more wafers processed in a current process step using baseline processing. The graph displays the data as a wafer map of tessellated rectangles located at the spatial coordinates of each measurement type and shaded using a grayscale to represent the numerical value of each data point. The data depicted in Figure 3A is then modeled using a finite (e.g., 21-term) series of Zernike polynomials that are functions of the polar coordinates (r, □).

[0047] The optimized set of 21 coefficients is displayed as a histogram in Figure 3B, where the horizontal axis is the order of the Zernike polynomial and the vertical axis is the magnitude of each coefficient. In some embodiments, the number of terms may be adjustable, e.g., higher order polynomials may be added to the series if the minimum fitting error after optimization is higher than an acceptable threshold.

[0048] As can be seen in the histogram in Figure 3B, some of the coefficients are relatively small compared to the others, indicating that it may be possible to simplify the model without introducing excessive fitting error, since the contribution of each term is proportional to the strength of the respective coefficient. However, it is also important to consider that the basis functions are functions of 2D spatial coordinates, and therefore the relative contribution of the terms also depends on the location on the surface of the wafer. For example, a term that is dominant near the center of the wafer may be weaker near the edge of the wafer.

[0049] In FIG. 3C, the contributions of the five terms with the five highest coefficient intensities are plotted as a three-dimensional surface above the xy plane of the wafer surface. As can be seen from the histogram in FIG. 3B, the top five coefficients are the coefficients of Zernike polynomials of the 4th, 12th, 10th, 21st and 14th orders. Graphs such as that of FIG. 3C help reduce the complexity of the model. As will be further described below, a less complex FP model provides the advantage of reduced computation time for generating process models and performing subsequent analysis.

[0050] Next, in this embodiment, in block 240, a transfer function is obtained to decompose the measurements FP at the current process step to model the impact of the previous process step on the results of the in-line measurements of the wafer characteristics obtained at the current process step. In another embodiment, the transfer function may be generated after the generation of all measurements FP of the current process step and the higher-level FP (using a combination of measurements FP and calculations) is completed. As described above, the transfer function may be implemented and extracted using various techniques, such as a transformation matrix, a statistical correlation function, etc.

[0051] As shown in block 240 of the flow chart of the system 200 in FIG. 2, in this embodiment, the method of extracting the transfer function considers that the memory of previous processing is embedded in the state of the input wafer. In order to have a robust method of dividing the coefficient vector of the measurement value FP in the current process step, a set of input wafers may be generated by intentionally changing the process conditions in some previous process steps. For example, the measurement value FP of the resist CD in the photoresist development step is expected to correlate with the flatness of the wafer surface on which the resist pattern is formed. Therefore, the process parameters of the previous planarization process step may be intentionally changed from the baseline process flow to generate input wafers, each wafer having a different flatness FP obtained in the planarization step. Then, the response of the coefficient vector of the resist CD measurement value to the variation of the flatness FP of this specially prepared set of non-baseline input wafers is analyzed to identify the sensitivity of the deviation of each coefficient of the resist CD FP from its baseline value. Using this information, a transformation matrix can be defined that can map all input wafer flatness FP coefficient vectors to their respective resist CD response vectors (called transfer vectors), which are the portions of the resist CD coefficient vectors that are expected to contain all correlations with the wafer flatness FP at the planarization step. This response vector captures the memory of the planarization process and can be subtracted from the resist CD measurements FP to obtain the uncorrelated components of the resist CD coefficient vectors (called current step vectors) that are expected to be more strongly correlated with the processing conditions at the current process step.

[0052] The transformation matrix is ​​a mathematical implementation of a transfer function in the example embodiment described above, although it is understood that other mathematical implementations are possible, as previously mentioned.

[0053] The transfer function for a particular baseline wafer fabrication process flow does not need to be generated each time a batch of wafers is processed through the wafer fabrication production line. The transfer function can be generated once and stored electronically for future use. The transfer function can be updated periodically as modifications are made to the baseline wafer fabrication process flow.

[0054] In one example embodiment illustrated by the flowchart of Figure 2, the system 200 creates a process model for a process step from the response of the current step vector of measurements FP for that step. The steps for creating this process model are outlined in blocks 250, 260, and 270 and described with reference to Figure 4.

[0055] In block 250, the system 200 acquires in-line fabrication measurement data from a set of wafers processed using process parameter values ​​defined in the baseline wafer fabrication process flow and several surrounding process parameter values. Each process parameter is associated with a different adjustable equipment setting in the process step for which the process model is created. For example, in a process, conditions (e.g., etch rate, etch time, gas concentration, etc.) may be adjustable based on controls available on one or more tools of the process. Those process conditions are then process parameters.

[0056] FIG. 4A illustrates an example of raw data graphically depicted by a 4×4 matrix of wafer maps 400 of in-line measurement data. Each wafer map of the example matrix in FIG. 4A corresponds to measurements of the same measurement type made on one or more wafers processed using a particular process parameter vector that includes pairs of values ​​of two process parameters, a first process parameter par1 and a second parameter par2. For example, par1 can be etch rate and par2 can be etch time. In general, the number of process parameters that are changed can be other than two. Measurements of more than one measurement type can also be made. The raw data in FIG. 4A is displayed such that the wafer maps along the rows of the 4×4 matrix correspond to the four parameter values ​​of par1 while the parameter value of par2 remains unchanged, and the wafer maps along the columns correspond to the four parameter values ​​of par2 while the parameter value of par1 remains unchanged.

[0057] Similarly, in block 250, the system 200 generates FP models of raw data acquired from a set of wafers processed using different process parameter vectors, as described above with reference to FIG. 4A. One FP model is generated from raw data acquired from each process parameter vector. For example, the 16 histograms depicted in FIG. 4B are FP models for each of the raw data depicted by the 16 wafer maps depicted in FIG. 4A. The model function is a 21-term series Zernike function similar to that described with reference to FIG. 1B. Each bar is a coefficient of a 21-component coefficient vector of the measurement type FP model corresponding to each process parameter vector (par1, par2).

[0058] Continuing to refer to block 250, the system 200 may utilize the available transfer function of the baseline process flow to decompose the measurement FP coefficient vector in FIG. 4B and obtain a current step vector for each measurement FP by subtracting the transfer vector from the coefficient vector. As described above, in this embodiment, each coefficient of the coefficient vector is divided or decomposed into two parts. The first part is equal to the respective coefficient of the transfer vector calculated using the transfer function. The first part represents the correlation with one or more FPs obtained in the previous process step. Then, the remaining second part is equal to the respective coefficient of the current step vector representing the part determined by the process conditions of the current process step. It is desirable to generate a process model using the current step vector so that the parameters of the process model of the current process step are not affected by the process parameters in one or more of the previous process steps.

[0059] In block 260, the system 200 selects a model function that models the response of each coefficient of the fingerprint's current step vector to changes in process parameters (e.g., par1 and par2). A different model function may be used to model each coefficient of the current step vector, such as the 21 coefficients of the 21-term series of Zernike polynomials shown as a1, a2, ... ai, ... a20, a21 in Figure 4C. In the example illustrated in Figure 4, there are 16 instances of each coefficient ai, corresponding to the 16 wafers and the 16 process vectors used in the process steps to generate the respective FPs.

[0060] The model parameters of the model functions selected in block 260 are adjusted in block 270 to best fit the 16 values ​​of each coefficient ai to generate an optimized process model of the process step, which includes 21 model functions, denoted as f1, f2, ... fi, ... f20, f21 in FIG. 4C. Each function fi is optimized according to an optimization algorithm. The first two process models f1 and f2 are graphically depicted in FIG. 4C as three-dimensional (3D) surfaces plotted as functions of two process parameters par1 and par2. The 16 points close to each 3D surface are the 16 values ​​a1 and a2 used to create the models f1 and f2, illustrating the good fit between the predictions of the process models and the coefficients of the current step vector of the FP model.

[0061] Figure 4D illustrates a wafer map calculated from the FP model and the associated process model. Comparison of the wafer map in Figure 4D with the raw data wafer map in Figure 4A shows good fitting, thereby illustrating the predictive ability of the FP model together with the associated process model in reproducing in-line fabrication metrology data, including spatial information, across the process parameter space around the baseline processing conditions.

[0062] Process models for process steps in the baseline wafer fabrication process flow, like the baseline transfer functions, may also be generated once and stored electronically for future use, and like the transfer functions, the process models may be updated periodically as modifications are made to the baseline process.

[0063] Baseline in-line wafer fabrication metrology data fingerprints may be generated more frequently for real-time yield analysis and advanced process control (APC), especially for process steps that strongly impact manufacturing yield. A reference set of FPs may be archived and compared to a set of FPs obtained from a live production line to detect, analyze, and correct anomalies.

[0064] 2, the lowest level FPs (which are measurement FPs) may be combined and calculations used to create higher level FPs and associated process models that can accurately predict relevant metrics for a process step. To combine multiple FPs with different units, it may be necessary to normalize the coefficient values ​​to obtain consistent units.

[0065] As described above, the FP model, transfer function, and associated process model generated using in-line measurements including 2D spatial coordinates of the measurement locations can be advantageously used in a wafer fabrication manufacturing system. As previously described and shown in block 290, the system 200 can identify the dominant coefficients of the FP and dominant parameters of the process model. This can not only help simplify the model by removing less significant parameters of the model, but can also provide useful insight into the impact of process parameters, equipment settings, and equipment selections on manufacturing yield. The models can be used to monitor and improve yield loss in conjunction with APC tools, and can even be used to improve the baseline wafer fabrication process flow to provide higher manufacturing yields, as described further below.

[0066] 5 illustrates a portion of a flow that may be used to generate metric fingerprints for a process module or layer 500, such as an active layer, a gate layer, a contact layer, a metal layer, etc., where each layer includes one or more process steps, where the FPs, transfer functions, and process models for the respective process steps may be generated by a manufacturing system, such as system 200, for example, using the flow described with reference to the flowchart illustrated in FIG.

[0067] The FP, transfer function, and process model for a layer (e.g., layer 500) may be generated by combination and calculation using the FPs, transfer functions, and process models of each process step. An example method for generating a layer FP is described with reference to the flowchart of FIG.

[0068] 5, layer 500 includes four representative process steps (A, B, C, D) such as resist coat, exposure, development, resist strip, etc. Although four process steps are shown for illustrative purposes, layer 500 may include any number of steps. The input provided to each process step is the input wafer along with the FP and transfer function generated in the previous process step.

[0069] A process step (e.g., step A, B, C, or D) includes processing equipment for wafer preparation, such as coaters, scanners, plasma etchers, test equipment, and associated chemicals, vacuum pumps, temperature controllers, etc., as known to those skilled in the art. Along with the equipment, each process step includes a process recipe that includes process parameter values, timing information, and instructions for processing the input wafer. The equipment has adjustable settings that can be used to control adjustable process parameters, such as etch rate, gas flow, exposure level, spin speed, etc. Each process parameter is represented in FIG. 5 by a unique capital italic subscript letter (J-U). For example, as seen in the first column of FIG. 5, the adjustable process parameters for process step A are AJ, AK, and AL.

[0070] One or more input wafers may be processed in a process step by executing one or more process recipes selected to obtain a desired result, such as, for example, depositing a thin film of a desired material and thickness. The processing may be monitored using various sensors, and the processing equipment may be controlled by an APC system to ensure that the process parameters achieve the results as intended by the process recipe. By default, the wafers are processed according to the baseline process recipe of the baseline wafer fabrication process flow.

[0071] As mentioned above, in-line measurements of wafer characteristics are collected as the first step of the FP model generation flowchart in FIG. 2. Multiple types of measurements can be made (e.g., deposited thin film thickness, first line resist CD, second line resist CD, step height, leakage current, etc.), with each measurement type having a unique letter as a subscript. In FIG. 5, there are eight measurement types, indicated by eight subscripts (a-h). In-line wafer fabrication metrology data can be collected from multiple wafers, but the set of locations on the wafer can be the same for all wafers measured at a given process step (e.g., step A) and a fixed measurement type (e.g., type a). Spatial information is preserved by relating each data point to the 2D spatial coordinates of the location on the wafer where the data was obtained.

[0072] In Figure 5, each data point of the same measurement type is identified by a unique italicized numeric value as a superscript (1, 2, 3, 4, etc.). Thus, a set of wafer measurements (including spatial information) of type a in process step A is denoted as {Aa1, Aa2, Aa3, Aa4...}. In the example of Figure 5, two types of measurements are made in each of the four process steps, for a total of eight types of measurements made in process module 500.

[0073] The lowest level FP model may be generated from in-line wafer fabrication metrology data at each step, for example, there may be two measurements FP for step A, one for the data set {Aa1, Aa2, Aa3, Aa4...} and another for the data set {Ab1, Ab2, Ab3, Ab4...}. Process step fingerprints created using combinations and calculations of measurements FP are shown in FIG. 5 with the process step name with subscript FP and numeric superscript to identify each process step fingerprint. For example, in FIG. 5, the two process steps FP in step A are shown as AFP1 and AFP2. Various combinations of the two measurement sets Aan and Abn can be used to arrive at the two process step fingerprints. For example, in one instance, measurement set Aan is used to create process step fingerprint AFP1, and measurement set Abn is used to create process step fingerprint AFP2. In another case, measurement sets Aan and Abn are used together to create process step fingerprint AFP1, and either measurement set Aan or Abn is used alone to create process step fingerprint AFP2. Several other combinations are possible, with each process step fingerprint created from one or more sets of wafer measurements using various weighting, scaling, averaging, fitting and / or other techniques. Although two process step fingerprints are shown for each process step for illustrative purposes, each process step may include one or more process step fingerprints.

[0074] The transfer function for each process step may be generated from a correlation between the FP model generated in the previous process step and the measured value FP of the current process step. One example method for identifying the correlation described in the description of the flowchart in FIG. 2 includes generating a set of non-baseline wafers by intentionally varying process parameters in a previous process step (e.g., step B in FIG. 5) and then using the wafers as input wafers processed in the current process step (e.g., step C) using the baseline process recipe. The response of the measured value FP in the current step C to the intentional variation of the FP in the previous step B provides information for generating a transformation matrix as a transfer function that predicts the change in the measurable result of process C from the wafer characteristics observed in process step B. As previously mentioned, it may be possible to define other ways of generating a transfer function other than a transformation matrix to model the effect of the wafer characteristics in one process step (e.g., step B) on the result of processing in a subsequent process step (e.g., step C).

[0075] Once all the transfer functions for a process step (e.g., specifically step A) are defined, each measurement FP for step A, represented by a respective coefficient vector, can be decomposed into a transfer vector that correlates with the previous operation and a current step vector that is separated from the process parameters of the previous process step. This separation provides the advantage of creating an accurate process model for step A from a set of in-line wafer metrology data acquired from a set of wafers that were created by varying only the process parameter vector (AJ,AK,AL) of step A using the method described above with reference to Figures 2 and 4.

[0076] It is understood that the description and illustration of the methods that allow generating fingerprints, transfer functions and process models for layers that include a process step or a collection of process steps are provided herein as examples and should not be considered limiting. As previously mentioned, methods other than those described are possible and these alternative methods can be derived from the description and illustration provided in this disclosure.

[0077] The process model of the lower level measurement FP can be extended to create a process model of the higher level FP derived from the measurement FP. The combinations and calculations used to generate AFP1 and AFP2 of the two process steps FP can be utilized to create a process model of process step A by respective combinations and calculations of the process models of the measurements FP.

[0078] 6A-6C illustrate an example of a method that allows a hierarchy of FPs to be generated by the combination and calculation of lower level FPs. In particular, in FIG. 6, starting from measurements FPs (lowest level) obtained from in-line measurements, a layer level FP of an EPE (called EPEA) is generated using the flow chart illustrated in FIG. 6A. An example formula that can be used to calculate EPEA is displayed in FIG. 6B. FIG. 6C illustrates a perspective view of a fabricated structure to illustrate that in-line wafer fabrication metrology data used to obtain measurements FPs can be collected at different process steps. In this example, the process steps belong to a process module called metal-1 layer. Raw in-line data is collected from measurements on two patterned films formed on the metal-1 layer, namely a first film A and a second film B, illustrated in FIG. 6C.

[0079] The five fingerprints, collectively denoted as FP 670, form a set of measurements FP{612, 622, 623, 632, 642} from which a higher level FP is obtained in the flow diagram illustrated in FIG. 6A. The higher level FPs 611, 621, 631, and 641 are generated in the flow diagram of FIG. 6A from the measurements FP 670 using various comparison, calculation, or other processes, collectively denoted as comparison, calculation, etc. 660. These fingerprints may be further compared and processed to arrive at aggregate, representative, or resultant fingerprints of overlay (OL)AB 610, pitch walk (PwalkA) 620, variable A (VarA) 630 (e.g., trench critical dimension (CD)), and variable B (VarB) 640 (e.g., block CD). The subscripts A and B refer to metrics related to thin films A and B, respectively, and the subscript AB is used for metrics related to both thin films A and B.

[0080] 6B, FPs 610, 620, 630, and 640 are used to calculate fingerprint EPEA, which is a layer-level fingerprint of edge placement error of patterned thin film A. Methods similar to those described herein can be applied to generate other fingerprints related to the manufacturing yield of wafer fabrication manufacturing systems and baseline process flows.

[0081] The elements of the set of measurements FP in the example flow chart of FIG. 6A are Overlay 612, Line #4 CD 622, Line #5 CD 623, Trench #4 CD 632, and Block 1T CD 642. These measurements FP raw in-line wafer fabrication metrology data concern two patterned thin films, a first patterned thin film A (formed using a self-aligned quad patterning (SAQP) technique) and a second patterned thin film B, as illustrated in FIG. 6C. Measurement FP Overlay 612 uses a measurement of the overlay error between these two patterns. Fingerprints Line #4 CD 622 and Line #5 CD 623 are extracted from line and space measurements collected during one or more of the SAQP process steps performed to form the patterned thin film A, and are then used to calculate a multi-patterning metric called pitch-walk. FP trench #4 CD632 can be generated from measurements of the space between pairs of adjacent lines of patterned thin film A of FIG. 6C created by a processing technique that includes the formation of pairs of self-aligned spacers on either side of a disposable mandrel. Fingerprint block 1T CD642 uses linewidth measurements of geometric features related to critical dimensions in the pattern of patterned thin film B of FIG. 6C. From the description of measurements provided herein, it is clear that the resulting layer FP EPEA incorporates in-line wafer fabrication metrology data collected at different process steps.

[0082] 6A, the top level FPs 611, 621, 631 and 641 generated using various comparisons, calculations and combinations 660 represent several metrics related to the calculation of edge placement error of features in the pattern of patterned thin film A. The magnitude of y overlay error derived from overlay 612 is represented by FP 611, the magnitude of pitch walk of thin film A derived from line #4 CD 622 and line #5 CD 623 is represented by FP 621, trench #4 CD 632 determines the magnitude of geometric variable / CD 631 in thin film A, and block 1T CD 642 determines the magnitude of geometric variable / CD 641 in thin film B. The comparisons, calculations and combinations can be of various types, such as simple algebraic operations, analytical linear and nonlinear functions, vector functions, geometric transformations, statistical analysis, computer algorithms of numerical methods, etc., or combinations thereof.

[0083] As previously mentioned, the upper level FPs may be further processed to arrive at fingerprints (OL)AB 610, PwalkA 620, VarA 630, and VarB 640, which are used in the exemplary equation 680 displayed in FIG. 6B. This exemplary equation defines a metal-1 layer level FP, EPEA, which can be used to calculate the edge placement error for that layer. In this equation, (MP)A refers to the geometric line-space ratio of the minimum pitch line, PregA refers to the pattern registration error (patterning error caused by the photomask, so the same error is repeated in every exposure field), and LspecA represents the geometric line specification from the pattern design. In equation 680, VarA, VarB, PregA, (OL)AB, and PwalkA are fingerprints, and (MP)A and LspecA are constants. The terms PregA, (MP)A, and LspecA are additional fingerprints / constants not shown in FIG. 6A but used in equation 680 as examples. The formula may include various constants that are obtained from independent sources such as photomask specifications, processing equipment manufacturer specifications, and the like.

[0084] A layer-level FP such as the layer-level FP EPEA can be used to perform a Pareto analysis to identify the dominant factors that affect the metrics of the layer and thus the manufacturing yield. For example, a calculation using the formula of FIG. 6B can rank the contributions of overlay error, pitch walk in the pattern of thin film A, trench width variability of the trenches in thin film A, and line width variation of the lines in thin film B to the EPE of the layer. In one example, such a Pareto analysis reveals that the most dominant factor is overlay error, which contributes about 55% of the total edge placement error, and the impact of trench width variation is negligible with a contribution of only about 1%. In this example, the contribution to EPE is an aggregate obtained by combining all spatial locations on the wafer. A more targeted analysis can be performed that can further analyze the yield loss in particularly vulnerable areas on the wafer, such as areas near the edge of the wafer. Such an analysis can be used to improve the baseline process flow and manufacturing yield.

[0085] A more general flowchart illustrated in FIG. 7 describes an embodiment of a flow that enables system 700 to extend the methods and techniques described above to create process step transfer functions and process models that predict metric fingerprints, and therefore wafer characteristics, at any step of a baseline wafer fabrication process flow.

[0086] In block 710 of the flowchart of FIG. 7, in-line measurements with associated spatial information are obtained from a wafer processed according to a baseline process flow. This in-line wafer fabrication metrology data can be used to generate a measurement FP and a higher-level FP that characterizes the entire baseline process flow, as shown in block 720. A non-baseline wafer can then be generated in block 730 by modifying process parameters in the process steps of the baseline process flow. Because advanced process flows are complex and involve hundreds of process steps, it can be advantageous to first identify the dominant process steps that affect manufacturing yield using a Pareto analysis similar to that described above, for example, utilizing the layer-level fingerprint EPE formula displayed in FIG. 6B. In block 740, in-line measurements and respective fingerprints are obtained using the wafer metrology data and associated process parameter values ​​of the non-baseline wafers generated in block 730.

[0087] Subsequent blocks in FIG. 7 illustrate how information captured from in-line measurements along with associated spatial coordinates and process parameter values ​​can be utilized to create a predictive model of the baseline process flow.

[0088] In block 750, a transfer function is created to model the correlation between the variation of the wafer characteristics at one process step and the wafer characteristics at a subsequent process step. The variation at the previous process step may be caused by natural deviations in processing conditions or may be intentionally created by changing adjustable process parameters. In block 760, the response of all the coefficients or parameters of the fingerprint to the intentionally changed process parameters at a particular process step is obtained.

[0089] In block 770, the component of the fingerprint response that correlates with the treatment in the previous process step is calculated from the transfer function. The component that is not correlated with the previous process step can then be partitioned. This component is fitted to a mathematical model to obtain the process model for the current process step.

[0090] Process models for all process steps that may have been selected as dominant process steps in block 730 may be generated using the methods described above, as shown in block 780. In block 780, the baseline fingerprint, transfer function, and process models may be used to predict wafer characteristics with associated spatial information at any step in the baseline process flow.

[0091] Collectively, the fingerprint, transfer function, and process model provide a mathematical model of the wafer fabrication process flow that can be used by a wafer fabrication system. Once such a model is created, the fabrication system can use such a model to predict, optimize, adjust, and / or control one or more of the process steps to achieve a desired improvement in manufacturing yield in the production of wafers. In other words, the model can be used to modify / alter the process conditions, such that multiple wafers containing semiconductor dies can be manufactured with a higher yield, resulting in lower manufacturing costs.

[0092] For example, the dominant process steps identified by analyzing the baseline fingerprint can be monitored more frequently. Fingerprints generated from in-line metrology data collected to monitor a production line can not only detect wafers that fail to meet specifications (called non-conformances), but also identify the spatial coordinates of areas of high non-conformance or high density of non-conformances. Such information is advantageous for the detection and determination of systematic non-conformances. The process model can be used to identify one more piece of equipment that may be a possible source of manufacturing yield loss and provide information for the system to adopt a single-tool or multi-tool process control strategy. Furthermore, when used in conjunction with an APC tool, the model can assist the manufacturing system in suggesting or recommending adjustments to specific process parameters to improve the non-conformance and recover the yield loss. In some cases, the system can directly adjust the specific process parameters.

[0093] Additionally, the process model and transfer function may be used to improve the baseline process flow. For example, the system may use the process model to optimize process parameters such that the optimized fingerprint improves a target metric such as EPE. The optimized process parameters may be fed into the process as a new plan of reference (POR), thereby improving the manufacturing yield of the baseline process flow.

[0094] This can be described like this: The system obtains a target range of values ​​for an associated predictable characteristic of a target semiconductor wafer. This target range is the range of acceptable or desired values ​​for an acceptable or desired semiconductor wafer produced by the semiconductor wafer fabrication process. For example, a customer may specify a range of acceptable values ​​for the EPE.

[0095] Using the process model, the system optimizes one or more of the process parameters of the semiconductor wafer fingerprint such that the value of the associated predictable characteristic of the semiconductor wafer produced by the semiconductor wafer fabrication process is within the obtained target range. That is, using the process model, the system calculates values ​​of one or more of the process parameters that effectively produce a value of the associated predictable characteristic that falls within the obtained target range. Of course, in some implementations, the range can be a plus / minus range around the target value.

[0096] Furthermore, because the process model maintains spatial characteristics, process parameters that affect EPE in specific regions of high incompatibility can be identified and adjusted to improve manufacturing yield.

[0097] The methods illustrated in Figures 2 and 7 and associated Figures 1, 3-6 may be implemented in or using a non-transitory computer-readable storage medium that includes instructions that, when executed, cause a processor of a computing device to perform operations in conjunction with a semiconductor wafer fabrication process. In addition, some of the instructions for performing the steps of Figures 2 and 7 may be stored in separate locations of different non-transitory computer-readable storage media and configured to be executed by different processors of different computing devices. Examples of non-transitory computer-readable storage media include various types of memory and other storage media, including non-volatile solid-state memory. For example, non-transitory computer-readable storage media may include, but are not limited to, magnetic storage devices (e.g., hard disks, floppy disks, and magnetic strips), optical disks (e.g., compact disks (CDs) and digital versatile disks (DVDs)), smart cards, flash memory devices (e.g., thumb drives, sticks, key drives, and secure digital (SD) cards), and volatile and non-volatile memory (e.g., random access memory (RAM), read-only memory (ROM)).

[0098] For example, steps 220-290 of Figure 2 may be instructions configured to be executed on one or more processors that result in the development of a process model. Similarly, steps 720-780 of Figure 7 may be instructions configured to be executed on one or more processors that result in the development of a process model.

[0099] The techniques described in relation to Figures 1-7 describe a method for generating fingerprints and using the fingerprints to create a process model. In one application of the fingerprint-based model, a method for detecting any anomalies in a process or process tool may be provided. In another embodiment of an application of the fingerprint-based model, a method for detecting defects is provided.

[0100] A sensitivity calculation of the process model through the rate of change of the model fingerprint to the process variables is provided. A table of fingerprint sensitivities is generated and the process variables are associated with a set of fingerprint sensitivities. The fingerprint of the input substrate is monitored throughout the production process by applying the same fingerprint methodology used in the process model. A calculation of the difference between the input substrate fingerprint and the predicted fingerprint calculated using the process model is performed. This difference fingerprint is compared against the table of fingerprint sensitivities to find the process variable that is most likely to be the cause of the difference. A chart ranking this likelihood can then be created and reported to the user. A spatial relationship between the process variables and the actual measurements on the substrate can be obtained. Direct correlation through fingerprint sensitivities improves the ability to pinpoint defective process tools. In another alternative, the fingerprint process can be utilized to detect defects formed on the substrate. For example, particulates that may be formed on the substrate in a particular process step can be detected through the use of the fingerprint comparison process described herein.

[0101] A defective process tool (or part of a process tool) can significantly impact the fingerprint of a processed substrate. Similarly, defects can significantly impact the fingerprint of a processed substrate. The disclosed method presents details of using fingerprint modeling to detect process variable related drifts to identify defective process tools and / or parts early and / or detect the formation of defects in a process step. The disclosed technique does not require sensor input to detect defective tools and / or defects. Thus, an alternative method of identifying the root cause of a substrate processing problem or defective tools and / or parts by isolating process variables having contributing fingerprint components and detecting based on process variable sensitivity is provided. Similarly, the disclosed method presents details of using fingerprint modeling to detect the formation of defects in a process step. The disclosed technique does not require sensor input to defects. Thus, the use of fingerprint techniques provides an alternative method of identifying substrate processing problems that form defects.

[0102] In one embodiment for process fault detection, after a process model is created (e.g., as described above), the method and system involves calculating the sensitivity of the process model through the rate of change of the fingerprint to each process variable (or "knob"). A table of fingerprint sensitivities is generated through this method, with each process variable associated with a set of fingerprint sensitivities. This table may be stored for use in the monitoring step, as described below.

[0103] In one embodiment, the system monitors the fingerprint of an input substrate (e.g., an input semiconductor wafer) through a production line by applying the same fingerprinting methodology used in the process model. The system then calculates the difference between the input wafer fingerprint and a predicted fingerprint calculated using the process model. This difference fingerprint is compared against a table of fingerprint sensitivities to find the process variable that is most likely to be the cause of the difference. A chart ranking this likelihood can then be created and reported to a user.

[0104] The method of generating such charts reporting process variable related defect correlations is unique in that it does not rely on sensors other than the measured metrology. Traditional methods using sensors rely on other types of measurements that only indirectly affect the substrate. Fingerprint based methods are able to detect spatial relationships between process variables and actual measurements on the substrate. Direct correlation through fingerprint sensitivity improves the ability to pinpoint defective process components and detect wafer performance failures early.

[0105] A defective process tool (or part of a process tool) can significantly impact the fingerprint of a processed wafer. The disclosed method presents details of using fingerprint modeling to detect process variable related drifts to identify defective process tools and / or parts early. The disclosed technique does not require sensor input to detect defective tools and / or parts. Thus, isolating process variables with contributing fingerprint components and detecting them based on process variable sensitivity provides an alternative method of identifying the root cause of substrate processing process issues or defective tools and / or parts.

[0106] FIG. 8 illustrates an exemplary workflow diagram for implementing a fingerprint-based defect detection technique for use with semiconductor wafers. As shown in FIG. 8, initially, in step 800, an experimental design is performed for one or more process steps of a semiconductor process flow. The experimental design may consider a variety of process conditions and variables that may be expected to experience potential changes or variations in a typical process environment. The experimental process may vary those process conditions and variables alone and / or in various combinations on a number of different experimental wafers. Next, wafer data may be collected for each wafer in the experiment, as shown in step 805. A fingerprint may be created, as shown in step 810. Using the experimental data, a process model is created in step 815. The process model may provide fingerprint components as a function of all process conditions.

[0107] When a process model is created in step 815 of Figure 8, the process model may be applied to wafers utilized in a production manufacturing process. To that end, wafer data may be collected, as shown in step 820, for each wafer in the production manufacturing process at a particular point in the manufacturing process flow. A fingerprint may then be created, as shown in step 825. Using the process model created in step 815, a difference may be created in step 835 between the fingerprint of step 825 and the modeled fingerprint calculated in step 830. The techniques described above with respect to Figures 1-7 may be utilized to create the calculated difference in step 835.

[0108] The calculated differences of step 835 can then be utilized in conjunction with the process model of step 815, thus comparing the calculated differences to the process model sensitivities in step 840. The comparison of step 840 can then be used in step 845 to detect faulty process variables ("knobs") that caused the differences detected on the wafer fingerprint compared to the expected modeled fingerprint. In this manner, the fingerprinting process can be utilized to detect defects in the process flow that caused changes to the wafer fingerprint.

[0109] 9-14 provide an exemplary application of the techniques described herein. More specifically, these figures illustrate an example process step in which a thin film is formed on a semiconductor wafer. This example illustrates the use of a fingerprint model to detect faulty process variables in a thin film formation process. Semiconductor processing techniques include a wide range of process variables for each particular process step, including but not limited to surface preparation, ion implantation, thermal steps (e.g., rapid thermal oxidation (RTO), rapid thermal anneal (RTA), laser anneal, etc.), photolithography steps (e.g., resist coat, exposure, development, resist stripping, etc.), electroplating, plasma deposition, plasma etching, wet etching, chemical mechanical polishing (CMP), etc. The particular process variables for any of these process steps can be of a wide range, including but not limited to temperature, pressure, gas, gas flow rate, power setting, voltage setting, current setting, spin speed, dispense volume, liquid, liquid flow rate, liquid density, time, etc. Furthermore, any particular process step may be composed of a series of sub-steps, each with a set of variables for each sub-step (e.g., a plasma etch process or a plasma deposition process may be composed of two, three, four or even more steps).

[0110] FIG. 9 illustrates an exemplary table illustrating various process variables (in this case 19 process model terms 900 shown as Par1-Par19) for a thin film formation process. As shown in FIG. 9, the terms are listed by sensitivity rank (lower ranks are more sensitive). In the illustrated example, Par4 has the lowest rank and is therefore the most sensitive. The corresponding fingerprint terms 905 are also shown. FIG. 10 illustrates film thickness raw data collected spatially across a grid of monitor wafers. FIG. 10 also illustrates the corresponding coefficient magnitudes 1020 and coefficients 1030 provided by the fingerprint model 1040.

[0111] With reference to the workflow diagram of FIG. 8, coefficient intensities 1020 and coefficients 1030 of FIG. 10 provide the fingerprint for step 825 of FIG. 8. FIGS. 11A and 11B illustrate workflow steps 825, 830, and 835 of FIG. 8 for an example film thickness. More specifically, FIG. 11A illustrates the steps applied to a presumed "good" wafer, in this example a wafer processed without process defects. FIG. 11B illustrates the steps applied to a "bad" wafer that experienced a process defect during processing. As shown in FIG. 11A, the coefficients and coefficient intensities of the good wafer create a fingerprint 1110 (such as step 825 of FIG. 8). The predicted coefficients and coefficient intensities are calculated using a process model to create a modeled fingerprint 1120 (such as step 830 of FIG. 8). A difference fingerprint 1130 is then obtained by calculating the difference between the fingerprint 1110 and the modeled fingerprint 1120. 11B illustrates the workflow steps for a wafer subjected to a defective production process as applied in this example. As shown in FIG. 11B, the coefficients and coefficient intensities of the bad wafer are calculated (such as step 825 in FIG. 8) to create a fingerprint 1140. The predicted coefficients and coefficient intensities are calculated using the process model to create a modeled fingerprint 1150 (such as step 830 in FIG. 8). A difference fingerprint 1160 is then obtained by calculating the difference between the fingerprint 1140 and the modeled fingerprint 1150.

[0112] The differential fingerprints (e.g., differential fingerprint 1130 of FIG. 11A and differential fingerprint 1160 of FIG. 11B) can then be compared against process model sensitivities to facilitate a determination of whether a particular process variable is defective. FIGS. 12A and 12B illustrate exemplary results of such a comparison. For example, using the differential fingerprint 1130 can indicate that any difference from the predicted fingerprint is not caused by any one (or set) of the defective process variables. As shown in FIG. 12A, 19 process variables ("process model terms") indicate that no process model exhibits a high probability of being defective. More specifically, FIG. 12A illustrates a chart 1210 that plots the process variables (process model terms 1202) against the defect probability 1204 of the particular process variable. In this example, the analyzed wafers were "good" wafers, i.e., wafers that did not exhibit a particular poor spatial film thickness profile indicative of a defect, and therefore no particular process variable exhibits a significantly high level of defect probability. Based on the analysis, the difference between the actual wafer and the modeled results does not indicate a particular defective process variable. However, FIG. 12B shows the probability of a "bad" wafer, highlighting the detected defects. More specifically, FIG. 12B illustrates a chart 1220 plotting the process variables (process model terms 1202) against the defect probability 1204 of the particular process variable. In this example, a defect related to one of the process variables is detected. As shown, a high defect probability 1230 of over 90% is shown from the process model term 10. Based on the analysis, the difference between the actual wafer (in this case a bad wafer) and the modeled results indicates a defect related to the process variable 10. In this manner, defects in the processing of the wafer can be detected and identified utilizing fingerprinting techniques. A predetermined defect probability level can be established for each process variable to identify when the process variable should be identified as defective.

[0113] As previously mentioned, the fingerprint analysis techniques described herein can also be utilized to identify localized defects on a wafer, such as, for example, induced particles, pattern collapse, voids, hot spots, etc. More specifically, the process modeling techniques described herein can be combined with defect detection techniques. Defect detection can be identified by looking for large spatially localized spikes in data acquired from the wafer, but such techniques may result in false positive detection of defects. To reduce false positive detection of defects, potential process variable variations can also be combined with the analysis. Thus, the process model created through the design of experiments process is utilized in the defect analysis process. By accounting for process variable variations, a more robust defect detection process can be achieved that reduces the occurrence of false positive detections.

[0114] FIG. 13 illustrates an exemplary workflow diagram for implementing a fingerprint-based defect detection technique for use with semiconductor wafers similar to the defect detection technique of FIG. 8. As shown in FIG. 13, steps 800, 805, 810, and 815 similar to FIG. 8 are used to create a process model. Similarly, steps 820, 830, and 835 may be utilized as shown in FIG. 13 with the same step numbers as FIG. 8. It is noted that for production wafers, the fingerprint creation step is not required since defects are associated with localized high frequency spikes and fingerprints typically capture long range spatial variations. Thus, the calculated difference of step 835 may be obtained from the wafer data collected in step 820 and the modeled fingerprint calculated in step 830. Using the calculated difference obtained in step 835, defects may then be detected in step 1310 through analysis of the calculated difference and consideration of the impact of potential process variable changes provided from the process model. In this way, spatially localized spikes in the data can be more confidently identified as defects because the analysis takes into account the effects of potential process variable changes. In this manner, fingerprint-based defect detection can be used to provide a more accurate assessment of the presence of defects.

[0115] 14-16 illustrate an exemplary method for using the processing techniques described herein. It should be appreciated that the embodiments of FIGS. 14-16 are merely exemplary and that additional methods may utilize the techniques described herein. Additionally, additional processing steps may be added to the methods shown in FIGS. 14-16, as the steps described are not intended to be exclusive. Additionally, the order of steps is not limited to the order shown in FIGS. 14-16, as different orders may occur and / or various steps may be combined or performed simultaneously.

[0116] FIG. 14 illustrates a method of characterizing a fabrication process for manufacturing semiconductor wafers, the fabrication process including at least one process step, the at least one process step being associated with a plurality of process variables. As shown, step 1405 includes performing a design of experiment process for the at least one process step, the plurality of process variables being varied for a plurality of design of experiment semiconductor wafers. Step 1410 includes acquiring design of experiment wafer measurements of a first characteristic from a plurality of design of experiment semiconductor wafers, each of the design of experiment wafer measurements being associated with a spatial location on the design of experiment semiconductor wafer at which the measurement is acquired. Step 1415 includes creating a design of experiment process step fingerprint from the acquired design of experiment wafer measurements for each design of experiment semiconductor wafer to provide a plurality of design of experiment process step fingerprints. Step 1420 includes utilizing the plurality of design of experiment process step fingerprints to create a process model for the at least one process step. Step 1425 includes performing the at least one process step on the production semiconductor wafers. Step 1430 includes acquiring production wafer measurements of a first characteristic of the production semiconductor wafer, each of the production wafer measurements being associated with a spatial location on the production semiconductor wafer where the measurement is acquired. Step 1435 includes creating a production semiconductor wafer process step fingerprint from the acquired production semiconductor wafer measurements. Step 1440 includes detecting a faulty process variable of at least one process step utilizing the production semiconductor wafer process step fingerprint and the process model.

[0117] FIG. 15 illustrates a method of characterizing a fabrication process for manufacturing semiconductor wafers, the fabrication process including a plurality of process steps, at least a first one of the plurality of process steps being associated with a plurality of process variables. The method includes performing an experimental design process, the experimental design process including steps 1505-1520. Step 1505 includes performing a first one of the plurality of process steps on the set of experimental design semiconductor wafers for a set of experimental design semiconductor wafers, at least one or more of the values ​​of the plurality of process variables being changed for each of the set of experimental design semiconductor wafers. Step 1510 includes acquiring experimental design wafer measurements of a first characteristic from the set of experimental design semiconductor wafers, each of the experimental design wafer measurements being associated with a spatial location on the experimental design semiconductor wafer at which the experimental design wafer measurement is acquired. Step 1515 includes creating an experimental design process step fingerprint from the acquired experimental design wafer measurements for each experimental design semiconductor wafer to provide a plurality of experimental design process step fingerprints. Step 1520 includes utilizing the plurality of design of experiment process step fingerprints to create a process model for a first one of the plurality of process steps. The method then includes step 1525 of performing a first one of the plurality of process steps on at least one production semiconductor wafer. Step 1530 includes acquiring production wafer measurements of a first characteristic of the production semiconductor wafer, each of the production wafer measurements being associated with a spatial location on the production semiconductor wafer at which the measurement is acquired. Step 1535 includes creating a production wafer process step fingerprint from the acquired production wafer measurements. Step 1540 includes utilizing the production wafer process step fingerprints and the process model to detect faulty process variables.

[0118] FIG. 16 illustrates a method including characterizing a fabrication process for manufacturing semiconductor wafers, the fabrication process including a plurality of process steps, at least a first one of the plurality of process steps being associated with a plurality of process variables. The method includes performing an experimental design process, the experimental design process including steps 1605-1620. Step 1605 includes performing a first one of the plurality of process steps on the set of experimental design semiconductor wafers for a set of experimental design semiconductor wafers, at least one or more of the values ​​of the plurality of process variables being changed for each of the set of experimental design semiconductor wafers. Step 1610 includes acquiring experimental design measurements of a first characteristic from the set of experimental design semiconductor wafers, each of the experimental design wafer measurements being associated with a spatial location on the experimental design semiconductor wafer at which the experimental design wafer measurement is acquired. Step 1615 includes creating an experimental design process step fingerprint from the acquired experimental design wafer measurements for each experimental design semiconductor wafer to provide a plurality of experimental design process step fingerprints. Step 1620 includes creating a process model for a first one of the plurality of process steps utilizing the plurality of design of experiment process step fingerprints. Step 1625 includes performing a first one of the plurality of process steps on at least one production semiconductor wafer. Step 1630 includes acquiring production wafer measurements of a first characteristic of the at least one production semiconductor wafer, each of the production wafer measurements being associated with a spatial location on the at least one production semiconductor wafer at which the measurement is acquired. Step 1635 includes computing a modeling fingerprint for the first one of the plurality of process steps utilizing a process model for the production semiconductor wafer. Step 1640 includes detecting defects on the at least one production semiconductor wafer utilizing the computed modeling fingerprint and the process model for the production semiconductor wafer, the process model being utilized to account for variations in process variables to improve accuracy of defect detection.

[0119] The substrate utilized in the techniques disclosed herein may be any substrate for which etching and patterning of materials is desired. For example, in one embodiment, the substrate may be a semiconductor substrate having one or more semiconductor processing layers formed thereon, all of which together may constitute the substrate. In one embodiment, the substrate may be a substrate that has been subjected to multiple semiconductor processing steps resulting in various structures and layers, all of which are known in the substrate processing art. In one embodiment, the substrate may be a semiconductor wafer that includes various structures and layers formed thereon. In one example, microelectronic devices are formed on the substrate.

[0120] Further modifications and alternative embodiments of the present invention will be apparent to those skilled in the art in view of the description herein. Accordingly, this description is to be interpreted as illustrative only and for the purpose of teaching those skilled in the art how to carry out the present invention. It is to be understood that the forms and methods of the present invention shown and described herein are to be interpreted as presently preferred embodiments. Equivalent techniques may be used in place of those illustrated and described herein, and certain features of the present invention may be utilized independently of the use of other features, all of which will become apparent to those skilled in the art after having the benefit of the description herein of the present invention.

Claims

1. 1. A method for characterizing a fabrication process for manufacturing semiconductor wafers, the fabrication process including at least one process step, the at least one process step being associated with a plurality of process variables, the method comprising: performing a design of experiments process for the at least one process step, wherein the plurality of process variables are varied for a plurality of design of experiments semiconductor wafers; acquiring design of experiment wafer measurements of a first characteristic from the plurality of design of experiment semiconductor wafers, each design of experiment wafer measurement being associated with a spatial location on the design of experiment semiconductor wafer at which the design of experiment wafer measurement was acquired; creating, for each design of experiment semiconductor wafer, a design of experiment process step fingerprint from the acquired design of experiment wafer measurements to provide a plurality of design of experiment process step fingerprints; utilizing the plurality of Design of Experiment process step fingerprints to generate a process model for the at least one process step; performing said at least one process step on a production semiconductor wafer; acquiring production wafer measurements of the first characteristic of the production semiconductor wafers, each of the production wafer measurements being associated with a spatial location on the production semiconductor wafer at which the production wafer measurement is acquired; creating a production semiconductor wafer process step fingerprint from the acquired production semiconductor wafer measurements; Utilizing the process model of the at least one process step to calculate a modeled fingerprint of the production semiconductor wafer; calculating a difference between the modeled fingerprint and the production semiconductor wafer process step fingerprint; utilizing the calculated difference between the modeled fingerprint and the production semiconductor wafer process step fingerprint to detect faulty process variables of the at least one process step; A method comprising:

2. 10. The method of claim 1, wherein the faulty process variable is detected by comparing the calculated difference against a process model sensitivity to facilitate determining whether a particular process variable is faulty.

3. The method of claim 2 , wherein the particular process variable is identified using a probability determination.

4. 4. The method of claim 3, wherein the particular process variable is identified by analyzing a plurality of process model terms obtained by comparing the calculated difference against the process model sensitivities to identify process variables that exceed a predetermined fault probability level.

5. 1. A method for characterizing a fabrication process for manufacturing semiconductor wafers, the fabrication process including a plurality of process steps, at least a first of the plurality of process steps being associated with a plurality of process variables, the method comprising: conducting an experimental design process, the experimental design process comprising: performing, for a series of design-of-experiment semiconductor wafers, the first of the plurality of process steps on the series of design-of-experiment semiconductor wafers, wherein at least one or more of the values ​​of the plurality of process variables are changed for each of the series of design-of-experiment semiconductor wafers; acquiring design of experiments wafer measurements of a first characteristic from the set of design of experiments semiconductor wafers, each design of experiments wafer measurement being associated with a spatial location on the design of experiments semiconductor wafer at which the design of experiments wafer measurement was acquired; creating, for each design of experiment semiconductor wafer, a design of experiment process step fingerprint from the acquired design of experiment wafer measurements to provide a plurality of design of experiment process step fingerprints; utilizing the plurality of design-of-experiment process step fingerprints to generate a process model of the first of the plurality of process steps; and performing said first of said plurality of process steps on at least one production semiconductor wafer; acquiring production wafer measurements of the first characteristic of the production semiconductor wafers, each of the production wafer measurements being associated with a spatial location on the production semiconductor wafer at which the production wafer measurement is acquired; creating a production wafer process step fingerprint from the acquired production wafer measurements; calculating a modeled fingerprint of the production semiconductor wafer utilizing the process model for the first of the plurality of process steps; calculating a difference between the modeled fingerprint and the production wafer process step fingerprint; utilizing the calculated differences between the modeled fingerprints and the production wafer process step fingerprints to detect faulty process variables; A method comprising:

6. 6. The method of claim 5, wherein the faulty process variable is detected by comparing the calculated difference against a variable sensitivity level of the process model to facilitate determining that a particular process variable is the faulty process variable.

7. The method of claim 6 , wherein the faulty process variable is identified utilizing a probability determination.

8. 8. The method of claim 7, wherein the faulty process variables are identified by analyzing a plurality of process model terms obtained by comparing the calculated differences against the variable sensitivity levels to identify process variables that exceed a predetermined fault probability level.

9. The method of claim 5 , wherein the faulty process variable is identified utilizing a probability determination.

10. 10. The method of claim 9, wherein the faulty process variables are identified by analyzing a plurality of process model terms obtained by comparing the calculated differences against variable sensitivity levels to identify process variables that exceed a predetermined fault probability level.

11. 1. A method for characterizing a fabrication process for manufacturing semiconductor wafers, the fabrication process including a plurality of process steps, at least a first of the plurality of process steps being associated with a plurality of process variables, the method comprising: conducting an experimental design process, the experimental design process comprising: performing, for a series of design-of-experiment semiconductor wafers, the first of the plurality of process steps on the series of design-of-experiment semiconductor wafers, wherein at least one or more of the values ​​of the plurality of process variables are changed for each of the series of design-of-experiment semiconductor wafers; acquiring design of experiments wafer measurements of a first characteristic from the set of design of experiments semiconductor wafers, each design of experiments wafer measurement being associated with a spatial location on the design of experiments semiconductor wafer at which the design of experiments wafer measurement was acquired; creating, for each design of experiment semiconductor wafer, a design of experiment process step fingerprint from the acquired design of experiment wafer measurements to provide a plurality of design of experiment process step fingerprints; utilizing the plurality of design-of-experiment process step fingerprints to generate a process model of the first of the plurality of process steps; and performing said first of said plurality of process steps on at least one production semiconductor wafer; acquiring production wafer measurements of the first characteristic of the at least one production semiconductor wafer, each of the production wafer measurements being associated with a spatial location on the at least one production semiconductor wafer at which the production wafer measurement is acquired; calculating a modeled fingerprint of the production semiconductor wafer utilizing the process model for a first one of the plurality of process steps; calculating a difference between the acquired production wafer measurements and the calculated modeled fingerprint; detecting defects on the at least one production semiconductor wafer utilizing the calculated modeled fingerprint of the at least one production semiconductor wafer and the process model, wherein the process model is utilized to account for variations in process variables to improve accuracy of defect detection; and A method comprising:

12. 12. The method of claim 11 , wherein the defects on the at least one production semiconductor wafer are determined by identifying spatially localized anomalies and eliminating false positive defects by accounting for variations in process variables.

13. utilizing the calculated difference when detecting the defects on the at least one production semiconductor wafer. The method of claim 11 further comprising:

14. 14. The method of claim 13, wherein the defects on the at least one production semiconductor wafer are determined by identifying spatially localized anomalies and eliminating false positive defects by accounting for variations in process variables.

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