Memory Transaction Management

Abstract

The device includes a processor coupled to a memory, the processor configured to assign a distinct domain identifier to each of a plurality of software threads, and the processor configured to control operation of one or more components of the processor based on a number of memory transactions associated with the domain identifier.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of priority to commonly owned U.S. patent application Ser. No. 17 / 451,988, filed October 22, 2021, the entire contents of which are expressly incorporated by reference into this specification.

[0002]

[0002] The present disclosure relates generally to managing memory transactions. [Background technology]

[0003]

[0003] Advances in technology have resulted in smaller and more powerful computing devices. For example, there are now a variety of portable personal computing devices, including wireless telephones such as mobile phones and smartphones, tablet and laptop computers, that are small, lightweight, and easily carried by users. These devices can communicate voice and data packets over wireless networks. In addition, many such devices incorporate additional features, such as digital still cameras, digital video cameras, digital recorders, and audio file players. Such devices can also process executable instructions, including software applications, such as web browser applications that can be used to access the Internet. Thus, these devices can include significant computing power.

[0004]

[0004] Such computing devices incorporate functionality to support memory transactions such as reading from and writing to memory. Data to be read from or written to memory is often temporarily stored in a buffer. Buffer resources are consumed when a software thread makes a memory request. A software thread stalls when there are no buffer resources available for a memory transaction. Some data may stay in the buffer longer for software threads that take longer to consume or process the data. Slower traffic can congest the system and block memory requests from other software threads, resulting in delays and poor quality of service. Summary of the Invention

[0005]

[0005] According to one implementation of the present disclosure, a device includes a memory and a processor. The processor is coupled to the memory and configured to assign a distinct domain identifier to each of a plurality of software threads. The processor is also configured to control operation of one or more components of the processor based on a number of memory transactions associated with the domain identifier.

[0006]

[0006] According to another implementation of the present disclosure, a computer-implemented method includes, in a device, assigning a distinct domain identifier to each of a plurality of software threads, the method also including, in the device, controlling operation of one or more components of a processor based on a number of memory transactions associated with the domain identifier.

[0007] According to another implementation of the present disclosure, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to assign a distinct domain identifier to each of a plurality of software threads. The instructions, when executed by the processor, also cause the processor to control operation of one or more components of the processor based on a number of memory transactions associated with the domain identifier.

[0008] According to another implementation of the present disclosure, an apparatus includes means for assigning a distinct domain identifier to each of a plurality of software threads, the apparatus also including means for controlling operation of one or more components of a processor based on a number of memory transactions associated with the domain identifier.

[0009]

[0009] Other aspects, advantages, and features of the present disclosure will become apparent after consideration of the entire application, including the following sections: Brief Description of the Drawings, Forms for Implementing the Invention, and Claims. [Brief description of the drawings]

[0010] [Figure 1]

[0010] FIG. 1 is a block diagram of a particular illustrative aspect of a system operable to manage memory transactions in accordance with certain examples of the present disclosure. [Diagram 2]

[0011] 2 is a diagram of an example of consistency domain configuration data for the system of FIG. 1 in accordance with some examples of the present disclosure. [Diagram 3]

[0012] 2 is a diagram of an example of capacity domain configuration data for the system of FIG. 1 in accordance with some examples of the present disclosure. [Figure 4A]

[0013] 2 is a diagram of an exemplary aspect of the operation of the system of FIG. 1 in accordance with some examples of the present disclosure. [Figure 4B]

[0014] 2 is a diagram of an exemplary aspect of the operation of the system of FIG. 1 in accordance with some examples of the present disclosure. [Figure 4C]

[0015] 2 is a diagram of an exemplary aspect of the operation of the system of FIG. 1 in accordance with some examples of the present disclosure. [Diagram 5]

[0016] 2 is a diagram of an exemplary embodiment of the system of FIG. 1 according to some examples of the present disclosure. [Figure 6]

[0017] 2 is a diagram of an exemplary embodiment of the system of FIG. 1 according to some examples of the present disclosure. [Figure 7]

[0018] 2 is a diagram of an exemplary embodiment of the system of FIG. 1 according to some examples of the present disclosure. [Figure 8]

[0019] 2 is a diagram of an exemplary embodiment of the system of FIG. 1 according to some examples of the present disclosure. [Figure 9]

[0020] 2 is a diagram of an exemplary embodiment of the system of FIG. 1 according to some examples of the present disclosure. [Figure 10A]

[0021] 2 is a diagram of an exemplary aspect of the operation of the system of FIG. 1 in accordance with some examples of the present disclosure. [Figure 10B]

[0022] 2 is a diagram of an exemplary aspect of the operation of the system of FIG. 1 in accordance with some examples of the present disclosure. [Figure 11]

[0023] 2 is a diagram of an exemplary embodiment of the system of FIG. 1 according to some examples of the present disclosure. [Figure 12]

[0024] 2 is a diagram of an exemplary embodiment of the system of FIG. 1 according to some examples of the present disclosure. [Figure 13]

[0025] 2 is a diagram of an exemplary embodiment of the system of FIG. 1 according to some examples of the present disclosure. [Figure 14]

[0026] 2 is a diagram of an exemplary embodiment of the system of FIG. 1 according to some examples of the present disclosure. [Figure 15]

[0027] 2 is a diagram of an exemplary embodiment of the system of FIG. 1 according to some examples of the present disclosure. [Figure 16]

[0028] 2 is a diagram of an exemplary embodiment of the system of FIG. 1 according to some examples of the present disclosure. [Figure 17]

[0029] 2 is a diagram of an exemplary embodiment of the system of FIG. 1 according to some examples of the present disclosure. [Figure 18]

[0030] FIG. 1 is a diagram of a mobile device operable to manage memory transactions, according to some examples of the present disclosure. [Figure 19]

[0031] FIG. 1 illustrates a diagram of a headset operable to manage memory transactions, according to some examples of the present disclosure. [Figure 20]

[0032] FIG. 1 is a diagram of a wearable electronic device operable to manage memory transactions, according to some examples of the present disclosure. [Figure 21]

[0033] FIG. 1 illustrates a diagram of a voice-controlled speaker system operable to manage memory transactions, according to some examples of the present disclosure. [Figure 22]

[0034] 1 is a diagram of a camera operable to manage memory transactions, according to some examples of the present disclosure. [Figure 23]

[0035] FIG. 1 illustrates a diagram of a headset operable to manage memory transactions, such as a virtual reality headset, a mixed reality headset, or an augmented reality headset, in accordance with some examples of the present disclosure. [Figure 24]

[0036] FIG. 2 illustrates a first example of a vehicle operable to manage memory transactions, according to some examples of the present disclosure. [Diagram 25]

[0037] FIG. 13 is a diagram of a second example of a vehicle operable to manage memory transactions, according to some examples of the present disclosure. [Figure 26]

[0038] 2 is a diagram of a particular implementation of a method for managing memory transactions that may be performed by the device of FIG. 1 in accordance with some examples of the present disclosure. [Figure 27]

[0039] 1 is a block diagram of a particular illustrative example of a device operable to manage memory transactions, in accordance with some examples of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011]

[0040] Data read from memory or to be written to memory may be stored in a buffer. Buffer resources are consumed when a software thread makes a memory request. A software thread stalls when there are no buffer resources available for a memory transaction. Some data may stay in the buffer longer due to software threads that take longer to consume or process the data. Slower traffic can congest the system and block memory requests from other software threads, resulting in delays and poor quality of service.

[0012]

[0041] A synchronization operation can be used to enforce ordering. When a typical synchronization operation is performed, all pending transactions must be completed before any subsequent data access operations can be executed. This can lead to software threads being stalled for long periods of time.

[0013]

[0042] Systems and methods for memory transaction management are disclosed. For example, a memory manager assigns a domain identifier to a software thread. The domain identifier is assigned to the software thread based on a thread type of the software thread. The thread type may be based on an application, application type, device, device type, traffic type, or combinations thereof associated with the thread. As an illustrative example, the memory manager assigns a first domain identifier to a first software thread based on a thread type of the first software thread and assigns a second domain identifier to a second software thread based on a thread type of the second software thread. The memory manager tracks a number (e.g., count) of memory transactions associated with each of the first domain identifier and the second domain identifier. The memory manager controls operation of one or more components of the processor based on the number of memory transactions associated with the domain identifier.

[0014]

[0043] In some implementations, the synchronization instruction is used to enforce consistency (e.g., ordering of data accesses) of the software threads. As an illustrative example, a first domain identifier assigned to a first software thread includes a first consistency domain identifier, and a second domain identifier assigned to a second software thread includes a second consistency domain identifier. In response to receiving a synchronization instruction for the first software thread, any pending store operations associated with the first consistency domain identifier are completed before executing any subsequent data access instructions associated with the first consistency domain identifier, thereby enforcing consistency for the first software thread. For example, assigning a first consistency domain identifier to a software thread of a first application allows for enforcing consistency for the software thread of the first application independent of software threads of other applications.

[0015]

[0044] In some examples, some consistency domain identifiers (e.g., sub-domain identifiers) that are not the same as the first consistency domain identifier may match the first consistency domain identifier. In these examples, in response to a synchronization instruction, any pending store operation associated with the first consistency domain identifier or the second consistency domain identifier is completed before executing any subsequent data access instruction associated with the first consistency domain identifier or the second consistency domain identifier if the second consistency domain identifier matches the first consistency domain identifier.

[0016]

[0045] A data access instruction associated with a consistency domain identifier that does not match the first consistency domain identifier is not affected (e.g., is not delayed) by a synchronization instruction associated with the first software thread. By way of illustration, a data access instruction associated with a second software thread is not delayed by a synchronization instruction if the second consistency domain identifier does not match the first consistency domain identifier.

[0017]

[0046] Controlling operation of one or more components of the processor includes, in response to receiving the synchronization instruction, completing any pending store operations associated with any consistency domain identifier matching the first consistency domain identifier before executing any subsequent data access instructions associated with any consistency domain identifier matching the first consistency domain, such that any subsequent data access instructions associated with any consistency domain identifier matching the first consistency domain are executed after a number of preceding pending memory transactions associated with any consistency domain identifier matching the first consistency domain identifier becomes zero, while subsequent data access instructions associated with consistency domain identifiers not matching the first consistency domain identifier are similarly not delayed.

[0018]

[0047] In some implementations, up to a threshold count of memory access instructions associated with a domain identifier may be pending at any time such that some resources may be available for memory access instructions associated with other domain identifiers. As an illustrative example, a first domain identifier assigned to a first software thread includes a first capacity domain identifier and a second domain identifier assigned to a second software thread includes a second capacity domain identifier. The first capacity domain identifier is associated with a first threshold count. In response to determining that the count of pending memory access instructions associated with the first capacity domain identifier is less than the first threshold count, memory access instructions from the first software thread are selectively enabled. In these implementations, controlling the operation of one or more components of the processor includes selectively enabling memory access instructions based on a capacity limit. Limiting the count of pending memory access instructions associated with a capacity domain identifier may allow resources to be made available for memory access instructions associated with other non-matching capacity domain identifiers. For example, assigning a first capacity domain identifier to a software thread of a first application allows for the enforcement of resource limits for the first application independent of resource limits for other applications.

[0019]

[0048] Certain aspects of the present disclosure are described below with reference to the drawings. In this description, common features are designated by common reference numerals. Various terms used herein are used only for the purpose of describing particular implementations and are not intended to limit the implementations. For example, the singular forms "a," "an," and "the" are intended to include the plural unless the context clearly indicates otherwise. Furthermore, some features described herein are singular in some implementations and plural in other implementations. For illustrative purposes, FIG. 1 illustrates a device 102 including one or more processors ("processor(s)" 190 in FIG. 1), indicating that in some implementations the device 102 includes a single processor 190 and in other implementations the device 102 includes multiple processors 190.

[0020]

[0049] In some figures, multiple instances of a particular type of feature are used. Although these features are physically and / or logically different, the same reference number is used for each, and the different instances are distinguished by the addition of a letter to the reference number. When features as a group or type are referred to herein, for example, when no specific one of the features is referred to, the reference number is used without the distinguishing letter. However, when one specific feature of multiple features of the same type is referred to herein, the reference number is used with the distinguishing letter. For example, with reference to FIG. 1, multiple cache control registers (CCRs) are illustrated and associated with reference numbers 154A and 154B. When referring to a specific one of these cache control registers, such as cache control register (CCR) 154A, the distinguishing letter "A" is used. However, when referring to any one of these cache control registers or to these cache control registers as a group, the reference number 154 is used without the distinguishing letter.

[0021]

[0050] As used herein, the terms "comprise", "comprises", and "comprising" may be used interchangeably with "include", "includes", or "including". Additionally, the term "wherein" may be used interchangeably with "where". As used herein, "exemplary" refers to an example, implementation, and / or aspect, and should not be construed as limiting, or as indicating a preferred or preferred implementation. As used herein, orthogonal terms (e.g., "first", "second", "third", etc.) used to modify an element, such as a structure, component, operation, etc., do not in themselves indicate a priority or order of the element with respect to another element, but merely distinguish the element from other elements having the same name (apart from the use of orthogonal terms). As used herein, the term "set" refers to one or more of a particular element, and the term "plurality" refers to a multiple (e.g., two or more) of a particular element.

[0022]

[0051] As used herein, "coupled" may include "communicatively coupled," "electrically coupled," or "physically coupled," as well as (or alternatively) any combination thereof. Two devices (or components) may be directly or indirectly coupled (e.g., communicatively coupled, electrically coupled, or physically coupled) via one or more other devices, components, wires, buses, networks (e.g., wired networks, wireless networks, or combinations thereof), and the like. Two devices (or components) that are electrically coupled may be included in the same device or in different devices, and may be connected via electronic circuits, one or more connectors, or inductive coupling, as illustrative and non-limiting examples. In some implementations, two devices (or components) that are communicatively coupled, such as in electrical communication, may send and receive signals (e.g., digital or analog signals) directly or indirectly via one or more wires, buses, networks, and the like. As used herein, "directly coupled" may include two devices that are coupled (e.g., communicatively coupled, electrically coupled, or physically coupled) with no intervening components.

[0023]

[0052] In this disclosure, terms such as "determining," "calculating," "estimating," "shifting," "adjusting," and the like may be used to describe how one or more operations are performed. It should be noted that such terms should not be construed as limiting, and other techniques may be utilized to perform similar operations. Additionally, "generating," "calculating," "estimating," "using," "selecting," "accessing," and "determining" referred to herein may be used interchangeably. For example, "generating," "calculating," "estimating," or "determining" a parameter (or signal) may refer to actively generating, estimating, calculating, or determining a parameter (or signal), or may refer to using, selecting, or accessing a parameter (or signal) that has already been generated, such as by another component or device.

[0024]

[0053] 1, a particular example embodiment of a system 100 configured to manage memory transactions is disclosed. The system 100 includes a device 102 configured to manage memory transactions using a memory manager 140.

[0025]

[0054] The device 102 includes one or more processors 190 coupled to the memory 120. In certain aspects, the memory 120 includes a data storage, a memory controller, or both. In some aspects, a cache 172 (e.g., a memory buffer) is coupled to the memory 120 via an interface 174. The one or more processors 190 include a memory manager 140 and one or more components 170. In some aspects, the one or more components 170 include one or more of the cache 172, the interface 174, the memory 120, a data bus, a modem, an antenna, an instruction buffer, or a coprocessor (e.g., a graphics processing unit (GPU), a digital signal processor (DSP), or another type of processor). The memory manager 140 can access the configuration data 146, the domain identifier data 150, the transaction tracker 160, or a combination thereof. The memory manager 140 includes a coherence domain manager 142, a capacity domain manager 144, or both.

[0026]

[0055] Transaction tracker 160 is configured to track a consistency domain number 162 of transaction data, a capacity domain number 164 of transaction data, or both. In a particular aspect, the consistency domain number 162 of transaction data indicates a number (e.g., count) of transactions associated with each of one or more consistency domain identifiers 156. In a particular aspect, the capacity domain number 164 of transaction data indicates a number (e.g., count) of transactions associated with each of one or more capacity domain identifiers 158.

[0027]

[0056] Memory manager 140 is configured to assign a separate domain identifier (e.g., consistency domain identifier 156, capacity domain identifier 158, or both) to each of multiple software threads 152. In some aspects, a process (e.g., an application) executing on one or more processors 190 initializes software threads 152. In some aspects, software threads 152 correspond to database worker threads. For example, software threads 152 receive data access requests from another process or device and service the data access requests by sending memory access instructions to memory manager 140.

[0028]

[0057] The memory manager 140 is configured to manage memory transactions of one or more software threads 152 based on the domain identifier. For example, the coherence domain manager 142 is configured to manage memory transactions based on the coherence domain number 162 of the transaction data. As another example, the capacity domain manager 144 is configured to manage memory transactions based on the capacity domain number 164 of the transaction data. In some examples, the memory transaction includes one or more of reading data from the memory 120 to the cache 172 via the interface 174, providing data from the cache 172 to the software thread 152, updating data in the cache 172 based on data received from the software thread 152, or writing updated data from the cache 172 to the memory 120 via the interface 174. In some aspects, controlling the operation of the one or more components 170 includes or corresponds to performing a memory transaction.

[0029]

[0058] In some implementations, the device 102 corresponds to or is included in one of a variety of types of devices. In the illustrated example, the one or more processors 190 are incorporated into a headset device, as further described with reference to FIG. 19. In other examples, the one or more processors 190 are incorporated into at least one of a mobile phone or tablet computing device, as described with reference to FIG. 18, a wearable electronic device, as described with reference to FIG. 20, a voice-controlled speaker system, as described with reference to FIG. 21, a camera device, as described with reference to FIG. 22, or a virtual reality, mixed reality, or augmented reality headset, as described with reference to FIG. 23. In another illustrated example, the one or more processors 190 are incorporated into a vehicle, as further described with reference to FIG. 24 and FIG. 25.

[0030]

[0059] During operation, memory manager 140 assigns a distinct domain identifier to each of one or more software threads 152 based on the corresponding thread type. For example, software threads of a first thread type are assigned a domain identifier with a particular prefix (e.g., "00"), and software threads of a second thread type are assigned a domain identifier with a different prefix (e.g., "01"). The thread type of a software thread may be based on an application, an application type, a device, a device type, a traffic type, or a combination thereof, associated with the software thread.

[0031]

[0060] In some implementations, the cache control register 154 associated with the software thread 152 indicates the coherence domain identifier 156, the capacity domain identifier 158, or both, assigned to the software thread 152. For example, during initialization of the software thread 152A, the coherence domain manager 142 updates the cache control register 154A associated with the software thread 152A to indicate that the coherence domain identifier 156A has been assigned to the software thread 152A. In some aspects, the capacity domain manager 144 updates the cache control register 154A during initialization of the software thread 152A to indicate that the capacity domain identifier 158A has been assigned to the software thread 152A.

[0032]

[0061] Similarly, during initialization of software thread 152B, coherence domain manager 142 updates cache control register 154B associated with software thread 152B to indicate that coherence domain identifier 156B is assigned to software thread 152B. Coherence domain identifier 156A is distinct from coherence domain identifier 156B. In some aspects, capacity domain manager 144 updates cache control register 154B during initialization of software thread 152B to indicate that capacity domain identifier 158B is assigned to software thread 152B. Capacity domain identifier 158A is distinct from capacity domain identifier 158B.

[0033]

[0062] 1 represents cache control register 154A indicating that coherence domain identifier 156A, capacity domain identifier 158A, or both are assigned to software thread 152A. In a particular aspect, domain identifier data 150 of Figure 1 represents cache control register 154B indicating that coherence domain identifier 156B, capacity domain identifier 158B, or both are assigned to software thread 152B.

[0034]

[0063] Memory manager 140 manages memory transactions based at least in part on whether software thread 152A and software thread 152B have matching domain identifiers, as will be further described with reference to Figures 2-15. For example, consistency domain manager 142 manages memory transactions based at least in part on whether consistency domain identifier 156A matches consistency domain identifier 156B, as will be further described with reference to Figures 2 and 4-15. To illustrate, consistency domain manager 142 updates (e.g., increments) consistency domain number 162 of the transaction data to indicate a pending store operation associated with consistency domain identifier 156A in response to a store associated with software thread 152A being committed, as will be further described with reference to Figure 5. In response to receiving a synchronization instruction for software thread 152A and determining that consistency domain number 162 of transaction data indicates at least one pending store operation that matches consistency domain identifier 156A, consistency domain manager 142 refrains from executing any subsequent memory access instruction that matches consistency domain identifier 156A, as will be further described with reference to Figures 6-7. In response to determining that the pending store operation is associated with a consistency domain identifier (e.g., consistency domain identifier 156A or another consistency domain identifier) ​​that matches consistency domain identifier 156A, consistency domain manager 142 determines that the pending store operation "matches" consistency domain identifier 156A, as will be further described with reference to Figure 2. In response to receiving an acknowledgment from memory 120 that the pending store operation has completed, consistency domain manager 142 updates (e.g., decrements) consistency domain number 162 of transaction data, as will be further described with reference to Figure 8.

[0035]

[0064] In some aspects, following receiving a synchronization instruction for software thread 152A, in response to determining that there is no pending store operation matching consistency domain identifier 156A, consistency domain manager 142 allows a subsequent memory access operation associated with any consistency domain identifier that matches consistency domain identifier 156A (e.g., consistency domain identifier 156A or another consistency domain identifier) ​​to be executed.

[0036]

[0065] In some examples, capacity domain manager 144 manages memory transactions associated with software thread 152A and software thread 152B based at least in part on whether capacity domain identifier 158A matches capacity domain identifier 158B, as further described with reference to FIGS. 3 and 16-17. To illustrate, capacity domain number 164 of transaction data indicates a count of pending memory accesses that match capacity domain identifier 158A. In some aspects, a pending memory access "matches" capacity domain identifier 158A when the pending memory access is associated with a capacity domain identifier (e.g., capacity domain identifier 158A or another capacity domain identifier) ​​that matches capacity domain identifier 158A. Capacity domain manager 144 determines whether the count of pending memory accesses is equal to or greater than a threshold count in response to receiving a memory access instruction from software thread 152A, as further described with reference to FIGS. 16-17. In response to determining that the count of pending memory accesses is less than the threshold count, the capacity domain manager 144 initiates a memory access associated with the memory access instruction and updates (e.g., increments) the count of memory accesses indicated by the transaction data capacity domain number 164. Alternatively, in response to determining that the count of pending memory accesses is equal to or greater than the threshold count, the capacity domain manager 144 refrains from performing the memory access. In response to receiving an acknowledgment that the pending memory access has completed, the capacity domain manager 144 updates (e.g., decrements) the transaction data capacity domain number 164, as will be further described with reference to FIGS. 16-17.

[0037]

[0066] Capacity domain manager 144 limits the count of pending memory accesses that match a capacity domain identifier to allow resources to be available for memory accesses associated with other non-matching capacity domain identifiers. Consistency domain manager 142 ensures that synchronization instructions associated with a particular consistency domain identifier do not affect (e.g., delay) memory access instructions associated with other consistency domain identifiers that do not match the particular consistency domain identifier.

[0038]

[0067] Memory manager 140 is described as managing memory transactions for memory 120 included in device 102 as an illustrative example. In other examples, memory manager 140 may perform similar operations based on the domain identifier to manage transactions for another component of device 102 or to manage transactions for another device. In an illustrative example, memory manager 140 manages data transactions with external devices (e.g., data storage to or retrieval from an external device) based on consistency domain identifier 156, capacity domain identifier 158, or a combination thereof.

[0039]

[0068] 2, an example of consistency domain configuration data 202 is shown along with multiple sets 222-228 of consistency domain identifiers based on the consistency domain configuration data 202. In a particular aspect, the consistency domain configuration data 202 is included in the configuration data 146 of FIG. 1. The consistency domain configuration data 202 may be implemented as a collection of bits (e.g., a bit mask) with a value of "1" specifying which bits are compared when determining whether two or more consistency domain identifiers 156 "match" one another, as described further below.

[0040]

[0069] Each cache control register 154 includes a first count of bits (e.g., 32 bits), from the least significant bit (e.g., bit 0) to the most significant bit (e.g., bit 31). In some aspects, a first set of bits (e.g., bits 8 through 15) of a cache control register 154 associated with a software thread 152 may be used to indicate a consistency domain identifier 156 assigned to the software thread 152.

[0041]

[0070] In some implementations, a first set of bits (e.g., bits 8 through 15) of the cache control register 154 indicate multiple sets of consistency domain identifiers that may be used to define a domain or sub-domain of consistency domain identifiers. The consistency domain configuration data 202 indicates which bits of the cache control register 154 are implemented to indicate a set of consistency domain identifiers. For illustration, the consistency domain configuration data 202 indicates that a first subset (e.g., bits 14 through 15) of the first set of bits (e.g., bits 8 through 15) of the cache control register 154 are implemented to indicate a set of consistency domain identifiers. For example, a first subset (e.g., bits 14 through 15) of a particular consistency domain identifier 156 indicates the set of consistency domain identifiers that includes that particular consistency domain identifier 156.

[0042]

[0071] In certain aspects, the count of bits in the first subset (e.g., 2) may be greater than or equal to the count of the set of supported consistency domain identifiers (e.g., 2 (ビットのカウント)or a set of four). For example, a first subset of bit values ​​212 (e.g., a value of 0 for each of bit 15 and bit 14) indicates a set of consistency domain identifiers 222 (e.g., binary numbers 00000000 to 00111111 or decimal numbers 0 to 63). A first subset of bit values ​​214 (e.g., a value of 0 for bit 15 and a value of 1 for bit 14) indicates a set of consistency domain identifiers 224 (e.g., binary numbers 01000000 to 01111111 or decimal numbers 64 to 127). A first subset of bit values ​​216 (e.g., a value of 1 for bit 15 and a value of 0 for bit 14) indicates a set of consistency domain identifiers 226 (e.g., binary numbers 10000000 to 10111111 or decimal numbers 128 to 195). The first subset bit values ​​218 (e.g., a value of 1 for each of bit 15 and bit 14) indicate a set of consistency domain identifiers 228 (e.g., binary numbers 11000000 to 11111111 or decimal numbers 196 to 255). In the illustrated example, the first subset includes two bits that can support four sets of consistency domain identifiers. However, in other examples, the first subset can include any count of bits that support a corresponding count of sets of consistency domain identifiers (e.g., a first subset including three bits can support eight sets of consistency domain identifiers, etc.).

[0043]

[0072] In some implementations, each set of consistency domain identifiers corresponds to a separate consistency domain. In these implementations, two or more consistency domain identifiers "match" each other if they have the same bit values ​​for the first subset (e.g., bits 14 to 15). For example, consistency domain identifier 156A matches consistency domain identifier 156B if each of consistency domain identifier 156A and consistency domain identifier 156B has the same bit values ​​for the first subset (e.g., bits 14 to 15). To illustrate, consistency domain identifier 156A matches consistency domain identifier 156B if both consistency domain identifier 156A and consistency domain identifier 156B are included in the same set of consistency domain identifier set 222 (e.g., decimal numbers 0 to 63), consistency domain identifier set 224 (e.g., decimal numbers 64 to 127), consistency domain identifier set 226 (e.g., decimal numbers 128 to 195), or consistency domain identifier set 228 (e.g., decimal numbers 196 to 255).

[0044]

[0073] In an example where consistency domain identifier 156A has a first value "4" and consistency domain identifier 156B has a second value "6", consistency domain identifier 156A having a first value (e.g., decimal number 4) included in consistency domain identifier set 222 (e.g., decimal number 0 to 63) matches consistency domain identifier 156B having a second value (e.g., decimal number 6) also included in consistency domain identifier set 222. In an example where consistency domain identifier 156A has a first value "4" and consistency domain identifier 156B has a second value "125", consistency domain identifier 156A having a first value (e.g., decimal number 4) included in consistency domain identifier set 222 (e.g., decimal number 0 to 63) does not match consistency domain identifier 156B having a second value (e.g., decimal number 125) not included in consistency domain identifier set 222.

[0045]

[0074] In some implementations, one or more of the consistency domains may include multiple sets of consistency domain identifiers. For example, the first consistency domain includes a set of consistency domain identifiers 222 (e.g., decimal numbers 0 to 63) and a set of consistency domain identifiers 224 (e.g., decimal numbers 64 to 127). The second consistency domain includes a set of consistency domain identifiers 226 (e.g., decimal numbers 128 to 195) and a set of consistency domain identifiers 228 (e.g., decimal numbers 196 to 255). In this example, the first consistency domain corresponds to a value of 0 for bit 15, and the second consistency domain corresponds to a value of 1 for bit 15. In some implementations, a consistency domain identifier 156A (e.g., decimal number 3) included in the first consistency domain (e.g., decimal numbers 0 to 127) matches a consistency domain identifier 156B (e.g., decimal number 70) included in the first consistency domain. However, a consistency domain identifier 156A (e.g., decimal number 3) that is included in the first consistency domain (e.g., decimal number 0 to 127) does not match a consistency domain identifier 156B (e.g., decimal number 129) that is not included in the first consistency domain.

[0046]

[0075] In some aspects, the coherence domain manager 142 assigns software threads 152 associated with a first thread type a domain identifier from a first coherence domain (e.g., decimal 0 to 127) and assigns software threads 152 associated with a second thread type a domain identifier from a second coherence domain (e.g., decimal 128 to 255). The thread type of the software threads 152 can be based on an application, an application type, a device, a device type, a traffic type, or combinations thereof associated with the software threads 152. In certain aspects, the traffic type can include communication traffic types such as cellular traffic, wireless local area network (WLAN) traffic, Bluetooth® (registered trademark of BLUETOOTH SIG, INC., of Washington) traffic, fifth generation (5G) cellular digital networks, Institute of Electrical and Electronic Engineers (IEEE) 802.11 type networks (e.g., WiFi) traffic, or other types of communication traffic. As an example, a first thread type is associated with cellular modem traffic and a second thread type is associated with WLAN traffic. By assigning software threads 152 associated with cellular modem traffic with a consistency domain identifier from a first consistency domain (e.g., decimal numbers 0 to 127) and software threads 152 associated with WLAN traffic with a consistency domain identifier from a second consistency domain (e.g., decimal numbers 128 to 255), separation of the cellular modem traffic and the WLAN traffic is enabled. For example, cellular modem memory transactions are not blocked by synchronization operations associated with WLAN memory transactions and vice versa.

[0047]

[0076] In some implementations, a consistency domain may be divided into subdomains. For example, a first consistency domain may include a first subdomain that includes a set of consistency domain identifiers 222 (e.g., decimal numbers 0 to 63) and a second subdomain that includes a set of consistency domain identifiers 224 (e.g., decimal numbers 64 to 127). In some aspects, a second consistency domain includes a set of consistency domain identifiers 226 (e.g., 128 to 195) and a set of consistency domain identifiers 228 (e.g., 196 to 255) that are not divided into subdomains.

[0048]

[0077] In some implementations, a consistency domain identifier 156A (e.g., decimal number 3) included in a first sub-domain (e.g., decimal numbers 0 to 63) matches a consistency domain identifier 156B (e.g., decimal number 62) included in the first sub-domain. However, a consistency domain identifier 156A (e.g., decimal number 3) included in a first sub-domain (e.g., decimal numbers 0 to 63) does not match a consistency domain identifier 156B (e.g., decimal number 70) that is not included in the first sub-domain. For example, a consistency domain identifier 156A included in a first sub-domain (e.g., decimal numbers 0 to 63) of a first consistency domain does not match a consistency domain identifier 156B included in a second sub-domain (e.g., decimal numbers 64 to 127) of the first consistency domain.

[0049]

[0078] In some aspects, the consistency domain manager 142 assigns a consistency domain identifier 156 from a first subdomain (e.g., decimal 0 to 63) to a software thread 152 associated with a first thread subtype of a first thread type and assigns a consistency domain identifier 156 from a second subdomain (e.g., decimal 64 to 127) to a software thread 152 associated with a second thread subtype of the first thread type. The thread subtype of the software thread 152 can be based on an application, an application type, a device, a device type, a traffic type, or a combination thereof associated with the software thread 152. For example, the first thread subtype is associated with cellular modem traffic from the device 102 to a first device and the second thread subtype is associated with cellular modem traffic from the device 102 to a second device.

[0050]

[0079] By assigning a consistency domain identifier 156 from a first sub-domain (e.g., decimal 0 to 63) to a software thread 152 associated with cellular modem traffic to a first device and a consistency domain identifier from a second sub-domain (e.g., decimal 64 to 127) to a software thread 152 associated with cellular modem traffic to a second device, separation between the cellular modem traffic to the first device and the cellular modem traffic to the second device is enabled. For example, cellular modem memory transactions associated with the first device are not blocked by synchronization operations associated with cellular modem memory transactions associated with the second device, and vice versa. Thus, in some implementations, matching is determined at a sub-domain level rather than a domain level.

[0051]

[0080] In some implementations, the match may be determined at the domain level or at the sub-domain level. For example, a particular value (e.g., 0) of the consistency domain identifier 156A may be used to indicate that a synchronization operation is associated with the entire domain compared to one of the sub-domains. In some aspects, a particular value (e.g., 0) is reserved to indicate the entire domain and is not included in any sub-domain. In a particular example, the consistency domain identifier 156A (e.g., decimal 0) is used to indicate a first consistency domain that includes a first sub-domain (e.g., decimal 1 to 63) and a second sub-domain (e.g., decimal 64 to 127). For example, the consistency domain identifier 156B (e.g., decimal 1 to 63 of the first sub-domain) matches the consistency domain identifier 156A (e.g., decimal 0 indicating the first consistency domain) to block cellular modem memory transactions of the first sub-domain during a synchronization operation associated with the consistency domain identifier 156A. As another example, the consistency domain identifier 156B (e.g., decimal 64 to 127 in the second sub-domain) also matches the consistency domain identifier 156A (e.g., decimal 0 indicating the first consistency domain) to block cellular modem memory transactions in the second sub-domain during synchronization operations associated with the consistency domain identifier 156A.

[0052]

[0081] Subsequent cellular modem memory transactions associated with both the first device and the second device are blocked by a synchronization operation associated with a consistency domain identifier 156A that indicates the first consistency domain. If memory transactions of a sub-domain are to be blocked, a synchronization operation associated with a consistency domain identifier that indicates a sub-domain (rather than the entire domain) can be used. For example, a synchronization operation associated with a consistency domain identifier 156A that corresponds to a first sub-domain (e.g., decimal 1 to 63) blocks subsequent memory transactions of the first sub-domain, but does not block memory transactions of the second sub-domain. As another example, a synchronization operation associated with a consistency domain identifier 156A that corresponds to a second sub-domain (e.g., decimal 64 to 127) blocks subsequent memory transactions of the second sub-domain, but does not block memory transactions of the first sub-domain.

[0053]

[0082] 3, an example of capacity domain configuration data 302 is shown along with multiple sets 322-328 of capacity domain identifiers based on the capacity domain configuration data 302. In a particular aspect, the capacity domain configuration data 302 is included in the configuration data 146 of FIG. 1. The capacity domain configuration data 302 may be implemented as a collection of bits (e.g., a bit mask) with a value of "1" specifying which bits are compared when determining whether two or more capacity domain identifiers 158 "match" each other, as described further below.

[0054]

[0083] In some aspects, a second set of bits (e.g., bits 0 to 5) of cache control register 154 may be used to indicate a capacity domain identifier 158 assigned to software thread 152. In some implementations, the second set of bits (e.g., bits 0 to 5) of cache control register 154 indicate multiple sets of capacity domain identifiers that may be used to define domains or sub-domains of capacity domain identifiers. Capacity domain configuration data 302 indicates bits of cache control register 154 that are implemented to indicate a set of capacity domain identifiers. For illustration, capacity domain configuration data 302 indicates that a second subset (e.g., bits 4 to 5) of the second set of bits (e.g., bits 0 to 5) of cache control register 154 is implemented to indicate a set of capacity domain identifiers. For example, the second subset (e.g., bits 4 to 5) of capacity domain identifier 158 indicates a set of capacity domain identifiers that includes capacity domain identifier 158.

[0055]

[0084] In certain aspects, the count of bits in the second subset (e.g., 2) may be greater than or equal to the count of the set of supported capacity domain identifiers (e.g., 2 (ビットのカウント)or a set of four). For example, second subset bit values ​​312 (e.g., a value of 0 for each of bit 5 and bit 4) indicate a set of capacity domain identifiers 322 (e.g., binary numbers 000000 to 001111 or decimal numbers 0 to 15). Second subset bit values ​​314 (e.g., a value of 0 for bit 5 and a value of 1 for bit 4) indicate a set of capacity domain identifiers 324 (e.g., binary numbers 010000 to 011111 or decimal numbers 16 to 31). Second subset bit values ​​316 (e.g., a value of 1 for bit 5 and a value of 0 for bit 4) indicate a set of capacity domain identifiers 326 (e.g., binary numbers 100000 to 101111 or decimal numbers 32 to 47). The second subset bit values ​​318 (e.g., a value of 1 for each of bit 5 and bit 4) indicate a set of capacity domain identifiers 328 (e.g., binary 110000 to 111111 or decimal 48 to 63). A second subset including two bits capable of supporting four sets of capacity domain identifiers is provided as an illustrative example. In other examples, the second subset may include any count of bits that support a corresponding count of sets of capacity domain identifiers. A second subset (e.g., bits 4 to 5) of capacity domain identifier 158 including the same count (e.g., 2) of bits included in the first subset (e.g., bits 14 to 15) of coherency domain identifier 156 is provided as an illustrative example. In other examples, the second subset may include fewer or more bits than included in the first subset. The capacity domain identifiers are used to enforce resource utilization restrictions, while the coherency domain identifiers are used to enforce synchronization.

[0056]

[0085] In some implementations, each set of capacity domain identifiers corresponds to a separate capacity domain. In these implementations, two or more capacity domain identifiers "match" each other if they have the same bit values ​​for the second subset (e.g., bits 4 to 5). For example, capacity domain identifier 158A matches capacity domain identifier 158B if capacity domain identifier 158A and capacity domain identifier 158B each have the same bit values ​​for the second subset (e.g., bits 4 to 5). To illustrate, capacity domain identifier 158A matches capacity domain identifier 158B if both capacity domain identifier 158A and capacity domain identifier 158B are included in the same set of capacity domain identifier set 322 (e.g., decimal numbers 0 to 15), capacity domain identifier set 324 (e.g., decimal numbers 16 to 31), capacity domain identifier set 326 (e.g., decimal numbers 32 to 47), or capacity domain identifier set 328 (e.g., decimal numbers 48 to 63).

[0057]

[0086] In an example where capacity domain identifier 158A has a first value "4" and capacity domain identifier 158B has a second value "6," capacity domain identifier 158A having a first value (e.g., decimal number 4) included in set of capacity domain identifiers 322 (e.g., decimal numbers 0 to 15) matches capacity domain identifier 158B having a second value (e.g., decimal number 6) also included in set of capacity domain identifiers 322. In an example where capacity domain identifier 158A has a first value "4" and capacity domain identifier 158B has a second value "18," capacity domain identifier 158A having a first value (e.g., decimal number 4) included in set of capacity domain identifiers 322 (e.g., decimal numbers 0 to 15) does not match capacity domain identifier 158B having a second value (e.g., decimal number 18) not included in set of capacity domain identifiers 322.

[0058]

[0087] In some implementations, one or more of the capacity domains may include multiple sets of domain identifiers. For example, a first capacity domain includes a set of capacity domain identifiers 322 (e.g., decimal numbers 0 to 15) and a set of capacity domain identifiers 324 (e.g., decimal numbers 16 to 31). A second capacity domain includes a set of capacity domain identifiers 326 (e.g., decimal numbers 32 to 47) and a set of capacity domain identifiers 328 (e.g., decimal numbers 48 to 63). In this example, the first capacity domain corresponds to a value of 0 for bit 5 and the second capacity domain corresponds to a value of 1 for bit 5. In some implementations, a capacity domain identifier 158A (e.g., decimal number 3) included in the first capacity domain (e.g., decimal numbers 0 to 31) matches a capacity domain identifier 158B (e.g., decimal number 17) included in the first capacity domain. However, capacity domain identifier 158A (eg, decimal number 3) that is included in the first capacity domain (eg, decimal numbers 0 to 31) does not match capacity domain identifier 158B (eg, 41) that is not included in the first capacity domain.

[0059]

[0088] In some aspects, the capacity domain manager 144 assigns software threads 152 associated with a first thread type a capacity domain identifier from a first capacity domain (e.g., decimal numbers 0 to 31) and assigns software threads 152 associated with a second thread type a domain identifier from a second capacity domain (e.g., decimal numbers 32 to 63). For example, a first thread type is associated with cellular modem traffic and a second thread type is associated with wireless local area network (WLAN) traffic. By assigning software threads 152 associated with cellular modem traffic a capacity domain identifier from the first capacity domain (e.g., decimal numbers 0 to 31) and assigning software threads 152 associated with WLAN traffic a capacity domain identifier from the second capacity domain (e.g., decimal numbers 32 to 63), separate capacity limitations are enabled for cellular modem traffic and WLAN traffic. For example, cellular modem memory transactions are not blocked by too many WLAN memory transactions and vice versa.

[0060]

[0089] In some implementations, a capacity domain may be divided into subdomains. For example, a first capacity domain may include a first subdomain that includes a set of capacity domain identifiers 322 (e.g., decimal numbers 0 to 15) and a second subdomain that includes a set of capacity domain identifiers 324 (e.g., decimal numbers 16 to 31). In some aspects, a second capacity domain includes a set of capacity domain identifiers 326 (e.g., 32 to 47) and a set of capacity domain identifiers 328 (e.g., 48 to 63) that are not divided into subdomains.

[0061]

[0090] In some implementations, capacity domain identifier 158A (e.g., decimal number 3) included in the first subdomain (e.g., decimal numbers 0 to 15) matches capacity domain identifier 158B (e.g., decimal number 6) included in the first subdomain. However, capacity domain identifier 158A (e.g., decimal number 3) included in the first subdomain (e.g., decimal numbers 0 to 15) does not match capacity domain identifier 158B (e.g., decimal number 17) not included in the first subdomain. For example, capacity domain identifier 158A included in the first subdomain (e.g., decimal numbers 0 to 15) of the first capacity domain does not match capacity domain identifier 158B included in the second subdomain (e.g., decimal numbers 16 to 31) of the first capacity domain.

[0062]

[0091] In some aspects, the capacity domain manager 144 assigns a capacity domain identifier 158 from a first subdomain (e.g., decimal numbers 0 to 15) to a software thread 152 associated with a first thread subtype of a first thread type and assigns a capacity domain identifier 158 from a second subdomain (e.g., decimal numbers 16 to 31) to a software thread 152 associated with a second thread subtype of the first thread type. For example, the first thread subtype is associated with cellular modem traffic of a first device and the second thread subtype is associated with cellular modem traffic of a second device.

[0063]

[0092] By assigning the software thread 152 associated with the cellular modem traffic of the first device with a capacity domain identifier 158 from a first sub-domain (e.g., decimal numbers 0 to 15) and the software thread 152 associated with the cellular modem traffic of the second device with a capacity domain identifier from a second sub-domain (e.g., decimal numbers 16 to 31), separate capacity limitations are possible for the cellular modem traffic of the first device and the cellular modem traffic of the second device. For example, cellular modem memory transactions of the first device are not blocked by too many cellular modem memory transactions of the second device, and vice versa. Thus, in some implementations, matching is determined at a sub-domain level rather than a domain level.

[0064]

[0093] In some implementations, the match may be determined at the domain level or at the sub-domain level. For example, a particular value (e.g., 0) of the capacity domain identifier 158A may be used to indicate the entire domain compared to one of the sub-domains. In some aspects, a particular value (e.g., 0) is reserved to indicate the entire domain and is not included in any sub-domain. In a particular example, the capacity domain identifier 158A (e.g., decimal number 0) is used to indicate a first capacity domain that includes a first sub-domain (e.g., decimal numbers 1 to 15) and a second sub-domain (e.g., decimal numbers 16 to 31). For example, the capacity domain identifier 158B (e.g., decimal numbers 1 to 15 of the first sub-domain) matches the capacity domain identifier 158A (e.g., decimal number 0 indicating the first capacity domain). As another example, capacity domain identifier 158B (eg, decimal numbers 16 through 31 for the second sub-domain) also matches capacity domain identifier 158A (eg, decimal number 0 for the first capacity domain).

[0065]

[0094] In some examples, the first capacity domain is associated with a domain threshold count (e.g., 8), the first subdomain is associated with a first subdomain threshold count (e.g., 5), and the second subdomain is associated with a second subdomain threshold count (e.g., 5). For example, the first subdomain traffic is limited when either the capacity limit of the first subdomain is reached or the capacity limit of the first capacity domain is reached. To illustrate, the first subdomain traffic may be limited when the count of pending memory accesses associated with the first subdomain (e.g., 3 first subdomain pending memory accesses and 5 second subdomain memory accesses) is equal to the domain threshold count (e.g., 8), but the count of pending memory accesses associated with the first subdomain (e.g., 3) is less than the first subdomain threshold count (e.g., 5). In some implementations, when the domain threshold count differs from the sum of the subdomain threshold counts, the subdomain threshold count corresponds to the maximum capacity limit of the subdomain instead of the guaranteed capacity limit.

[0066]

[0095] Figures 4A-4C show an example of updating cache 172 in response to a write instruction from software thread 152A. Figure 5 shows an example of updating transaction tracker 160 to indicate a pending store associated with consistency domain identifier 156A of software thread 152A. For example, the pending store in Figure 5 can be associated with data in cache 172 that is updated in response to the write instruction in the example of Figures 4A-4C.

[0067]

[0096] 4A, in example 400, software thread 152A sends a write instruction 440 that indicates an opcode 442, an address 444, and data 446. The opcode 442 (e.g., an identifier) ​​indicates that the write instruction 440 corresponds to a memory write instruction.

[0068]

[0097] 1 receives the write command 440 indicating the address 444 and initiates a load 452 of the data from the address 444 of the memory 120 in response to determining that the data associated with the address 444 is not available in the cache 172. In some aspects, the memory manager 140 initiates the load 452 in response to determining that the coherence domain manager 142 indicates that the coherence domain identifier 156A does not match any coherence domain identifier associated with a pending synchronization operation, as will be further described with reference to FIGS. 5-8, and that the capacity domain manager 144 indicates that the capacity domain identifier 158A does not match any capacity domain identifier having a count of pending memory accesses that has reached a corresponding threshold count, as will be further described with reference to FIGS. 16-17.

[0069]

[0098] 4B , data 448 stored at address 444 is received from memory 120 via interface 174 and stored in portion 460 of cache 172. For example, memory manager 140 receives data 448 and stores data 448 in portion 460.

[0070]

[0099] In some implementations, memory manager 140 also updates metadata for portion 460 to indicate software thread 152A and address 444. For example, the metadata indicates that portion 460 includes data associated with address 444 and is associated with a memory access of software thread 152A. In some implementations, the metadata includes a dirty bit, and memory manager 140 updates the metadata to set the dirty bit to a first value (e.g., 0) to indicate that portion 460 includes data read from memory 120 that has not been updated in cache 172.

[0071]

[0100] 4C , memory manager 140 replaces (e.g., overwrites) data 448 with (e.g., overwrites) data 446 of write instruction 440. In some implementations, memory manager 140 updates the dirty bit to a second value (e.g., 1) to indicate that portion 460 contains data that has been updated in cache 172.

[0072]

[0101] Write instruction 440 is provided as an example of a memory access instruction for software thread 152A. A read instruction may be another example of a memory access instruction for software thread 152A. The read instruction may include an opcode and an address. In response to receiving the read instruction for software thread 152A, memory manager 140 loads data from an address in memory 120 into a portion of cache 172 and sets a dirty bit (e.g., metadata) for the portion to a first value (e.g., 0) to indicate that the portion stores data that has been retrieved from memory 120 and has not been updated in cache 172.

[0073]

[0102] 5, a system 500 operable to manage memory transactions is disclosed. In certain aspects, the system 100 of FIG.

[0074]

[0103] The transaction tracker 160 includes a transaction tracking scoreboard 562 configured to track one or more pending stores associated with one or more consistency domain identifiers 156. The transaction tracking scoreboard 562 includes a plurality of entries 564, such as entry 564A, one or more additional entries, entry 564N, or any combination thereof. Each of the plurality of entries 564 includes a tag field 572, a valid indicator field 574, an eviction indicator field 576, a domain identifier field 578, and an address field 580.

[0075]

[0104] The tag field 572 of the entry 564 indicates an identifier of the entry 564. For example, the tag field 572A of the entry 564A contains an identifier of the entry 564A (e.g., A). As another example, the tag field 572N of the entry 564N contains an identifier of the entry 564N (e.g., N).

[0076]

[0105] The valid indicator field 574 of the entry 564 indicates whether the entry 564 contains valid data. For example, a first value (e.g., 0) in the valid indicator field 574 indicates that the entry 564 contains invalid data, while a second value (e.g., 1) in the valid indicator field 574 indicates that the entry 564 contains valid data.

[0077]

[0106] The eviction indicator field 576 of the entry 564 is used to indicate a pending eviction to the address indicated by the address field 580. For example, a first value (e.g., 0) in the eviction indicator field 576 indicates no pending eviction, while a second value (e.g., 1) in the eviction indicator field 576 indicates a pending eviction.

[0078]

[0107] The domain identifier field 578 of an entry 564 is used to indicate one or more consistency domain identifiers 156 associated with the entry 564. In some aspects, the consistency domain number 162 of the transaction data corresponds to a count of pending transactions associated with the consistency domain identifier 156. The count of pending transactions may be determined based on a count of entries 564 that include valid data (e.g., as indicated by the valid indicator field 574) associated with the consistency domain identifier 156 (e.g., as indicated by the domain identifier field 578).

[0079]

[0108] Software thread 152A issues a commit 542 following write instruction 440 of example 400 of FIG. 4A. In a particular aspect, in response to determining that portion 460 of cache 172 contains data associated with software thread 152A (e.g., as indicated by metadata) and that portion 460 contains updated data (e.g., as indicated by a dirty bit), coherence domain manager 142 determines that a store associated with portion 460 corresponding to software thread 152A is committed. Alternatively, if a second portion of cache 172 contains data associated with software thread 152A that has not been updated in cache 172 (e.g., as indicated by a dirty bit), coherence domain manager 142 determines that a store associated with the second portion (e.g., corresponding to a read instruction) is not committed.

[0080]

[0109] The coherence domain manager 142 corresponds to the software thread 152A, and in response to the store associated with the portion 460 being committed, updates the entry 564A to indicate a pending store operation associated with the portion 460. For example, the coherence domain manager 142 updates the address field 580A to indicate the address 444 associated with the portion 460. The coherence domain manager 142 updates the domain identifier field 578A to indicate the coherence domain identifier 156A (e.g., 0) assigned to the software thread 152A associated with the portion 460. The coherence domain manager 142 sets the eviction indicator field 576A to a first value (e.g., 0) to indicate that there is no pending eviction. The coherence domain manager 142 updates the valid indicator field 574A to a second value (e.g., 1) to indicate that the entry 564A contains valid data.

[0081]

[0110] Following updating entry 564A, coherence domain manager 142 initiates the storing of data 446 to address 444. For example, coherence domain manager 142 causes data 446 to be provided to memory 120 via interface 174 for storage at address 444.

[0082]

[0111] The transaction tracking scoreboard 562 indicates the consistency domain number 162 of the transaction data. For example, the consistency domain number 162 of the transaction data indicates a count 584 of pending stores associated with the consistency domain identifier 156. In some implementations, the consistency domain manager 142 increments (e.g., by one) the count 584A of pending stores associated with the consistency domain identifier 156A upon updating the entry 564A, initiating a store of the data 446, or both. In some implementations, the count 584A is indicated by a count of valid entries (e.g., indicated by the valid indicator field 574) in the transaction tracking scoreboard 562 associated with the consistency domain identifier 156A (e.g., indicated by the domain identifier field 578).

[0083]

[0112] Operations that may be performed in the case of a synchronous operation are described with reference to system 600 of Figure 6, system 700 of Figure 7, and system 800 of Figure 8. Each of systems 600, 700, and 800 is operable to manage memory transactions and may include one or more components included in system 100 of Figure 1. In particular, Figure 6 illustrates an example of initiating a synchronous operation for software thread 152A, Figure 7 illustrates an example of receiving an access instruction during a synchronous operation, and Figure 8 illustrates an example of completing a pending store and synchronous operation.

[0084]

[0113] 6, the consistency domain manager 142 includes or can access synchronization data 650 that indicates whether a synchronization operation associated with one or more consistency domain identifiers 156 is pending. For example, the synchronization data 650 includes a synchronization indicator 654 for each of the one or more consistency domain identifiers 156. To illustrate, the synchronization data 650 includes a synchronization indicator 654A and a synchronization indicator 654B for the consistency domain identifiers 156A and 156B, respectively. Each of the one or more synchronization indicators 654 is initialized to a first value (e.g., 0) to indicate that no pending synchronization operation is associated with the corresponding consistency domain identifier 156.

[0085]

[0114] Software thread 152A initiates a synchronization operation by issuing a synchronization instruction 644. In some implementations, the synchronization instruction 644 corresponds to a barrier instruction or a store release load acquire instruction. In response to receiving the synchronization instruction 644 for software thread 152A and determining that the domain identifier data 150 indicates that software thread 152A is assigned to consistency domain identifier 156A, the coherence domain manager 142 updates a synchronization indicator 654A associated with the consistency domain identifier 156A to a second value (e.g., 1) to indicate a pending synchronization operation associated with the consistency domain identifier 156A, for example.

[0086]

[0115] In some implementations, the consistency domain manager 142 selectively updates the synchronization indicator 654A based on a count of pending stores matching the consistency domain identifier 156A. For example, the count of pending stores matching the consistency domain identifier 156A corresponds to a count of valid entries in the transaction tracking scoreboard 562 having a domain identifier field 578 indicating one or more consistency domain identifiers 156 matching the consistency domain identifier 156A, such as entry 564A. For illustrative purposes, the consistency domain identifier 156A matches itself, and the count of pending stores is based on the count 584A associated with the consistency domain identifier 156A. In one example, another consistency domain identifier (e.g., consistency domain identifier 156B) also matches the consistency domain identifier 156A, and the count of pending stores matching the consistency domain identifier 156A is also based on the count 584B of pending stores associated with the consistency domain identifier 156B, as described with reference to FIG. 2. In this example, the count of pending stores matching consistency domain identifier 156A is based on the sum of count 584A and count 584B.

[0087]

[0116] In some implementations, in response to determining that the count of pending stores matching the consistency domain identifier 156A is greater than zero, the consistency domain manager 142 updates a synchronization indicator 654A associated with the consistency domain identifier 156A to a second value (e.g., 1) to indicate a pending synchronization operation associated with the consistency domain identifier 156A. Thus, the synchronization indicator 654A is set based on the consistency domain number 162 of the transaction data to control operation of one or more components 170 as further described with reference to FIGS.

[0088]

[0117] 7, the coherence domain manager 142 receives an access instruction 744 (e.g., a read instruction or a write instruction) for the software thread 152A. In response to determining that the software thread 152A has been assigned a coherence domain identifier 156A (e.g., as indicated by the domain identifier data 150) and the synchronization data 650 indicates that a pending synchronization operation is associated with the coherence domain identifier 156A, the coherence domain manager 142 refrains from executing the access instruction 744. Controlling the operation of the one or more components 170 includes refraining from executing the access instruction 744. In some aspects, refraining from executing the access instruction 744 includes adding the access instruction 744 for the software thread 152A to the instruction buffer 750 along with a corresponding ready flag set to a first value (e.g., 0) indicating that the access instruction 744 is not ready to be executed.

[0089]

[0118] In a particular example, the consistency domain manager 142 receives an access instruction 746 from software thread 152B and determines that a consistency domain identifier 156B has been assigned to software thread 152B (e.g., as indicated by domain identifier data 150). The consistency domain manager 142 determines whether the consistency domain identifier 156B matches the consistency domain identifier 156A in response to determining that the synchronization data 650 indicates that the consistency domain identifier 156A has a pending synchronization operation, as described with reference to FIG.

[0090]

[0119] The coherence domain manager 142 refrains from executing the access instruction 746 in response to determining that the coherence domain identifier 156B matches the coherence domain identifier 156A. Controlling the operation of the one or more components 170 includes refraining from executing the access instruction 746. In some aspects, refraining from executing the access instruction 746 includes adding the access instruction 746 of the software thread 152B to the instruction buffer 750 with a corresponding ready flag set to a first value (e.g., 0) indicating that the access instruction 746 is not ready to be executed. Alternatively, the coherence domain manager 142 begins executing the access instruction 746 or adds the access instruction 746 to the instruction buffer 750 with a corresponding ready flag set to a second value (e.g., 1) indicating that the access instruction 746 is ready to be executed in response to determining that the coherence domain identifier 156B does not match any coherence domain identifier with a pending synchronization operation.

[0091]

[0120] Thus, during a synchronization operation of consistency domain identifier 156A, consistency domain manager 142 refrains from executing access instructions associated with consistency domain identifiers that match consistency domain identifier 156A. However, execution of access instructions associated with consistency domain identifiers that do not match consistency domain identifier 156A is not blocked by the synchronization operation of software thread 152A.

[0092]

[0121] 8, memory 120 issues an acknowledgement (ack.) 844 indicating that the storage of data to address 444 is complete. In response to receiving the acknowledgement 844, coherence domain manager 142 determines a coherence domain identifier associated with address 444 and updates transaction tracking scoreboard 562 to indicate that there are no pending stores associated with address 444. For example, coherence domain manager 142 determines that entry 564A is valid (e.g., as indicated by valid indicator field 574A) and indicates that address 444 (e.g., indicated by address field 580A) is associated with coherence domain identifier 156A (e.g., indicated by domain identifier field 578A). Coherence domain manager 142 updates valid indicator field 574A of entry 564A to a first value (e.g., 0) to indicate that entry 564A is invalid and that there are no pending stores associated with address 444. In some implementations, the consistency domain manager 142 decrements the count 584A corresponding to the consistency domain identifier 156A associated with the address 444 (eg, by one).

[0093]

[0122] In response to determining that the synchronization data 650 indicates a pending synchronization operation associated with the consistency domain identifier 156A (e.g., corresponding to the address 444 indicated by the acknowledgement 844), the consistency domain manager 142 determines whether the transaction tracking scoreboard 562 indicates any remaining pending store operations that match the consistency domain identifier 156A. For example, the consistency domain manager 142 determines the count of pending stores that match the consistency domain identifier 156A based on the count 584A associated with the consistency domain identifier 156A. In some examples, another consistency domain identifier (e.g., the consistency domain identifier 156B) matches the consistency domain identifier 156A. In these examples, the consistency domain manager 142 determines the count of pending stores that match the consistency domain identifier 156A also based on the count 584B. For example, the count of pending stores that match the consistency domain identifier 156A is based on the sum of the counts associated with the consistency domain identifier that matches the consistency domain identifier 156A. In response to determining that the count of pending stores matching the consistency domain identifier 156A is 0, the consistency domain manager 142 updates the synchronization indicator 654A to a first value (e.g., 0) to indicate that the synchronization operation associated with the consistency domain identifier 156A is completed.

[0094]

[0123] In a particular aspect, the coherence domain manager 142 designates one or more instructions in the instruction buffer 750 as ready to be executed in response to determining that the synchronization operation associated with the coherence domain identifier 156A is completed. For example, the coherence domain manager 142 determines that an access instruction 744 included in the instruction buffer 750 is designated as not ready to be executed (e.g., as indicated by a ready flag). The coherence domain manager 142 determines that the access instruction 744 is associated with a software thread 152A that is assigned a coherence domain identifier 156A (e.g., as indicated by domain identifier data 150). The coherence domain manager 142 designates the access instruction 744 as ready to be executed by setting the ready flag to a second value (e.g., 1) in response to determining that the coherence domain identifier 156A does not match any coherence domain identifier that has a pending synchronization operation (e.g., as indicated by synchronization data 650). Similarly, in another example, the consistency domain manager 142 designates the access instruction 746 as ready to be executed in response to determining that the consistency domain identifier 156B does not match any consistency domain identifier that has a pending synchronization operation.

[0095]

[0124] 1 based on the number (e.g., count) of pending stores that match the consistency domain identifier 156A in response to receiving a synchronization instruction 644 for software thread 152A. Controlling the operation of the one or more components 170 includes completing any pending stores that match the consistency domain identifier 156A before executing any subsequent data access instructions associated with any consistency domain identifier that matches the consistency domain identifier 156A.

[0096]

[0125] Operations that may be performed in the case of a capacity eviction are described with reference to system 900 of Figure 9, example 1000 of Figure 10A, example 1090 of Figure 10B, and system 1100 of Figure 11. Each of systems 900 and 1100 is operable to manage memory transactions and may include one or more components included in system 100 of Figure 1. In particular, Figure 9 illustrates an example of initiating a capacity eviction of updated data from a portion of cache 172 in response to a second memory access instruction, Figures 10A and 10B illustrate loading data corresponding to the second memory access instruction into a portion of the cache, and Figure 11 illustrates an example of completing the capacity eviction in response to an acknowledgment that the storing of the updated data is complete.

[0097]

[0126] 9, portion 460 of cache 172 includes data 446 for software thread 152A that has been updated in cache 172 (e.g., as indicated by a dirty bit) and is associated with address 444, as described with reference to FIG. 4C. Software thread 152B issues an access instruction 946 (e.g., a memory read instruction or a memory write instruction) that indicates at least an opcode 942 and address 944. For example, opcode 942 includes an identifier for access instruction 946. In a particular aspect, access instruction 946 corresponds to a memory write instruction and also indicates the data to be written to address 944.

[0098]

[0127] The coherence domain manager 142 receives the access instruction 946, determines that data corresponding to the address 944 is not available in the cache 172, and in response to determining that the cache 172 is full, uses various cache eviction strategies (e.g., least recently accessed) to select a portion 460 of the cache 172 to store the data corresponding to the address 944. If the selected portion (e.g., portion 460) contains data that has not been updated in the cache 172 (e.g., as indicated by a dirty bit), the selected portion may be overwritten without eviction. Alternatively, in response to determining that the selected portion (e.g., portion 460) contains data that has been updated in the cache 172 (e.g., as indicated by a dirty bit), the coherence domain manager 142 initiates eviction of the data 446 stored in portion 460.

[0099]

[0128] Initiating an eviction of the data 446 associated with the address 444 includes updating an available entry 564 (e.g., an invalid entry indicated by a valid indicator field 574) of the transaction tracking scoreboard 562 and initiating a store of the data 446 to the address 444 of the memory 120. For example, the coherence domain manager 142 sets the address field 580A of the entry 564A to indicate the address 444 associated with the portion 460. The coherence domain manager 142 sets the eviction indicator field 576A to a second value (e.g., 1) to indicate the pending eviction. The coherence domain manager 142 sets the domain identifier field 578A of the entry 564A to indicate the coherence domain identifier 156A assigned to the software thread 152A associated with the portion 460. In some implementations, the pending eviction corresponds to a pending store associated with the coherence domain identifier 156A due to a synchronization operation. For example, in some implementations, the consistency domain manager 142 updates (e.g., increments by 1) the count 584A corresponding to the consistency domain identifier 156A assigned to the software thread 152A. The consistency domain manager 142 sets the valid indicator field 574A to a second value (e.g., 1) to indicate that the entry 564A corresponds to a valid entry.

[0100]

[0129] The coherence domain manager 142 initiates the store of data 446 by causing the data 446 to be sent over interface 174 to be written to address 444 of memory 120. The data from address 944 is loaded into portion 460 following the initiation of the store of data 446. In the example 1000 of FIG. 10A , the coherence domain manager 142 initiates the load 1042 of data from address 944 of memory 120.

[0101]

[0130] 10B , data 1048 stored at address 944 is received from memory 120 via interface 174 and stored in portion 460 of cache 172. For example, coherence domain manager 142 receives notification that data 1048 is to be stored in portion 460.

[0102]

[0131] In some implementations, the consistency domain manager 142 also updates the metadata of the portion 460 to indicate software thread 152B (associated with the access instruction 946) and the address 944. For example, the metadata indicates that the portion 460 includes data associated with the address 944 and is associated with the memory access of the software thread 152B. In some implementations, the metadata includes a dirty bit, and the memory manager 140 updates the metadata to set the dirty bit to a first value (e.g., 0) to indicate that the portion 460 includes data read from the memory 120 that has not been updated in the cache 172.

[0103]

[0132] If the access instruction 946 corresponds to a write instruction and indicates updated data to be written to address 944, then the data 1048 is replaced (e.g., overwritten) with the updated data and the metadata is updated to indicate that portion 460 contains updated data in cache 172 by setting the dirty bit to a second value (e.g., 1).

[0104]

[0133] 11, memory 120 issues an acknowledgement (ack.) 1144 indicating that storage of data to address 444 is complete. In response to receiving the acknowledgement 1144 and determining that entry 564A is valid (e.g., as indicated by valid indicator field 574A) and that entry 564A is associated with address 444 (e.g., indicated by address field 580A), coherence domain manager 142 updates valid indicator field 574A to a first value (e.g., 0) to indicate that entry 564A is invalid and that the pending eviction is complete. In some implementations, in response to receiving the acknowledgement 1144, coherence domain manager 142 updates (e.g., decrements by 1) count 584A corresponding to coherence domain identifier 156A associated with address 444 (e.g., indicated by domain identifier field 578A) before setting valid indicator field 574A to the first value (e.g., 0).

[0105]

[0134] Operations that may be performed in the event of a cache operation hit are described with reference to system 1200 of Figure 12 and system 1300 of Figure 13. Each of system 1200 and system 1300 is operable to manage memory transactions and may include one or more components included in system 100 of Figure 1. In particular, Figures 12 and 13 illustrate an example of initiating a cache operation corresponding to a hit in cache 172 and an example of completing the cache operation, respectively.

[0106]

[0135] 12, portion 460 of cache 172 includes data 446 for software thread 152A that has been updated in cache 172 (e.g., as indicated by a dirty bit) and associated with address 444, as described with reference to FIG. 4C. Software thread 152B initiates a cache operation 1246 (e.g., a clean cache line operation or a clean and invalidate cache line operation) that indicates opcode 1242 and address 444. For example, opcode 1242 includes an identifier for cache operation 1246. Cache operation 1246 is associated with consistency domain identifier 156B that has been assigned to software thread 152B (e.g., as indicated by domain identifier data 150).

[0107]

[0136] The coherence domain manager 142 detects a cache hit in response to determining that the portion 460 of the cache 172 contains the data 446 associated with the address 444 indicated by the cache operation 1246. In response to detecting a cache hit, the coherence domain manager 142 initiates an eviction of the data 446 and updates the cache 172 to indicate that the portion 460 of the cache 172 is available (e.g., contains invalid data).

[0108]

[0137] Initiating the eviction of the data 446 associated with the address 444 includes performing one or more of the operations described with reference to FIG. 9. For example, the coherence domain manager 142 updates the available entries 564 (e.g., invalid entries) of the transaction tracking scoreboard 562 and initiates the storing of the data 446 to the address 444 in the memory 120. To illustrate, the coherence domain manager 142 sets the address field 580A of the entry 564A to indicate the address 444 associated with the portion 460. The coherence domain manager 142 sets the eviction indicator field 576A to a second value (e.g., 1) to indicate the pending eviction. The coherence domain manager 142 sets the domain identifier field 578A of the entry 564A to indicate the coherence domain identifier 156A (e.g., 0) assigned to the software thread 152A associated with the portion 460.

[0109]

[0138] In some implementations, initiating the eviction of data 446 includes setting the domain identifier field 578A to also indicate the consistency domain identifier 156B (e.g., 1) assigned to the software thread 152B associated with the cache operation 1246 (shown as domain identifier field 578A including a 0 value representing the consistency domain identifier 156A assigned to software thread 152A and also including a 1 value representing the consistency domain identifier 156B assigned to software thread 152B).

[0110]

[0139] In some aspects, the pending eviction due to the cache hit operation corresponds to a pending store operation associated with the consistency domain identifier 156A and the consistency domain identifier 156B. For example, in some implementations, the consistency domain manager 142 updates (e.g., increments by 1) the count 584A corresponding to the consistency domain identifier 156A and the count 584B corresponding to the consistency domain identifier 156B. The consistency domain manager 142 sets the valid indicator field 574A to a second value (e.g., 1) to indicate that the entry 564A corresponds to a valid entry. The consistency domain manager 142 initiates the store of the data 446 by sending the data 446 to be written to the address 444 of the memory 120 via the interface 174.

[0111]

[0140] 13, memory 120 issues an acknowledgement (ack.) 1344 indicating that storage of data to address 444 is complete. In response to receiving the acknowledgement 1344 and determining that entry 564A is valid (e.g., as indicated by valid indicator field 574A) and determining that entry 564A is associated with address 444 (e.g., as indicated by address field 580A), coherency domain manager 142 updates valid indicator field 574A to a first value (e.g., 0) to indicate that entry 564A is invalid and that the pending eviction is complete.

[0112]

[0141] In some implementations, in response to receiving the positive response 1344, the consistency domain manager 142 updates (e.g., decrements by 1) the counts 584A and 584B corresponding to the consistency domain identifier 156A and the consistency domain identifier 156B, respectively, associated with the address 444 (e.g., as indicated by the domain identifier field 578A) before setting the valid indicator field 574A to a first value (e.g., 0).

[0113]

[0142] Operations that may be performed in the event of a cache operation miss are described with reference to system 1400 of Figure 14 and system 1500 of Figure 15. Each of system 1400 and system 1500 is operable to manage memory transactions and may include one or more components included in system 100 of Figure 1. In particular, Figure 14 illustrates an example of initiating a cache operation corresponding to a miss in cache 172, and Figure 15 illustrates an example of completing the cache operation.

[0114]

[0143] 14, entry 564A of transaction tracking scoreboard 562 indicates a pending eviction associated with address 444. In a particular aspect, the pending eviction corresponds to a capacity eviction, as described with reference to FIG 9. In another aspect, the pending eviction corresponds to a cache operation hit, as described with reference to FIG 12.

[0115]

[0144] Software thread 152B initiates a cache operation 1246 (e.g., a clean cache line operation or a clean and invalidate cache line operation) that indicates opcode 1242 and address 444. The cache operation 1246 is associated with a consistency domain identifier 156B that is assigned to software thread 152B (e.g., as indicated by domain identifier data 150).

[0116]

[0145] In response to determining that valid data associated with address 444 is not stored in cache 172, coherence domain manager 142 detects a cache miss. In response to detecting a cache miss, coherence domain manager 142 assigns a coherence domain identifier 156B associated with cache operation 1246 to any pending eviction associated with address 444. For example, in response to determining that entry 564A is valid (e.g., as indicated by validity indicator field 574A) and corresponds to a pending eviction (e.g., indicated by eviction indicator field 576A) associated with address 444 (e.g., indicated by address field 580A), coherence domain manager 142 updates domain identifier field 578A of entry 564A to also indicate coherence domain identifier 156B.

[0117]

[0146] In certain aspects, the pending eviction indicated by entry 564A corresponds to a pending store operation associated with consistency domain identifier 156B in addition to any other consistency domain identifiers indicated by domain identifier field 578A. For example, in some implementations, consistency domain manager 142 updates (e.g., increments by one) a count 584A corresponding to consistency domain identifier 156A and another count (e.g., count 584B) corresponding to another consistency domain identifier (e.g., consistency domain identifier 156B) indicated by domain identifier field 578A.

[0118]

[0147] 15, memory 120 issues an acknowledgement (ack.) 1544 indicating that storage of data to address 444 is complete. In response to receiving the acknowledgement 1544 and determining that entry 564A is valid (e.g., as indicated by valid indicator field 574A) and determining that entry 564A is associated with address 444 (e.g., as indicated by address field 580A), coherency domain manager 142 updates valid indicator field 574A to a first value (e.g., 0) to indicate that entry 564A is invalid and that the pending eviction is complete.

[0119]

[0148] In some implementations, the coherence domain manager 142, in response to receiving the acknowledgment 1544, updates (e.g., decrements by 1) the count 584A corresponding to the coherence domain identifier 156A associated with the address 444 (e.g., as indicated by the domain identifier field 578A) before setting the valid indicator field 574A to a first value (e.g., 0). In addition, the coherence domain manager 142 also updates (e.g., decrements by 1) the count (e.g., count 584B) corresponding to any other coherence domain identifier (e.g., coherence domain identifier 156B) associated with the address 444 (e.g., as indicated by the domain identifier field 578A) before setting the valid indicator field 574A to a first value (e.g., 0).

[0120]

[0149] Operations that may be performed that take into account capacity domains are described with reference to system 1600 of Figure 16 and system 1700 of Figure 17. Each of system 1600 and system 1700 is operable to manage memory transactions and may include one or more components included in system 100 of Figure 1. In particular, Figure 16 illustrates an example of updating a count of pending memory access instructions corresponding to a capacity domain identifier in response to a read instruction, and Figure 17 illustrates an example of updating a count of pending memory access instructions corresponding to a capacity domain identifier in response to a write instruction.

[0121]

[0150] 16 , transaction tracker 160 includes transaction data capacity domain number 164 indicating capacity threshold 1676 associated with capacity domain identifier 158. For example, transaction data capacity domain number 164 indicates that capacity domain identifier 158A is associated with capacity threshold 1676A, capacity domain identifier 158B is associated with capacity threshold 1676B, etc. Capacity threshold 1676B may be the same as capacity threshold 1676A or may be separate. In certain aspects, capacity threshold 1676 is based on configuration settings, user input, default data, or a combination thereof.

[0122]

[0151] Capacity domain manager 144 is configured to track a count 1674 of pending memory access instructions associated with capacity domain identifier 158 using the capacity domain number 164 of the transaction data. Software thread 152A issues a read instruction 1640. Capacity domain manager 144 selectively enables the read instruction 1640 based on the count 1674. In some aspects, capacity domain manager 144 determines whether a capacity limit associated with any capacity domain identifier that matches capacity domain identifier 158A (assigned to software thread 152A) has been reached. For example, capacity domain identifier 158A is a match of its own, and capacity domain manager 144 determines that a capacity limit associated with capacity domain identifier 158A has been reached in response to determining that a count 1674A associated with capacity domain identifier 158A is equal to or greater than a capacity threshold 1676A associated with capacity domain identifier 158A. In some examples, another capacity domain identifier (e.g., capacity domain identifier 158B) that is not the same as capacity domain identifier 158A may also match capacity domain identifier 158A, as described with reference to Figure 3. The capacity domain manager 144 determines that the capacity limit associated with capacity domain identifier 158B has been reached in response to determining that the count 1674B associated with capacity domain identifier 158B is greater than or equal to the capacity threshold 1676B associated with capacity domain identifier 158B.

[0123]

[0152] In response to determining that a capacity limit has been reached for at least one capacity domain identifier that matches the capacity domain identifier 158A, the capacity domain manager 144 invalidates the read instruction 1640. In some implementations, invalidating the read instruction 1640 includes discarding the read instruction 1640. In other implementations, invalidating the read instruction 1640 includes adding the read instruction 1640 to an instruction buffer to be executed when capacity is available (e.g., a capacity limit has not been reached) for all capacity domain identifiers that match the capacity domain identifier 158A.

[0124]

[0153] In response to determining that capacity is available for all capacity domain identifiers that match capacity domain identifier 158A, capacity domain manager 144 enables read instruction 1640 and updates count 1674A (e.g., increments by one). In some aspects, data associated with the address indicated by read instruction 1640 is available in cache 172. In these aspects, enabling read instruction 1640 includes providing the data from cache 172 to software thread 152A.

[0125]

[0154] In some aspects, the data associated with the address indicated by the read instruction 1640 is not available in the cache 172. In these aspects, validating the read instruction 1640 includes initiating a memory access associated with the read instruction 1640. For example, the capacity domain manager 144 initiates a load 1642 of the data from the memory 120. The capacity domain manager 144 receives the data 1648 (e.g., stored at the address indicated by the read instruction 1640) from the memory 120 via the interface 174. The capacity domain manager 144 stores the data 1648 in the cache 172 and provides the data 1648 from the cache 172 to the software thread 152A.

[0126]

[0155] Once software thread 152A completes reading data 1648 from cache 172, software thread 152A issues an acknowledgement 1650 indicating that the memory access associated with read instruction 1640 is complete. In response to receiving acknowledgement 1650, capacity domain manager 144 updates count 1674A (e.g., decrements by one).

[0127]

[0156] 17, software thread 152A issues a write command 1740. Capacity domain manager 144 selectively enables the write command 1740 based on count 1674. Capacity domain manager 144 determines whether a capacity limit associated with any capacity domain identifier that matches capacity domain identifier 158A (assigned to software thread 152A) has been reached, as described with reference to FIG.

[0128]

[0157] In response to determining that a capacity limit has been reached for at least one capacity domain identifier that matches capacity domain identifier 158A, capacity domain manager 144 invalidates write instruction 1740. In some implementations, invalidating write instruction 1740 includes discarding write instruction 1740. In other implementations, invalidating write instruction 1740 includes adding write instruction 1740 to an instruction buffer to be executed when capacity is available (e.g., a capacity limit has not been reached) for all capacity domain identifiers that match capacity domain identifier 158A.

[0129]

[0158] In response to determining that capacity is available for all capacity domain identifiers matching capacity domain identifier 158A, capacity domain manager 144 enables write instruction 1740 and updates count 1674A (e.g., increments by one). Enabling write instruction 1740 includes initiating a memory access associated with write instruction 1740. In some aspects, initiating the memory access includes initiating a store operation of data 1748 indicated by write instruction 1740 to an address indicated by write instruction 1740. To illustrate, capacity domain manager 144 provides data 1748 to memory 120 via interface 174. Memory 120 provides acknowledgement 1750 indicating that the memory access (e.g., store operation) associated with write instruction 1740 is completed.

[0130]

[0159] In some aspects, initiating the memory access includes storing the data 1748 in the cache 172. In these aspects, software thread 152A may provide an acknowledgment 1750 indicating that the memory access associated with the write instruction 1740 (e.g., a store to the cache 172) is completed.

[0131]

[0160] In response to receiving the acknowledgment 1750, the capacity domain manager 144 updates the count 1674A (e.g., decrements it by one). In some implementations, following decrementing the count 1674A, the capacity domain manager 144 determines whether a memory access instruction stored in the instruction buffer is a candidate for validation. For example, in response to determining that capacity is available for all capacity domain identifiers that match the capacity domain identifier associated with the memory access instruction, the capacity domain manager 144 validates the memory access instruction, removes the memory access instruction from the instruction buffer, and updates (e.g., increments) the count associated with the capacity domain identifier.

[0132]

[0161] 17-18 as not including a coherence domain manager 142 in addition to a capacity domain manager 144. In some implementations, the memory manager 140 may include a coherence domain manager 142 and a capacity domain manager 144. For example, the coherence domain manager 142 updates the transaction tracking scoreboard 562 upon initiating a write of data 1748 to memory 120, and updates the transaction tracking scoreboard 562 in response to receiving an acknowledgment 1750, as described with reference to FIGS.

[0133]

[0162] It should be noted that various functions performed by one or more processors 190 are described as being performed by several components or modules. However, this division of components and modules is for illustrative purposes only. In alternative aspects, functions described herein as being performed by a particular component or module are divided among multiple components or modules. Moreover, in alternative aspects, two or more components or modules of one or more processors 190 are combined into a single component or module. In certain aspects, one or more functions described herein as being performed by device 102 are divided among multiple devices (e.g., device 102, a central server, a distributed system, or any combination thereof).

[0134]

[0163] 18 illustrates an implementation 1800 in which the device 102 includes a mobile device 1802, such as a phone or tablet, as an illustrative, non-limiting example. The mobile device 1802 includes a display screen 1804. Components of one or more processors 190, including a memory manager 140, are incorporated into the mobile device 1802 and are shown using dashed lines to indicate internal components that are not typically visible to a user of the mobile device 1802. In a particular example, the memory manager 140 operates to access the memory of the mobile device 1802 and perform one or more operations on the mobile device 1802, such as to launch a graphical user interface or otherwise display other information on the display screen 1804 (e.g., via an incorporated “smart assistant” application).

[0135]

[0164] In some aspects, memory manager 140 allows memory access transactions for a consistency domain identifier to remain unaffected by synchronization operations of non-matching consistency domain identifiers. For example, memory accesses of a first application (e.g., video playback) associated with a first consistency domain identifier are not blocked by synchronization operations of a second application (e.g., social networking application) associated with a second consistency domain identifier that does not match the first consistency domain identifier. In some aspects, memory manager 140 separates capacity restrictions based on capacity domain identifiers. For example, memory accesses of a second application (e.g., social networking application) are not blocked by too many memory accesses of a first application (e.g., video playback).

[0136]

[0165] 19 illustrates an implementation 1900 in which the device 102 includes a headset device 1902. One or more processor 190 components, including a memory manager 140, are incorporated into the headset device 1902. In a particular example, the memory manager 140 operates to access memory of the headset device 1902 to perform one or more operations at the headset device 1902.

[0137]

[0166] FIG. 20 illustrates an implementation 2000 in which the device 102 includes a wearable electronic device 2002 depicted as a “smart watch.” A memory manager 140 is incorporated into the wearable electronic device 2002. In a particular example, the memory manager 140 operates to access the memory of the wearable electronic device 2002 to perform one or more operations on the wearable electronic device 2002, such as launching a graphical user interface or otherwise displaying other information associated with a user's speech on a display screen 2004 of the wearable electronic device 2002. To illustrate, the wearable electronic device 2002 may include a display screen configured to display notifications based on a user's speech detected by the wearable electronic device 2002. In a particular example, the wearable electronic device 2002 includes a haptic device that provides a haptic notification (e.g., vibration) in response to detection of a user voice activity. For example, the haptic notification may cause the user to look at the wearable electronic device 2002 to see a displayed notification indicating detection of a keyword spoken by the user.

[0138]

[0167] FIG. 21 is an implementation 2100 in which the device 102 includes a wireless speaker and voice-activated device 2102. The wireless speaker and voice-activated device 2102 can have wireless network connectivity and is configured to perform assistant operations. One or more processors 190 including a memory manager 140 are included in the wireless speaker and voice-activated device 2102. The wireless speaker and voice-activated device 2102 also includes a speaker 2104. In operation, the memory manager 140 operates to access the memory of the wireless speaker and voice-activated device 2102 to perform assistant operations, such as through execution of a voice-activated system (e.g., an integrated assistant application). Assistant operations can include adjusting the temperature, playing music, turning on lights, etc. For example, assistant operations can be performed in response to receiving a command after a keyword or key phrase (e.g., "hello, assistant").

[0139]

[0168] 22 shows an implementation 2200 in which the device 102 includes a portable electronic device corresponding to a camera device 2202. A memory manager 140 is included in the camera device 2202. In operation, the memory manager 140 accesses the memory of the camera device 2202 to perform actions in response to spoken user commands, such as adjusting image or video capture settings, image or video playback settings, or image or video capture instructions, as illustrative examples.

[0140]

[0169] 23 illustrates an implementation 2300 in which the device 102 includes a portable electronic device corresponding to a virtual reality headset, a mixed reality headset, or an augmented reality headset 2302. The memory manager 140 is integrated into the headset 2302. The memory manager 140 operates to access the memory of the headset 2302 to perform operations in the headset 2302. In certain aspects, user voice activity detection may be performed based on audio signals received from one or more microphones of the headset 2302. The visual interface device is placed in front of the user's eyes to enable augmented reality, mixed reality, or virtual reality images or scenes to be displayed to the user while the headset 2302 is worn. In certain examples, the visual interface device is configured to display notifications indicative of user speech detected in the audio signal.

[0141]

[0170] 24 illustrates an implementation 2400 in which the device 102 corresponds to or is incorporated into a vehicle 2402, depicted as a manned or unmanned aerial device (e.g., a package delivery drone). A memory manager 140 is incorporated into the vehicle 2402. The memory manager 140 operates to access the memory of the vehicle 2402 and perform operations on the vehicle 2402. User voice activity detection may be performed based on audio signals received from one or more microphones of the vehicle 2402, such as for delivery orders from an authorized user of the vehicle 2402.

[0142]

[0171] FIG. 25 illustrates another implementation 2500 in which the device 102 corresponds to or is incorporated in a vehicle 2502, depicted as an automobile. The vehicle 2502 includes one or more processors 190, including a memory manager 140. The memory manager 140 operates to access the memory of the vehicle 2502 to perform operations in the vehicle 2502. User voice activity detection may be performed based on audio signals received from one or more microphones of the vehicle 2502. In some implementations, user voice activity detection may be performed based on audio signals received from an internal microphone, such as for voice commands from an authorized passenger. For example, user voice activity detection may be used to detect voice commands from an operator of the vehicle 2502. In some implementations, user voice activity detection may be performed based on audio signals received from an external microphone, such as an authorized user of the vehicle. In particular implementations, in response to receiving a verbal command identified as a user's speech, the voice activation system initiates one or more actions of the vehicle 2502 based on one or more keywords detected in the input signal (e.g., "unlock," "start engine," "play music," "show weather forecast," or another voice command), such as by providing feedback or information via the display 2520 or one or more speakers.

[0143]

[0172] 26, a particular implementation of a method 2600 of memory transaction management is illustrated. In a particular aspect, one or more operations of the method 2600 are performed by at least one of the memory manager 140, the one or more processors 190, the device 102, the system 100, or a combination thereof of FIG. 1. In a particular aspect, the method 2600 is computer-implemented.

[0144]

[0173] Method 2600 includes, at 2602, assigning a distinct domain identifier to each of a plurality of software threads. For example, consistency domain manager 142 assigns consistency domain identifier 156 to each of a plurality of software threads 152, as described with reference to FIGURE 1. As another example, capacity domain manager 144 assigns capacity domain identifier 158 to each of a plurality of software threads 152, as described with reference to FIGURE 1.

[0145]

[0174] Method 2600 also includes, at 2604, controlling operation of one or more components of a processor based on the number of memory transactions associated with the domain identifier. For example, coherence domain manager 142 controls operation of one or more components 170 of one or more processors 190 based on the coherence domain number 162 of the transaction data, as described with reference to FIG. 1. As another example, capacity domain manager 144 controls operation of one or more components 170 of one or more processors 190 based on the capacity domain number 164 of the transaction data, as described with reference to FIG. 1.

[0146]

[0175] In an implementation in which the domain identifier corresponds to a capacity domain identifier, the method 2600 may limit a count of pending memory accesses that may be associated with the capacity domain identifier to allow resources to be available for memory accesses associated with other capacity domain identifiers. To illustrate, software thread 152A is associated with capacity domain identifier 158A, as described with reference to FIG. 16. Controlling the operation of one or more components 170 includes refraining from initiating memory accesses of software thread 152A in response to determining that a count of pending memory accesses associated with any capacity domain identifier (e.g., capacity domain identifier 158B) that matches capacity domain identifier 158A is equal to a corresponding threshold count, as described with reference to FIGS. 16-17. Memory accesses associated with other capacity domain identifiers that do not match capacity domain identifier 158A are not affected by the count of pending memory accesses associated with capacity domain identifier 158A.

[0147]

[0176] Alternatively or additionally, in implementations where the domain identifier corresponds to a consistency domain identifier, the method 2600 can ensure that a synchronization instruction associated with a particular consistency domain identifier does not affect (e.g., does not delay) memory access instructions associated with other consistency domain identifiers that do not match the particular consistency domain identifier. For illustrative purposes, the synchronization instruction 644 is associated with the consistency domain identifier 156A, as described with reference to FIG. 6. Controlling the operation of the one or more components 170 includes allowing pending memory access instructions associated with any consistency domain identifier (e.g., consistency domain identifier 156B) that matches the consistency domain identifier 156A to be executed (e.g., count of pending memory access instructions=0) before executing any subsequent memory access instructions associated with the matching consistency domain identifier (e.g., consistency domain identifier 156B), as described with reference to FIGS. 6-8. The synchronization instruction 644 does not affect (e.g., does not delay) memory access instructions associated with other consistency domain identifiers that do not match the consistency domain identifier 156A.

[0148]

[0177] The method 2600 of Figure 26 may be implemented by a field-programmable gate array (FPGA) device, an application-specific integrated circuit (ASIC), a processing unit such as a central processing unit (CPU), a DSP, a GPU, a controller, another hardware device, a firmware device, or any combination thereof. As an example, the method 2600 of Figure 26 may be performed by a processor executing instructions, such as those described with reference to Figure 27.

[0149]

[0178] 27, a block diagram of a particular example implementation of a device 2700 is shown. In various implementations, the device 2700 may have more or fewer components than shown in FIG. 27. In an example implementation, the device 2700 may correspond to the device 102. In an example implementation, the device 2700 may perform one or more operations described with reference to FIGS. 1-26.

[0150]

[0179] In certain implementations, device 2700 includes a processor 2706 (e.g., a CPU). Device 2700 may include one or more additional processors 2710 (e.g., one or more DSPs, one or more GPUs, or a combination thereof). In certain aspects, one or more processors 190 of FIG. 1 correspond to processor 2706, processor 2710, or a combination thereof. Processor 2710 may include a speech and music coder-decoder (codec) 2708, including a voice coder ("vocoder") encoder 2736, a vocoder decoder 2738, or both. Processor 2710 may include one or more components 170, memory manager 140, transaction tracker 160, configuration data 146, domain identifier data 150, or a combination thereof.

[0151]

[0180] 1. In other implementations, the memory 120 is separate from the memory 2786. The memory 2786 may include instructions 2756 executable by one or more additional processors 2710 (or processor 2706) to implement functions described with respect to the memory manager 140. The device 2700 may include one or more modems 2770 coupled to one or more antennas 2752 via one or more transceivers 2750.

[0152]

[0181] In some aspects, the processor 2710 (or processor 2706) is configured to communicate with device 2780, device 2782, or both, via one or more modems 2770 and one or more transceivers 2750. In a particular example, device 2700 exchanges traffic 2781 (e.g., cellular modem traffic) with device 2780, exchanges traffic 2783 (e.g., WLAN traffic) with device 2782, or both. For example, traffic 2781 is exchanged with device 2780 along a data path via at least one of one or more modems 2770 (e.g., cellular modems), at least one of one or more transceivers 2750, and at least one of one or more antennas 2752. Similarly, traffic 2783 is exchanged with device 2782 along a data path via at least one of one or more modems 2770 (e.g., a WLAN modem), at least one of one or more transceivers 2750, and at least one of one or more antennas 2752.

[0153]

[0182] In a particular implementation, the coherence domain manager 142 of the memory manager 140 enforces synchronization of the traffic 2781 (e.g., cellular modem traffic) independent of the traffic 2783 (e.g., WLAN traffic). For example, the coherence domain manager 142 ensures that a synchronization operation associated with a cellular modem memory transaction does not block a subsequent WLAN memory transaction, and vice versa. In a particular aspect, the capacity domain manager 144 of the memory manager 140 enforces resource utilization of the traffic 2781 (e.g., cellular modem traffic) independent of the traffic 2783 (e.g., WLAN traffic). For example, the capacity domain manager 144 ensures that a cellular modem memory transaction is not blocked by a WLAN memory transaction, and vice versa.

[0154]

[0183] The device 2700 may include a display 2728 coupled to a display controller 2726. One or more speakers 2792, one or more microphones 2790, or a combination thereof may be coupled to a codec 2734. The codec 2734 may include a digital-to-analog converter (DAC) 2702, an analog-to-digital converter (ADC) 2704, or both. In certain implementations, the codec 2734 may receive analog signals from the one or more microphones 2790, convert the analog signals to digital signals using the analog-to-digital converter 2704, and provide the digital signals to a speech and music codec 2708. The speech and music codec 2708 may process the digital signals. In certain implementations, the speech and music codec 2708 may provide the digital signals to the codec 2734. The codec 2734 can convert the digital signal to an analog signal using a digital-to-analog converter 2702 and can provide the analog signal to one or more speakers 2792.

[0155]

[0184] In certain implementations, the device 2700 may be included in a system-in-package or system-on-chip device 2722. In certain implementations, the memory 2786, the processor 2706, the processor 2710, the display controller 2726, the codec 2734, and the one or more modems 2770 are included in the system-in-package or system-on-chip device 2722. In certain implementations, the input device 2730 and the power source 2744 are coupled to the system-in-package or system-on-chip device 2722. Moreover, in certain implementations, the display 2728, the input device 2730, the one or more speakers 2792, the one or more microphones 2790, the one or more antennas 2752, and the power source 2744 are external to the system-in-package or system-on-chip device 2722, as shown in FIG. In particular implementations, each of the display 2728, the input device 2730, the one or more speakers 2792, the one or more microphones 2790, the one or more antennas 2752, and the power source 2744 may be coupled to a component of the system-in-package or system-on-chip device 2722, such as an interface or controller.

[0156]

[0185] Device 2700 may include a smart speaker, a speaker bar, a mobile communications device, a smartphone, a cellular phone, a laptop computer, a computer, a tablet, a personal digital assistant, a display device, a television, a game console, a music player, a radio, a digital video player, a digital video disc (DVD) player, a tuner, a camera, a navigation device, a vehicle, a headset, an augmented reality headset, a mixed reality headset, a virtual reality headset, an aviation vehicle, a home automation system, a voice-activated device, a wireless speaker and a voice-activated device, a portable electronic device, an automobile, a computing device, a communications device, an internet-of-things (IoT) device, a virtual reality (VR) device, a base station, a mobile device, or any combination thereof.

[0157]

[0186] In accordance with the described implementation, the apparatus includes means for assigning a distinct domain identifier to each of the multiple software threads. For example, the means for assigning a distinct domain identifier may correspond to the consistency domain manager 142, the capacity domain manager 144, the memory manager 140, the one or more processors 190, the device 102, the system 100 of FIG. 1, the processor 2706, the one or more processors 2710, the device 2700, one or more other circuits or components configured to assign a distinct domain identifier to each of the multiple software threads, or any combination thereof.

[0158]

[0187] The apparatus also includes means for controlling operation of one or more components of the processor based on the number of memory transactions associated with the domain identifier. For example, the means for controlling operation may correspond to the coherence domain manager 142, the capacity domain manager 144, the memory manager 140, the one or more processors 190, the device 102, the system 100 of FIG. 1, the processor 2706, the one or more processors 2710, the device 2700, one or more other circuits or components configured to assign a distinct domain identifier to each of the multiple software threads, or any combination thereof.

[0159]

[0188] In some implementations, a non-transitory computer-readable medium (e.g., a computer-readable storage device such as memory 2786) includes instructions (e.g., instructions 2756) that, when executed by one or more processors (e.g., one or more processors 2710 or processor 2706), cause the one or more processors to assign a distinct domain identifier (e.g., consistency domain identifier 156, capacity domain identifier 158, or both) to each of a plurality of software threads. The instructions, when executed by one or more processors, also cause the one or more processors to control operation of one or more components of the processor (e.g., one or more components 170) based on a number of memory transactions associated with the domain identifier (e.g., consistency domain number of transaction data 162, capacity domain number of transaction data 164, or both).

[0160]

[0189] Certain aspects of the disclosure are described below in a set of interrelated clauses.

[0161]

[0190] According to clause 1, the device includes a memory and a processor coupled to the memory, the processor configured to assign a distinct domain identifier to each of a plurality of software threads and to control operation of one or more components of the processor based on a number of memory transactions associated with the domain identifier.

[0162]

[0191] Clause 2 includes the device of clause 1, further including a cache control register associated with the first software thread, and wherein assigning the first domain identifier to the first software thread includes updating the cache control register to indicate the first domain identifier.

[0163]

[0192] Clause 3 includes the device of clause 1 or clause 2, wherein the processor is configured to receive a synchronization instruction for a first software thread, the first software thread being assigned a first consistency domain identifier, and controlling operation includes, in response to receiving the synchronization instruction, completing any pending store operations associated with the first consistency domain identifier before executing any subsequent data access instructions associated with the first consistency domain identifier.

[0164]

[0193] Clause 4 includes the device of clause 3, wherein the processor is configured, in response to receiving a synchronization instruction associated with a second consistency domain identifier that matches the first consistency domain identifier, to complete any pending store operations associated with the first consistency domain identifier before executing any subsequent data access instructions associated with the second consistency domain identifier.

[0165]

[0194] Clause 5 includes the device of clause 4, wherein the second consistency domain identifier indicates a sub-domain of the consistency domain indicated by the first consistency domain identifier.

[0166]

[0195] Clause 6 includes the device of clause 4, wherein the first consistency domain identifier is the same as the second consistency domain identifier.

[0167]

[0196] Clause 7 includes the device of any of clauses 3 to 6, wherein the synchronization instruction includes a barrier instruction or a store release load acquire instruction.

[0168]

[0197] Clause 8 includes the device of any of clauses 1 to 7, further including a cache configured to store data in the memory; and a transaction tracking scoreboard configured to track one or more pending stores associated with one or more consistency domain identifiers, wherein the processor is configured to receive a write instruction of a first software thread indicating a first memory location, and in response to determining that data associated with the first memory location is not available in the cache, load the first data from the first memory location into a first portion of the cache and update the first data in the cache.

[0169]

[0198] Clause 9 includes the device of clause 8, wherein the processor is configured to update an entry in the transaction tracking scoreboard to indicate a pending store operation of the updated first data to the first memory location in response to a store associated with the first software thread being committed, the entry being updated to indicate the first memory location and a first consistency domain identifier of the first software thread.

[0170]

[0199] Clause 10 includes the device of clause 9, wherein the processor is further configured to receive an acknowledgment indicating that storage of the updated first data in the first memory location is complete, and in response to receiving the acknowledgment, update the transaction tracking scoreboard to indicate that the entry in the transaction tracking scoreboard is invalid.

[0171]

[0200] Clause 11 includes the device of any of clauses 8 to 10, wherein the processor is configured to, in response to receiving a memory access instruction of the second software thread indicating the second memory location, initiate an eviction of the updated first data from the cache and load the second data from the second memory location into the first portion of the cache when data corresponding to the second memory location is not available in the cache and the cache is full.

[0172]

[0201] Clause 12 includes the device of clause 11, wherein initiating the eviction of the updated first data includes updating an entry in a transaction tracking scoreboard to indicate a pending eviction of the updated first data corresponding to the first memory location.

[0173]

[0202] Clause 13 includes the device of clause 12, wherein the processor is further configured to receive an acknowledgment indicating that storage of the updated first data in the first memory location is complete, and in response to receiving the acknowledgment, update the transaction tracking scoreboard to indicate that the entry in the transaction tracking scoreboard is invalid.

[0174]

[0203] Clause 14 includes the device of any of clauses 8 to 13, wherein the processor is configured to, in response to determining that a cache operation having the second consistency domain identifier is associated with a first memory location corresponding to the updated first data stored in the first portion of the cache, initiate an eviction of the updated first data from the cache and update the cache to indicate that the first portion of the cache is available.

[0175]

[0204] Clause 15 includes the device of clause 14, wherein initiating an eviction of the updated first data includes updating an entry in a transaction tracking scoreboard to indicate a pending eviction of the updated first data and to indicate a pending store operation associated with the second consistency domain identifier.

[0176]

[0205] Clause 16 includes the device of clause 15, wherein the processor is further configured to receive an acknowledgment indicating that storage of the updated first data in the first memory location is completed, and in response to receiving the acknowledgment, update the transaction tracking scoreboard to indicate that the entry in the transaction tracking scoreboard is invalid.

[0177]

[0206] Clause 17 includes the device of any of clauses 1 to 16, further including a cache configured to store data in the memory, and wherein the processor is configured to assign a second consistency domain identifier of the cache operation to any pending eviction associated with the second memory location in response to determining that the cache operation is associated with a second memory location and that valid data associated with the second memory location is not stored in the cache.

[0178]

[0207] Clause 18 includes the device of any of clauses 1 to 17, further including a cache configured to store data of the memory; and a transaction tracking scoreboard, wherein the processor is configured to update the entry in the transaction tracking scoreboard to indicate a second consistency domain identifier of the cache operation in response to determining that the cache operation is associated with a second memory location, that valid data associated with the second memory location is not stored in the cache, and that the entry in the transaction tracking scoreboard corresponds to a pending eviction associated with the second memory location.

[0179]

[0208] Clause 19 includes the device of clause 18, wherein the processor is further configured to receive an acknowledgment indicating that a store associated with the transaction tracking scoreboard entry is completed, and in response to receiving the acknowledgment, update the transaction tracking scoreboard to indicate that the transaction tracking scoreboard entry is invalid.

[0180]

[0209] Clause 20 includes the device of any of clauses 1 to 19, wherein the processor is configured to receive memory access instructions from a first software thread, the first software thread being assigned a first capacity domain identifier, and controlling the operation includes selectively enabling the memory access instructions based on a count of pending memory access instructions associated with the first capacity domain identifier.

[0181]

[0210] Clause 21 includes the device of clause 20, wherein the processor is configured to, based on determining that the count of pending memory access instructions is less than a threshold count corresponding to the first capacity domain identifier, initiate a memory access associated with the memory access instruction and increment the count of pending memory access instructions associated with the first capacity domain identifier.

[0182]

[0211] Clause 22 includes the device of clause 21, wherein the processor is configured to receive an acknowledgment indicating that the memory access is completed, and in response to receiving the acknowledgment, decrement a count of pending memory access instructions associated with the first capacity domain identifier.

[0183]

[0212] Clause 23 includes a device described in any of clauses 1 to 22, wherein a first domain identifier is assigned to a first software thread based at least in part on a communication type associated with the first software thread, the communication type including cellular modem traffic or wireless local area network (WLAN) traffic.

[0184]

[0213] According to clause 24, a computer-implemented method includes, in a device, assigning a distinct domain identifier to each of a plurality of software threads; and controlling, in the device, operation of one or more components of a processor based on a number of memory transactions associated with the domain identifier.

[0185]

[0214] Clause 25 includes the computer-implemented method of clause 24, wherein a cache control register is associated with the first software thread, and assigning a first domain identifier to the first software thread includes updating the cache control register to indicate the first domain identifier.

[0186]

[0215] Clause 26 includes the computer-implemented method of clause 24 or clause 25, further including receiving a synchronization instruction for a first software thread, the first software thread being assigned a first consistency domain identifier, and controlling operation includes, in response to receiving the synchronization instruction, completing any pending store operations associated with the first consistency domain identifier before executing any subsequent data access instructions associated with the first consistency domain identifier.

[0187]

[0216] Clause 27 includes the computer-implemented method of clause 26, further including, in response to receiving a synchronization instruction associated with a second consistency domain identifier that matches the first consistency domain identifier, completing any pending store operations associated with the first consistency domain identifier before executing any subsequent data access instructions associated with the second consistency domain identifier.

[0188]

[0217] Clause 28 includes the computer-implemented method of clause 27, wherein the second consistency domain identifier indicates a sub-domain of the consistency domain indicated by the first consistency domain identifier.

[0189]

[0218] Clause 29 includes the computer-implemented method of clause 27, wherein the first consistency domain identifier is the same as the second consistency domain identifier.

[0190]

[0219] Clause 30 includes the computer-implemented method of any of clauses 26 to 29, wherein the synchronization instruction includes a barrier instruction or a store-release-load-acquire instruction.

[0191]

[0220] Clause 31 includes the computer-implemented method of any of clauses 24 to 30, further including receiving a write instruction of a first software thread indicating a first memory location and, in response to determining that data associated with the first memory location is not available in the cache, loading the first data from the first memory location into a first portion of the cache and updating the first data in the cache.

[0192]

[0221] Clause 32 includes the computer-implemented method of clause 31, further including updating an entry in the transaction tracking scoreboard to indicate a pending store operation of the updated first data to the first memory location in response to the store associated with the first software thread being committed, the entry being updated to indicate the first memory location and a first consistency domain identifier of the first software thread.

[0193]

[0222] Clause 33 includes the computer-implemented method of clause 32, further including receiving an acknowledgment indicating that storage of the updated first data in the first memory location is complete, and in response to receiving the acknowledgment, updating the transaction tracking scoreboard to indicate that the entry in the transaction tracking scoreboard is invalid.

[0194]

[0223] Clause 34 includes the computer-implemented method of any of clauses 31 to 33, further including, when data corresponding to the second memory location is not available in the cache and the cache is full, in response to receiving a memory access instruction of the second software thread indicating the second memory location, initiating an eviction of the updated first data from the cache, and loading the second data from the second memory location into the first portion of the cache.

[0195]

[0224] Clause 35 includes the computer-implemented method of clause 34, wherein initiating an eviction of the updated first data includes updating an entry in a transaction tracking scoreboard to indicate a pending eviction of the updated first data corresponding to the first memory location.

[0196]

[0225] Clause 36 includes the computer-implemented method of clause 35, further including receiving an acknowledgment indicating that storing the updated first data in the first memory location is complete, and in response to receiving the acknowledgment, updating the transaction tracking scoreboard to indicate that the entry in the transaction tracking scoreboard is invalid.

[0197]

[0226] Clause 37 includes the computer-implemented method of any of clauses 31 to 36, wherein the processor is configured to, in response to determining that a cache operation having the second consistency domain identifier is associated with a first memory location corresponding to the updated first data stored in the first portion of the cache, initiate an eviction of the updated first data from the cache and update the cache to indicate that the first portion of the cache is available.

[0198]

[0227] Clause 38 includes the computer-implemented method of clause 37, where initiating an eviction of the updated first data includes updating an entry in a transaction tracking scoreboard to indicate a pending eviction of the updated first data and to indicate a pending store operation associated with the second consistency domain identifier.

[0199]

[0228] Clause 39 includes the computer-implemented method of clause 38, further including receiving an acknowledgment indicating that storage of the updated first data in the first memory location is complete, and in response to receiving the acknowledgment, updating the transaction tracking scoreboard to indicate that the entry in the transaction tracking scoreboard is invalid.

[0200]

[0229] Clause 40 includes the computer-implemented method of any of clauses 24 to 39, further including, in response to determining that the cache behavior is associated with a second memory location and that valid data associated with the second memory location is not stored in the cache, assigning a second consistency domain identifier of the cache behavior to any pending evictions associated with the second memory location.

[0201]

[0230] Clause 41 includes the computer-implemented method of any of clauses 24 to 40, further including, in response to determining that the cache behavior is associated with a second memory location, that valid data associated with the second memory location is not stored in the cache, and that the transaction tracking scoreboard entry corresponds to a pending eviction associated with the second memory location, updating the transaction tracking scoreboard entry to indicate a second consistency domain identifier of the cache behavior.

[0202]

[0231] Clause 42 includes the computer-implemented method of clause 41, further including receiving an acknowledgment indicating that the store associated with the transaction tracking scoreboard entry is completed, and in response to receiving the acknowledgment, updating the transaction tracking scoreboard to indicate that the transaction tracking scoreboard entry is invalid.

[0203]

[0232] Clause 43 includes the computer-implemented method of any of clauses 24 to 42, further including receiving a memory access instruction from a first software thread, the first software thread being assigned a first capacity domain identifier, and controlling the operation includes selectively enabling the memory access instruction based on a count of pending memory access instructions associated with the first capacity domain identifier.

[0204]

[0233] Clause 44 includes the computer-implemented method of clause 43, further including initiating a memory access associated with the memory access instruction based on determining that the count of pending memory access instructions is less than a threshold count corresponding to the first capacity domain identifier, and incrementing the count of pending memory access instructions associated with the first capacity domain identifier.

[0205]

[0234] Clause 45 includes the computer-implemented method of clause 44, further including receiving an acknowledgment indicating that the memory access is completed, and in response to receiving the acknowledgment, decrementing a count of pending memory access instructions associated with the first capacity domain identifier.

[0206]

[0235] Clause 46 includes the computer-implemented method of any of clauses 24 to 45, wherein the first domain identifier is assigned to the first software thread based at least in part on a communication type associated with the first software thread, the communication type including cellular modem traffic or wireless local area network (WLAN) traffic.

[0207]

[0236] According to clause 47, a device includes a memory configured to store instructions and a processor configured to execute the instructions to perform a method according to any of clauses 24 to 46.

[0208]

[0237] According to clause 48, a non-transitory computer readable medium stores instructions which, when executed by a processor, cause the processor to perform a method according to any of clauses 24 to 46.

[0209]

[0238] According to clause 49, the apparatus comprises means for carrying out the method according to any of clauses 24 to 46.

[0210]

[0239] According to clause 50, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to assign a distinct domain identifier to each of a plurality of software threads and control operation of one or more components of the processor based on a number of memory transactions associated with the domain identifier.

[0211]

[0240] Clause 51 includes the non-transitory computer-readable medium of clause 50, wherein the instructions, when executed by the processor, cause the processor to receive a synchronization instruction for a first software thread, the first software thread being assigned a first consistency domain identifier, and controlling the operation includes, in response to receiving the synchronization instruction, completing any pending store operations associated with the first consistency domain identifier before executing any subsequent data access instructions associated with the first consistency domain identifier.

[0212]

[0241] According to clause 52, the apparatus includes means for assigning a distinct domain identifier to each of a plurality of software threads, and means for controlling operation of one or more components of the processor based on a number of memory transactions associated with the domain identifier.

[0213]

[0242] Clause 53 includes the apparatus of clause 52, wherein the means for allocating and the means for controlling are incorporated into at least one of a smart speaker, a speaker bar, a display device, a television, a game console, a music player, a camera, a navigation device, a vehicle, a headset, an augmented reality headset, a mixed reality headset, a virtual reality headset, an aviation vehicle, a home automation system, a voice-activated device, a wireless speaker and a voice-activated device, a computing device, a communications device, an Internet of Things (IoT) device, a virtual reality (VR) device, a base station, or a mobile device.

[0214]

[0243] Those skilled in the art will further appreciate that the various exemplary logical blocks, configurations, modules, circuits, and algorithmic steps described with respect to the implementations disclosed herein may be implemented as electronic hardware, computer software executed by a processor, or a combination of both. Various exemplary components, blocks, configurations, modules, circuits, and steps have been generally described above with respect to their functionality. Whether such functionality is implemented as hardware or as processor-executable instructions depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, and such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0215]

[0244] The steps of a method or algorithm described in connection with the implementations disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a register, a hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of non-transitory storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an Application Specific Integrated Circuit (ASIC), which may reside in a computing device or user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a computing device or user terminal.

[0216]

[0245] The foregoing description of the disclosed aspects is provided to enable any person skilled in the art to make or use the disclosed aspects. Various modifications of these aspects will be readily apparent to those skilled in the art, and the principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein, but is to be accorded the widest possible scope consistent with the principles and novel features defined by the following claims.

Claims

1. Memory and a processor coupled to the memory, the processor: assigning a distinct domain identifier to each of the plurality of software threads; and controlling operation of one or more components of the processor based on a number of memory transactions associated with a consistency domain identifier. It is structured as follows: the processor is configured to receive a synchronization instruction for a first software thread, the first software thread being assigned a first consistency domain identifier, and controlling the operation includes, in response to receiving the synchronization instruction for the first software thread, completing any pending store operations associated with the first consistency domain identifier before executing any subsequent data access instructions associated with the first consistency domain identifier; 1. A device, comprising: a processor configured to, in response to receiving a synchronization instruction associated with a second consistency domain identifier that matches the first consistency domain identifier, complete any pending store operations associated with the first consistency domain identifier before executing any subsequent data access instructions associated with the second consistency domain identifier.

2. The device of claim 1, further comprising a cache control register associated with the first software thread, and wherein assigning the first consistency domain identifier to the first software thread includes updating the cache control register to indicate the first consistency domain identifier.

3. The device of claim 1, wherein the first consistency domain identifier is assigned to the first software thread based at least in part on a communication type associated with the first software thread, the communication type including cellular modem traffic or wireless local area network traffic.

4. The device of claim 1 , wherein the second consistency domain identifier indicates a sub-domain of a consistency domain indicated by the first consistency domain identifier.

5. The device of claim 1 , wherein the first consistency domain identifier is the same as the second consistency domain identifier.

6. The device of claim 1, wherein the synchronization instruction of the first software thread includes a barrier instruction or a store release load acquire instruction.

7. a cache configured to store data from the memory; a transaction tracking scoreboard configured to track one or more pending stores associated with the one or more consistency domain identifiers; In response to the processor receiving a write instruction of the first software thread indicating a first memory location and determining that data associated with the first memory location is not available in the cache, loading first data from the first memory location into a first portion of the cache; updating the first data in the cache; The device of claim 1 , configured to:

8. 8. The device of claim 7, wherein the processor is configured to, in response to a store associated with the first software thread being committed, update an entry in the transaction tracking scoreboard to indicate a pending store operation of the updated first data to the first memory location, the entry being updated to indicate the first memory location and a first consistency domain identifier of the first software thread.

9. The processor: receiving an acknowledgment indicating that the updated first data has been stored in the first memory location; In response to receiving the acknowledgment, updating the transaction tracking scoreboard to indicate that the entry in the transaction tracking scoreboard is invalid. The device of claim 8 further configured to:

10. When data corresponding to a second memory location is not available in the cache and the cache is full, the processor, in response to receiving a memory access instruction of a second software thread indicating the second memory location, Initiating an eviction of the updated first data from the cache; loading second data from the second memory location into the first portion of the cache; The device of claim 7 , configured to:

11. 11. The device of claim 10, wherein initiating the eviction of the updated first data includes updating an entry in the transaction tracking scoreboard to indicate a pending eviction of the updated first data corresponding to the first memory location.

12. assigning, in the device, a distinct domain identifier to each of a plurality of software threads; controlling, in the device, operation of one or more components of a processor based on a number of memory transactions associated with a consistency domain identifier; receiving, at the device, a synchronization instruction for a first software thread, the first software thread being assigned a first consistency domain identifier, and controlling operation includes, in response to receiving the synchronization instruction for the first software thread, completing any pending store operations associated with the first consistency domain identifier before executing any subsequent data access instructions associated with the first consistency domain identifier; In response to receiving, at the device, a synchronization instruction associated with a second consistency domain identifier that matches the first consistency domain identifier, completing any pending store operations associated with the first consistency domain identifier before executing any subsequent data access instructions associated with the second consistency domain identifier; 11. A computer-implemented method comprising:

13. 13. The computer-implemented method of claim 12, wherein a cache control register is associated with the first software thread, and wherein assigning the first consistency domain identifier to the first software thread comprises updating the cache control register to indicate the first consistency domain identifier.

14. 14. A non-transitory computer readable medium storing instructions that, when executed by a processor, cause the processor to perform the method of claim 12 or 13.

15. An apparatus comprising a device according to any one of claims 1 to 11, the apparatus being a smart speaker, a speaker bar, a display device, a television, a games console, a music player, a camera, a navigation device, a vehicle, a headset, an augmented reality headset, a mixed reality headset, a virtual reality headset, an aviation vehicle, a home automation system, a voice-activated device, a wireless speaker and a voice-activated device, a computing device, a communications device, an Internet of Things device, a virtual reality device, a base station, or a mobile device.

Images