Error pin training using graphics DDR memory

Abstract

The receiver is trained to receive a signal via the data bus. The volatile memory is instructed via the data bus to place a selected pulse amplitude modulation (PAM) driver into a mode having a specified steady-state output level. In a receiver circuit coupled to the selected PAM driver, a respective reference voltage associated with the specified steady-state output level is swept across a voltage range and the respective reference voltage is compared to a voltage received from the PAM driver to determine a respective voltage level received from the PAM driver.

Description

[Background technology]

[0001] Modern dynamic random-access memory (DRAM) provides high memory bandwidth by increasing the speed of data transmission on a bus connecting the DRAM and one or more data processors, such as a graphics processing unit (GPU) or a central processing unit (CPU). DRAM is typically inexpensive and dense, which allows for a large number of DRAMs to be integrated per device. Most DRAM chips sold today conform to various double data rate (DDR) DRAM standards promoted by the Joint Electron Devices Engineering Council (JEDEC). Typically, several DDR DRAM chips are combined on a single printed circuit board to form a memory module that is relatively fast but also offers scalability. However, while these enhancements have improved the speed of DDR memory used for main memory in computer systems, further improvements are required.

[0002] One type of DDR DRAM, known as graphics double data rate (GDDR) memory, has pushed the boundaries of data transmission rates to accommodate the high bandwidth required for graphics applications. As new GDDR standards are developed, they tend to support higher data rates. However, operation at these higher data rates generally requires improvements in the process of training the data link's transmit and receive circuits. Also, the link training process becomes complicated when the number of signaling levels employed on a signaling link exceeds two. [Brief description of the drawings]

[0003] [Figure 1] 1 is a block diagram illustrating a data processing system according to some embodiments. [Diagram 2] 2 is a block diagram showing a GDDR PHY-DRAM link of the data processing system of FIG. 1; [Diagram 3] 2 is a block diagram illustrating a read clock circuit for selectively providing a read clock signal from a memory to a memory controller via a memory bus in accordance with some embodiments. [Figure 4] 1 illustrates a flow diagram of a process for training a PAM4 receiver in accordance with some embodiments. [Diagram 5] 5 is an "eye" diagram illustrating various signaling levels that may be employed with the process of FIG. 4. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0004] In the following description, the use of the same reference numbers in different figures indicates similar or identical items. Unless otherwise noted, the word "coupled" and its related verb forms include both direct and indirect electrical connections by means well known in the art, and unless otherwise noted, any description of a direct connection also refers to alternative embodiments using a suitable form of indirect electrical connection.

[0005] A method is used for training a receiver that receives a signal via a data bus. The method includes instructing a volatile memory via the data bus to place a selected pulse-amplitude modulation 4-level (PAM4) driver into a mode having a specified steady-state output level, and then waiting for a predetermined period of time. In a receiver circuit coupled to the selected PAM4 driver, the method includes sweeping respective reference voltages associated with the specified steady-state output levels over a voltage range and comparing the respective reference voltages to voltages received from the PAM4 driver to determine respective voltage levels received from the PAM4 driver. The specified steady-state output levels are then changed, and the process of sweeping the respective reference voltages and determining the voltage levels is repeated for the new output levels.

[0006] A physical layer (PHY) circuit for coupling to a volatile memory via a data bus includes a pulse amplitude modulation four level (PAM4) receiver and a receiver control circuit. The receiver includes a decoder circuit and three sub-receiver circuits, each sub-receiver circuit including an output coupled to the decoder circuit, a first input coupled to a data bus terminal, and a second input coupled to a respective reference voltage circuit. The receiver control circuit is operable to (a) instruct the volatile memory via the data bus to place a selected PAM4 driver into a mode having a specified steady-state output level, (b) wait a predetermined period of time, (c) sweep a reference voltage of a respective one of the reference voltage circuits across a range of voltages and compare the reference voltage to a voltage received from the selected PAM4 driver to determine a respective voltage level received from the selected PAM4 driver, and (d) after performing (a)-(c), change the specified steady-state output level and repeat (a)-(c).

[0007] The memory system includes a volatile memory, a data bus coupled to the volatile memory, and a memory controller. The memory controller includes a physical layer (PHY) circuit coupled to the data bus, and a receiver control circuit. The PHY circuit includes a pulse amplitude modulation four level (PAM4) receiver including three sub-receiver circuits, each sub-receiver circuit including a first input coupled to the data bus terminal and a second input coupled to a respective reference voltage circuit. The receiver control circuit is operable to (a) instruct the volatile memory via the data bus to place a selected PAM4 driver into a mode having a specified steady-state output level, (b) wait a predetermined period of time, (c) sweep a reference voltage of a respective one of the reference voltage circuits across a range of voltages and compare the reference voltage to a voltage received from the selected PAM4 driver to determine a respective voltage level received from the selected PAM4 driver, and (d) after performing (a)-(c), change the specified steady-state output level and repeat (a)-(c).

[0008] 1 is a block diagram illustrating a data processing system 100 in accordance with some embodiments. Data processing system 100 generally includes data processors in the form of a graphics processing unit (GPU) 110, a host central processing unit (CPU) 120, double data rate (DDR) memory 130, and graphics DDR (GDDR) memory 200.

[0009] The GPU 110 is a discrete graphics processor that has very high performance for optimized graphics processing, rendering and display, but requires high memory bandwidth to perform these tasks. The GPU 110 generally includes a set of command processors 111, a graphics single instruction multiple data (SIMD) core 112, a set of caches 113, a memory controller 114, a DDR physical interface circuit (DDR PHY) 115, and a GDDR PHY 116. Although a GPU is shown in this embodiment, the GPU 110 can be any of a variety of data processing elements, such as a machine learning parallel acceleration processor.

[0010] Command processor 111 is used to interpret high-level graphics instructions such as those specified in the OpenGL programming language. Command processor 111 has a bidirectional connection to memory controller 114 for receiving high-level graphics instructions such as OpenGL instructions, a bidirectional connection to cache 113, and a bidirectional connection to graphics SIMD core 112. In response to receiving the high-level instructions, command processor issues low-level instructions for rendering, geometric processing, shading, and rasterization of data such as frame data, using cache 113 as temporary storage. In response to the graphics instructions, graphics SIMD core 112 executes the low-level instructions on large data sets in a massively parallel manner. Command processor 111 and cache 113 are used for temporary storage of input data and output (e.g., rendered and rasterized) data. Cache 113 also has a bidirectional connection to graphics SIMD core 112 and a bidirectional connection to memory controller 114.

[0011] The memory controller 114 has a first upstream bidirectional port connected to the command processor 111, a second upstream bidirectional port connected to the cache 113, a first downstream bidirectional port to the DDR PHY 115, and a second downstream bidirectional port to the GDDR PHY 116. As used herein, the "upstream" port is the side of the circuitry towards the data processor and away from the memory, and the "downstream" port is in the direction away from the data processor and towards the memory. The memory controller 114 controls the timing and ordering of data transfers between the DDR memory 130 and the GDDR memory 200. DDR and GDDR memories have asymmetric access, i.e., access to open pages in the memory is faster than access to closed pages. The memory controller 114 stores memory access commands and processes them out of order for efficiency, for example, by prioritizing access to open pages while adhering to certain quality of service targets.

[0012] The DDR PHY 115 has an upstream bidirectional port connected to a first downstream port of the memory controller 114 and a downstream port bidirectionally connected to the DDR memory 130. The DDR PHY 115 meets all specified timing parameters of a version of the DDR memory 130, such as DDR version 5 (DDR5), and performs timing calibration operations at the direction of the memory controller 114. Similarly, the GDDR PHY 116 has an upstream port connected to a second downstream port of the memory controller 114 and a downstream port bidirectionally connected to the GDDR memory 200. The GDDR PHY 116 meets all specified timing parameters of a version of the GDDR memory 200, and performs timing calibration operations at the direction of the memory controller 114. The GDDR memory 200 includes a set of mode registers 141 programmable on the GDDR PHY 116 to configure the GDDR memory 200 for operation.

[0013] During operation, the data processing system can be used as a graphics card or accelerator due to the high bandwidth graphics processing performed by the graphics SIMD cores 112. The host CPU 120, which runs an operating system or application programs, sends graphics processing commands to the GPU 110 through the DDR memory 130, which serves as a unified memory for the GPU 110 and the host CPU 120. It may send commands to the GPU interface, for example, using OpenGL commands or through any other host CPU. OpenGL is a cross-language, cross-platform application programming interface for rendering 2D and 3D vector graphics. The host CPU 120 interacts with the GPU 110 using an application programming interface (API) to provide hardware accelerated rendering.

[0014] Data processing system 100 uses two types of memory. The first type of memory is DDR memory 130, which is accessible by both GPU 110 and host CPU 120. As part of the high performance of graphics SIMD core 112, GPU 110 uses high speed graphics double data rate (GDDR) memory.

[0015] 2 is a block diagram illustrating a GDDR PHY-DRAM link 200 of the data processing system 100 of FIG. 1 in accordance with some embodiments. The GDDR PHY-DRAM link 200 includes a GPU 110 and a portion of a GDDR memory 200 that communicate through a physical interface 260.

[0016] GPU 110 includes a phase locked loop (PLL) 210, a command and address ("C / A") circuit 220, a read clock circuit 230, a data circuit 240, and a write clock circuit 250. These circuits form part of GDDR PHY 116 of GPU 110.

[0017] The phase-locked loop 210 operates as a reference clock generating circuit and generates a clock signal “CK IN ” and an output.

[0018] C / A circuit 220 includes delay element 221, selector 222, transmit buffer 223 labeled "TX", and "ERR" receiver 216. Delay element 221 has an input connected to the output of PLL 210, an output, and has a variable delay controlled by an input not specifically shown in FIG. 2. The variable delay is determined at start-up by calibration controller 115 and adjusted during operation by a compensation circuit. Selector 222 has a first input for receiving a first command / address value, a second input for receiving a second command / address value, and a control input connected to the output of delay element 221. Transmitter 223 has an input connected to the output of selector 222 and an output connected to a corresponding integrated circuit terminal for providing a command / address signal labeled "C / A". C / A circuit 220 includes a set of individual buffers for each signal in the C / A signal group, configured similarly to the exemplary selector 222 and buffer 223 shown in FIG. 2, but it should be noted that only the exemplary C / A circuit 220 is shown.

[0019] Read clock circuit 230 includes a receive buffer 231, labeled "RX," and a selector 232. Receive buffer 231 has an input connected to a corresponding integrated circuit terminal for receiving a signal labeled "RCK," and an output. Receive clock selector 232 has a first input connected to the output of PLL 210, a second input connected to the output of receive buffer 231, an output, and a control input for receiving a mode signal, not shown in FIG.

[0020] Data circuit 240 includes a receive buffer 241, a latch 242, delay elements 243 and 244, a serializer 245, and a transmit buffer 246. Receive buffer 241 has a first input connected to an integrated circuit terminal that receives a data signal generally labeled "DQ" and a second input connected to an integrated circuit terminal that receives a data signal generally labeled "V REF Latch 242 is a D-type latch having an input labeled "D" connected to the output of receive buffer 241, a clock input, and an output labeled "Q" for providing an output data signal. The interface between GDDR PHY 116 and GDDR memory 200 implements a four-level Pulse Amplitude Modulation data signaling system known as "PAM4," which encodes two data bits into one of four nominal voltage levels. Receive buffer 241 thus identifies which of the four levels is indicated by the input voltage and outputs two data bits representing a state accordingly. For example, receive buffer 241 may have V 100, V 200 , V 300 , V 400 , V 500 , V 600 , V 700 , V 800 , V 900 , V 1000 , V 1100 , V 220 , V 320 , V 400 , V 500 , V 600 , V 700 , V 800 , V 900 REFBased on the above, three slicing levels can be generated and three comparators can be used to determine which range the received data signal falls into. Data circuit 240 includes a latch that latches two data bits and is replicated for each bit position. Delay element 243 has an input connected to the output of selector 232 and an output connected to the clock input of latch 242. Delay element 244 has an input connected to the output of PLL 210 and an output. Serializer 245 has inputs for receiving a first data value for a given bit position and a second data value for a given bit position corresponding to successive cycles of the burst, a control input connected to the output of delay element 244, and an output connected to a corresponding DR terminal. Each data byte of the data bus has a set of data circuits such as data circuit 240 for each bit of the byte. This replication allows different data bytes with different routing on the printed circuit board to have different delay values.

[0021] Write clock circuit 250 includes a delay element 251, a selector 252, and a transmit buffer 253. Delay element 251 has an input connected to the output of PLL 210 and an output. Selector 252 has a first input for receiving a first clock state signal, a second input for receiving a second clock voltage, a control input connected to the output of delay element 251, and an output. Transmit buffer 253 has an input connected to the output of selector 252, a first output connected to a corresponding integrated circuit terminal for providing a true write clock signal labeled "WCK_t" and a second output connected to a corresponding integrated circuit terminal for providing a complementary write clock signal labeled "WCK_c."

[0022] GDDR memory 200 generally includes write clock receiver 270, command / address receiver 280, and data path transceiver 290. Write clock receiver 270 includes receive buffer 271, buffer 272, divider 273, buffer / tree 274, and divider 275. Receive buffer 271 has a first input connected to an integrated circuit terminal of GDDR memory 200 that receives a WCK_t signal, a second input connected to an integrated circuit terminal of GDDR memory 200 that receives a WCK_c signal, and an output. In the example shown in FIG. 2, the output of receive buffer 271 is a clock signal having a nominal frequency of 8 GHz. Buffer 272 has an input connected to the output of receive buffer 271 and an output. Divider 273 has an input connected to the output of buffer 272 and an output for providing a divided clock having a nominal frequency of 4 GHz. Divider 275 has an input connected to the output of buffer / tree 274, and an output for providing a clock signal labeled "CK4" having a nominal frequency of 2 GHz.

[0023] The command / address receiver 280 includes a receiving buffer 281 and a slicer 282. The receiving buffer 281 has a first input connected to a corresponding integrated circuit terminal of the GDDR memory 200 that receives the C / A signal, and a second input connected to a V REF The C / A input signal is received as a normal binary signal having two logic state levels and is considered a non-return-to-zero (NRZ) signal encoding. Slicer 282 has a set of two data latches, each having a D input connected to the output of receive buffer 281, a clock input for receiving a corresponding one of the outputs of divider 275, and a Q output for providing a corresponding C / A signal. A PAM4 driver 215 is also included, labeled "ERR", and provides command and address (CA) parity and write CRC information as further described below.

[0024] The data path transceiver 290 includes a serializer 291, a transmitter 292, a serializer 293, a transmitter 294, a receive buffer 295, and a slicer 296. The serializer 291 has an input for receiving a first read clock level, a second input for receiving a second read clock level, a select input connected to an output of the buffer / tree 274, and an output. The transmitter 292 has an input connected to an output of the serializer 293 and an output connected to an RCK terminal of the GDDR memory 200. The serializer 293 has an input for receiving a first read data value, a second input for receiving a second data value, a select input connected to an output of the buffer / tree 274, and an output connected to a DQ terminal of the GDDR memory 200. The transmitter 294 has an input connected to an output of the serializer 293 and an output connected to a corresponding DQ terminal of the GDDR memory 200. The receive buffer 295 has a first input connected to a corresponding DQ terminal of the GDDR memory 200, and a second input connected to a V REF Slicer 296 has a set of four data latches, each having a D input connected to the output of receive buffer 295, a clock input connected to the output of buffer / tree 274, and a Q output for providing a corresponding DQ signal.

[0025] The interface 260 includes a set of physical connections routed from the bond pads of the GPU 110 die, through the package impedance to the package terminals, through traces on the printed circuit board to the package terminals of the GDDR memory 200, and back through the package impedance to the bond pads of the GDDR memory 200 die.

[0026] 3 is a block diagram illustrating a portion of a memory system 300 showing a portion of a physical layer (PHY) circuitry on a system-on-chip (SOC) and associated circuitry on a DRAM, according to some embodiments. The illustrated portion of memory system 300 includes a PAM4 driver 215, a PAM4 receiver 216, a training control circuit 310, an error mode register 320, and a control, command / address parity and cyclic redundancy check circuit 330, labeled "CTRL / CA PARITY / CRC."

[0027] Although a PAM4 driver is shown in this embodiment, the techniques herein are applicable to PAM signaling having more than two PAM levels, e.g., PAM3, PAM4, PAM6, PAM8 drivers and receivers.

[0028] The illustrated portion of memory system 300 is suitable for use with GDDR memory compliant DRAMs employing multi-level PAM signaling, such as the illustrated GDDR PHY-DRAM link shown in FIG. 2. PAM4 driver 215, in this embodiment, drives a signal on the “ERR” pin of the GDDR PHY over the memory bus to the host SOC. PAM4 driver 215 has an input that receives a 2-bit signal labeled “DIN<1:0>” and an output connected to the ERR pin labeled “ERR(PAM4).” The ERR pin carries the PAM4 signal sent asynchronously by the GDDR DRAM to the host system-on-chip (SOC) and communicates command and address (CA) parity and write CRC information provided by CTRL / CA PARITY / CRC circuit 330 to the host SOC.

[0029] The PAM4 receiver 216 is part of the PHY circuitry of the host SOC for coupling to the DRAM. The PAM4 receiver 216 has an input connected to the ERR pin of the PHY, a second input receiving a reference voltage "VR_L3", a third input receiving a reference voltage "VR_L2", and a fourth input receiving a reference voltage "VR_L1". The PAM4 receiver 216 includes a decoder circuit 302 having three inputs labeled "A01", "A02", and "A03", and three sub-receiver circuits 304, 306, 308, each including an output coupled to a respective input of the decoder circuit 302, a first input connected to a first input of the PAM4 receiver 216, and a second input connected to receive a respective one of the reference voltages VR_L3, VR_L2, VR_L1. Each sub-receiver is implemented as a voltage comparator that compares a reference voltage at its input with the voltage received via the ERR pin, and outputs a "1" if the ERR voltage is higher than the reference voltage and a "0" if the ERR voltage is lower than the reference voltage.

[0030] The PAM4 scheme allows the data transmission bandwidth to be doubled for a given clock speed, but makes training the various bit lanes of the PHY more difficult than training a conventional PHY bit lanes employing two signaling levels. Thus, training for the various DQ drivers and receivers employed in the GDDR PHY 116 (e.g., FIG. 2, 241, 246, 294, 295) is longer and more complex than training for a GDDR PHY that interfaces with two-level signaling. The training control circuit 310 includes digital logic for controlling a simplified PAM training process for the PAM4 driver 215 and the PAM4 receiver 216. The training control circuit 310 includes a connection to the PHY digital control logic (not shown) and a communication connection to an error mode register 320 on the DRAM, in this embodiment through a mode register set (MRS) command interface.

[0031] An error mode register 320 on the DRAM can be programmed with MRS programming commands through the GDDR command interface and generally holds values ​​for controlling the operating mode of the CTRL / CA PARITY / CRC circuit 330 and its associated PAM4 driver 215. The CTRL / CA PARITY / CRC circuit 330 has an input connected to the error mode register 320, inputs (not shown) for receiving control and CA data for producing parity and CRC information, and an output connected to the PAM4 driver 215 for providing the DIN<1:0> signal.

[0032] In operation, the PAM4 receiver 216 receives data asynchronously, i.e., data is received asynchronously without reference to RCK. In this embodiment, the PAM4 driver 215 transmits data at a rate of 4 Gbps, which is a lower rate than that used for the DQ lines of the GDDR PHY 116. Thus, a more efficient and simplified version of link training for the PAM4 receiver 216 is provided than that employed for the DQ lines. The training control circuit 310 programs the error mode register 320 to put the CTRL / CA PARITY / CRC circuit 330 into various modes to implement a simplified training process, as will be further described with respect to FIG. 4. In this embodiment, the ERR-related mode register states selectable by the training control circuit 310 include a normal mode (where the CTRL / CA PARITY / CRC circuit 330 operates normally to provide parity information), a forced "00" mode, a forced "01" mode, a forced "10" mode, and a forced "11" mode. In forced mode, the value of DIN<1:0>, and therefore the value sent by the PAM4 driver 215, is forced to a constant value that represents one of the PAM levels that the PAM4 driver 215 is capable of sending.

[0033] Figure 4 illustrates a flow diagram 400 of a process for training a PAM4 receiver according to some embodiments. Figure 5 illustrates an "eye" diagram 500 illustrating various signaling levels that may be employed with the process of Figure 4. With reference to both Figures 4 and 5, the process illustrated in flow diagram 400 is suitable for use with various GDDR PHY circuits, such as those shown in Figures 2 and 3, to implement a simplified training process for a PAM4 receiver, such as PAM4 receiver 216, that is trained to receive signals from a DRAM or other volatile memory.

[0034] Generally, this process has the advantage of reducing the complexity of ERR pin training, e.g., training performed during system boot or reset of the DRAM PHY. Ideally, a system should avoid training the ERR pin altogether, but such an approach is often impractical due to process, voltage, and temperature variations associated with the driver and receiver circuits of the PHY. The illustrated process has the advantage of providing a low-cost training method that is simple to implement and operates quickly, as compared to a typical PAM4 receiver training process. The illustrated process generally employs a DC level driven by the DRAM device on the ERR pin to train the host ERR receiver reference voltage (VREF) level.

[0035] The process begins with training the receiver for the ERR pin at block 402. In this example, as shown, a PAM4 receiver is employed, however, a similar process may be used with other types of PAM receivers, such as, for example, a PAM6 or PAM8 receiver.

[0036] In block 404, a receiver control circuit, such as training control circuit 310 (FIG. 3), commands the DRAM via the data bus to place the selected PAM4 driver into a mode with a specified steady-state output level. In this embodiment, an MRS command, such as a forced "01", is stored in the error mode register 320 to command the CTRL / CA PARITY / CRC circuit 330 to set the specified output level. In other embodiments, other methods of achieving the specified DC output level can be used, such as, for example, sending a training pattern of bits with a repeating value for the desired steady-state DC output level. Referring to block 404, the MRS command may be issued before, after, or any time during the command address (CA) training on the PHY. During this training time, a host ERR exit is preferably applied to ensure proper reference signal levels.

[0037] The process then waits for a predetermined period of time in block 406. After this waiting period, the DRAM is assumed to have driven the ERR pin to a specified DC state with the commanded DC output level driven by a PAM4 driver, such as PAM4 driver 215. The DC output levels of the PAM4 driver are shown in FIG. 5 as labeled "00", "01", "10", and "11".

[0038] In block 408, the process then sweeps the reference voltage of each one of the reference voltage circuits providing the voltages VR_L1, VR_L2, VR_L3 by continuously varying the voltage across a voltage range and comparing the reference voltage to the voltage received from the selected PAM4 driver after each variation to determine the respective voltage level received from the selected PAM4 driver. In this embodiment, as shown in block 410, determining the particular voltage level received is performed by each one of the multiple sub-receiver circuits of the PAM4 receiver, e.g., sub-receivers 304, 306, 308. When the reference voltage passes the voltage received at the selected one of the sub-receivers, the sub-receiver changes the received value from low to high (if the reference voltage is swept upward) or from high to low (if the reference voltage is swept downward). This detected crossover point is stored in block 414 for appropriately setting all the reference voltages VR_L1, VR_L2, VR_L3.

[0039] As shown in block 412, the process is repeated for all PAM levels, although in other embodiments it need not be repeated for all levels. For example, block 412 may instead repeat the process for a designated subset of the PAM levels. For example, levels "01", "10", and "11" may be trained by repeating blocks 404-410, with level "00" being assumed to be 0 volts.

[0040] At block 414, reference voltage levels for continued operation of the PAM4 receiver are set based on the crossover points detected at block 410. Preferably, the reference voltages are selected as the average of the two surrounding crossover points, although other selection methods may be used. These settings establish a "window" for the range of voltage levels within which a particular value will be recognized as received by the PAM4 receiver.

[0041] In an exemplary scenario in which the PAM4 receiver 216 (FIG. 3) is trained, a force "11" command is loaded into the error mode register 320, causing the PAM4 driver 215 to output a "11" level, which is the highest level shown in FIG. 5. The reference voltage VR_L3 is then changed at a specified pace starting at a specified level, such as the exemplary level shown in FIG. 5, by increasing the voltage level of VR_L3 until the sub-receiver 304 changes from outputting a "1" to outputting a "0," indicating that VR_L3 has crossed the actual voltage level received at the ERR terminal. A force "10" command is then loaded, causing the PAM4 driver 215 to output a "10" level, and VR_L2 is similarly swept from the specified value until the sub-receiver 306 detects a crossover. An example of sweeping the voltage level of the reference voltage VR_L2 is shown in FIG. 5, which shows six different voltage levels 501, 502, 503, 504, 505, 506 at which VR_L2 is changed. Although the voltage levels 501-506 are shown spread over time during the period of the eye, this representation is for ease of understanding the voltage levels, and the actual timing of the reference voltage change and measurement will vary from embodiment to embodiment. For example, in one embodiment, the measurement is made at the same point of the eye. In another embodiment, the measurement is made as fast as the reference voltage is changed and the output of the sub-receiver circuit is recognized. At each voltage level, the process compares the reference voltage to the voltage received through the PAM4 driver to determine whether it is higher or lower. In this embodiment, the comparison is performed with the respective sub-receiver circuit (e.g., 306 in FIG. 3) for the reference voltage. If the sub-receiver circuit output transitions from LOW to HIGH, the process has detected that the reference voltage being swept has become higher than the received voltage. Although six voltage levels are shown, typically many more voltage levels spaced at suitable voltage intervals are used to detect received voltage levels with a resolution suitable for use by the receiver. For example, the voltage level may increase with each change by a selected voltage increment that is greater than the minimum increment provided by the reference voltage generating circuit or the minimum increment available.

[0042] A force "01" command is then loaded, causing the PAM4 driver 215 to output a "01" level, and VR_L1 is swept upward until the sub-receiver 308 detects a crossover. Finally, a force "00" command may also be included, in which case VR_L1 is swept downward until a crossover is detected. In the case of a downward sweep, the crossover point is detected by the output of the respective sub-receiver circuit transitioning from HIGH to LOW, indicating that the reference voltage being swept has become lower than the received voltage. It may be appreciated that for the "01" and "10" levels, a downward sweep of the reference voltage above a specified level may be used, rather than an upward sweep of the reference voltage below the specified level.

[0043] As shown in block 416, after the reference levels are set, another optional step in the training is to enable a mode register setting in the DRAM device to set the ERR pin to toggle mode to perform phase training. In such a process, the center of the "eye" as shown in FIG. 5 is adjusted by adjusting the phase delay or phase lead at which the PAM4 receiver values ​​are measured until an optimal value is received. In block 416, the ERR pin can be configured to periodically cycle through all or a subset of the four levels at the expected toggle frequency of the ERR pin in normal operation to phase train each opening in the eye diagram. In some embodiments, such phase training is useful under certain operating modes.

[0044] As shown in block 418, another optional step is to provide the reference voltage levels determined in block 414 for use by other PAM4 receivers in the PHY circuitry based on the efficient level training process performed in blocks 404-414. For example, block 418 may include providing the determined reference voltage levels for VR_L1, VR_L2, VR_L3 to a training process for the DQ receiver (e.g., 241 in FIG. 2) for purposes such as DQ VREF level adaptation, or to provide initial VREF level settings for use in training or operating the DQ receiver.

[0045] An integrated circuit or integrated circuits including the reference voltage generating circuit described herein, or any portion thereof, may be described or represented by a computer-accessible data structure in the form of a database or other data structure that may be read and used by a program to directly or indirectly manufacture the integrated circuit. For example, the data structure may be a behavioral level description or a register-transfer level (RTL) description of the hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool that may synthesize the description to generate a netlist that includes a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware that includes the integrated circuit. The netlist may then be placed and routed to generate a data set that describes the geometric shapes to be applied to a mask. The mask may then be used in various semiconductor manufacturing steps to manufacture the integrated circuit. Alternatively, the database on the computer-accessible storage medium may be a netlist (with or without a synthesis library) or a data set, or Graphic Data System (GDS) II data, if desired.

[0046] Although specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, various PAM4 driver designs may be used with different numbers of PAM levels. Furthermore, various methods of instructing the PAM4 driver to transmit a desired steady state value for an efficient training process may be used. The disclosed technology is applicable to a wide variety of integrated circuits that use high speed data transmission. In one particular example, one integrated circuit may be a data processor, a system on chip (SOC) or a graphics processing unit (GPU), and the other integrated circuit is a DDR or GDDR SDRAM, although the technology described herein may be used with many other types of integrated circuits. Also, the transmission medium may vary between embodiments depending on the physical structure of the memory bus and may include printed circuit board traces, bond wires, through-silicon vias (TSVs), etc.

[0047] It is therefore intended that the appended claims cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. 1. A method for training a receiver, comprising: instructing a volatile memory via a data bus to place selected pulse amplitude modulation (PAM) drivers operating at at least three PAM levels into a mode having a specified steady-state output level; while the selected PAM driver is in a mode having the specified steady-state output level, sweeping, in a receiver circuit coupled to the selected PAM driver, respective reference voltages associated with the specified steady-state output level over a voltage range, and comparing the respective reference voltages to voltages received from the PAM driver to determine respective voltage levels received from the PAM driver. method.

2. instructing the selected PAM driver to toggle at an expected operating rate through either (i) all of its output levels and (ii) a subset of its output levels; performing phase training of the receiver circuit while the selected PAM driver is toggling.

10. The method of claim 1.

3. instructing the volatile memory via a data bus to place the selected PAM driver into a mode having a second specified steady-state output level; while the selected PAM driver is in a mode having the second designated steady-state output level, sweeping, in a receiver circuit coupled to the selected PAM driver, a second respective reference voltage associated with the second designated steady-state output level over a voltage range, and comparing the second respective reference voltage to a voltage received from the PAM driver to determine a second respective voltage level received from the PAM driver.

10. The method of claim 1.

4. setting initial levels for two reference voltages associated with an additional PAM receiver coupled to the volatile memory based on the respective voltage levels and the second respective voltage levels. The method of claim 3.

5. the selected PAM driver is connected to a designated output terminal of the volatile memory that provides command and address (CA) parity and write cyclic redundancy check (CRC) information to a host; instructing the volatile memory via the data bus is performed by issuing a mode register set (MRS) command to the volatile memory; The method of claim 4.

6. the additional PAM receiver is a receiver for a data input / output (DQ) terminal of the data bus; The method of claim 5.

7. Sweeping the respective reference voltages associated with the specified steady-state output levels over a voltage range includes selecting one of at least two sub-receiver circuits and sweeping a reference voltage coupled to the selected one of the at least two sub-receiver circuits.

10. The method of claim 1.

8. A physical layer (PHY) circuit for coupling to a volatile memory via a data bus, comprising: a pulse amplitude modulation (PAM) receiver operating at at least three PAM levels; a receiver control circuit; The PAM receiver comprises: A decoder circuit; at least two sub-receiver circuits, each including an output coupled to said decoder circuit, a first input coupled to a data bus terminal, and a second input coupled to a respective reference voltage circuit; The reception control circuit includes: and operable to instruct the volatile memory via the data bus to place a selected PAM driver into a mode having a specified steady-state output level, and while the selected PAM driver is in the mode having the specified steady-state output level, to sweep a reference voltage of each one of the sub-receiver circuits across a voltage range and compare the reference voltage with a voltage received from the selected PAM driver to determine a respective voltage level received from the selected PAM driver. PHY circuit.

9. The receiver control circuit includes: instructing the selected PAM driver to toggle at an expected operating rate through either (i) all of its output levels and (ii) a subset of its output levels; Operable to perform phase training of the PAM receiver while the selected PAM driver is toggling. The PHY circuit of claim 8.

10. The receiver control circuit includes: instructing the volatile memory via a data bus to place the selected PAM driver into a mode having a second specified steady-state output level; and operable, while the selected PAM driver is in a mode having the second designated steady-state output level, to sweep a second respective reference voltage associated with the second designated steady-state output level across a voltage range and compare the second respective reference voltage with a voltage received from the PAM driver to determine a second respective voltage level received from the PAM driver. The PHY circuit of claim 8.

11. The receiver control circuit includes: and operable to set initial levels for two reference voltages associated with an additional PAM receiver coupled to the volatile memory based on the respective voltage levels and the second respective voltage levels. The PHY circuit of claim 10.

12. the selected PAM driver is connected to a designated output terminal of the volatile memory that provides command and address (CA) parity and write cyclic redundancy check (CRC) information to a host; instructing the volatile memory via the data bus is performed by issuing a mode register set (MRS) command to the volatile memory; The PHY circuit of claim 11.

13. the additional PAM receiver is a receiver for a data input / output (DQ) terminal of the data bus; 13. The PHY circuit of claim 12.

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