Apparatus and method for successive cancellation list decoding of polar code using power gating
By employing power gating to control current supply to a subset of continuous cancellation list decoding units, the method addresses the increased computation and power consumption of SCL decoding, achieving reduced power usage and improved error correction performance.
Patent Information
- Application Number
- JP2023214889
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-06-20
- Filing Date
- 2023-12-20
- Publication Date
- 2025-01-08
- Estimated Expiration
- 2043-12-20
AI Technical Summary
Polar codes' error correction performance is improved by the continuous cancellation list (SCL) decoding method, but it requires approximately L times the amount of calculation and power consumption compared to the conventional SC decoding method.
A power gating circuit is used to control current supply to a subset of continuous cancellation list decoding units, reducing the computation and power consumption while maintaining error correction performance.
The method reduces computation and power consumption by L times, while maintaining or improving error correction performance compared to the conventional SCL decoding method.
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Figure 2025001619000001_ABST
Abstract
Description
[Technical field]
[0001] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a successive cancellation list decoding technique for polar codes using power gating. [Background technology]
[0002] Polar Codes are the first error-correcting codes that can achieve channel capacity in discrete non-memory channels. Polar Codes use the Successive Cancellation (SC) algorithm in their basic decoding scheme, but they have drawbacks. They exhibit poor error correction performance compared to Low-Density Parity-Check (LDPC) and Turbo codes.
[0003] In order to improve such a drawback, several decoding methods have been proposed to improve error correction performance based on successive cancellation algorithms. One of them is the successive cancellation list (SC List, SCL) decoding method. The SCL decoding method basically proceeds in the same way as the SC decoding method, but it differs in that there are paths whose number is a power of 2 (L=2l, l=1, 2, 3, ...). The number of these paths is the list size of the SCL decoding. In the SCL decoding method, each path performs a separate SC decoding, and the bits decoded in each path are stored to obtain the final codeword decoded in that path. In the SCL decoding method, each path is copied into two paths every time one information bit is decoded. That is, as the decoding proceeds, the number of L paths increases to 2L, and the most reliable L paths are selected again through a path selection process. When all bits are decoded, a cyclic redundancy check (CRC) is performed on each path result, and the codeword of the path that passed the CRC is output as the final decoded result. When such an SCL decoding method is used, the poor error correction performance of the SC decoding method can be improved.
[0004] That is, the SCL decoding method can decode polar codes with improved error correction performance. However, the SCL decoding method has the disadvantage that it requires about L times (the size of the list) more computational complexity than the conventional SC decoding method. [Prior art documents] [Patent documents]
[0005] Korean Patent Registration No. 10-1951663 (2019.02.19.) Summary of the Invention [Problem to be solved by the invention]
[0006] SUMMARY OF THE PRESENT EMBODIMENTS An embodiment of the present invention is directed to providing an apparatus and method for successive cancellation list decoding of polar codes using power gating. [Means for solving the problem]
[0007] According to an exemplary embodiment of the present invention, a device for decoding successive cancellation list of polar codes using power gating is provided, the device including a plurality of successive cancellation list decoders for receiving polar encoded codewords and decoding the codewords using a successive cancellation list technique, and a power gating circuit unit connected to a predetermined number of successive cancellation list decoders among the plurality of successive cancellation list decoders and controlling current supply.
[0008] The power gating circuit unit may further include a signal generating unit that generates a power signal according to a preset condition, and a current control unit that increases or decreases a gate voltage of a sleep transistor according to the generated power signal and controls current supply to the preset number of successive cancellation list decoding units.
[0009] The signal generator may generate a first power signal to cut off current supply to the preset number of successive cancellation list decoders during a decoding process when the plurality of successive cancellation list decoders receive the codeword.
[0010] The signal generator may generate a second power signal to cut off current supply to the predetermined number of successive cancellation list decoders during a predetermined interval during a decoding process when the plurality of successive cancellation list decoders receive the codeword.
[0011] The signal generation unit may, when the plurality of successive cancellation list decoding units receive the codeword, extract a Rate-1 node from the codeword, and generate the second power signal to cut off current supply to the predetermined number of successive cancellation list decoding units in a section corresponding to the Rate-1 node during a decoding process. Effect of the Invention
[0012] According to an embodiment of the present invention, by using power gating in a SCL (Successive Cancellation List) decoding method, it is possible to improve error correction performance while reducing the amount of calculation and power consumption of the SCL decoding method, which is L times larger than that of the existing SC decoding method. [Brief description of the drawings]
[0013] [Figure 1] 1 is a diagram for explaining a successive cancellation list encoding-decoding device for polar codes according to an embodiment of the present invention. [Diagram 2] 1 is a diagram illustrating a successive cancellation list decoding device for polar codes using power gating according to an embodiment of the present invention. [Diagram 3] 1 is a diagram illustrating an operation method of a successive cancellation list decoding device for polar codes using power gating according to an embodiment of the present invention. [Figure 4]11 is a diagram illustrating an operation method of a successive cancellation list decoding device for polar codes using power gating according to another embodiment of the present invention. [Diagram 5] 1 is a graph comparing error correction performance by polar code decoding devices. [Figure 6] FIG. 13 is a diagram showing a reduction rate of the amount of calculation of a successive cancellation list decoding device for polar codes using power gating according to the disclosed embodiment. [Figure 7] FIG. 1 is a block diagram illustrating and explaining a computing environment including a computing device according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0014] Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. The following detailed description is provided to facilitate a comprehensive understanding of the method, device and / or system described herein. However, this is for illustrative purposes only, and the present invention is not limited thereto.
[0015] In describing the embodiments of the present invention, if it is determined that a detailed description of the known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. The terms described below are defined in consideration of the functions in the present invention, and may vary depending on the intention or practice of the user or operator. Therefore, the definitions should be based on the overall contents of this specification. The terms used in the detailed description are merely for describing the embodiments of the present invention and should not be limiting in any way. Unless clearly used otherwise, expressions in the singular form include the plural form. In this description, expressions such as "including" or "comprising" are intended to indicate certain characteristics, numbers, steps, operations, elements, parts or combinations thereof, and should not be interpreted as excluding the presence or possibility of one or more other characteristics, numbers, steps, operations, elements, parts or combinations thereof other than those described.
[0016] Meanwhile, embodiments of the present invention may include a program for executing the methods described herein on a computer, and a computer-readable recording medium containing the program. The computer-readable recording medium may include program instructions, local data files, local data structures, and the like, alone or in combination. The medium may be one specially designed and constructed for the present invention, or one commonly available in the field of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical recording media such as CD-ROMs and DVDs, and hardware devices specially configured to store and execute program instructions, such as ROMs, RAMs, and flash memories. Examples of the program instructions may include not only machine language code, such as that produced by a compiler, but also high-level language code that can be executed by a computer using an interpreter, etc.
[0017] FIG. 1 is a diagram for explaining a successive cancellation list encoding-decoding device for polar codes according to an embodiment of the present invention.
[0018] Referring to FIG. 1, the present invention can be described by taking as an example a polar encoder 1 and a successive cancellation list decoder 2 used in a communication system. The polar encoder 1 can encode data (information bits) to be transmitted through a polar encoder 5, and transmit the encoded data (codewords) through a channel 2 to a successive cancellation list decoder 3. Here, the polar code is a code that achieves channel capacity by using a channel polarization phenomenon that occurs when a plurality of channels are combined and then appropriately separated. In addition, the successive cancellation list decoder 3 can decode the codewords received from the polar encoder 1 through the channel 2 through a successive cancellation list decoder 6 based on a successive cancellation list (SCL) decoding technique, and estimate and output the data encoded by the polar encoder 1. At this time, a CRC code is generated through a CRC encoder 4 of the polar encoder 1, and the CRC code of the result generated through a CRC decoder 7 of the successive cancellation list decoder 3 is compared with the CRC code generated by the CRC encoder 4 to check whether an error occurs in the data. It is checked whether an error has occurred, and if no error has occurred, the data is output.
[0019] Such a consecutive cancellation list decoding device 2 is made up of L (list size) consecutive cancellation list decoding units 6 that operate simultaneously in parallel. In this case, the consecutive cancellation list decoding device 2 made up of L consecutive cancellation list decoding units 6 requires an area and amount of calculations that are approximately L times larger than those of a conventional consecutive cancellation decoding device. In particular, the amount of calculations is an issue that is directly linked to power consumption, and the device consumes approximately L times more power than the consecutive cancellation decoding device.
[0020] In the present invention, a method can be provided that can reduce the amount of calculation and power consumption of the polar code successive cancellation list decoding device 100 by controlling the power supply to some of the L successive cancellation list decoding units 200 using power gating.
[0021] FIG. 2 is a diagram for explaining a successive cancellation list decoding device for polar codes using power gating according to an embodiment of the present invention.
[0022] Referring to FIG. 2, a successive cancellation list decoding apparatus 100 for polar codes using power gating according to an embodiment may include a successive cancellation list decoding unit 200 and a power gating circuit unit 300.
[0023] In the following embodiments, each component may have different functions and capabilities in addition to those described below, and may include additional components in addition to those not described below.
[0024] Furthermore, in the following embodiments, the successive cancellation list decoding unit 200 and the power gating circuit unit 300 may be implemented using one or more physically separate devices, or may be implemented by one or more processors, or a combination of one or more processors and software, and may not be clearly separated in specific operations, unlike the illustrated examples.
[0025] The successive cancellation list decoding unit 200 can decode the received codeword using the successive cancellation list scheme.
[0026] On the other hand, the successive cancellation list method used in the present invention is already a well-known technology, so a detailed explanation will be omitted. However, to briefly explain, the successive cancellation list decoding device is a decoding method proposed by Tal and Vardy in 2011, and is a decoding method that improves the decoding performance of conventional polar code successive cancellation (SC) decoding.
[0027] The power gating circuit unit 300 can control the current supply to the successive cancellation list decoding unit 200. The power gating circuit unit 300 can include a signal generating unit 310, a sleep transistor 320, and a current control unit 330. The power gating circuit unit 310 can control the current supply to the successive cancellation list decoding unit 200 by the current control unit 330 increasing or decreasing the gate voltage of the sleep transistor 320 according to a power signal generated by the signal generating unit 310. For example, since the sleep transistor 320 in an active mode is in a linear region, the gate VSS has a value close to VSS. Meanwhile, since the sleep transistor 320 in a sleep mode is turned off, the gate VSS has a value close to VDD. At this time, the power gating circuit unit 300 can be connected to a preset number of successive cancellation list decoding units 200. For example, the power gating circuit unit 320 may be connected to four of the eight successive cancellation list decoding units 200 .
[0028] The signal generator 310 may generate a power signal according to preset conditions, which will be described in detail with reference to FIGS.
[0029] FIG. 3 is a diagram for explaining an operation method of the successive cancellation list decoding apparatus for polar codes using power gating according to an embodiment of the present invention.
[0030] 3, the power gating-based successive cancellation list decoding apparatus 100 for polar codes according to an embodiment can cut off current supply to a preset number of decoders during decoding when a codeword having a total code length of 8 bits is received. Here, the codeword can be composed of an information bit and a frozen bit. In this case, the signal generator 310 can generate a power signal to cut off current supply to a preset number of successive cancellation list decoders 200 when the successive cancellation list decoders 200 receive a codeword. For example, by cutting off current supply to M (e.g., 2) successive cancellation list decoders 200-3 and 200-4 among L (e.g., 4) successive cancellation list decoders 200-1, 200-2, 200-3 and 200-4 while decoding is in progress, the amount of calculation and power consumption can be reduced in proportion to M / L. Here, L may represent the number of all successive cancellation list decoding units 200, and M may represent the number of successive cancellation list decoding units 200 to which the power gating circuit is applied.
[0031] That is, the successive cancellation list decoding device 100 for polar codes using power gating according to one embodiment can select an error correction performance priority mode or a power efficiency priority mode by applying a power gating circuit to a certain number of successive cancellation list decoding units 200.
[0032] FIG. 4 is a diagram illustrating an operation method of a successive cancellation list decoding apparatus for polar codes using power gating according to another embodiment of the present invention.
[0033] Referring to FIG. 4, when a codeword having a total code length of 8 bits is received, the apparatus 100 for decoding successive cancellation list of polar code using power gating according to an embodiment can cut off current supply to a preset number of successive cancellation list decoders 200 in a preset interval during the progress of decoding. Here, the codeword may be composed of information bits and frozen bits. Also, the preset interval may be a decoding interval of a Rate-1 node. The Rate-1 node may mean a node consisting of information bits that are continuous for a certain length or more. Here, the interval including the 7th and 8th bits, the interval including the 11th and 12th bits, and the interval including the 13th to 16th bits may be the Rate-1 node.
[0034] In this case, when the consecutive cancellation list decoder 200 receives a codeword, the signal generator 310 may extract a Rate-1 node and generate a power signal to cut off current supply to a preset number of consecutive cancellation list decoders 200 in an interval corresponding to the Rate-1 node during the decoding process. For example, among the L consecutive cancellation list decoders 200-1, 200-2, 200-3, 200-4, current supply to M consecutive cancellation list decoders 200-3, 200-4 may be cut off in an interval corresponding to the Rate-1 node during the progress of decoding.
[0035] In other words, since the decoding path splitting and pruning in the SCL decoding process is performed on information bits, the amount of calculation and power consumption can be reduced by cutting off power to a preset number of consecutive cancellation list decoding units 200 at node Rate-1, which consists of consecutive information bits of a certain length or more.
[0036] FIG. 5 is a graph comparing the error correction performance of polar code decoding devices, and FIG. 6 is a diagram showing the reduction rate of the amount of calculation of a polar code successive cancellation list decoding device using power gating according to the disclosed embodiment.
[0037] 5 and 6, when a polar code is decoded using the successive cancellation list decoding device 100 for a polar code using power gating according to an embodiment of the present invention, the error correction performance is deteriorated compared to the same list size, but the amount of calculations can be reduced compared to the same list size, thereby reducing power consumption. For example, it can be confirmed that SCL 8-4 has a deteriorated error correction performance compared to SCL 8, but has an improved error correction performance compared to SCL 4, and it can be confirmed that SCL 8-4 has a 19% reduction in the amount of calculations compared to SCL 8. Here, SCL 8-4 may mean that power gating is applied to four of the eight successive cancellation list decoding units 200, and SCL 4-2 may mean that power gating is applied to two of the four successive cancellation list decoding units 200.
[0038] In other words, when only a portion of the successive cancellation list decoding units 200 are used in the polar code successive cancellation list decoding device 100, there is a degradation in error correction performance compared to when all of the successive cancellation list decoding units 200 are operated, but the effect of a reduction in the amount of calculations and therefore a reduction in power consumption can be confirmed.
[0039] FIG. 7 is a block diagram illustrating an exemplary computing environment 10 including a computing device 12 according to one embodiment.
[0040] In the illustrated embodiment, each component may have different functions and capabilities in addition to those described below and may include additional components in addition to those not described below.
[0041] The illustrated computing environment 10 includes a computing device 12. In one embodiment, the computing device 12 may be one or more components included in an apparatus 100 for successive cancellation list decoding of polar codes with power gating.
[0042] Computing device 12 includes at least one processor 14, a computer-readable storage medium 16, and a communication bus 18. Processor 14 can cause computing device 12 to operate in accordance with the exemplary embodiments described above. For example, processor 14 can execute one or more programs stored on computer-readable storage medium 16. The one or more programs may include one or more computer-executable instructions that, when executed by processor 14, can be configured to cause computing device 12 to perform operations in accordance with the exemplary embodiments.
[0043] The computer readable storage medium 16 is configured to store computer executable instructions or program code, program data, and / or other suitable forms of information. The program 20 stored on the computer readable storage medium 16 includes a set of instructions executable by the processor 14. In one embodiment, the computer readable storage medium 16 may be memory (volatile memory, such as random access memory, non-volatile memory, or a suitable combination thereof), one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other forms of storage media capable of being accessed by the computing device 12 and storing desired information, or a suitable combination thereof.
[0044] The communications bus 18 interconnects the processor 14 , the computer-readable storage medium 16 , and various other components of the computing device 12 .
[0045] The computing device 12 may also include one or more input / output interfaces 22 and one or more network communication interfaces 26 that provide an interface for one or more input / output devices 24. The input / output interfaces 22 and the network communication interfaces 26 are connected to the communication bus 18. The input / output devices 24 may be connected to other components of the computing device 12 via the input / output interfaces 22. Exemplary input / output devices 24 may include input devices such as a pointing device (such as a mouse or trackpad), a keyboard, a touch input device (such as a touchpad or touchscreen), a voice or sound input device, various types of sensor devices and / or photographic devices, and / or output devices such as a display device, a printer, a speaker, and / or a network card. The exemplary input / output devices 24 may be included within the computing device 12 as a component constituting the computing device 12, or may be connected to the computing device 12 as a separate device distinct from the computing device 12.
[0046] Although the representative embodiment of the present invention has been specifically described above, those having ordinary skill in the art to which the present invention pertains will understand that various modifications of the above-described embodiment are possible without departing from the scope of the present invention. Therefore, the scope of the rights of the present invention should not be limited to the described embodiment, but should be determined not only by the claims below, but also by equivalents to the claims. [Explanation of symbols]
[0047] 100: A successive cancellation list decoder for polar codes using power gating 200: Successive cancellation list decoding section 300: Power gating circuit section 310: Signal generation unit 320: Sleep transistor 330: Current control unit
Claims
1. a plurality of successive cancellation list decoders for receiving polar encoded codewords and decoding the codewords using a successive cancellation list technique; a power gating circuit unit connected to a preset number of successive cancellation list decoding units among the plurality of successive cancellation list decoding units to control current supply.
2. The power gating circuit unit includes: A signal generating unit that generates a power signal according to preset conditions; 2. The apparatus for decoding successive cancellation lists of polar codes using power gating according to claim 1, further comprising: a current control unit that increases or decreases a gate voltage of a sleep transistor in response to the generated power signal, thereby controlling current supply to the preset number of successive cancellation list decoding units.
3. The signal generating unit 3. The device for decoding successive cancellation list of polar codes using power gating according to claim 2, wherein when the plurality of successive cancellation list decoding units receive the codeword, a first power signal is generated to cut off current supply to the predetermined number of successive cancellation list decoding units during the decoding process.
4. The signal generating unit 3. The device for decoding successive cancellation list of polar codes using power gating according to claim 2, wherein when the plurality of successive cancellation list decoding units receive the codeword, a second power signal is generated to cut off current supply to the predetermined number of successive cancellation list decoding units during a predetermined interval during a decoding process.
5. The signal generating unit 5. The apparatus for decoding successive cancellation list of polar codes using power gating according to claim 4, wherein, when the plurality of successive cancellation list decoding units receive the codeword, a Rate-1 node is extracted from the codeword, and the second power signal is generated so as to cut off current supply to the preset number of successive cancellation list decoding units in a section corresponding to the Rate-1 node during the decoding process.
6. one or more processors; and 1. A method for successive cancellation list decoding of polar codes with power gating executed on a computing device having a memory storing one or more programs executed by the one or more processors, comprising: generating a power signal according to a preset condition; and increasing or decreasing the gate voltage of a sleep transistor in response to the generated power signal to control current supply to a plurality of successive cancellation list decoding units.
7. The step of generating a power signal comprises:
7. The method for decoding successive cancellation list of polar codes using power gating according to claim 6, further comprising generating a first power signal to cut off current supply to a preset number of successive cancellation list decoding units among the plurality of successive cancellation list decoding units during a decoding process when the plurality of successive cancellation list decoding units receive a codeword.
8. The step of generating a power signal comprises:
7. The method for decoding successive cancellation list of polar codes using power gating according to claim 6, further comprising generating a second power signal to cut off current supply to a predetermined number of successive cancellation list decoding units among the plurality of successive cancellation list decoding units during a predetermined interval during a decoding process when the plurality of successive cancellation list decoding units receive a codeword.
9. The step of generating a power signal comprises: When the plurality of successive cancellation list decoding units receive the codeword, extracting a Rate-1 node from the codeword; The method of claim 8, further comprising: generating the second power signal to cut off current supply to the predetermined number of successive cancellation list decoding units in a section corresponding to the Rate-1 node during the decoding process.
Citation Information
Patent Citations
Scrambling sequence design for multi-mode block discrimination on DCI blind detection
CN110463093A
Memory Management and Path Sorting Techniques in Polar Code Successive Elimination List Decoders
JP2018535608A
Dynamic power adjusting device for viterbi decoder
US20070277081A1
Adaptive-SCL Polar Decoder
US20200295786A1
Polar encoding and polar decoding systems and methods
US20210306005A1