Direct digital synthesizer

Abstract

To solve the problem in the conventional direct digital synthesizer in which a clock of a power of 2 is required, a precise frequency is not generated if not the case, and it is difficult that a digit of a decimal point or smaller is increased.SOLUTION: In addition to an accumulator that adds an accumulator output and frequency setting data, in the case where an accumulator output exceeds a predetermined value, the predetermined value is subtracted, and a clock of a power of 2 is not required. Also, by setting each of quotients and remainders obtained by dividing the frequency setting data with the predetermined value to a high-order digit and a low-order digit, a frequency setting range is increased. Also, by separately setting an accumulator of which a digit of a decimal point or smaller, a setting of the digit of the decimal point or smaller can be easily made.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a direct digital synthesizer (hereinafter abbreviated as "DDS") that can obtain a set frequency with high accuracy. [Background technology]

[0002] DDS, which can obtain any frequency from a reference clock, is widely used in various fields. Conventional DDS has a problem that it is not possible to obtain a precise frequency when using a crystal oscillator, which is easily available, as the reference clock, and therefore has a problem of poor accuracy. Therefore, the current situation is that a high-resolution DDS is used to set a frequency as close as possible to the target frequency.

[0003] Some systems use a crystal oscillator with a frequency that is a power of two to obtain a precise frequency as the reference clock, but these systems require a custom-made crystal oscillator or are limited in the frequency range that can be set. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 9-83250 [Non-patent literature]

[0005] [Non-Patent Document 1] ANALOG DEVICES AD9833 Datasheet Date of issue unknown Summary of the Invention [Problem to be solved by the invention]

[0006] The problem to be solved is that when using a readily available crystal oscillator as the reference clock, it is not possible to generate a highly accurate frequency. For example, the conventional DDS AD9833 has a 28-bit accumulator, and when using a 25MHz clock, the resolution is 25000000 / 2 28 =0.093, so we get a high resolution of 0.093Hz, but it is not exactly 0.1Hz. To get the resolution to exactly 0.1Hz, we need to multiply it by 0.1×2. 28 =26843545.6, so a clock of 26.8435456Hz is required, which is not widely available on the market and is difficult to obtain for small-scale production.

[0007] An object of the present invention is to provide a DDS that can generate precise and accurate frequencies even when using a readily available crystal oscillator as the reference clock.

[0008] Another object of the present invention is to provide a DDS that can easily generate frequencies that include fractions below the decimal point. [Means for solving the problem]

[0009] In the present invention, the clock frequency / set frequency unit is divided by a power of 2 to set a predetermined value, and when the updated value of the accumulator exceeds the predetermined value, the accumulator value is updated by subtracting this value, thereby making it easier and more accurate to set the target frequency. (The power includes 0.)

[0010] In addition, by allowing the update of the upper accumulator when the value obtained by subtracting this value is selected, the quotient and remainder obtained by dividing the target frequency setting data by the value obtained by dividing the clock frequency / setting frequency unit by a power of 2 are set in the upper and lower digits as the second frequency setting data and the first frequency setting data, respectively, thereby making it possible to support high frequencies.

[0011] In addition, when the target frequency has a decimal point, if the lower accumulator has a decimal point, for example, 10 is subtracted, if it has two decimal places, 100 is subtracted, and if it has three decimal places, 1000 is subtracted. By allowing the higher accumulator to be updated, the frequency after the decimal point can be easily set. Effect of the Invention

[0012] The DDS of the present invention has the advantages that the target frequency can be easily set, the frequency is precise, and the decimal point can be easily set, so that it is possible to obtain a frequency with the same accuracy as the reference clock. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a block diagram showing a first embodiment of a DDS according to the present invention. (Embodiment 1) [Diagram 2] FIG. 2 is a block diagram showing a second embodiment of the DDS of the present invention. (Embodiment 2) [Diagram 3] FIG. 3 is a block diagram showing a third embodiment of the DDS of the present invention. (Embodiment 3) [Figure 4] FIG. 4 is a block diagram showing a fourth embodiment of the DDS of the present invention. (Fourth embodiment) [Diagram 5] FIG. 5 is a block diagram showing a fifth embodiment of the DDS of the present invention. (Embodiment 5) [Figure 6] FIG. 6 is a block diagram showing a sixth embodiment of the DDS of the present invention. (Sixth embodiment) DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The objective of the present invention is to easily set the target frequency and also to easily set the decimal point, and to eliminate the need for a crystal oscillator with a special frequency for the clock, and to enable the clock to be configured using a crystal oscillator that is generally easy to obtain. EXAMPLES

[0015] 1 is a block diagram of a first embodiment of the device of the present invention, in which frequency setting data is set in a register 1, and the output value of an accumulator 2 and the setting value of the register 1 are added by a first arithmetic unit 3. A second arithmetic unit 4 subtracts a predetermined value from the output value of the first arithmetic unit 3, and the outputs of the first arithmetic unit 3 and the second arithmetic unit 4 are input to a selector 5, and if the output of the second arithmetic unit 4 is a negative value, the output of the first arithmetic unit 3 is selected, and if not, the output of the second arithmetic unit 4 is selected and output from the selector 5. The output of the selector 5 is input to an accumulator 2, and the accumulator value is updated to the output value of the selector 5 in synchronization with a clock.

[0016] With this configuration, a pulse having a frequency based on the frequency setting data set in register 1 is output from the most significant bit of accumulator 2. Here, the frequency setting data is data obtained by calculating output frequency / setting unit frequency, and the output frequency is frequency setting data x setting unit frequency.

[0017] For example, if the clock is 16MHz and the predetermined value is 16000000, accumulator 2 will increment by the value set in register 1 for each clock, and if it exceeds 16000000, it will return to the value minus 16000000. As a result, a frequency of register 1's setting value x 1 Hz is output from the most significant bit of accumulator 2, and the setting unit frequency becomes 1 Hz. In this case, the accumulator has a value of 0 to 15999999, so the number of bits needs to be 24. The same applies to the number of bits for register 1. The frequency setting range is 1 to 15999999 Hz.

[0018] If the clock is 16MHz and the specified value is 160000000, a frequency of register 1's setting value x 0.1Hz is output from the most significant bit of accumulator 2, and the setting unit frequency is 0.1Hz. In this case, the accumulator has a value of 0 to 159999999, so 28 bits are required. The same applies to the number of bits of register 1. The frequency setting range is 0.1 to 15999999.9Hz.

[0019] The register referred to here refers to a register that holds a value set from a logic device such as a microcomputer (not shown), or an output port register of a microcomputer. Frequency setting data is set in register 1 from the logic device and this value is supplied to adder 3. An accumulator is a register intended for cumulative addition, and the value is replaced with the addition result in synchronization with the clock by an enable signal. In the first embodiment, it is always in an enabled state, and the value is updated with each clock. EXAMPLES

[0020] 2 is a block diagram of the device according to the second embodiment of the present invention, which is configured to output an analog waveform such as a sine wave by adding an incrementer 6, a ROM 7, and a DAC (digital-to-analog converter) 8 to the device according to the first embodiment. The register 1, the accumulator 2, the first arithmetic unit 3, the second arithmetic unit 4, and the selector 5 operate in the same manner as in the first embodiment.

[0021] If the clock is 16MHz and the set frequency unit is 1Hz, then 16000000 / 1=2 10 × 15625, the incrementer 6 is set to 10 bits, the predetermined value is set to 15625, and the incrementer 6 is enabled so that the value of the incrementer 6 is increased by one when the output value of the fourth calculator becomes positive or 0. The incrementer 6 increases within a 10-bit range, and returns to 0 when it overflows. The monotonically increasing output is input to ROM 7 for converting to a sine wave, etc., and the value converted to a sine wave is input to DAC 8, which outputs a sine wave. The frequency setting range is 1 to 15625 Hz.

[0022] If the clock is 16MHz and the set frequency unit is 10Hz, then 16000000 / 10=2 9×3125, the incrementer 6 is set to 9 bits, the predetermined value is set to 3125, and the incrementer 6 is enabled so that the value of the incrementer 6 increases by one when the output value of the fourth calculator becomes positive or 0. The incrementer 6 increases within a 9-bit range, and returns to 0 when it overflows. The monotonically increasing output is input to ROM 7 for converting to a sine wave, etc., and when the value converted to a sine wave is input to DAC 8, a sine wave is output from the output. The frequency setting range is 10 to 31250 Hz.

[0023] If you want to make the output to ROM7 12 bits, set the frequency unit to 1 / 4Hz, and you get 16000000 / (1 / 4)=2 12 × 15625, and since the incrementer 6 is 12 bits, the output to the ROM 7 can be 12 bits. The predetermined value here is 15625.

[0024] In this way, by setting the frequency unit to 1 / power of 2, the number of output bits to the ROM 7 can be increased according to the power value.

[0025] Of course, the waveform to be converted does not have to be a sine wave; depending on the data in ROM7, a triangular wave, a square wave, or any other waveform can be output.

[0026] An incrementer is a device that increments a value by one in sync with the clock when an enable signal is input. (It is a type of accumulator, but is called an incrementer because the increment value is 1.) EXAMPLES

[0027] FIG. 3 is a block diagram of the device according to the third embodiment of the present invention. In the second embodiment, only a low frequency of 15625 Hz could be set when the set frequency unit is 1 Hz, but this embodiment is improved so that a high frequency can be set. Instead of the incrementer 6, a register 9, a second accumulator 10, and a third calculator 11 are provided, and the high-order data of the frequency setting is set in the second register 9, and the output value of the second accumulator 10 and the set value of the second register 9 are added by the third calculator 11. The output of the third calculator 11 is input to the second accumulator 10, and when the output value of the second calculator 4 becomes a positive or 0 value, the value of the second accumulator 10 is enabled to be updated to the output value of the third calculator 11 in synchronization with the clock as a carry-over of the accumulator 2. The register 1, the accumulator 2, the first calculator 3, the second calculator 4, the selector 5, the ROM 7, and the DAC 8 operate in the same manner as in the second embodiment.

[0028] Here, if the clock is 16 MHz and the set frequency unit is 1 Hz, the frequency setting data is divided by 15625 to find the quotient and remainder, the quotient is set in the second register 9 as the second frequency data, and the remainder is set in the register 1 as the first frequency data, and the predetermined value input to the second calculator 4 is set to 15625. By doing so, the maximum value of the frequency setting range is 1023 x 15625 + 15624 = 15999999 Hz, and frequencies from 1 to 15999999 Hz can be generated. Here, 15625 is 2, which is the power of 2 of 16000000, which is 16 MHz. 10 This is the value divided by .

[0029] Accumulator 10 is 2 10 Since the accumulator 2 completes one revolution in powers of 2, DAC8 output is possible via ROM7 with a 10-bit address, but since the accumulator 2 does not complete one revolution in powers of 2, if the DAC output is performed via the ROM, the waveform will be discontinuous and the target waveform cannot be output. Therefore, if you want to output more bits, you can increase the number of output bits according to the value of the power by setting the frequency unit to 1 / power of 2 as explained in the second embodiment. EXAMPLES

[0030] 4 is a block diagram of the fourth embodiment of the device of the present invention, in which, in the third embodiment, when the set frequency unit is 1 Hz, it was only possible to set the frequency in 1 Hz units, but in this embodiment, it is possible to set the frequency after the decimal point by adding a third register 12, a third accumulator 13, a fourth calculator 14, a fifth calculator 15, and a second selector 16. Also, the register 1, the accumulator 2, the first calculator 3, the second calculator 4, the selector 5, the ROM 7, the DAC 8, the second register 9, the second accumulator 10, and the third calculator 11 operate in the same way as in the third embodiment.

[0031] Here, we will explain a case where three decimal places can be set. Data with three decimal places is set in the third register 12, and is added to the output value of the third accumulator 13 by the fourth arithmetic unit 14, and the output is subtracted by a predetermined value by the fifth arithmetic unit 15. Here, the predetermined value is 1000. In other words, when the output of the fourth arithmetic unit 14 is less than 1000, the output of the fourth arithmetic unit 14 is selected by the second selector 16, and when it is 1000 or more, the output of the fifth arithmetic unit 15 with 1000 subtracted is selected, and the third accumulator 13 is replaced with the selected value in synchronization with the clock. In this case, the third accumulator 13 can have a value from 0 to 999, so 10 bits are required.

[0032] A signal indicating that the output of the fifth arithmetic unit 15 is selected is input to the enable terminal of the accumulator 2, and the value of the accumulator 2 is updated.

[0033] In a DDS configured in this manner, by setting the quotient described in the third embodiment in the second register 9, the remainder in register 1, and the frequency value after the decimal point in the third register 12, it is possible to generate frequencies from 0.001 to 15999999.999 Hz.

[0034] Here, the predetermined value is 10 if the setting is one decimal place, and 100 if it is two decimal places, and the configuration is the same. Even if the number of digits is increased further, the configuration is the same except that the predetermined value and the number of bits required for the third accumulator 13 change. The number of bits required for the third accumulator 13 is 4 bits when the predetermined value is 10, and 7 bits when it is 100. EXAMPLES

[0035] FIG. 5 is a block diagram of a fifth embodiment of the device of the present invention. This is an example of a VF converter that outputs a frequency proportional to an analog value, configured using a DDS of the present invention. An example of a VF converter (voltage-frequency converter) that outputs 25 kHz when the analog value is 1 V and outputs a frequency proportional to the analog value will be described.

[0036] Reference numeral 18 denotes an ADC (analog / digital converter) that converts analog values ​​into digital values, and 17 denotes a logic device such as a microcontroller. The register 1, the accumulator 2, the first arithmetic unit 3, the second arithmetic unit 4, the selector 5, and the incrementer 6 operate in the same manner as in the second embodiment.

[0037] The voltage, which is an analog value, is converted to a digital value by ADC 18 and input into logic unit 17. If this ADC is 10-bit and the reference voltage is 1.023 V, then when the voltage is 1 V, the digital value becomes 1000, and when it is 0.001 V, the digital value becomes 1. When the digital value is 1000, the frequency to be output is 25 kHz, and when the digital value is 1, the frequency to be output is 25 Hz.

[0038] If the clock is 16MHz and the setting unit frequency is 25Hz, then 16000000 / 25=2 9 × 1250, so if the incrementer 6 is 9 bits and the specified value is set to 1250, then when the digital value is 1000, 25 kHz is output, and when it is 1, 25 Hz, a frequency proportional to the digital value is output.Since the digital value is proportional to the analog value, a frequency proportional to the analog value is also output. EXAMPLES

[0039] FIG. 6 is a block diagram of the sixth embodiment of the present invention. In the previous embodiments, the second arithmetic unit subtracts a predetermined value from the first arithmetic unit, which requires calculations to be performed through two arithmetic units within the time of one clock, which poses a problem that the clock frequency cannot be increased too much. This embodiment solves this problem and speeds up the third embodiment.

[0040] The register 1, accumulator 2, first arithmetic unit 3, selector 5, ROM 7, DAC 8, second register 9, second accumulator 10, and third arithmetic unit 11 operate in the same manner as in the third embodiment, but the second arithmetic unit 4 is an adder with an additional subtractor 19, unlike the third embodiment. Also, a D-FF (D flip-flop) 20 is added as a pipeline to increase speed.

[0041] The lower-order data of the frequency setting to be set in the first register 1 is added to the output value of the accumulator 2 by the first arithmetic unit 3, and a value obtained by subtracting a predetermined value by the subtractor 19 is added to the output value of the accumulator 2 by the second arithmetic unit 4. The outputs of the first arithmetic unit 3 and the second arithmetic unit 4 are input to the selector 5, and if the output of the second arithmetic unit 4 is a negative value, the output of the first arithmetic unit 3 is selected, and if not, the output of the second arithmetic unit 4 is selected and output from the selector 5. The output of the selector 5 is input to the accumulator 2, and the accumulator is updated to the output value of the selector 5 in synchronization with the clock. Also, if the output of the second arithmetic unit 4 is negative, D-FF20 is set.

[0042] The output of the third arithmetic unit 11 is input to the second accumulator 10, and enables the value of the second accumulator 10 to be updated to the output value of the third arithmetic unit 11 in synchronization with the clock as a carry-up of the accumulator 2 when D-FF20 is set.

[0043] With this configuration, delays in the first arithmetic unit 3 and the second arithmetic unit 4 are added in the third embodiment, but in this embodiment, no addition is made, resulting in high speed. There is no need to worry about the input value of the subtractor 19, since it does not change with every clock. Here, the second register 9 and the first register 1 are registers that are set and held by a logic device such as a microcomputer, or are microcomputer output port registers, and the subtractor 19 may perform subtraction calculations within the microcomputer and output the subtraction result to an output port register.

[0044] Furthermore, the delay time until the selection of the selector 5 is reduced by using the D-FF 20 as a pipeline, since it is not accumulated with the operation delay of the accumulator 10.

[0045] In the case of the fifth arithmetic unit 15 in the fourth embodiment, the signal line from the output of the fifth arithmetic unit 15 to the accumulator 2 can also be configured in a similar manner to increase the speed.

[0046] In the explanations so far, a crystal oscillator has been used to generate the clock, but it is also possible to input the output of a crystal oscillator of a more readily available frequency into a PLL to obtain a clock of the required frequency. When configuring a DDS with an FPGA, the FPGA usually has a PLL for clock generation; for example, a 10MHz crystal oscillator can be used and multiplied by 64 with the PLL to obtain 640MHz, which can then be divided by 40 to obtain a 16MHz clock. If you want to increase the frequency generated by the DDS, you can divide it by 20 to create a 32MHz clock, or by 10 to create a 64MHz clock. [Industrial Applicability]

[0047] DDS is widely used in radio equipment and frequency generators called function generators. It is very useful to have a DDS that can generate frequencies easily and with high accuracy. It can also easily handle an increase in the number of decimal points. There are many other applications that require variable frequency, and this invention can be applied to them. [Explanation of symbols]

[0048] 1 register (first register) 2 Accumulator (First Accumulator) 3. First arithmetic unit 4. Second arithmetic unit 5 Selector (First Selector) 6 Incrementer 7 ROM 8 DAC 9 Second Register 10 Second Accumulator 11 Third arithmetic unit 12 The third register 13 Third Accumulator 14 The fourth calculator 15 The fifth calculator 16 Second selector 17 Logical Units 18 ADC 19 Subtractor 20 D-FF

Claims

1. A direct digital synthesizer comprising: a first accumulator operated by a clock signal; a first calculator that calculates (the output value of the first accumulator) + (first frequency setting data); a second calculator that obtains a result of calculating (the output value of the first accumulator) + (first frequency setting data) - (a predetermined value); and a first selector that selects either the output of the first calculator or the output of the second calculator depending on the output of the second calculator, wherein the input of the first accumulator is the output of the first selector.

2. 2. The direct digital synthesizer according to claim 1, further comprising an incrementer which increases a value by one when said first selector selects said second arithmetic unit.

3. 2. The direct digital synthesizer according to claim 1, further comprising a second accumulator and a third calculator that calculates (the second accumulator) + (second frequency setting data), and when the first selector selects the output of the second calculator, updating of the second accumulator to the output of the third calculator is enabled.

4. 2. The direct digital synthesizer of claim 1, comprising: a third accumulator operated by a clock signal; a fourth arithmetic unit that calculates (the output value of the third accumulator) + (third frequency setting data); a fifth arithmetic unit that obtains a result of calculating (the output value of the third accumulator) + (third frequency setting data) - (second predetermined value); and a second selector that selects either the output of the fourth arithmetic unit or the output of the fifth arithmetic unit depending on the output of the fifth arithmetic unit, wherein an input of the third accumulator is the output of the second selector, and the first accumulator enables updating when the second selector selects the fifth arithmetic unit.

5. 2. The direct digital synthesizer according to claim 1, wherein the predetermined value is a value obtained by dividing the frequency of the clock signal by a set unit frequency and dividing the value by a power of 2 (the power includes 0).

6. 5. The direct digital synthesizer according to claim 3, wherein the quotient obtained by dividing the frequency of the clock signal by a set unit frequency and then dividing the result by the predetermined value is used as the second frequency setting data, and the remainder is used as the first frequency setting data.

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