Method for determining state of time-bin qubit in quantum cryptography key distribution system using TDC and quantum cryptography key distribution system using the same

Abstract

To provide a new structure for determining states of time-bin qubits by introducing a time-to-digital converter (TDC) in a quantum cryptography key distribution system using a quantum signal including the time-bin qubits.SOLUTION: Disclosed is a quantum cryptography key distribution system. A receiving device of the system includes: a first single-photon detector outputting a data signal including a time-bin encoding pulse indicating a quantum signal; and a TDC receiving a predetermined reference timing signal and the data signal. The TDC is configured to determine a state of a time-bin qubit indicated by the time-bin encoding pulse based on a time difference between a first generation time point of a reference pulse included in the reference timing signal, and a second generation time point of the time-bin encoding pulse generated after the first generation time point.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a quantum key distribution technique, and more particularly to a technique for measuring time-bin qubits using a Time to Digital Converter (TDC) in a system using a quantum key distribution protocol that uses a time-bin encoding method. [Background technology]

[0002] Quantum key distribution technology is being researched as a technology to solve the risk of communication eavesdropping (monitoring). Quantum key distribution technology is a technology that distributes and shares encryption keys among users in remote locations by using the quantum mechanical properties of photons. If an attacker (or eavesdropper) intervenes in the quantum key distribution process to obtain encryption key information distributed among users, the presence of the attacker can be detected by utilizing the fact that the encryption key information can be altered due to the quantum mechanical properties of photons.

[0003] In all quantum key distribution systems, such as the BB84, B92, and T12 protocols, the quantum state can be encoded in a time bin format. Among quantum key distribution protocols using the time bin encoding method, the coherent one-way (COW) quantum key distribution protocol is a representative quantum key distribution protocol according to the prior art. In this case, a sender (Alice) of a cryptographic key generates two pulse lasers having a certain phase difference, and the two pulses are transmitted to a receiver (Bob) as one information unit. In this case, a state in which only the preceding pulse of the two pulses is generated indicates bit information "0", and a state in which only the succeeding pulse is generated indicates bit information "1". A state in which both of the two pulses are generated indicates a decoy state, and the decoy state is used to detect the presence of an attacker (eavesdropper) (Eve) who attacks the quantum key distribution system. The receiver (Bob) may have a data line for detecting the received state and a monitoring line for detecting the presence of an attacker. A part of one pulse received by the receiver is transmitted to the data line and used to generate an encryption key, and another part is transmitted to the monitoring line and used to detect the presence of an attacker. In this case, the monitoring line can include a delay interferometer that delays the phase interval (ρ) used by the sender (Alice) to generate a coherent laser pulse, and two photon detectors to detect constructive and destructive interference of the signal. If there is no attack by the attacker, constructive interference can be detected, and if there is an attack, destructive interference can be detected. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention aims to provide a new structure for determining the state of a time bin qubit in a quantum cryptographic key distribution system using a quantum signal including a time bin qubit by introducing a time to digital converter (TDC). [Means for solving the problem]

[0005] According to one aspect of the present invention, a receiving device for a quantum cryptography key distribution system may be provided. The receiving device includes a data line 241 for transmitting a state of a received quantum signal, a first single photon detector 221 connected to the data line, and a TDC 250 for receiving a predetermined reference timing signal (Srt) and a data signal (Sd) output from the first single photon detector. The TDC is adapted to determine a time difference between an occurrence time of a reference pulse included in the reference timing signal and an occurrence time of a time bin coded pulse included in the data signal.

[0006] In this case, the receiving device can be adapted to use the time difference to determine the state of the time bin qubit indicated by the time bin coded pulse.

[0007] In this case, the receiving apparatus may further include a second controller 270 configured to determine a state of a time bin qubit indicated by the time bin coded pulse using the time difference.

[0008] In this case, the reference timing signal may be a pulse train having the same period as the generation period of qubits generated in the quantum cryptography key distribution system, or a pulse train signal synchronized with the generation period of the qubits.

[0009] In this case, the TDC may include a first delay line unit 20 to which an input pulse having a width equal to the time difference between a first generation point of the reference pulse and a second generation point of the time bin coded pulse generated after the first generation point is input, and a calculation unit 60 to determine the generation time difference using a thermometer code output from the first delay line unit.

[0010] In this case, the TDC may further include a code conversion unit 30 for converting and outputting the order of elements of the thermometer code. The calculation unit is configured to determine the occurrence time difference by using a conversion code output by the code conversion unit, and the conversion code is obtained by arranging the order of elements of the thermometer code according to a predetermined criterion, and the predetermined criterion may be a data path delay from an output node of the input pulse to each output node of a plurality of flip-flops (FFs) included in the first delay line unit.

[0011] In this case, the TDC may be implemented by an FPGA, and the FPGA may be programmed to include the first delay line unit and the arithmetic unit.

[0012] In this case, the TDC may be implemented by an FPGA, and the FPGA may be programmed to determine the state of the time bin qubit indicated by the time bin coded pulse using the time difference.

[0013] In this case, the TDC may be implemented by any one of an ASIC (Application Specific Integrated Circuit) and an IC (Integrated Circuit), and the any one of the devices may be configured to determine the state of a time bin qubit indicated by the time bin coded pulse using the time difference.

[0014] In this case, the TDC may further include a second delay line unit to which the input pulse is input. The code conversion unit may be configured to generate the conversion code by aligning and merging elements of the thermometer code output by the first delay line unit and elements of the thermometer code output by the second delay line unit according to a predetermined second criterion. The predetermined second criterion may be a data path delay from an output node of the input pulse to each output node of a plurality of flip-flops included in the first delay line unit and the second delay line unit.

[0015] In this case, the TDC may use a clock signal (clk) having a period shorter than the generation period of the qubits generated in the quantum key distribution system. The TDC may further include an input signal generating unit 10 for generating the input pulse having a width equal to the time difference between the rising edge of the reference pulse and the rising edge of the time bin coded pulse, a clock pulse counting unit 40 for counting the number of clock pulses of the clock signal generated during the sustain period of the input pulse, and the calculation unit for determining the value of the generation time difference using a first thermometer code (TC1) output by the code converting unit at the rising edge of a first clock pulse among the generated clock pulses, a second thermometer code (TC2) output by the code converting unit at the rising edge of a clock pulse generated immediately after the last clock pulse among the generated clock pulses, and the number of counted clock pulses.

[0016] In this case, the receiving device may further include a beam splitter 210 for receiving the quantum signal, and the data line 241 may be connected to the beam splitter.

[0017] According to another aspect of the present invention, a quantum cryptography key distribution system may be provided, including a transmitting device for generating and transmitting a quantum signal including a time bin qubit, and a receiving device for receiving the quantum signal and determining a state of the quantum signal. The receiving device includes a first single photon detector 221 for receiving the quantum signal and outputting a data signal (Sd) including a time bin coded pulse representing the quantum signal, and a TDC 250 for receiving a predetermined reference timing signal (Srt) and the data signal (Sd). The TDC is adapted to determine a time difference between a first generation point of a reference pulse included in the reference timing signal and a second generation point of the time bin coded pulse generated after the first generation point.

[0018] In this case, the TDC may include a first delay line unit 20 to which an input pulse having the time difference as a width is input, a code conversion unit 30 to convert the order of elements of the thermometer code output by the first delay line unit and output the converted code, and a calculation unit 60 to determine the occurrence time difference using the converted code output by the code conversion unit.

[0019] In this case, the conversion code is obtained by arranging the order of the elements of the thermometer code according to a predetermined criterion, and the predetermined criterion may be a data path delay from an output node of the input pulse to each output node of a plurality of flip-flops (FFs) included in the first delay line section.

[0020] The time bin qubit measurement method provided according to one embodiment of the present invention can be performed using a TDC 250 that is connected to the beam splitter 210 of the receiver 200 and receives an input of a data signal (Sd) output by a first single photon sensor 221 connected to a data line 241 for sensing the received state.

[0021] A TDC (Time to Digital Converter) is a device or circuit that converts the time interval between two events into a digital output. A TDC works by measuring the time difference between two events, which can be a signal arrival or a signal emission and reflection at two points in a circuit. A counter is typically used to count the number of clock periods between the two events. The count is then converted into a digital output that indicates the time interval. There are various types of TDCs such as leading edge TDC, trailing edge TDC, and interpolation TDC. A leading edge TDC measures the time between the leading edge (rising edge) of a start signal and the leading edge of a stop signal, while a trailing edge TDC measures the time between the trailing edge (falling edge) of a start signal and the trailing edge of a stop signal. An interpolation TDC uses an interpolation technique to estimate the time interval between two clock periods to increase the resolution of the TDC.

[0022] TDCs can be implemented using ASICs (Application-Specific Integrated Circuits), MCUs (Microcontrollers), PSoCs (Programmable System-on-Chip), DSPs (Digital Signal Processors), FPAAs (Field Programmable Analog Arrays), TACs (Time-to-Amplitude Converters), TFCs (Time-to-Frequency Converters), and FPGAs (Field Programmable Gate Arrays), etc.

[0023] When a TDC is implemented using an FPGA, the following problems may occur. First, resources including logic cells, look-up tables (LUTs), and routing channels provided in an FPGA are limited, which may limit the resolution and accuracy of a TDC implemented in an FPGA. Second, at high clock frequencies, jitter may introduce errors into the TDC measurement. Here, jitter refers to variations in the timing of a clock signal due to factors such as noise and temperature. Third, due to factors such as voltage drop, temperature change, and manufacturing process differences, the TDC may exhibit nonlinear behavior, which may introduce errors into the TDC measurement at high resolution. Fourth, the FPGA generates delays due to signal processing and routing, which may introduce errors into the TDC measurement for small time intervals.

[0024] Routing in FPGAs refers to the process of connecting programmable logic elements (e.g., look-up tables, flip-flops, and multiplexers) to a chip to form a desired logic circuit. Routing determines the way signals propagate through a chip and can have a significant impact on the overall performance of a design. One of the main factors that can cause delays in FPGA routing is the capacitance of the interconnect wires that connect the logic elements. As the number of logic elements and the distance between them increases, the capacitance of the interconnect wires also increases. This capacitance can slow the signal waves through the wires and increase the overall design delay. Another factor that can cause delays in FPGA routing is routing congestion. Routing congestion occurs when an FPGA has limited routing resources and a large number of logic elements that must be connected. Routing congestion can cause delays because it increases the distance between logic elements and increases the capacitance of the interconnect wires.

[0025] A tapped delay line is a digital signal processing technique used to implement thermometer code. In a thermometer code, each bit of a binary number is represented on a separate signal line, with a line that corresponds to an "on" bit indicating the value of the binary number. To implement a thermometer code using a tapped delay line, a series of delay elements are used to represent each bit. An input binary number is converted into a series of pulses, with each pulse representing one bit of a binary number. These pulses are delayed by different amounts depending on their respective bit positions and then fed into the tapped delay line. At the output of the tapped delay line, each output signal line represents a bit of a binary number, with an "on" line indicating the value of the binary number. This technique is commonly used to convert digital signals to analog signals in a digital-to-analog converter (DAC).

[0026] In FPGAs, a carry chain block is a hardware block used to perform high-speed arithmetic operations, especially addition and subtraction. In digital circuits, addition and subtraction of multi-bit numbers requires the calculation of a carry bit, which can cause a bottleneck in high-speed operations. The carry chain block efficiently handles such carry bit calculations, allowing for faster and more efficient arithmetic operations. A carry chain block typically consists of a series of global adder circuits interconnected in a specific manner to form a carry chain. Each global adder circuit calculates one bit of the output and a carry bit that is transmitted to the next stage of the chain. By connecting such global adder circuits into a chain, the carry bit propagates through the chain for one clock cycle, allowing for high-speed addition and subtraction of multi-bit numbers. In addition to providing high-speed arithmetic operations, carry chain blocks can also be used to implement counters and delay circuits that require the calculation of a carry bit.

[0027] A timing report tool is a software tool used to analyze the timing performance of a design implemented in an FPGA. The tool generates a report that provides information on the timing characteristics of the design, including data path delay, critical paths, setup and hold times, clock skew, and maximum operating frequency. The data path delay is the time it takes for a data signal to propagate through the logic elements of the FPGA.

[0028] A multiplexer, or "MUX" for short, is an electronic circuit that selects one of multiple input signals and transmits the selected input to an output line. The input-output structure of a multiplexer typically consists of multiple input lines, a select line, and one or more output lines. The number of input lines corresponds to the number of input signals the multiplexer can select, and the select line determines the selected input signal. For example, a 4-to-1 multiplexer has four input lines, one output line, and a select line that determines which of the four input signals to transmit as the output. The select line can be controlled with a binary code that indicates the selected input line. Multiplexers are often used in digital systems to reduce the number of wires required to transmit data and control signals. They can be used to implement functions such as data selectors, memory address decoders, and bus allocation circuits.

[0029] According to another aspect of the present invention, there may be provided a non-volatile recording medium readable by an electronic device having a binary file recorded thereon, the binary file including configuration data adapted to program an FPGA, the FPGA being an FPGA included in a quantum cryptography key distribution system, the configuration data being adapted to program the FPGA to configure a digital circuit including a signal receiving unit for receiving a data signal (Sd) outputted from a first single photon detector, and a time difference determining unit adapted to determine a time difference between an occurrence time of a reference pulse included in a predetermined reference timing signal (Srt) and an occurrence time of a time bin coded pulse included in the data signal.

[0030] In this case, the digital circuit may further include a qubit state determining unit configured to determine a state of a time bin qubit indicated by the time bin coded pulse using the time difference.

[0031] In this case, the digital circuit may further include a pulse train generator for generating a pulse train having the same period as a generation period of a qubit generated in the quantum cryptographic key distribution system, and the reference timing signal is the pulse train.

[0032] In this case, the digital circuit may further include a first delay line unit 20 to which an input pulse having a width equal to the time difference between a first generation point of the reference pulse and a second generation point of the time bin coded pulse generated after the first generation point is input, and a calculation unit 60 for determining the generation time difference using a thermometer code output from the first delay line unit.

[0033] In this case, the digital circuit may further include a code conversion unit 30 for converting and outputting the order of elements of the thermometer code. The calculation unit is configured to determine the occurrence time difference by using a conversion code output by the code conversion unit, the conversion code being obtained by arranging the order of elements of the thermometer code according to a predetermined criterion, and the predetermined criterion may be a data path delay from an output node of the input pulse to each output node of a plurality of flip-flops (FFs) included in the first delay line unit.

[0034] In this case, the digital circuit may further include a second delay line unit to which the input pulse is input. The code conversion unit may be configured to generate the conversion code by aligning and merging elements of the thermometer code output by the first delay line unit and elements of the thermometer code output by the second delay line unit according to a predetermined second criterion. The predetermined second criterion may be a data path delay from an output node of the input pulse to each output node of a plurality of flip-flops included in the first delay line unit and the second delay line unit.

[0035] In this case, the digital circuit may use a clock signal (clk) having a period shorter than a generation period of qubits generated in the quantum cryptographic key distribution system.The digital circuit may further include an input signal generating unit for generating the input pulse having a width equal to a time difference between a rising edge occurrence time of the reference pulse and a rising edge occurrence time of the time bin coded pulse, a clock pulse counting unit for counting the number of clock pulses of the clock signal generated during a sustain period of the input pulse, and the calculation unit for determining a value of the generation time difference using a first thermometer code output by the code converting unit at a rising edge time of a first clock pulse among the generated clock pulses, a second thermometer code output by the code converting unit at a rising edge time of a clock pulse generated immediately after a last clock pulse among the generated clock pulses, and the number of counted clock pulses. Effect of the Invention

[0036] According to the present invention, in a quantum cryptography key distribution system that utilizes a quantum signal containing a time-bin qubit, a new structure for determining the state of the time-bin qubit can be provided by introducing a time-to-digital converter (TDC).

[0037] The TDC having the structure provided by the present invention has an advantage that it can be implemented by an FPGA operating at a few hundred MHz, which is lower than 10 GHz. [Brief description of the drawings]

[0038] [Figure 1] FIG. 2 illustrates three quantum states utilized in a quantum cryptography key distribution system provided by one embodiment of the present invention. [Diagram 2] 1 is a diagram showing the configuration of a quantum cryptography key distribution system provided by an embodiment of the present invention. [Diagram 3]1 is a diagram showing the configuration of a receiving device of a quantum key distribution system including a TDC provided by an embodiment of the present invention. [Figure 4] FIG. 2 illustrates an example of a data signal and a reference timing signal provided to a TDC provided by one embodiment of the present invention. [Diagram 5] FIG. 2 is a diagram showing the configuration of a TDC according to an embodiment of the present invention. [Figure 6] 5 is a diagram illustrating an input pulse input to a first delay line unit according to an embodiment of the present invention. FIG. [Figure 7] FIG. 2 is a diagram showing a configuration of a first delay line unit in an embodiment of the present invention. [Figure 8] FIG. 8 is a diagram for explaining the indexes of the buffer in FIG. 7. [Figure 9] FIG. 13 is a diagram showing a table for explaining a data path delay. [Figure 10a] FIG. 13 is a diagram showing a parallel configuration of a plurality of delay line units according to an embodiment of the present invention. [Figure 10b] FIG. 13 is a diagram showing a parallel configuration of a plurality of delay line units according to an embodiment of the present invention. [Figure 11a] FIG. 10b shows the configurations of the first delay line section and the second delay line section. [Figure 11b] 11A and 11B are diagrams illustrating the operation of a code conversion unit when two delay line units are used according to an embodiment of the present invention. [Figure 12] 11 is a graph showing a delay depending on whether or not a code conversion unit is applied according to an embodiment of the present invention; FIG. [Figure 13] 13 is a diagram for explaining an arrangement standard of flip-flop output values ​​depending on whether a code conversion unit is applied or not and an increase in the number of taps in FIG. 12 according to an embodiment of the present invention. [Figure 14] 1 is a block diagram showing the main functional parts of a PCB board including an FPGA provided by one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0039] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiment described in this specification, and may be embodied in various other forms. The terms used in this specification are intended to facilitate understanding of the embodiments, and are not intended to limit the scope of the present invention. In addition, the singular form used below includes the plural form unless the wording clearly indicates the opposite.

[0040] The protocol used in the quantum cryptographic key distribution system 1000 provided by one embodiment of the present invention is based on a time bin encoding method.

[0041] The general format of one qubit is shown in Equation 1.

number

[0042] A time bin qubit consists of two time modes, denoted early (E) and late (L). A time bin qubit is 0 >=|α> E |0> L and |ψ 1 >=|0> E |α> L In most QKD implementations, the weak coherent state α is approximated as |ψ>=(|ψ 0 >+e iΦ |ψ 1 >) / root(2), where Φ∈{0, π / 2, π, 3π / 2}.

[0043] FIG. 1 illustrates three quantum states utilized in a quantum encryption key distribution system provided according to one embodiment of the present invention.

[0044] In one embodiment of the present invention, only the three quantum states having the encoding shown in FIG. 1 are used.

[0045] In the Z basis used to generate the raw key, the sender (Alice) sets bits 0 or 1 to state |ψ 0 > or |ψ 1 >

[0046] The X basis can be used to estimate the eavesdropper's information. In this basis, the sender (Alice) has |ψ + >=(|ψ 0 >+|ψ 1 >) / send root(2).

[0047] The probability of choosing the Z and X bases is p Z A , p X A It is.

[0048] Since weak coherent pulses are used, photon number splitting attacks can be prevented by using a decoy state method.

[0049] Two different mean photon numbers μ 1 and μ 2 The average number of photons in each qubit μ = |α| 2 is the probability p 1 and p 2 In μ 1 and μ 2 are selected at random from among them.

[0050] The receiver (Bob) receives the message with probability p Z B , p X B to measure the qubit in the Z or X basis. The Z basis measurement is a direct measurement of the arrival time of the photon that allows the receiver to recover the bit value. In the X basis, the coherence between two successive pulses is measured by an unbalanced interferometer.

[0051] FIG. 2 shows the configuration of a quantum cryptographic key distribution system 1000 provided according to an embodiment of the present invention.

[0052] The sender (Alice) 100 is a transmitting device that transmits pulses, and may include a laser 110, a filter 120, a piezoelectric fiber stretcher 133, a transmitting side first Faraday mirror 131, a transmitting side second Faraday mirror 132, an intensity modulator (IM) 140, an RF amplifier 141, a digital-to-analog converter (DAC) 142, a first control unit 170, a dispersion compensating fiber (DCF) 150, and a variable attenuator (VA) 160.

[0053] For example, laser 110 may be a 1550 nm fast gain-switched distributed feedback laser, filter 120 may be a 270 pm bandpass filter, and first controller 170 may be an FPGA operating at 10 GHz, but the invention is not limited thereto.

[0054] The receiver (Bob) 200 used in one embodiment of the present invention is a receiving device for receiving pulses, and may include a beam splitter (BS) 210, a data line 241 connected to the beam splitter 210 for detecting the received state, a monitoring line 242 connected to the beam splitter 210 for detecting the presence of an attacker, a first single-photon detector (SPD) 221 connected to the data line 241, a second single-photon detector 222 connected to the monitoring line 242, a first receiving Faraday mirror 231, a second receiving Faraday mirror 232, a Time to Digital Converter (TDC) 250, and a second control unit 270.

[0055] The first single photon detector 221 and the second single photon detector 222 are devices for detecting individual photons and may be referred to as single photon detectors. The single photon detectors are designed to detect individual photons with high sensitivity and are not easily affected by noise or background light, and can reliably distinguish the presence or absence of a single photon. Various types of single photon detectors may be used in QKD. The single photon detectors may be high-energy photodiodes (Avalanche Photodiodes, APDs), Superconducting Nanowire Detectors (SNSPDs), or Single Photon Avalanche Diodes (SPADs), or may be different types of devices. Each of these single photon detectors is based on a different principle and has the common characteristic of being able to detect one photon.

[0056] The second control unit 270 may be an FPGA that operates at a high-speed clock of, for example, 10 GHz, but the present invention is not limited to this. The second control unit 270 may be an FPGA that operates at a clock slower than 10 GHz, for example.

[0057] In one embodiment of the present invention, a pulse generated by a sender 100 can be transmitted to a receiver 200 via a quantum channel 300. The quantum channel 300 can be composed of, for example, a single-mode optical fiber (SMF; Single-Mode Fiber).

[0058] The sender (Alice) and receiver (Bob) devices each have, for example, f X These can be controlled by a FPGA (Field Programmable Gate Array) with a sampling rate of f X The quantum channel may be constructed from a spool of single mode optical fiber (SMF) with an attenuation of about 0.2 dB / km. X can be, for example, 10 or a smaller number.

[0059] At the sender (Alice) side, a laser 110 is used to generate pulses with arbitrary phase, for example at a rate of 2.5 Ghz. A narrow band filter (270 pm) limits the spectrum of the optical pulses to limit the chromatic dispersion effects of the fiber optic link. Such pulses are also chirped, so filtering reduces their duration to about 30 ps. The pulses then pass through an unbalanced Michelson interferometer with an arm length difference of 200 ps. The effect is to split each pulse into two pulses that are coherent with each other. In one arm the optical fiber can encase a piezoelectric cylinder that is used to adjust the interferometer phase.

[0060] A single intensity modulator (IM) 140 may be implemented to encode the three states shown in FIG.

[0061] The qubit state to be encoded and the pulse amplitude can be selected randomly by the first controller 170. For this, the first controller 170 can use a pseudorandom number generator. The high-speed output from the first controller 170 is coupled to a 3-bit programmable DAC (digital-to-analog converter) 142, which generates a radio frequency (RF) pulse with the appropriate amplitude. The output of the DAC 142 is additionally amplified by an RF amplifier 141. Such a pulse drives a Lithium Niobate (LiNbO3) IM [IXblue], which adjusts the intensity of the pulse leaving the interferometer. Using a DAC, only four independently adjustable levels can be generated. These four levels correspond to the average number of photons μ after the final attenuation. 1 , μ 2 =μ 1 / 2, μ 2 / 2 and 0. Therefore, μ 2 =μ 1 / 2, which is close to the optimum at almost all distances.

[0062] The Dispersion Compensating Fiber (DCF) 150 pre-compensates for the chromatic dispersion of the quantum channel. Without this DCF 150, the overlap between two consecutive pulses at the receiver (Bob) side after 50 km would dramatically increase the quantum bit error rate (QBER). Since the sender (Alice) is a part of the DCF 150, the DCF 150 does not add any attenuation to the quantum channel.

[0063] Finally, a variable attenuation stage 160 placed at the output of the sender (Alice) attenuates the signal to set the desired average number of photons in the outgoing pulse.

[0064] On the receiver (Bob) 200 side, the division ratio between the Z-base and the X-base is r Z :r X The measurement basis is passively selected via the beam splitter 210, which is Z +r X=100). The splitting ratio can be optimized for each transmission distance. In the Z basis, the state is transmitted directly to the first single-photon detector 221, which measures the arrival time of the photon. The measurement result is |ψ 0 > or |ψ 1 >. In the X basis, there is an unbalanced Michelson interferometer with the same delay as on the sender (Alice) side. After this second interferometer, three pulses are observed: a central interfering and two side peaks. The interferometer delay is exactly half the clock period, so that the side peaks of adjacent qubits overlap at the output port. Detection in the central interfering time bin leads to the state |ψ->=(|ψ 0 >-|ψ 1 We can fix the phase difference between the sender (Alice) and receiver (Bob) interferometers so that |ψ+>=(|ψ 0 >+|ψ 1 >) / root(2) state photons leave the interferometer through the second port, the input port. It is not sensitive to such events. The phase difference is kept constant in a feedback loop that takes the QBER in the X basis as an error signal. Also, to compensate for the length variations of the quantum channel, an automatic feedback loop continuously adjusts an electrical delay placed between the detector and the FPGA. As the sampling by the FPGA is done at, say, 10 Ghz, |ψ 0 > and |ψ 1 > are isolated as "empty" time bins that can be used for this time tracking.

[0065] FIG. 3 shows the configuration of a receiver (Bob) 200 of a quantum key distribution system including a TDC provided by an embodiment of the present invention.

[0066] The recipient (Bob) 200 may further include a TDC 250 .

[0067] The TDC250 is utilized to measure the Z ground state.

[0068] The TDC 250 is connected to the beam splitter 210 of the receiver 200, and receives the data signal (Sd) output from the first single photon detector 221 connected to the data line 241 for sensing the received state.

[0069] The data signal (Sd) output by the first single photon sensor 221 may be a binary signal having a value of 0 or 1. The time-dependent waveform of the data signal (Sd) may have a form of a pulse train in which pulses are generated. For example, the first single photon sensor 221 may be a device that outputs a pulse having a predetermined duration when a single photon is input to the first single photon sensor 221 and detects the same.

[0070] In addition, a clock signal (clk) may be input to the TDC 250. The clock signal may be a train of clock pulses counted by the TDC 250. The clock signal (clk) may be the clock pulses used in the TDC shown in FIG.

[0071] A predetermined reference timing signal (Srt) is also input to the TDC 250. The reference timing signal (Srt) may be provided by the second control unit 270.

[0072] The sender 100 and the receiver 200 can share information about a transmission period of a series of qubits. Also, the receiver 200 can obtain information about the time or time interval when the sender 100 starts transmitting a series of qubits, and thus the receiver 200 can prepare for receiving the transmitted qubits. And, the receiver 200 can synchronize the time when a single photon arrives at the receiver 200 with the detection time when the receiver 200 detects the single photon. Specific configurations for the above-mentioned techniques are already well known in the art.

[0073] In one embodiment, the single-photon sensor may be configured to operate only when an enable signal input to the single-photon sensor is in a specific logic state (e.g., logical high). The reference timing signal (Srt) may be provided as the enable signal. The generation period of a series of pulses included in the reference timing signal (Srt) may match the generation period of a qubit generated by the sender 100.

[0074] In addition, the TDC 250 may generate a data timing signal including a value indicating a generation time point of a pulse included in the data signal (Sd) and provide the data timing signal to the second controller 270. In this case, the data timing signal may be a value indicating a difference between a generation time point of a pulse included in the data signal (Sd) and a corresponding generation time point of a specific pulse in the reference timing signal (Srt).

[0075] FIG. 4 illustrates an example of a data signal and a reference timing signal provided to a TDC provided by one embodiment of the present invention.

[0076] The reference timing signal (Srt) may be a pulse train having a predetermined period. The pulse period (Tq) of the pulse train may be the same as the transmission period of the unit information transmitted by the sender (Alice) 100. That is, the pulse period (Tq) may be the same as the transmission period of the qubit transmitted by the sender 100.

[0077] Each pulse of said reference timing signal (Srt), ie each reference pulse (Pr1, Pr2, Pr3, . . . ), is considered as a start signal (S1) as described below.

[0078] The data signal (Sd) presented in FIG. 4 is illustrated as including a first time bin qubit (first qubit information) (QI1) and a second time bin qubit (second qubit information) (QI2).

[0079] Each pulse, ie each time bin coded pulse (Pt1, Pt2, . . . ) contained in the data signal (Sd) is considered as a termination signal (S2) which will be described later.

[0080] In the example of FIG. 4, the first time bin qubit (QI1) is in a state (ψ 0 >=|α> E |0> L ), and the second time bin qubit (QI2) is in a state where a time bin-coded pulse exists only in the later time bin (L) out of the early time bin (E) and the later time bin (L), (|ψ 1 >=|0> E |α> L ) is shown.

[0081] The TDC 250 measures the occurrence time difference (T) between the rising edge of a reference pulse (S1) of the reference timing signal (Srt) and the rising edge of a time bin encoded pulse (S2) of the data signal that occurs immediately after said reference pulse. Such a measurement can be performed repeatedly for all reference pulses of the reference timing signal (Srt).

[0082] If the width of one reference pulse (S1) and the width of one time bin coded pulse (S2) are identical to each other, the TDC 250 can also be modified to measure the occurrence time difference between the falling edge of the reference pulse (S1) and the falling edge of the time bin coded pulse (S2).

[0083] The occurrence time difference (T) can be substantially T1 or T2, but the time bin qubit measured in the case of T1 is in a state (|ψ 0 >), and the time bin qubit measured at time T2 is in the state (|ψ 1 >).

[0084] If the pulse generation timing of the reference timing signal (Srt) used by the receiver 200 is exactly synchronized with the arrival timing of the photons input to the single photon detector, then T1 = 0 may be possible.

[0085] In FIG. 4, T1 < T2. However, depending on the specific value of the relative phase between the reference timing signal (Srt) and the data signal (Sd), T1 > T2 may also be possible. The relative phase between the reference timing signal (Srt) and the data signal (Sd) can be controlled by the quantum key distribution system 1000.

[0086] The above-described generation time difference (T) can be included in the data timing signal described in FIG. 3 and provided to the second control unit 270.

[0087] Hereinafter, the operating principle of the TDC 250 provided by an embodiment of the present invention will be described in detail. The TDC 250 can be implemented by the FPGA 1.

[0088] FIG. 5 shows a configuration diagram of an FPGA implementing a TDC according to an embodiment of the present invention.

[0089] When the second control unit 270 shown in FIG. 3 is an FPGA, the FPGA 1 implementing the TDC 250 can be the second control unit 270.

[0090] Differently, when the second control unit 270 shown in FIG. 3 is not an FPGA, the TDC 250 can be implemented by an FPGA provided separately from the second control unit 270.

[0091] The TDC 250 can be implemented by a relatively low-speed FPGA operating at a clock of, for example, 100 to 300 MHz, rather than a high-speed FPGA operating at a clock of, for example, 10 GHz.

[0092] FIG. 6 is a diagram for explaining an input pulse input to the first delay line unit according to an embodiment of the present invention.

[0093] The following description will be given with reference to both FIG. 5 and FIG.

[0094] The FPGA 1 may include an input signal generating section 10 , a first delay line section 20 , a code converting section 30 , a clock pulse counting section 40 , a priority encoder section 50 , and a calculation section 60 .

[0095] Specifically, the above-mentioned configuration of the FPGA 1 may be that of a TDC (Time to Digital converter).

[0096] 5, the input signal generating unit 10 can generate an input pulse (P1) having a width equal to the generation time difference (T) between the rising edge (E1) of a given start signal (S1) and the rising edge (E2) of a given end signal (S2). The input signal generating unit 10 can be configured with logic gates required for the generation.

[0097] The first delay line unit 20 may receive an input pulse P1 having a width equal to the generation time difference T between the start signal S1 and the end signal S2. The first delay line unit 20 may output a thermometer code O1. In this case, the thermometer code may be an 8-bit value, for example, consisting of output values ​​of flip-flops included in the first delay line unit 20, and the output values ​​of each flip-flop may be referred to as elements of the thermometer code.

[0098] FIG. 7 shows a configuration of a first delay line section according to an embodiment of the present invention.

[0099] FIG. 8 is a diagram for explaining the indexes of the buffers in FIG.

[0100] The first delay line section 20 may include a delay line (D_L) including a plurality of buffers (delay elements, delay elements) (B) and a D-flip-flop (FF) tapped to the output terminal of each buffer (B) of the delay line.

[0101] The multiple buffers may be connected in a cascade delay manner, i.e., the multiple buffers may be arranged according to the order in which the input pulse (P1) flows.

[0102] The waveform (signal) of the input pulse (P1) in Fig. 7 may be output with a predetermined delay from the output terminal of each buffer (B). That is, the output value of the first buffer (B1) is output with a predetermined delay from the output terminal of the first buffer (B1), and the output terminal of the first buffer (B1) is connected to the input terminal of the second buffer (B2). The output value (e.g., "1") of the first buffer (B1) may also be input to the first flip-flop (FF1).

[0103] At this time, a data path delay may occur between each buffer (B) and through the flip-flop (FF). For example, a delay of d1 may occur until an input value ("1") of the first buffer (B1) is transferred to the second buffer (B2), and a delay of d11 may occur until an output value ("1") of the first buffer (B1) is transferred to the first flip-flop (FF1). Similarly, a delay may occur every time data is transferred from a previous buffer to a next buffer, and a delay may occur every time data is transferred from any buffer to a flip-flop connected to the any buffer.

[0104] FIG. 8 is a diagram for explaining buffer indexes according to an embodiment of the present invention.

[0105] Each field in the table in FIG. 8 indicates a buffer name, an index, and an output value of the buffer.

[0106] Each buffer can be assigned an index that defines the order of each buffer. For example, the first buffer (B1) can be assigned an index "1", the second buffer (B2) can be assigned an index "2", and similarly the eighth buffer (B8) can be assigned an index "8". In this way, when each buffer (B) is arranged according to the order in which the input pulse (P1) flows and the indexes are arranged according to that order, for example, 1000 buffers can be assigned indexes from 1 to 1000.

[0107] FIG. 9 shows a table for explaining the data path delay.

[0108] 5 and 9, the code conversion unit 30 may convert and output the order of elements (e.g., 1, 2, 3, 4, 5, 6, 7, 8) of the thermometer code (O1) (e.g., 11100000) output from the first delay line unit 20. In this case, the code (e.g., 11010000) (the order of indexes of the corresponding buffer is 1, 2, 4, 5, 3, 6, 7, 8) output by the code conversion unit 30 may be referred to as a "conversion code (CO1)."

[0109] The converted code (CO1) output by the code conversion unit 30 may be a code obtained by rearranging the order of elements of the thermometer code (O1) according to a predetermined criterion. In this case, the predetermined criterion may be the data path delay from the output node (N1) of the input pulse (P1) to each output node (N2) of the plurality of flip-flops (FF) included in the first delay line unit 20. This will be described in detail with reference to FIG. 9.

[0110] Each field in the table may indicate a buffer index number, a first delay value, a second delay value, and a total value (rank). In this case, the rank may indicate a rank with respect to the total value. In this case, the rank may be such that the buffer with the smallest total value has the first rank and the buffer with the highest total value has the last rank, or vice versa in other embodiments.

[0111] As described above with reference to FIG. 7, the sum value may refer to the time it takes for data to be transferred from the node (N1) where the input pulse (P1) is output to an arbitrary flip-flop (eg, FF4).

[0112] There may be a first delay, which is the time it takes for an input value of a given buffer to be transferred to another buffer connected to the given buffer, and a second delay, which is the time it takes for an output value of the given buffer to be transferred to the input of a flip-flop connected to the given buffer.

[0113] In this case, the sum of the first delay value and the second delay value for each buffer can be referred to as the data path delay.

[0114] 7 and 9, when the indexes of each buffer are listed in order, the rank of the sum of the first delay value and the second delay value may be different from the rank of the index number of each buffer. For example, in the case of the third buffer, since the buffer arrangement rank is third, the index number is "3", but the rank of the sum may be "5". In more detail, in order for data to be transmitted to the third flip-flop (FF3), it must pass through the first buffer (B1), the second buffer (B2), and the third buffer (B3). At this time, a certain delay (d1, d2, d3) occurs each time the data passes through the first buffer (B1), the second buffer (B2), and the third buffer (B3), and a delay (d13) may also occur until the data output from the third buffer (B3) is output to the output value of the third flip-flop (FF3). That is, the delay until data is transmitted from the output node (N1) of the input pulse (P1) to the output node (N2, N23) of the third flip-flop (FF3) may be the sum of d1, d2, d3, and d13.

[0115] In this manner, the delay (ie, the total value) until the data is transmitted to the output node of each flip-flop FF3 can be calculated.

[0116] For example, in this embodiment, the buffer index for the third flip-flop (FF3) is 3, and the buffer index for the fourth flip-flop (FF4) is 4. That is, the fourth flip-flop (FF3) must go through one more buffer than the third flip-flop (FF4), but nevertheless the total delay to the output node of the third flip-flop with a buffer index of 3 may be greater.

[0117] The code conversion unit 30 can convert the order of the elements of the thermometer code (O1) based on the calculated delay (sum) (for example, in ascending order of sum).

[0118] The converted code (CO1) output by the code conversion unit 30 can be provided to the priority encoder unit 50.

[0119] The priority encoder unit 50 can digitize a long thermometer code. For example, the priority encoder unit 50 can convert a 5200-bit thermometer code into a 13-bit thermometer code. For example, if there are 5200 buffers (delay elements) (B) and 5200 flip-flops (FF) connected to the buffers as described above in FIG. 7, a sequence of 5200 consecutive binary numbers is output, which can be expressed as a 13-bit binary number.

[0120] That is, the priority encoder unit 50 can express the 5200-bit first thermometer code (TC1) and second thermometer code (TC2) as a 13-bit binary number as the output value (CO1) of the code converter 30 according to time.

[0121] 6, the first thermometer code TC1 may be a code output by the code conversion unit 30 in relation to the rising edge of the input pulse P1 at the rising edge E4 of the clock pulse CK2 which is generated first after the rising edge E1 of the input pulse P1 of the generated clock pulses CK. The first thermometer code TC1 expressed in 13 bits may be provided as an input to the calculation unit 60.

[0122] The second thermometer code TC2 may be a code output by the code conversion unit 30 in relation to the falling edge E2 of the input pulse P1 at the rising edge E6 of the clock pulse CK4 that is generated first after the falling edge E2 of the input pulse P1 of the generated clock pulses CK. The second thermometer code TC2 expressed in 13 bits may be provided as an input to the calculation unit 60.

[0123] At this time, the time interval of the first thermometer code (TC1) and the time interval of the second thermometer code (TC2) may be smaller than the period of the clock pulse (CK).

[0124] 5 and 6, the clock pulse counting unit 40 can receive an input pulse P1 from the input signal generating unit 10. As shown in FIG.

[0125] The clock pulse counting unit 40 can count the number of clock pulses (CK) generated during the sustain period (T) of the input pulse (P1). For example, in FIG. 6, the number of rising edges of the clock pulses generated during the period in which the input pulse (P1) is in an ON state is two, the same as the edges (E4, E5), so the counted value may be two.

[0126] An output value (coarse count) of the clock pulse counting unit 40, i.e., the counted value, can be provided to a calculation unit 60.

[0127] 5 and 6, the calculation unit 60 may determine the value of the generation time difference using the first thermometer code (TC1), the second thermometer code (TC2), and the number of counted clock pulses. For example, the generation time difference may be 2*Period+TC1-TC2.

[0128] 10a and 10b are diagrams showing a parallel configuration of multiple delay line sections according to one embodiment of the present invention.

[0129] 10a, two or more delay line units 20 may be connected in parallel. In this case, the input pulse (P1) output from the input signal generating unit 10 may be input to the first delay line unit 21, the second delay line unit 22, the third delay line unit 23, and the fourth delay line unit 24, respectively. And, the first thermometer code (O1), the second thermometer code (O2), the third thermometer code (O3), and the fourth thermometer code (O4) output from the first delay line unit 21, the second delay line unit 22, the third delay line unit 23, and the fourth delay line unit 24 may be input to the code converting unit 30.

[0130] In another embodiment, it can be assumed that two delay line sections 20 are connected in parallel, as in FIG. 10b.

[0131] For example, the input pulse (P1) output from the input signal generating unit 10 can be provided along a first path (path1) in which the output terminal of the input signal generating unit 10 and the input terminal of the first delay line unit 21 are connected to each other, and along a second path (path2) in which the output terminal of the input signal generating unit 10 and the input terminal of the second delay line unit 22 are connected to each other.

[0132] At this time, the time at which the input pulse (P1) output from the input signal generating unit 10 reaches the input terminal of the first delay line unit 21 and the input terminal of the second delay line unit 22 may differ from each other. This is because there is an input delay due to the difference in length between the first path (path1) and the second path (path2). In the embodiment of Fig. 10a, it can be seen that since the length of the first path (path1) is shorter than the length of the second path (path2), the input time interval of the input pulse (path1) via the first path (path1) is shorter than the input time interval of the input pulse (path2) via the second path (path2).

[0133] FIG. 11a is a diagram showing the configuration of the first delay line unit and the second delay line unit of FIG. 10b, and FIG. 11b is a diagram for explaining the operation of the code conversion unit when two delay line units are used according to one embodiment of the present invention.

[0134] For ease of explanation, FIG. 11a shows each delay line section as including four buffers and four flip-flops.

[0135] In FIG. 11b, each field of the table may indicate a delay line section number, a buffer index number, a first delay value, a second delay value, a first sum value (first rank), and a first sum value (overall rank). In this case, the first rank may indicate a rank for each sum value for a buffer index of a buffer in each delay line section. And, the overall rank may indicate a rank for each sum value for a buffer index of all buffers in the first delay line section and the second delay line section. In this case, the first rank and the overall rank may be such that a buffer with the smallest sum value has the first rank, and a buffer with the highest sum value has the last rank. Or, in other embodiments, the reverse is also possible. A method of calculating the sum value may be as described in FIG. 5.

[0136] The code conversion unit 30 may be configured to generate one conversion code by arranging and merging elements of a first set (e.g., {(D1, 1), (D2, 2), (D3, 3), (D4, 4)}) in which the sums of the elements of the thermometer code output by the first delay line unit 21 and the buffer index pairs are arranged in ascending order of sum values, and elements of a second set (e.g., {(D5, 5), (D6, 6), (D7, 7), (D8, 8)}) in which the sums of the elements of the thermometer code output by the second delay line unit 22 and the index pairs are arranged in ascending order of sum values.

[0137] That is, the elements of the first set and the elements of the second set can be sorted in ascending order of sum values.

[0138] For example, the reference output value of the buffer index in the first delay line unit 21 may be {1, 2, 3, 4}, and the reference output value of the buffer index in the second delay line unit 22 may be {5, 6, 7, 8}. In the embodiment of FIG. 10b and FIG. 11a, the delay (d1) may be smaller than the delay (d5). Therefore, the sorted order may be (D1, 1), (D2, 2), (D5, 5), (D3, 3), (D6, 6), (D4, 4), (D7, 7), (D8, 8). The output value of the flip-flop for each buffer index may be sorted in the sorted order. For example, the sorted values ​​(buffer index) may be 0(1), 0(2), 1(4), 1(6), 1(3), 1(5), 0(7), 0(8).

[0139] As mentioned above, when multiple delay line sections 20 are used, it is possible to have slightly different input delays depending on the arrangement. Figure 12, described below, shows the delays due to the arrangement when multiple delay line sections are used.

[0140] FIG. 12 shows a graph of delay depending on whether or not a code conversion unit is applied according to an embodiment of the present invention.

[0141] FIG. 13 is a diagram for explaining an arrangement standard of flip-flop output values ​​depending on whether or not a code conversion unit is applied and an increase in the number of taps in FIG. 12 according to an embodiment of the present invention.

[0142] FIG. 12a shows a delay graph according to the number of taps when the code conversion unit 30 is not applied, and FIG. 12b shows a delay graph according to the number of taps when the code conversion unit 30 is applied.

[0143] The fields in the table of FIG. 13 include before and after sorting, the sorting criteria of the flip-flop output values, and the sorting order of the total delay value.

[0144] The following description will be given with reference to both FIG. 12 and FIG.

[0145] The horizontal axis of the graphs (g1, g2) indicates the number of taps. Referring to FIG. 11b, one tap may mean one buffer (delay element) (e.g., B1) and a pair of flip-flops (FF1) connected thereto. For example, if the number of pairs of buffers and flip-flops connected thereto is 1000 in total, the total number of taps may be 1000.

[0146] The vertical axis of the graphs (g1, g2) indicates delay time (ns), which may mean the total delay time required for data to be transmitted to the output node of the flip-flop tapped to each buffer described above in FIG.

[0147] 11a to 13, an increase in the number of taps in graph (g1) may mean, for example, an increase in the buffer index. For example, if the number of taps on the horizontal axis of graph (g1) is 4, it may mean buffer index 4. In this case, the delay value on the vertical axis of graph (g1) may be D4 (=d1+d2+d3+d4+d14) as shown in FIG. 11b. For example, if the number of taps is 5, it may mean buffer index 5. In this case, the delay value on the vertical axis of graph (g1) may be D5 (=d5+d15) as shown in FIG. 11b. In this case, referring to FIG. 13, it may be D4>D5. Here, it can be seen that the delay observed in the flip-flop of each tap does not increase as the tap index (e.g., index 4->index 5) increases, but may also decrease locally even if the tap index increases.

[0148] On the other hand, in graph (g2), an increase in the number of taps does not mean an increase in the buffer index, but rather an increase in position according to the alignment order in the state where the output values of each flip-flop are aligned by the code conversion unit 30. For example, when the number of taps is 4 on the horizontal axis of graph (g2), the position order of the aligned buffer indexes is 1, 2, 5, 3, which can represent buffer index 3. And the delay value on the vertical axis of graph (g2) in this case can be D3 (= d1 + d2 + d3 + d13). For example, when the number of taps is 5, the position order of the aligned buffer indexes is 1, 2, 5, 3, 6, which can represent buffer index 6. And the delay value in this case can be D6 (= d5 + d6 + d16). At this time, referring to FIG. 13, D3 < D6 can hold.

[0149] That is, as shown in FIG. 12a, when the code conversion unit 30 of the present invention is not applied, it can be seen that the graph (g1) for the delay with an increase in the number of taps does not have the property of monotonically increasing. On the other hand, as shown in FIG. 12b, when the code conversion unit 30 of the present invention is applied, it can be seen that the graph (g2) for the delay with an increase in the number of taps exhibits a non-decreasing increasing phenomenon.

[0150] For example, unlike an ASIC, which is an order-type semiconductor (application-specific integrated circuit), an FPGA that can be directly designed by programming can change the functions of the chip by programming. Therefore, unlike an ASIC, the functions of each component included in the FPGA can change (or depending on the arrangement of the components), and the delay does not always increase every time the number of taps increases, and may decrease, so there may be no non-decreasing increasing phenomenon.

[0151] However, as described above, it can be confirmed that the code conversion unit 30 can correct the monotonically increasing property of the first delay line unit 20 by graph (g2).

[0152] As described above, when multiple delay line units 20 are used, the code conversion unit can provide delay alignment. As a result, it is possible to correct errors due to jitter and provide a TDC with high time resolution. For example, when four delay line units are configured in parallel to have a total of 9600 taps, it is possible to provide a TDC with a resolution of 0.8 ps per tap.

[0153] FIG. 14 is a block diagram showing the main functional parts of a PCB board including an FPGA provided according to one embodiment of the present invention.

[0154] 3 may include an electronic device including a TDC 250 and a second controller 270. In this case, the TDC 250 and / or the second controller 270 may be implemented as an FPGA 1. The FPGA 1 may be implemented on a PCB board 600 installed in the receiver 200.

[0155] The PCB board 600 is a device capable of digital signal processing, and can include not only the FPGA 1, but also a data interface 601, a clock generating unit 603, a power supply unit 604, and other functional units not shown in FIG.

[0156] The data interface 601 is a device that allows data exchange between the PCB board 600 and the computing device 700, and can be, but is not limited to, a USB, Ethernet, or UART.

[0157] The clock generation unit 603 can provide a train of clock pulses that the FPGA 1 counts.

[0158] The time difference value of the two selected signals calculated by the FPGA 1 may be output from the FPGA 1 and provided to the data interface 601. The data interface 601 may provide the time difference value of the two signals to the computing device 700.

[0159] The power supply section 604 supplies the power used by the PCB board 600 .

[0160] The computing device 700 may include a data interface 701, a CPU 702, and a memory 703. A binary file including configuration data adapted to program the FPGA 1 may be recorded in the memory 703. The CPU 702 may transmit the binary file to the data interface 601 via the data interface 701.

[0161] The binary file can be stored in the ROM 80 of the FPGA 1 and used by the FPGA 1.

[0162] The configuration data may be such that the FPGA 1 configures a predetermined digital circuit therein.

[0163] The digital circuit may include a signal receiving unit 71 for receiving a data signal (Sd) output from a first single photon detector, a time difference determining unit 72 for determining a time difference between a generation time of a reference pulse included in a predetermined reference timing signal (Srt) and a generation time of a time bin coded pulse included in the data signal, a qubit state determining unit 73 for determining a state of a time bin qubit indicated by the time bin coded pulse using the time difference, and a pulse train generating unit 74 for generating a pulse train having the same period as the generation period of a qubit generated in the quantum cryptography key distribution system. The names of parts indicated by reference numbers 71, 72, 73, and 74 are presented as above for the convenience of explanation, but the specific names may be modified and presented.

[0164] In this case, the reference timing signal may be the pulse train.

[0165] In addition, the digital circuit may further include the input signal generating unit 10, the first delay line unit 21, the second delay line unit 22, the code converting unit 30, the clock pulse counting unit 40, the priority encoder unit 50, and the arithmetic unit 60.

[0166] In FIG. 14, computing device 700 is presented as including a data interface 701, a CPU 702, and a memory 703, but may have a different configuration than that shown in FIG. 14 as long as it is capable of providing the binary file to FPGA 1.

[0167] The name of the file containing the configuration data intended to program the FPGA 1 may have another name than the binary file mentioned above.

[0168] The ROM 80, the FPGA 1 including the ROM 80, and the memory 703 can all be regarded as non-volatile recording media readable by an electronic device, each of which is provided according to an embodiment of the present invention.

[0169] For convenience of explanation, an example of a coherent one-way (COW) scheme has been described in Fig. 2 to Fig. 4. However, the present invention is not limited to this embodiment, and the present invention can be applied to any QKD that uses time bin coding.

[0170] Using the above-described embodiments of the present invention, those skilled in the art of the present invention can easily make various changes and modifications without departing from the essential characteristics of the present invention. The contents of each claim in the claims can be combined with other claims that have no reference relationship within the scope of the present specification.

Claims

1. A data line (241) for transmitting the state of the received quantum signal; a first single-photon sensor (221) connected to the data line; and a TDC (250) for receiving a predetermined reference timing signal (Srt) and a data signal (Sd) output from the first single-photon detector; the TDC is adapted to determine a time difference between a time of occurrence of a reference pulse included in the reference timing signal and a time of occurrence of a time bin coded pulse included in the data signal; A receiver for a quantum key distribution system adapted to use the time difference to determine the state of the time bin qubit indicated by the time bin coded pulse.

2. delete

3. 2. The receiving device of claim 1, further comprising a second control unit (270) adapted to use the time difference to determine the state of the time bin qubit represented by the time bin coded pulse.

4. 2. The receiving device of a quantum cryptography key distribution system according to claim 1, wherein the reference timing signal is a pulse train having the same period as the generation period of a qubit generated in the quantum cryptography key distribution system or a pulse train signal synchronized with the generation period of the qubit.

5. The TDC is a first delay line unit (20) to which an input pulse having a width equal to a time difference between a first generation time point of the reference pulse and a second generation time point of the time bin coded pulse generated after the first generation time point is input; 2. The receiving device of a quantum cryptography key distribution system according to claim 1, further comprising a calculation unit (60) for determining the generation time difference by utilizing a thermometer code output from the first delay line unit.

6. The TDC further includes a code conversion unit (30) that converts the order of elements of the thermometer code and outputs the converted code, The calculation unit is configured to determine the occurrence time difference by utilizing the conversion code output by the code conversion unit, the conversion code is obtained by arranging the order of elements of the thermometer code according to a predetermined criterion; 6. The receiving device of a quantum cryptography key distribution system according to claim 5, wherein the predetermined reference is a data path delay from an output node of the input pulse to each output node of a plurality of flip-flops (FFs) included in the first delay line section.

7. 6. The receiver of claim 5, wherein the TDC is implemented by an FPGA, and the FPGA is programmed to include the first delay line unit and the arithmetic unit.

8. 2. The receiving device of claim 1, wherein the TDC is implemented by any one of a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), and an Integrated Circuit (IC), and the any one of the devices is configured to determine a state of a time bin qubit indicated by the time bin coded pulse using the time difference.

9. the TDC further includes a second delay line unit to which the input pulse is input, the code conversion unit aligns and merges elements of the thermometer code output by the first delay line unit and elements of the thermometer code output by the second delay line unit according to a second predetermined criterion to generate the conversion code; 7. The receiving device of a quantum cryptography key distribution system according to claim 6, wherein the predetermined second reference is a data path delay from an output node of the input pulse to each output node of a plurality of flip-flops included in the first delay line section and the second delay line section.

10. The TDC uses a clock signal (clk) having a period shorter than a generation period of a qubit generated by the quantum key distribution system; The TDC is an input signal generating unit (10) for generating the input pulse having a width equal to the time difference between the rising edge occurrence time point of the reference pulse and the rising edge occurrence time point of the time bin coded pulse; a clock pulse counting unit (40) for counting the number of clock pulses of the clock signal generated during a sustain period of the input pulse, 7. The receiving device of a quantum cryptography key distribution system according to claim 6, wherein the value of the generation time difference is determined by using the calculation unit, the first thermometer code (TC1) output by the code conversion unit at the rising edge of a first clock pulse among the generated clock pulses, the second thermometer code (TC2) output by the code conversion unit at the rising edge of a clock pulse generated immediately after a last clock pulse among the generated clock pulses, and the number of counted clock pulses.

11. a beam splitter (210) for receiving the quantum signal; 2. The receiving device of claim 1, wherein the data line (241) is coupled to the beam splitter.

12. The FPGA included in the quantum cryptography key distribution system is a signal receiving unit for receiving a data signal (Sd) output from the first single-photon detector; a time difference determiner adapted to determine the time difference between the occurrence times of a reference pulse comprised in a predetermined reference timing signal (Srt) and the occurrence times of time bin coded pulses comprised in said data signal; and A non-volatile recording medium readable by an electronic device, having recorded thereon a binary file including configuration data adapted to program the FPGA to configure a digital circuit including a qubit state determination unit adapted to use the time difference to determine the state of a time bin qubit indicated by the time bin coded pulse.

13. delete

14. The digital circuit further includes a pulse train generating unit that generates a pulse train having the same period as a generation period of a qubit generated in the quantum cryptographic key distribution system; 13. The non-volatile recording medium readable by an electronic device according to claim 12, wherein the reference timing signal is the pulse train.

15. The digital circuit includes: a first delay line unit (20) to which an input pulse having a width equal to a time difference between a first generation time point of the reference pulse and a second generation time point of the time bin coded pulse generated after the first generation time point is input; 13. The non-volatile recording medium readable by an electronic device according to claim 12, further comprising a calculation unit (60) for determining the occurrence time difference by using a thermometer code output by the first delay line unit.

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