Reducing number of regular coding bins

Abstract

To provide a method and an apparatus for reducing the number of conventional coding bins in entropy encoding and decoding.SOLUTION: For coding with context-based adaptive binary arithmetic coding (CABAC), the values of non-binary syntax elements are mapped to a binary sequence (bin string) via a binarization process. The binary arithmetic coding engine entropy codes one or more leading binary symbols of the binary symbols using a bypass mode and entropy codes the rest of the binary symbols in a context-based mode.SELECTED DRAWING: Figure 11A

Description

[Technical field]

[0001] The present embodiments relate generally to methods and apparatus for video encoding or decoding, and more particularly to methods and apparatus for reducing the number of conventional coding bins in entropy encoding and decoding. [Background technology]

[0002] To achieve high compression efficiency, image and video coding schemes usually exploit spatial and temporal redundancy in video content using prediction and transformation. In general, intra- or inter-prediction is used to exploit intra- or inter-picture correlation, and then the difference between the original block and the predicted block, often referred to as prediction error or prediction residual, is transformed, quantized, and entropy coded. To reconstruct the video, the compressed data is decoded by an inverse process corresponding to entropy coding, quantization, transformation, and prediction. Summary of the Invention

[0003] According to one embodiment, a method of video decoding is provided, the method including: decoding a plurality of binary symbols from a bitstream, where a first binary symbol of the plurality of binary symbols is entropy decoded using a context-based mode and each binary symbol following the first binary symbol is entropy decoded in a bypass mode; obtaining an index represented by the plurality of binary symbols, corresponding to a binarization scheme; and forming a prediction of the block as a weighted sum of two predictors, where the index indicates a respective weighting factor used for weighting the two predictors when forming the weighted sum.

[0004] According to one embodiment, there is provided a method of video encoding, the method comprising: accessing a block to be encoded; forming a prediction of the block as a weighted sum of two predictors; and encoding an index to indicate respective weighting factors used for weighting the two predictors when forming the weighted sum, the index being binarized into a plurality of binary symbols using a binarization scheme, a first binary symbol of the plurality of binary symbols being entropy coded using a context-based mode, and each binary symbol following the first binary symbol being entropy coded in a bypass mode.

[0005] According to another embodiment, there is provided an apparatus for video decoding including one or more processors configured to: decode a plurality of binary symbols from a bitstream, where a first binary symbol of the plurality of binary symbols is entropy decoded using a context-based mode and each binary symbol following the first binary symbol is entropy decoded in a bypass mode; obtain an index represented by the plurality of binary symbols, corresponding to a binarization scheme; and form a prediction of the block as a weighted sum of two predictors, where the index indicates a respective weighting factor used for weighting the two predictors when forming the weighted sum.

[0006] According to another embodiment, there is provided an apparatus for video encoding including one or more processors, the one or more processors configured to access a block to be encoded, form a prediction of the block as a weighted sum of two predictors, encode an index to indicate respective weighting coefficients used for weighting the two predictors when forming the weighted sum, the index being binarized into a plurality of binary symbols using a binarization scheme, a first binary symbol of the plurality of binary symbols being entropy coded using a context-based mode, and each binary symbol following the first binary symbol being entropy coded in a bypass mode.

[0007] According to another embodiment, an apparatus for video decoding is provided, the apparatus including: means for decoding a plurality of binary symbols from a bitstream, where a first binary symbol of the plurality of binary symbols is entropy decoded using a context-based mode and each binary symbol following the first binary symbol is entropy decoded in a bypass mode; means for obtaining an index represented by the plurality of binary symbols, corresponding to a binarization scheme; and means for forming a prediction of the block as a weighted sum of two predictors, where the index indicates a respective weighting coefficient used for weighting the two predictors when forming the weighted sum.

[0008] According to another embodiment, an apparatus for video encoding is provided, the apparatus including: means for accessing a block to be encoded; means for forming a prediction of the block as a weighted sum of two predictors; and means for encoding an index to indicate respective weighting coefficients used for weighting the two predictors when forming the weighted sum, the index being binarized into a plurality of binary symbols using a binarization scheme, a first binary symbol of the plurality of binary symbols being entropy coded using a context-based mode, and each binary symbol following the first binary symbol being entropy coded in a bypass mode. [Brief description of the drawings]

[0009] [Figure 1] 1 shows a block diagram of one embodiment of a video encoder. [Diagram 2] 1 is a diagrammatic example illustrating the concepts of coding tree units and coding trees for representing a compressed HEVC picture. [Diagram 3] 1 is a diagrammatic example showing division of coding tree units into coding units, prediction units, and transform units. [Figure 4] 2 shows a block diagram of one embodiment of a video decoder. [Diagram 5] The CABAC decoding process is shown. [Figure 6] The CABAC encoding process is shown. [Figure 7] 1 is a diagrammatic example showing a CTU representation of a quad tree plus binary tree (QTBT). [Figure 8] 1 is an illustrative example showing a coding unit partition mode; [Figure 9] The coding process of the GBi index in VVC Draft 4 is shown. [Figure 10] This shows the analysis process of the GBi index in VVC Draft 4. [Figure 11] 11A illustrates a coding process of a GBi index according to one embodiment, and FIG. 11A illustrates a coding process of a GBi index according to another embodiment. [Figure 12] FIG. 12A shows a GBi index parsing process according to one embodiment, FIG. 12A shows a GBi index parsing process according to another embodiment, FIG. 12B and FIG. 12C show the binarization and coding / parsing process of gbiCodingIndex in non-low latency mode and low latency mode, respectively, and FIG. 12D shows the tree when the first bin is equal to 0, signaling the default GBI mode. [Figure 13] 1 is an illustrative example showing the construction of a motion vector predictor candidate list in AMVP mode. [Figure 14] 1 is an illustrative example showing spatial and temporal motion vector prediction candidates that are considered to build an AMVP candidate list. [Figure 15] 1 shows CABAC coding of motion vector prediction indices in AMVP of VVC Draft 4. [Figure 16] 1 illustrates a bypass coding process for mvp_l0_flag and mvp_l1_flag syntax elements according to one embodiment. [Figure 17] This paper presents the principles of the SBT tool in VVC Draft 5. [Figure 18] 1 shows a decoding process of an INTER coding unit in SBT mode in VVC Draft 5. [Figure 19A] 19A illustrates an SBT mode decryption process according to one embodiment, and FIG. 19B illustrates an SBT mode decryption process according to another embodiment. [Figure 20A] 20A shows the allowable ISP partitioning for 4x8 and 8x4 INTRA coding units, while FIG. 20B shows the allowable ISP partitioning for INTRA coding units of sizes different from 4x8 or 8x4. [Figure 21] 1 illustrates the principle of multiple baseline intra prediction. [Figure 22] The parsing process of the “intra_luma_ref_idx” syntax element in VVC draft 5 is shown below. [Figure 23] 1 illustrates a simplified parsing process for the "Intra_luma_ref_idx" syntax element, according to one embodiment. [Figure 24] 1 illustrates a block diagram of a system in which aspects of the present embodiments may be implemented. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Figure 1 shows an example of a video encoder 100, such as a High Efficiency Video Coding (HEVC) encoder. Figure 1 may also show an encoder that improves on the HEVC standard or employs technology similar to HEVC, such as the Versatile Video Coding (VVC) encoder under development by the Joint Video Exploration Team (JVET).

[0011] In this application, the terms "reconstructed" and "decoded" can be used interchangeably, the terms "encoded" or "coded" can be used interchangeably, and the terms "image", "picture", and "frame" can be used interchangeably. Typically, but not necessarily, the term "reconstructed" is used on the encoder side while "decoded" is used on the decoder side.

[0012] Before being encoded, a video sequence may undergo a pre-encoding process (101), such as applying a color transformation to the input color picture (e.g., from RGB 4:4:4 to YCbCr 4:2:0) or performing a remapping of the input picture components to obtain a signal distribution that is more resilient to compression (e.g., using histogram equalization of one of the color components). Metadata may be associated with the pre-processing and may be attached to the bitstream.

[0013] To encode a video sequence with one or more pictures, a picture is partitioned into one or more slices, where each slice may, for example, contain one or more slice segments (102). In HEVC, slice segments are organized into coding units, prediction units, and transform units. The HEVC specification distinguishes between "blocks" and "units," where a "block" addresses a particular region of a sample array (e.g., luma, Y), and a "unit" includes a collocated block of all coded color components (Y, Cb, Cr, or monochrome), syntax elements, and prediction data (e.g., motion vectors) associated with the block.

[0014] In coding according to HEVC, as shown in FIG. 2, a picture is partitioned into square coding tree blocks (CTBs) with configurable size (usually 64×64, 128×128, or 256×256 pixels), and a contiguous set of coding tree blocks is grouped into a slice. A coding tree unit (CTU) encompasses the CTB of a coded color component. The CTB is the root of a quad-tree partitioning into coding blocks (CBs), which can be partitioned into one or more prediction blocks (PBs), forming the root of a quad-tree partitioning into transform blocks (TBs), as shown in FIG. 3. Corresponding to coding blocks, prediction blocks, and transform blocks, a coding unit (CU) includes a prediction unit (PU) and a tree-structured set of transform units (TUs), where a PU includes prediction information for all color components, and a TU includes a residual coding syntax structure for each color component. The sizes of the CB, PB, and TB of the luma component are applied to the corresponding CU, PU, ​​and TU. In this application, the term "block" may be used to refer to, for example, any of a CTU, CU, PU, ​​TU, CB, PB, and TB. In addition, a "block" may also be used to refer to macroblocks and partitions as specified in H.264 / AVC or other video coding standards, or more generally to arrays of data of various sizes.

[0015] In the encoder 100, a picture is encoded by the encoder elements as described below. The picture to be encoded is processed, for example, in units of a CU. Each coding unit is encoded using either intra mode or inter mode. If the coding unit is encoded in intra mode, intra prediction is performed (160). In inter mode, motion estimation (175) and motion compensation (170) are performed. The encoder decides (105) whether intra mode or inter mode is used to encode the coding unit, and indicates the intra / inter decision by a prediction mode flag. A prediction residual is calculated by subtracting the predicted block from the original image block (110).

[0016] The prediction residual is then transformed (125) and quantized (130). The quantized transform coefficients, as well as the motion vectors and other syntax elements, are entropy coded (145) to output a bitstream. As a non-limiting example, the syntax elements can be coded into the bitstream using context-based adaptive binary arithmetic coding (CABAC).

[0017] To code with CABAC, the values ​​of non-binary syntax elements are mapped to a binary sequence, called a bin string, via a binarization process. For a bin, a context model is selected. A "context model" is a probability model for one or more bins, chosen from a set of available models depending on the statistics of the most recent coded symbols. The context model for each bin is identified by a context model index (also used as a "context index"), with different context indices corresponding to different context models. A context model stores the probability that each bin is "1" or "0" and can be of adaptive or static type. A static model triggers the coding engine with equal probability for bins "0" and "1". In the adaptive coding engine, the context model is updated based on the actual coded value of the bin. The operating modes corresponding to the adaptive and static models are called normal and bypass modes, respectively. Based on the context, the binary arithmetic coding engine encodes or decodes the bin according to the corresponding probability model.

[0018] The encoder can also skip the transform and apply quantization directly to the untransformed residual signal, for example on a 4x4 TU basis. The encoder can also bypass both the transform and quantization, i.e., the residual is directly coded without applying a transform or quantization process. In direct PCM coding, no prediction is applied and the coded unit samples are coded directly into the bitstream.

[0019] The encoder decodes the coded block to provide a reference for further prediction. The quantized transform coefficients are dequantized (140) and inverse transformed (150) to decode the prediction residual. The decoded prediction residual is combined (155) with the predicted block to reconstruct an image block. An in-loop filter (165) is applied to the reconstructed picture, for example, to perform deblocking / sample adaptive offset (SAO) filtering to reduce coding artifacts. The filtered image is stored in a reference picture buffer (180).

[0020] Figure 4 illustrates a block diagram of an exemplary video decoder 200, such as an HEVC decoder, in which a bitstream is decoded by decoder elements as described below. The video decoder 200 generally performs a reverse decoding pass of the encoding pass as described in Figure 1, which performs video decoding as part of the encoding of the video data. Figure 4 may also illustrate a decoder that improves on the HEVC standard, such as a VVC decoder, or a decoder that employs HEVC-like technology.

[0021] In particular, the decoder input includes a video bitstream, such as may be generated by video encoder 100. The bitstream is first entropy decoded (230) to obtain transform coefficients, motion vectors, picture partitioning information, and other coded information. If CABAC is used for entropy coding, a context model is initialized in the same manner as the encoder context model, and syntax elements are decoded from the bitstream based on the context model.

[0022] Figure 5 shows the process of CABAC decoding of syntax elements given an input coded bitstream, which is the inverse of the syntax element coding process of Figure 6.

[0023] The input to the process of Figure 5 includes a coded bitstream, typically conforming to a video compression standard such as HEVC or VVC. At any point in the decoding process, the decoder knows the next syntax element to be decoded, which is fully specified in the standardized bitstream syntax and decoding process. In addition, it also knows how the current syntax element to be decoded is binarized (i.e., represented as a sequence of binary symbols called bins, each equal to "1" or "0"), and how each bin of the bin string is encoded.

[0024] Thus, the first stage of the CABAC decoding process (left side of Figure 5) is to decode a sequence of bins. For each bin, the decoder knows whether the bin is coded according to the bypass mode or the normal mode. The bypass mode consists in simply reading a bit in the bitstream and assigning the bit value thus obtained to the current bin. This mode has the advantage of being simple and therefore fast. As it is usually efficient, it is used for bins with a uniform statistical distribution, i.e. bins with equal probability of being equal to "1" or "0".

[0025] On the contrary, if the current bin is not coded in bypass mode, it means that it is coded in so-called normal mode, i.e. by context-based arithmetic coding. The decoding of the considered bin then proceeds as follows: First, a context for decoding the current bin is obtained using the context modeller module. The goal of the context is to obtain a conditional probability that the value of the current bin is "0" given the context information or prior information X. The prior X here can be the value of an already decoded syntax element, synchronously available on both the encoder and decoder sides at the time the current bin is decoded.

[0026] Typically, the prior X used for bin decoding is specified by the standard and is selected because it is statistically correlated with the current bin being decoded. The advantage of using this context information is to reduce the rate cost of bin coding. This is based on the fact that when the correlation between the bin and X is high, the conditional entropy of the bin given X is low. In information theory, the relationship H(bin│X) < H(bin) is well known.

[0027] This means that when the bin and X are statistically correlated, the conditional entropy of the bin knowing X is lower than the entropy of the bin. Therefore, the context information X is used to obtain the probabilities that the bin is "0" or "1". Given these conditional probabilities, a normal decoding engine performs arithmetic decoding of the binary bin. Next, the value of the bin is used to recognize the current context information X and update the value of the conditional probability associated with the current bin. This is called updating the context model. As long as the bin is being decoded (or encoded), updating the context model for each bin can gradually improve the context modeling of each binary element. Therefore, the CABAC decoder gradually learns the statistical behavior of each normally encoded bin. Note that the context modeler and the context model update step are exactly the same operations on both the encoder side and the decoder side.

[0028] The normal arithmetic decoding or its bypass decoding of the current bin leads to a series of decoded bins, depending on the coding method.

[0029] Next, in the second phase of CABAC decoding shown on the right side of Figure 5, this series of binary symbols is converted into syntax elements. The syntax element can take the form of a flag, in which case the value of the currently decoded bin is directly obtained. On the other hand, when the binarization of the current syntax element corresponds to a set of several bins according to the standard specification being considered, the conversion from the binary codeword to the syntax element is performed.

[0030] This performs the reverse step of the binarization performed by the encoder: the inverse transformation performed here thus obtains the values ​​of these syntax elements based on their respective decoded binarized versions.

[0031] For example, syntax elements corresponding to the prefix code of the last significant coefficient position and the merge index (which indicates the position of the candidate in the list of merge candidates) are binarized using truncated Rice binarization. In the case of the last significant coefficient position flag, all bins are coded in normal mode, and in the case of the merge index, the first bin is coded in normal mode and the other bins are coded in bypass mode.

[0032] The picture partitioning information indicates how a picture is partitioned, e.g., the size of the CTUs and how the CTUs are divided into CUs and, if applicable, into PUs. Thus, the decoder can, for example, divide the picture into CTUs (235) and divide each CTU into CUs according to the decoded picture partitioning information. The transform coefficients are dequantized (240) and inverse transformed (250) to decode the prediction residual.

[0033] The decoded prediction residual is combined with the predicted block (255) to reconstruct an image block. The prediction block may be obtained from intra prediction (260) or motion compensated prediction (i.e., inter prediction) (275) (270). An in-loop filter (265) is applied to the reconstructed image. The filtered image is stored in a reference picture buffer (280).

[0034] The decoded picture may further undergo a post-decoding process (285), such as an inverse color conversion (e.g., from YCbCr 4:2:0 to RGB 4:4:4) or an inverse remapping that performs the inverse of the remapping process performed in the pre-encoding process (101). The post-decoding process may use metadata derived in the pre-encoding process and signaled in the bitstream.

[0035] Recently, emerging video compression tools have been proposed that include a new coding tree unit representation in the compressed domain to represent picture data in a more flexible way in the compressed domain. A more flexible representation of the coding tree may improve compression efficiency compared to the CU / PU / TU arrangement of the HEVC standard.

[0036] In one example, the Quad Tree Plus Binary Tree (QTBT) coding tool is a new tool that provides increased flexibility. The QTBT coding tree can split coding units in both quad tree and binary tree ways. In QTBT technology, CUs have a square or rectangular shape. The size of a coding unit is always a power of 2, typically between 4 and 128. An example of a QTBT coding tree representing a coding tree unit is shown in FIG. 7.

[0037] The partitioning of the coding unit is determined via a rate-distortion optimization procedure, which may be performed at the encoder side by determining the QTBT representation of the CTU with the lowest rate-distortion cost. The QTBT decomposition of the CTU consists of two stages, where the CTU is first partitioned in a quad-tree manner, and then each quad-tree leaf can be further partitioned in a binary manner, as illustrated in Figure 7, where the solid lines represent the quad-tree decomposition phase and the dashed lines represent the binary decomposition spatially embedded in the quad-tree leaves. In intra slices, the partitioning structures of luma and chroma blocks are separated and determined independently.

[0038] No CU partitioning into prediction units or transform units is employed. In other words, each coding unit is systematically composed of a single prediction unit (2Nx2N prediction unit partition type) and a single transform unit (no division into transform trees).

[0039] An additional CU partitioning mode adopted in the Versatile Video Coding (VVC) video compression standard, called horizontal or vertical triple tree partitioning mode (HOR_TRIPLE, VER_TRIPLE), consists of partitioning a coding unit (CU) into three sub-coding units (sub-CUs), each with a size equal to ¼, ½, and ¼ of the parent CU size in the direction of the considered spatial partitioning, as shown in Figure 8.

[0040] The present embodiment is directed to encoding and decoding of syntax elements. In some embodiments, the entropy coding of some intra or inter prediction parameters is modified to reduce complexity.

[0041] As mentioned above, many binary symbols (or bins) are coded and decoded by a context-adaptive binary arithmetic coding process. This process involves two ways of coding the bins: normal mode and bypass mode. The bypass coding mode is much less complex than the normal coding mode. Therefore, it is advantageous to replace the normal coding process with the bypass coding process when the normal coding mode offers no or little coding efficiency improvement compared to the bypass coding.

[0042] In one embodiment, the bypass coding process is used to signal the first one or more bins of a bin string that represents a generalized bi-prediction index. In another embodiment, the bypass coding process is used instead of the normal coding process to signal which motion vector predictor is used to code the motion vectors of a coding unit (CU) coded in AMVP mode.

[0043] In fact, the conditional entropy of bins coded with these syntax elements is found to be close to one bit of information, despite the use of context-based arithmetic coding for these bins in current VVC coding systems. Moreover, experimental results show that using the proposed bypass coding has negligible impact on VVC compression performance.

[0044] In the following, the signaling of the generalized bi-prediction index and motion vector predictor is explained in more detail.

[0045] Signaling the generalized biprediction index Generalized bi-prediction for VVC Draft 4 VVC Draft 4 (Versatile Video Coding (Draft 4)), B. Bross et al., 13 th In the current standard (see JVET meeting, January 9-18, 2019, Marrakech), inter CUs can be temporally predicted via the use of so-called generalized bi-prediction (GBi). In generalized bi-prediction, the temporal prediction of a bi-predicted block is calculated as a weighted average of two reference blocks according to the following formula: P bipred =((8-w)×P0+w×P1+4)>>3 P0 and P1 are temporal predictors, and w is selected in the following set: - For low latency images (with all past reference images), w ∈ {-2, 3, 4, 5, 10}. For non-low latency images (with at least one past and one future reference image), w ∈ {3, 4, 5}. The weights w of -GBi are selected based on an encoder-side rate-distortion optimization process and signaled in the bitstream.GBi is also combined with various motion compensation tools in VVC, such as affine motion compensation and adaptive motion vector resolution.

[0046] The syntax element that signals the weight of GBi used in predicting a CU is called the GBi index.

[0047] Coding of GBi index in VVC Draft 4 (encoder) In VVC draft 4, the GBi index is first converted to another index, gbiCodingIndex. A flag is determined to indicate whether to use the default weights (equal weights). The flag is set to 1 for the default weight w=4 (equal weights for both predictors P0 and P1) and 0 for the other weights. The remaining gbiCodingIndex is binarized using the truncated Rice (truncated unary) bin string. The flags or each bin in the truncated Rice bin string are CABAC coded using a dedicated CABAC context. In particular, the flags are context-based coded with context model ID 0 (i.e., using normal mode). The bins, bin 1, bin 2, and bin 3, are context-based coded with context model IDs 4, 5, and 6, respectively.

[0048] Table 1 shows the GBi index (GBiIdx) coding for low latency mode, where the number of GBi modes is set to numGBiModes=5 and the maximum number of bins beyond the first bin is set to numBins=3. [Table 1]

[0049] Table 2 shows GBi index coding for non-low latency mode, where the number of GBi modes is set to numGBiModes=3 and the maximum number of bins beyond the first bin is set to numBins=1. [Table 2]

[0050] Note that the concatenation of flags and bin strings shown in Tables 1 and 2 can be directly viewed as a truncated Rice binarization of gbiCodingIndex. That is, gbiCodingIndex is binarized using the truncated Rice (truncated unary) bin string. Each bin is CABAC coded using a dedicated CABAC context. In particular, the first bin, bin 0, is context-based coded with context model ID 0 (i.e., using normal mode). Note that the first bin is set to 1 for the default weight w=4 (equal weights for both predictors P0 and P1) and 0 for other weights. Thus, the first bin can also be viewed as a flag indicating whether to use the default weight or not. Then, the subsequent bins, bin 1, bin 2, and bin 3, are context-based coded with context model IDs 4, 5, and 6, respectively.

[0051] FIG. 9 illustrates the coding of the GBi index as in VVC Draft 4. In step 910, the variable Idx is set to 0. In step 920, the GBiIdx value associated with the current CU is converted to gbiCodingIndex via the table GbiCodingOrder defined by the column "gbiCodingIndex" in Tables 1 and 2. In step 930, a flag (gbiCodingIndex==0) is coded, which indicates whether the value gbiCodingIndex is equal to zero. A zero value corresponds to the case where the GBiIdx value of the current CU is equal to GBI_DEFAULT, which corresponds to the default bi-prediction mode, i.e., w=4. If the value of gbiCodingIndex is zero (940), the process ends.

[0052] Otherwise, the encoder checks (945) whether the slice is of low-latency type. If the slice is of low-latency type, numGbiModes is set to 5 (950), otherwise, numGbiModes is set to 3 (955). In step 960, Idx is set to 1. In step 965, the context model ID contextId is set to 4. In step 970, numBins is set to numGbiModes-2. The gbiCodingIndex is binarized to a bin string. The bins representing the gbiCodingIndex are then coded one by one (980) using the corresponding contextId (985) until all bins have been coded (990). The process ends in step 999.

[0053] Figure 10 shows the parsing of a GBi index as in VVC Draft 4. The decoder decodes the value "Idx" from the bitstream and converts it to the actual GBiIdx associated with the input CU using a mapping table GbiParsingOrder that links the decoded value Idx with the CU-level GBiIdx parameter.

[0054] More specifically, in step 1010, the variable Idx is set to 0. In step 1020, a flag indicating whether the value gbiCodingIndex is equal to zero (gbiCodingIdx==0) is decoded using the context Id=0. The zero value corresponds to the current CU's GBiIdx value being equal to GBI_DEFAULT, which corresponds to the default bi-prediction mode, i.e., w=4. If the decoded symbol is 1, the decoder proceeds to step 1090.

[0055] Otherwise, if the flag is 1 (1025), then in step 1030 Idx is set to 1. In step 1035 the context model ID contextId is set to 4. The decoder checks (1040) whether the slice is of low-latency type. If the slice is of low-latency type, numGbiModes is set to 5 (1045), and if the slice is not of low-latency type, numGbiModes is set to 3 (1050). In step 1060 numBins is set to numGbiModes-2. Then the bins representing gbiCodingIndex are iteratively decoded (1070), one by one, using the corresponding contextId (1080), until a bin symbol equal to 1 is found or numBins bins have been parsed (1085). At each iteration the variable Idx is incremented. In step 1090 "Idx" is converted to a GBi index via the table GbiParsingOrder. The process ends at step 1099.

[0056] Proposed GBi index coding process (encoder) Tables 3 and 4 show the proposed modifications to the GBi index (GBiIdx) coding for low latency and non-low latency modes, respectively. In this proposed method, the first bin is coded in bypass mode (represented as "b" in the tables) and the other bins are coded in normal mode. [Table 3] [Table 4]

[0057] Figure 11 shows a proposed GBiIdx parameter coding process according to one embodiment. In step 1165, contextId is set to 5. In step 1170, the first bin of the truncated Rice bin string in Table 3 or Table 4 is coded in bypass mode instead of the context-based arithmetic coding mode. The other bins, if any, are coded in normal mode, similar to that described in Figure 9. The advantage of this proposed embodiment is that the complexity in coding the CU-level GBiIdx parameter is reduced.

[0058] Proposed GBi analysis process (decoder) Figure 12 shows a proposed modification to the GBiIdx parameter parsing process according to one embodiment. As can be seen, the first step of the proposed GBiIdx parsing process is the same as that described in Figure 10. Then, if the first decoded symbol is equal to 0 (not GBI_DEFAULT based), a series of bins representing a binarized string of truncated rice is parsed. According to the proposed embodiment, the first bin of this string is parsed using a bypass mode instead of a context-based arithmetic decoding mode. The other bins are decoded in the same way as in the prior art. The advantage of this proposed embodiment is that the complexity of parsing the GBiIdx CU level parameters is reduced.

[0059] In the above, if an index is represented by multiple bins, the first bin is coded in bypass mode and the remaining bins are coded in normal mode. More generally, more than one bin (the beginning of the bin string) can be coded in bypass mode and the remaining bins are coded in normal mode. It should also be noted that although truncated Rice binarization is described in the above example, the proposed coding method can be applied to other binarization schemes. In addition, the GBi index is used as an example of a syntax element above. However, the above method can be applied to other syntax elements.

[0060] It should be noted that when encoding other syntax elements, for example, the merge index as described above, both bypass and normal modes are used. In particular, to encode the merge index, the first bin is encoded in normal mode, since it is probably more efficient to encode it using context information. In the remaining bins, the probabilities may be more randomly distributed, and the bypass mode corresponding to equal probabilities may work as well. It should be noted that such encoding is opposite to that proposed in the present embodiment, where the first bin is encoded in bypass mode and the remaining bins are encoded in normal mode.

[0061] According to another embodiment, only the first flag, indicating whether the default GBi index (GBI_DEFAULT) corresponds to a weight factor w=4, is coded in normal mode. In this embodiment, all bins of the truncated Ricebin string following that flag are coded in bypass mode. The advantage of this embodiment is that the coding and parsing complexity of the GBi index is further reduced, possibly at the expense of a slightly reduced coding efficiency. FIG. 11A shows the proposed gbiCodingIndex coding process according to this embodiment. In step 1180, the bins of the truncated Ricebin string of Table 3 or Table 4 are coded consecutively in bypass mode instead of the context-based arithmetic coding mode. The advantage of this proposed embodiment is that it further reduces the complexity in coding the GBiIdx parameters at the CU level, without a penalty in terms of video compression efficiency.

[0062] Figure 12A shows the proposed modification to the gbiCodingIndex parsing process according to this embodiment. As can be seen, the first step of the proposed gbiCodingIndex parsing process is the same as that described in Figure 10. Next, if the first decoded symbol is equal to 0 (non-GBI_DEFAULT case), a set of bins representing a truncated Rice binarized string is parsed. According to the proposed embodiment, the bins of this string are parsed using a bypass mode instead of the context-based arithmetic decoding mode (1280).

[0063] Table 4A shows the compression performance of VTM-4.0 when this proposed embodiment (described in Fig. 11A, Fig. 12A) is used for gbiCodingIndex coding, compared with the performance of VTM-4.0 with the gbiCodingIndex coding method of Fig. 9 combined with the gbiCodingIndex analysis method of Fig. 10. The numerical values ​​presented in the table correspond to the average bitrate reduction of the proposed method at the same objective video quality. Thus, negative numbers indicate a reduction in bitrate and thus an improvement in coding efficiency, while positive numbers indicate an increase in bitrate and thus a decrease in coding efficiency. The Y, U, and V columns correspond to the luma, chroma Cb, and chroma Cr components, respectively. It can be seen that this embodiment does not result in an average bitrate change in luma compared to the method of Fig. 9, and therefore does not introduce a penalty in video compression efficiency, despite the reduction in complexity due to the use of more bypass coding bins. [Table 5]

[0064] In the following, we explain why the proposed gbiCodingIndex coding and parsing method does not compromise coding efficiency, i.e., why bypass coding of bins emitted from a Truncated Ricean (TR) bin string is as efficient as arithmetic coding of these bins.

[0065] Arithmetic coding is an optimal or near-optimal entropy coding method since it is known to achieve bit rates very close to the Shannon limit, i.e. the entropy of the symbols it codes.

[0066] The optimality of the bypass coding part of the process means that the binarization used for coding the gbiCodingIndex corresponds closely to a Huffman tree. This means that the TR binarization for coding the bins of gbiCodingIndex in bypass mode corresponds to a Huffman tree. Huffman coding is an optimal variable length coding method. Furthermore, Huffman coding is known to produce an average code length equal to the entropy of the signaled bins, when certain conditions are met. In particular, it is possible to achieve this when the probabilities associated with each branch of the Huffman tree are dyadic, i.e., when the probabilities are a negative power of two, i.e., 1 / 2. n Huffman coding is optimal when n is equal to n(n+n), where n is a positive integer value.

[0067] The two trees in Figures 12B and 12C show the binarization and coding / analysis process of gbiCodingIndex resulting from the proposed solution in non-low delay mode and in low delay inter-picture coding configuration, respectively. Filled nodes correspond to normal (context-based) coded bins, while unfilled nodes correspond to bypass coded bins. Let x be the probability that a context-based coded bin is equal to 0. The value associated with each edge of the trees in Figures 12B and 12C corresponds to the probability that a bin of the binarized gbiCodingIndex is equal to 1 or 0. For example, the probability that the second bin of the binarized gbiCodingIndex is equal to 0 is

number

number

[0068] The probabilities of bin strings resulting from truncated Ricean (TR) binarization of syntax elements are not always dyadic. For example, in the VVC specification, there are several syntax elements that are binarized following truncated Ricean binarization and have all bins coded in a context-based manner, such as syntax elements last_sig_coeff_x_prefix and last_sig_coeff_y_prefix. These two parameters are truncated Ricean binarized and all bins are coded in a context-based manner. Bypass coding some of them leads to a decrease in compression efficiency, which indicates that the corresponding bypass coding with dyadic probability distribution of bypass-coded bins does not correspond to an optimal Huffman coding process.

[0069] This embodiment recognizes that the probabilities of the bin strings of gbiCodingIndex after TR binarization are close to dyadic, and therefore applying a bypass coding pass corresponds to an optimal Huffman coding process, while being less computationally complex than arithmetic coding in normal mode.

[0070] Signaling Motion Vector Predictors Motion Vector Predictive Coding in AMVP Mode in VVC Draft 4 The AMVP motion vector coding mode involves coding the motion vector of a CU using the following elements: - Inter prediction direction, indicating whether bi- or uni-prediction is used to predict the current CU, and in the case of uni-prediction, which reference picture list is used. - Reference picture index(es), indicating which reference picture(s) are used to predict the current CU in each participating reference picture list. - A motion vector predictor, which is used to predict the actual motion vector of the current CU for each reference picture used to predict the current CU. This MV predictor (or MVP, or AMVP candidate) is selected by the encoder from an MV predictor list containing two candidates. Which MV candidate is selected is signaled via a flag marked mvp_l0_flag and mvp_l1_flag for the associated reference picture lists L0 and L1, respectively. -motion vectors, which for each reference picture list L0 and L1 are the difference between the actual motion vector of the current CU and the respective motion vector predictor.

[0071] The construction of the AMVP motion vector prediction candidate list is shown in Figures 13 and 14. The process basically consists of selecting at most two spatial candidates from five spatial positions around the current CU and pruning them to keep at most two. Then, a temporal MV prediction candidate is sought in the so-called collocated slice of the current slice at a spatial position corresponding to the bottom right position H or, if not available, at the central position "center". Then, a pruning process is applied between the spatial and temporal candidates and the list is filled with zero motion vectors up to a maximum of two elements in total. Finally, the AMVP candidate list contains exactly two motion vector prediction candidates.

[0072] Therefore, a single flag, denoted mvp_l0_flag and mvp_l1_flag, respectively, is signaled in the bitstream and parsed at the decoder side to indicate which AMVP candidate among the two elements contained in the AMVP list is used to predict the motion vector of the current CU in each reference picture list L0 and L1.

[0073] The process of parsing the flag mvp_l0_flag or mvp_l1_flag depending on the reference picture list L0 or L1 considered is shown in Figure 15. It consists of a context-based arithmetic decoding of the binary symbol "symbol" (1510). It employs a single CABAC context. The MV predictor index of the current PU or CU in the considered reference picture list is given the value of the decoded symbol (PU can be a motion partition within the current CU as used in HEVC; in VVC draft 4, PU partitioning is not used, so PU corresponds to a CU) (1520).

[0074] Proposed method: Coding mvp_l0_flag and mvp_l1_flag in bypass mode

[0075] It has been measured that across multiple coded video sequences, the average entropy used for CABAC signaling the mvp_l0_flag and mvp_l1_flag syntax elements is very close to 1 bit of information, meaning that no benefit is provided by CABAC coding of these flags compared to a simple bypass coding process.

[0076] Therefore, in this embodiment, it is proposed to code and analyze these flags via bypass coding mode. Figure 16 shows the proposed analysis process for decoding MV predictor indexes of one CU or PU for one given reference picture list (1610, 1620). The difference from the process of Figure 15 is that the CABAC decoding of the concerned bin is replaced by bypass decoding of this bin (1610). On the encoder side, the binary symbol representing mvp_l0_flag or mvp_l1_flag is coded in bypass mode. The advantage of this embodiment is that the complexity of the coding and analysis process of VVC is reduced with little impact on coding efficiency.

[0077] According to a further embodiment, mvp_l0_flag can be coded differently depending on whether the considered CU is coded in SMVD (Symmetric Motion Vector Difference) mode or not. The SMVD motion vector coding process of VVC consists of coding the motion vector difference of a given CU with respect to the first reference picture list L0. Then, the motion vector difference of the considered CU in the other reference picture list (L1) is derived from the motion vector difference of L0. Indeed, in this mode, the two motion vectors are symmetric. The L1 motion vector is equal to the inverse of the L0 motion vector in both components. In this embodiment, the MVP candidates in the case of SMVD can be coded in normal mode, while the MVP candidates in the conventional AMVP motion vector coding mode can be coded in bypass mode. This means that two separate syntax elements can be specified: the classical mvp_l0_flag and the smvd_mvp_l0flag, the latter is used to specify the MV used to predict the motion vector of the CU in SMVD mode.

[0078] According to another embodiment, the classical mvp_l0_flag may be coded in normal mode, while the smvd_mvp_l0flag may be coded in bypass mode. According to a variant, the classical mvp_l0_flag may be coded in normal mode, and the smvd_mvp_l0flag may also be coded in normal mode, but with a separate CABAC context than that used for coding the classical mvp_l0_flag.

[0079] Table 5 shows an example of the changes made to the syntax by the method proposed above, using the VVC Draft 4 syntax as an example. In particular, the descriptors of the syntax elements mvp_l0_flag and mvp_l1_flag have been changed from ae(v) to u(1), where ae(v) denotes the context-adaptive arithmetic entropy coding syntax element and u(n) denotes an unsigned integer using n bits. [Table 6-1] [Table 6-2]

[0080] Table 6 shows the performance results obtained in terms of the complexity reductions proposed above. It can be seen that the proposed simplifications result in little change in compression efficiency. [Table 7]

[0081] Above, examples are described for VVC Draft 4. Below, several examples are described for VVC Draft 5, including inter-subblock transform signaling, intra sub-partition (ISP) coding modes, multiple baseline intra prediction, and SMVD (Symmetric Motion Vector Difference) between tools (see "Versatile Video Coding (Draft 5)", B. Bross et al., 14th JVET meeting, March 19-27, 2019, Geneva, CH).

[0082] Sub-block transformation signaling Subblock Transformation (SBT) for VVC Draft 5 For inter-predicted CUs signaled as non-zero residual blocks, the SBT tool splits the CU into two transform units (TUs) in a binary manner. One of the two resulting TUs has a non-zero residual and the other has only zero residual data. The applied binary split can be symmetric or asymmetric. In the case of a symmetric split, the two resulting TUs have equal size, which is half the size of the CU in the direction of the split. In the case of an asymmetric binary split, the size of one TU is equal to 1 / 4 or the parent CU along the split direction, and the other TU size is 3 / 4 of the size of the CU along the split direction.

[0083] In addition to the spatial partitioning, TUs with non-zero residuals are coded with an estimated adaptive transform. The 1D transform used depends on the location of the non-zero residual TUs, as shown in Figure 17, where part "A" are TUs with non-zero residual data and other TUs have only zero residual data.

[0084] The TU split of the considered coding unit is signaled via three flags. First, cu_sbt_flag indicates to use SBT for the considered CU. Secondly, if SBT is used, SBT type and SBT position information are signaled. This takes the form of three coded flags: -cu_sbt_quad_flag indicates the use of asymmetric binary splitting. It is coded if both symmetric and asymmetric splitting are allowed for the current CU. -cu_sbt_horizontal_flag indicates the binary split direction. It is coded if both hot zone split and vertical split are allowed for the current CU and the previously signaled SBT split type (asymmetric or not). -cu_sbt_pos_flag indicates the position of the non-zero residual TU used to code the texture data of the considered CU.

[0085] In VVC Draft 5, the above four flags are coded on a context basis. The part of the VVC specification that corresponds to this aspect is shown in Table 7. [Table 8]

[0086] Figure 18 shows the decoding process of the SBT mode specified in VVC draft 5. At step 1810, the context ID for decoding cu_sbt_flag is obtained as ctxId = (width * height) <= 256? 1: 0. Next, at step 1820, the binary symbol cu_sbt_flag is CABAC decoded by the context ctxId. If cu_sbt_flag is equal to 0 (1830), the sub-block transform tool is not used. Otherwise, if cu_sbt_flag is not 0, the binary symbol cu_sbt_quad_flag is CABAC decoded at step 1840 with the context ctxId = 0. At step 1850, the decoder checks whether vertical and horizontal splitting is allowed for the current CU. If so, at step 1860, the context id for decoding cu_sbt_horizontal_flag is obtained as ctxId = (cuWidth == cuHeight)? 0: (cuWidth < cuHeight? 1: 2). Next, at step 1870, the binary symbol cu_sbt_horizontal_flag is CABAC decoded by the context ctxId. At step 1880, the binary symbol cu_sbt_pos_flag is CABAC decoded with the context ctxId = 0. The process ends at step 1899.

[0087] Simplified Coding of SBT Mode According to the proposed embodiment, "cu_sbt_pos_flag" is coded in bypass mode instead of the normal (context-based) CABAC mode. In fact, this simplified coding of "cu_sbt_pos_flag" hardly affects the overall coding efficiency of the codec while simplifying the entropy coding.

[0088] According to another embodiment, "cu_sbt_quad_flag" is coded in bypass mode instead of the normal mode. This simplification also hardly affects the performance of the codec.

[0089] According to another embodiment, both "cu_sbt_pos_flag" and "cu_sbt_quad_flag" are coded in bypass mode instead of normal mode.

[0090] According to another embodiment, "cu_sbt_horizontal_flag" is coded in bypass mode instead of normal mode, this simplification also has little impact on the codec performance.

[0091] According to another embodiment, three flags "cu_sbt_pos_flag", "cu_sbt_quad_flag", and "cu_sbt_horizontal_flag" are coded in bypass mode instead of normal mode. As shown in the simulation results in Table 8, there is little loss in coding efficiency resulting from this overall change. [Table 9]

[0092] Figure 19A shows the decoding process according to an embodiment in which both "cu_sbt_pos_flag" and "cu_sbt_quad_flag" are coded in bypass mode (1940, 1980). Figure 19B shows the decoding process according to an embodiment in which the three flags "cu_sbt_pos_flag", "cu_sbt_quad_flag" and "cu_sbt_horizontal_flag" are coded in bypass mode. [Table 10]

[0093] The standard syntax specification of VVC draft 5 can be changed as shown in Table 10. In particular, the descriptors of the syntax elements cu_sbt_quad_flag and cu_sbt_pos_flag are changed from ae(v) to u(1). [Table 11]

[0094] Signaling of intra-subpartition coding modes Intra-subpartitions in VVC Draft 5 The Intra Subpartition (ISP) coding mode specified in VVC Draft 5 can split an INTRA CU into two or four subpartitions horizontally or vertically. The splitting depends on the block size, as shown in Table 11. Essentially, a 4x4 CU cannot be split further. CUs of size 4x8 or 8x4 are split into two Tus (i.e., subpartitions). Other CUs are split into four Tus. [Table 12]

[0095] Figure 20A shows the allowed ISP partitioning for 4x8 and 8x4 INTRA coding units, and Figure 20B shows the allowed ISP partitioning for INTRA coding units of sizes different from 4x8 or 8x4. Inside a CU coded in ISP mode, TUs are decoded sequentially and intra predicted from TU to TU using the same intra prediction mode signaled at the CU level. Finally, the remaining coding is also adapted according to the size within the sub-partition. In fact, the sub-partitions can be of size 1xN, Nx1, 2xN, or Nx2, and coding groups of size 1x16, 1x1, 2x16, or 16x2 are used in each of these cases.

[0096] The ISP coding mode is signaled via two consecutive flags in VVC draft 5. -intra_subpartitions_mode_flag indicates to use ISP mode for the given intra CU. -intra_subpartitions_split_flag indicates the direction of splitting into intra subpartitions.

[0097] The above two flags are used to decode the value of the “IntraSubPartitionsSplitType” associated with the considered CU, as follows: IntraSubPartitionsSplitType=intra_subpartitions_mode_flag==0?0:(1+intra_subpartitions_split_flag) The meanings of the 'IntraSubPartitionsSplitType' values ​​are shown in Table 12. [Table 13]

[0098] These two flags are coded on a context basis according to VVC Draft 5, as shown in Table 13. [Table 14]

[0099] Simplified coding for ISP mode In one embodiment, the bin "intra_subparitions_split_flag", i.e., the second flag used to code the ISP mode of the CU, is coded in bypass mode. Changes to the VVC Draft 5 specification relevant to this embodiment are shown in Tables 14 and 15. In particular, the descriptor of the syntax element "intra_subpartitions_split_flag" is changed from ae(v) to u(1). [Table 15] [Table 16]

[0100] Signaling multiple baseline intra predictions VVC Draft 5 Multiple Baseline Intra Prediction The multiple reference line intra prediction used in INTRA CU in VVC draft 5 performs angular intra prediction of luma blocks based on reconstructed reference samples belonging to one top-left reference line and column of the current CU selected from three reference lines. The reference line used for intra prediction is signaled in the bitstream via the syntax element "intra_luma_ref_idx". Each reference line is identified by its index, as shown in Figure 21. The references actually used in VVC draft 5 are line 0, line 1, and line 3 shown in Figure 21. This syntax element is signaled before the intra prediction mode. In case the reference line is different from line 0, i.e. the line closest to the CU.

[0101] "intra_luma_ref_idx" is coded as follows: binarized as a truncated Rice bin string. This means that it is coded by a series of regular CABAC bins equal to 1, ending with a regular CABAC bin equal to 0. Overall, up to 3 bins are signaled.

[0102] The decoding process of "intra_luma_ref_idx" according to VVC draft 5 is shown in Fig. 22. In Fig. 22, a typical process with up to 4 reference lines is used. The array lineIDx[.] consists of 4 line reference indices and the value "MaxNumRefLInes" represents the maximum number of reference lines allowed for intra prediction. "MaxNumRefLInes" is equal to 3 for VVC and the array lineIdx consists of the following elements: lineIdx={0, 1, 3}.

[0103] The VVC decoding process of the syntax element "intra_luma_ref_idx" proceeds as follows: The output of the process is the decoded multiRefIdx. In particular, in step 2210, it checks whether multiple reference lines are allowed for the current CU. If yes, the output value multiRefIdx is initialized to 0 (2220). If MaxNumRefLines is not greater than 1 (2225), the process ends. Otherwise, in step 2230, the CABAC normal bin is parsed with a single CABAC context with index 0. If equal to 0, the multiRefIdx value is not changed and the process ends. Otherwise, multiRefIdx is set equal to lineIdx[1].

[0104] If MaxNumRefLines is strictly higher than 2 (2250), then in step 2255, the second normal CABAC bin is decoded with a single context of identifier 1. If the decoded bin is 0, multiRefIdx is not changed and the process ends. Otherwise, mutiRefIdx is set equal to lineIdx[2] (2260). If MaxNumRefLines is strictly higher than 3 (2270), then the third normal CABAC bin is decoded with a single context of identifier 2 (2280). If the decoded bin is 0, multiRefIdx is not changed and the process ends (2299). Otherwise, mutiRefIdx is set equal to lineIdx[3] (2290). Note that in practice, this step is not performed according to the VVC draft 5 specification, since the design selected for VVC draft 5 allows for up to three reference lines as described above. Therefore, the condition "MaxNumRefLines>3" is always false within VVC Draft 5.

[0105] As already described and shown in Table 16, two regular coded bins are used, with each bin using a single CABAC context, as signaled by the intra_luma_ref_idx syntax element in VVC Draft 5. [Table 17]

[0106] Simplified coding of multiple reference line indices In one embodiment, the coding of the "intra_luma_ref_idx" syntax element is simplified and only the first bin of this syntax element is coded in normal mode. The proposed modified parsing process for this syntax element is shown in Figure 23. In particular, in steps 2355 and 2380, the second and third bins are decoded in bypass mode. The other steps are similar to those shown in Figure 22.

[0107] According to this embodiment, the VVC Draft 5 specification can be modified as shown in Table 17. [Table 18]

[0108] SMVD Flag Signaling SMVD flags for VVC Draft 5 The sym_mvd_flag syntax element indicates the use of symmetric motion vector difference for INTER coding units. The SMVD motion vector coding process of VVC codes the motion vector difference of a given CU with respect to the first reference picture list L0. Then, the motion vector difference of the considered CU in the other reference picture list (L1) is derived from the motion vector difference of L0. In fact, in this mode, the difference between the two motion vectors is symmetric. The L1 motion vector difference is equal to the inverse of the L0 motion vector difference in both x and y components. In VVC draft 5, this sym_mvd_flag is coded and decoded in the normal CABAC mode using a single CABAC context.

[0109] Simplified coding of SMVD flags In one embodiment, it is proposed to encode and decode this flag in bypass mode. The proposed simplification does not affect the compression efficiency of VVC. According to this embodiment, the VVC draft 5 syntax specification can be modified as shown in Table 18. In particular, the descriptor of svm_mvd_flag is changed from ae(v) to u(1). [Table 19]

[0110] Various methods are described herein, each of which includes one or more steps or acts for achieving the described method. Unless a specific order of steps or acts is required for the correct operation of the method, the order and / or use of specific steps and / or acts may be varied or combined.

[0111] Various methods and other aspects described in the present application can be used to modify modules, such as the entropy encoding and decoding modules (145, 230) of the video encoder 100 and decoder 200, as shown in Figures 1 and 4. Furthermore, the aspects are not limited to VVC or HEVC, but can be applied, for example, to other standards and recommendations, and extensions of any such standards and recommendations. Unless otherwise indicated or technically excluded, the aspects described in the present application can be used individually or in combination.

[0112] Various numerical values ​​are used in this application, for example, Context Model ID, etc. The specific values ​​are for illustrative purposes and the described aspects are not limited to these specific values.

[0113] FIG. 24 illustrates a block diagram of an example of a system in which various aspects and embodiments are implemented. System 2400 may be embodied as a device including various components described below and configured to perform one or more of the aspects described in the present application. Examples of such devices include various electronic devices, such as, but not limited to, personal computers, laptop computers, smartphones, tablet computers, digital multimedia set-top boxes, digital television sets, personal video recording systems, connected home appliances, and servers. The elements of system 2400, either alone or in combination, may be embodied in a single integrated circuit, multiple ICs, and / or separate components. For example, in at least one embodiment, the processing and encoder / decoder elements of system 2400 are distributed across multiple ICs and / or separate components. In various embodiments, system 2400 is communicatively coupled to other systems or to other electronic devices, for example, via a communication bus or through dedicated input and / or output ports. In various embodiments, system 2400 is configured to implement one or more of the aspects described in the present application.

[0114] The system 2400 includes at least one processor 2410 configured to execute instructions loaded therein, for example, to implement various aspects described herein. The processor 2410 may include embedded memory, input / output interfaces, and various other circuits as known in the art. The system 2400 includes at least one memory 2420 (e.g., a volatile memory device and / or a non-volatile memory device). The system 2400 includes a storage device 2440, which may include non-volatile and / or volatile memory, including, but not limited to, EEPROM, ROM, PROM, RAM, DRAM, SRAM, flash, magnetic disk drives, and / or optical disk drives. The storage device 2440 may include, as non-limiting examples, an internal storage device, an attached storage device, and / or a network-accessible storage device.

[0115] The system 2400 includes an encoder / decoder module 2430 configured to process data to provide, for example, encoded or decoded video, which may include its own processor and memory. The encoder / decoder module 2430 represents a module or modules that may be included in an apparatus that performs encoding and / or decoding functions. As is known, an apparatus may include one or both of an encoding module and a decoding module. Furthermore, the encoder / decoder module 2430 may be implemented as a separate element of the system 2400 or may be incorporated within the processor 2410 as a combination of hardware and software known to those skilled in the art.

[0116] Program code to be loaded into the processor 2410 or the encoder / decoder 2430 to perform various aspects described herein may be stored in the storage device 2440 and subsequently loaded onto the memory 2420 for execution by the processor 2410. According to various embodiments, one or more of the processor 2410, the memory 2420, the storage device 2440, and the encoder / decoder module 2430 may store one or more of various items during the execution of the processes described herein. Such stored items may include, but are not limited to, input video, decoded video or portions of decoded video, bitstreams, matrices, variables, and intermediate or final results from the processing of equations, expressions, operations, and computational logic.

[0117] In some embodiments, memory within the processor 2410 and / or the encoder / decoder module 2430 is used to store instructions and provide working memory for processing required during encoding or decoding. However, in other embodiments, memory external to the processing unit (e.g., the processing unit can be either the processor 2410 or the encoder / decoder module 2430) is used for one or more of these functions. The external memory can be the memory 2420 and / or the storage 2440, and can be, for example, a dynamic volatile memory and / or a non-volatile flash memory. In some embodiments, an external non-volatile flash memory is used to store the television's operating system. In at least one embodiment, a high-speed external dynamic volatile memory, such as RAM, is used as working memory for video coding and decoding operations, such as MPEG-2, HEVC, or VVC.

[0118] Input to the elements of system 2400 may be provided via various input devices as shown in block 2405. Such input devices include, but are not limited to, (i) an RF section that receives an RF signal transmitted over the air by, for example, a broadcaster, (ii) a composite input, (iii) a USB input, and / or (iv) an HDMI input.

[0119] In various embodiments, the input devices of block 2405 have associated respective input processing elements as known in the art. For example, the RF section may be associated with elements suitable for (i) selecting a desired frequency (also referred to as selecting a signal or band-limiting a signal to a frequency band), (ii) down-converting the selected signal, (iii) band-limiting again to a narrower frequency band to select a signal frequency band, which in certain embodiments may be referred to as a channel (for example), (iv) demodulating the down-converted band-limited signal, (v) performing error correction, and (vi) demultiplexing to select a desired data packet stream. The RF section of various embodiments includes one or more elements that perform these functions, such as a frequency selector, a signal selector, a band limiter, a channel selector, a filter, a down-converter, a demodulator, an error corrector, and a demultiplexer. The RF section may include, for example, a tuner that performs various of these functions, including down-converting a received signal to a lower frequency (e.g., an intermediate frequency or a frequency close to baseband) or to baseband. In one set-top box embodiment, the RF section and its associated input processing elements perform frequency selection by receiving, filtering, downconverting, and filtering again to a desired frequency band an RF signal transmitted over a wired (e.g., cable) medium. Various embodiments rearrange the order of the above (and other) elements, remove some of these elements, and / or add other elements that perform similar or different functions. Adding elements can include inserting elements between existing elements, e.g., inserting amplifiers and analog-to-digital converters. In various embodiments, the RF section includes an antenna.

[0120] Additionally, the USB and / or HDMI terminals may include respective interface processors for connecting the system 2400 to other electronic devices over USB and / or HDMI connections. It should be appreciated that various aspects of the input processing, e.g., Reed-Solomon error correction, may be implemented, for example, in a separate input processing IC or in the processor 2410, as desired. Similarly, aspects of the USB or HDMI interface processing may be implemented, for example, in a separate interface IC or in the processor 2410, as desired. The demodulated, error corrected, and demultiplexed stream is provided to various processing elements, including, for example, the processor 2410 and an encoder / decoder 2430 operating in combination with memory and storage elements to process the data stream as desired for display on an output device.

[0121] The various elements of system 2400 can be provided within a unitary housing in which the various elements are interconnected and can transmit data between them using a suitable connection arrangement 2415, e.g., an internal bus as is known in the art, including an I2C bus, hardwired, and printed circuit boards.

[0122] The system 2400 includes a communication interface 2450 that enables communication with other devices over a communication channel 2490. The communication interface 2450 may include, but is not limited to, a transceiver configured to transmit and receive data over the communication channel 2490. The communication interface 2450 may include, but is not limited to, a modem or a network card, and the communication channel 2490 may be implemented in a wired and / or wireless medium, for example.

[0123] In various embodiments, data is streamed to the system 2400 using a Wi-Fi network, such as IEEE 802.11. The Wi-Fi signal in these embodiments is received via a communication channel 2490 and communication interface 2450 adapted for Wi-Fi communication. The communication channel 2490 in these embodiments is typically connected to an access point or router that provides access to external networks, including the Internet, enabling streaming applications and other over-the-top communications. Other embodiments provide streamed data to the system 2400 using a set-top box that delivers data via an HDMI connection in the input block 2405. Still other embodiments provide streamed data to the system 2400 using an RF connection in the input block 2405.

[0124] The system 2400 can provide output signals to various output devices, including a display 2465, speakers 2475, and other peripherals 2485. The other peripherals 2485, in various example embodiments, can include one or more of a stand-alone DVR, a disc player, a stereo system, a lighting system, and other devices that provide functionality based on the output of the system 2400. In various embodiments, control signals are transmitted between the system 2400 and the display 2465, speakers 2475, or other peripherals 2485 using signaling such as AV link, CEC, or other communication protocols that allow device-to-device control with or without user intervention. The output devices can be communicatively coupled to the system 2400 via dedicated connections through respective interfaces 2460, 2470, and 2480. Alternatively, the output devices can be connected to the system 2400 using a communication channel 2490 via the communication interface 2450. The display 2465 and speakers 2475 can be integrated into a single unit with other components of the system 2400, for example in an electronic device such as a television. In various embodiments, the display interface 2460 includes a display driver, for example a timing controller (T Con) chip.

[0125] The display 2465 and speakers 2475 may alternatively be separate from one or more of the other components, for example, if the RF portion of input 2405 is part of a separate set-top box. In various embodiments in which the display 2465 and speakers 2475 are external components, the output signal may be provided via a dedicated output connection, including, for example, an HDMI port, a USB port, or a COMP output.

[0126] According to one embodiment, a method of video decoding is provided, the method including: decoding a plurality of binary symbols from a bitstream, where a first binary symbol of the plurality of binary symbols is decoded using a bypass mode of an entropy decoding engine; and generating values ​​of syntax elements responsive to the plurality of binary symbols based on a binarization scheme.

[0127] According to one embodiment, a method of video encoding is provided, comprising accessing a plurality of binary symbols indicating a value of a syntax element and encoding the plurality of binary symbols, wherein a first binary symbol of the plurality of binary symbols is encoded using a bypass mode of an entropy encoding engine.

[0128] According to another embodiment, an apparatus for video decoding is provided that includes one or more processors configured to decode a plurality of binary symbols from a bitstream, where a first binary symbol of the plurality of binary symbols is decoded using a bypass mode of an entropy decoding engine, decode the binary symbols and generate values ​​of syntax elements responsive to the plurality of binary symbols based on a binarization scheme. The apparatus may further include one or more memories coupled to the one or more processors.

[0129] According to another embodiment, an apparatus for video encoding is provided that includes one or more processors, the one or more processors configured to access a plurality of binary symbols indicative of a value of a syntax element and encode the plurality of binary symbols, wherein a first binary symbol of the plurality of binary symbols is encoded using a bypass mode of an entropy encoding engine.

[0130] According to another embodiment, an apparatus for video decoding is provided, the apparatus including: means for decoding a plurality of binary symbols from a bitstream, where a first binary symbol of the plurality of binary symbols is decoded using a bypass mode of an entropy decoding engine; and means for generating values ​​of syntax elements responsive to the plurality of binary symbols based on a binarization scheme.

[0131] According to another embodiment, an apparatus for video encoding is provided, comprising: means for accessing a plurality of binary symbols indicating a value of a syntax element; and means for encoding the plurality of binary symbols, wherein a first binary symbol of the plurality of binary symbols is encoded using a bypass mode of an entropy encoding engine.

[0132] According to another embodiment, a signal including encoded video is formed by accessing a plurality of binary symbols indicative of a value of a syntax element and encoding the plurality of binary symbols, wherein a first binary symbol of the plurality of binary symbols is encoded using a bypass mode of an entropy decoding engine.

[0133] According to one embodiment, one or more other binary symbols of the plurality of binary symbols are decoded or encoded using a bypass mode.

[0134] According to one embodiment, the remainder of the plurality of binary symbols is decoded or encoded in a context-based manner. Each binary symbol of the remainder of the plurality of binary symbols may use a different context model. In another embodiment, all binary symbols of the plurality of binary symbols are decoded or encoded using a bypass mode.

[0135] According to one embodiment, the binary flag is context-based encoded or decoded, and the value of the syntax element is generated further in response to the binary flag.

[0136] In one embodiment, the flag indicates whether equal weights are applied in generating the weighted average of the two temporal predictors of a block.

[0137] According to one embodiment, the syntax element indicates the index of the weight used in generating the weighted average of the two temporal predictors of the block.

[0138] In one embodiment, the syntax element indicates which motion vector predictor is used to encode or decode a motion vector for a block.

[0139] In one embodiment, it is determined whether Symmetric Motion Vector Difference (SMVD) is applied to the block, and the bypass mode is used only if SMVD is applied to the block.

[0140] In one embodiment, truncated Rice binarization is used as the binarization scheme.

[0141] In one embodiment, when sub-block transforms are used, syntax elements that indicate the location of a non-zero residual transform unit used to code the texture data of a current coding unit are encoded and decoded in bypass mode.

[0142] In one embodiment, a syntax element that indicates whether or not asymmetric binary splitting is used in the sub-block transform is encoded and decoded in bypass mode.

[0143] In one embodiment, the syntax element indicating the direction of the binary split used in the sub-block transform is encoded and decoded in bypass mode.

[0144] In one embodiment, syntax elements that indicate the direction of dividing the current coding unit into sub-partitions are encoded and decoded in bypass mode.

[0145] In one embodiment, the first bin used to represent a syntax element indicating which reference line is used for intra prediction is encoded and decoded in normal mode, and one or more remaining bins used to represent the syntax element are encoded and decoded in bypass mode.

[0146] In one embodiment, a syntax element that indicates whether a symmetric motion vector differential coding mode is used for the current coding unit is encoded and decoded in bypass mode.

[0147] Embodiments provide computer programs including instructions that, when executed by one or more processors, cause the one or more processors to perform an encoding or decoding method according to any of the above-described embodiments. One or more of the embodiments also provide a computer-readable storage medium having stored thereon instructions for encoding or decoding video data according to any of the above-described methods. One or more embodiments also provide a computer-readable storage medium having stored thereon a bitstream generated according to the above-described methods. One or more embodiments also provide methods and apparatus for transmitting or receiving a bitstream generated according to the above-described methods.

[0148] Various implementations involve decoding. "Decoding" as used in this application can encompass all or part of the processing performed on a received encoded sequence, for example to generate a final output suitable for display. In various embodiments, such processing includes one or more of the processing typically performed by a decoder, for example, entropy decoding, inverse quantization, inverse transform, and differential decoding. Whether the phrase "decoding processing" is intended to refer specifically to a subset of operations or to the broader decoding process in general will be clear based on the context of the particular description and will be well understood by one of ordinary skill in the art.

[0149] Various implementations involve encoding. Similar to the above discussion of "decoding," "encoding" as used in this application can encompass, for example, all or part of the processing performed on an input video sequence to generate an encoded bitstream.

[0150] It should be noted that the syntax elements used herein, e.g., the syntax used to characterize a GBi index, are descriptive terms, and therefore do not preclude the use of other syntax element names.

[0151] The implementations and aspects described herein can be implemented, for example, in a method or process, an apparatus, a software program, a data stream, or a signal. Even if discussed only in the context of a single implementation (e.g., discussed only as a method), the implementation of the discussed features may also be implemented in other forms (e.g., an apparatus or a program). The apparatus can be implemented, for example, in appropriate hardware, software, and firmware. The method can be implemented, for example, in an apparatus, for example, a processor, which generally refers to a processing device, including a computer, a microprocessor, an integrated circuit, or a programmable logic device. Processors also include communication devices, for example, computers, mobile phones, portable / personal digital assistance ("PDAs"), and other devices that facilitate the transfer of information between end users.

[0152] References to "one embodiment" or "one implementation" or "one implementation," as well as other variations thereof, mean that a particular feature, structure, characteristic, etc. described in connection with an embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in one embodiment" or "in one implementation," as well as any other variations, in various places throughout this application are not necessarily all referring to the same embodiment.

[0153] Additionally, the application may refer to "determining" various portions of information. Determining information may include, for example, one or more of estimating information, calculating information, predicting information, or retrieving information from a memory.

[0154] Additionally, the application may refer to "accessing" various portions of information. Accessing information may include, for example, one or more of receiving information, retrieving information (e.g., from a memory), storing information, moving information, copying information, calculating information, determining information, predicting information, or estimating information.

[0155] Additionally, the application may refer to "receiving" various portions of information. Receiving, like "accessing," is intended to be a broad term. Receiving information may include, for example, one or more of accessing information or retrieving information (e.g., from a memory). Additionally, "receiving" typically involves, in some manner, during operation, for example, storing information, processing information, transmitting information, moving information, copying information, erasing information, calculating information, determining information, predicting information, or estimating information.

[0156] For example, in the case of "A / B," "A and / or B," and "at least one of A and B," it should be understood that the use of any of the following " / ," "and / or," and "at least one of" is intended to encompass the selection of only the first listed option (A), or the selection of only the second listed option (B), or the selection of both options (A and B). As a further example, in the case of "A, B, and / or C" and "at least one of A, B, and C," such language is intended to encompass the selection of only the first listed option (A), or the selection of only the second listed option (B), or the selection of only the third listed option (C), or the selection of only the first and second listed options (A and B), or the selection of only the first and third listed options (A and C), or the selection of only the second and third listed options (B and C), or the selection of all three options (A and B and C). This may be expanded as many times as there are items listed, as would be apparent to one of skill in the art.

[0157] Also, as used herein, the word "signal" refers to, among other things, instructing a corresponding decoder to do something. For example, in a particular embodiment, the encoder signals the number of pieces in the piecewise linear model to the decoder. In this way, in an embodiment, the same parameters are used on both the encoder side and the decoder side. Thus, for example, the encoder can send a particular parameter to the decoder (explicit signaling), so that the decoder can use the same particular parameter. Conversely, if the decoder already has the particular parameter as well as other parameters, signaling can be used without sending (implicit signaling) to allow the decoder to easily recognize and select the particular parameter. By avoiding sending any actual function, bit savings are realized in various embodiments. It should be seen that signaling can be achieved in various ways. For example, one or more syntax elements, flags, etc. are used in various embodiments to signal information to the corresponding decoder. Although the above is about the verb form of the word "signaling", the word "signaling" can also be used as a noun in this specification.

[0158] As will be apparent to one of ordinary skill in the art, implementations can generate a wide variety of signals formatted to carry information that can be, for example, stored or transmitted. Information can include, for example, instructions to perform a method or data generated by one of the described implementations. For example, a signal can be formatted to carry a bit stream of the described embodiments. Such a signal can be formatted, for example, as an electromagnetic wave (e.g., using a radio frequency portion of the spectrum) or as a baseband signal. Formatting can include, for example, encoding a data stream and modulating a carrier wave with the encoded data stream. The information that the signal carries can be, for example, analog or digital information. The signal can be transmitted over a wide variety of different wired or wireless links, as is known. The signal can be stored on a processor-readable medium.

Claims

1. 1. A method comprising: decoding a plurality of binary symbols from a bitstream, wherein a first binary symbol of the plurality of binary symbols is entropy decoded using a context-based mode and each binary symbol following the first binary symbol is entropy decoded in a bypass mode; obtaining an index represented by the plurality of binary symbols corresponding to a binarization scheme; forming a prediction of the block as a weighted sum of two predictors, the index indicating respective weighting coefficients used to weight the two predictors when forming the weighted sum.

2. The method of claim 1 , wherein the binarization scheme is a truncated Rice binarization scheme.

3. The method of claim 1 or 2, wherein the index indicates a weighting factor from a set of weighting factors for weighting one of the two predictors when forming the weighted sum.

4. 4. The method of claim 3, wherein a different weighting factor is obtained in response to the weighting factor, the different weighting factor being used to weight a different one of the two predictors when forming the weighted sum.

5. The method of any one of claims 1 to 4, wherein the first binary symbol indicates whether or not equal weights are applied to the two predictors when forming the weighted sum.

6. 6. The method of claim 1, wherein the second binary symbol of the plurality of binary symbols indicates whether a weighting factor of 5 is applied to one of the two predictors when forming the weighted sum.

7. 7. The method of claim 1, wherein the third binary symbol of the plurality of binary symbols indicates whether a weighting factor of three is applied to one of the two predictors when forming the weighted sum.

8. 1. A method comprising: Accessing a block to be encoded; forming a prediction of said block as a weighted sum of two predictors; and encoding an index to indicate each weighting factor used to weight the two predictors when forming the weighted sum; the index is binarized into a plurality of binary symbols using a binarization scheme; the first binary symbol of the plurality of binary symbols is entropy coded using a context-based mode; A method according to claim 1, wherein each binary symbol following the first binary symbol is entropy coded in bypass mode.

9. The method of claim 8 , wherein the binarization scheme is a truncated Rice binarization scheme.

10. 10. The method of claim 8 or 9, wherein the index indicates a weighting factor from a set of weighting factors for weighting one of the two predictors when forming the weighted sum.

11. 11. The method of claim 10, wherein a different weighting factor is obtained in response to the weighting factor, the different weighting factor being used to weight a different one of the two predictors when forming the weighted sum.

12. A method according to any one of claims 8 to 11, wherein the first binary symbol indicates whether or not equal weights are applied to the two predictors when forming the weighted sum.

13. 13. The method of claim 8, wherein the second binary symbol of the plurality of binary symbols indicates whether a weighting factor of 5 is applied to one of the two predictors when forming the weighted sum.

14. 14. The method of claim 8, wherein the third binary symbol of the plurality of binary symbols indicates whether a weighting factor of three is applied to one of the two predictors when forming the weighted sum.

15. 1. An apparatus including one or more processors, the one or more processors comprising: decoding a plurality of binary symbols from a bitstream, wherein a first binary symbol of the plurality of binary symbols is entropy decoded using a context-based mode and each binary symbol following the first binary symbol is entropy decoded in a bypass mode; obtaining an index represented by the plurality of binary symbols corresponding to a binarization scheme; forming a prediction of a block as a weighted sum of two predictors, the index indicating respective weighting coefficients used to weight the two predictors when forming the weighted sum.

16. 16. The apparatus of claim 15, wherein the binarization scheme is a truncated Rice binarization scheme.

17. 17. The apparatus of claim 15 or 16, wherein the index indicates a weighting factor from a set of weighting factors for weighting one of the two predictors when forming the weighted sum.

18. 20. The apparatus of claim 17, wherein a further weighting factor is obtained in response to the weighting factor, the further weighting factor being used to weight a further one of the two predictors when forming the weighted sum.

19. Apparatus according to any one of claims 15 to 18, wherein the first binary symbol indicates whether or not equal weights are applied to the two predictors when forming the weighted sum.

20. 20. The apparatus of claim 15, wherein the second binary symbol of the plurality of binary symbols indicates whether a weighting factor of 5 is applied to one of the two predictors when forming the weighted sum.

21. 21. The apparatus of claim 15, wherein the third binary symbol of the plurality of binary symbols indicates whether a weighting factor of three is applied to one of the two predictors when forming the weighted sum.

22. 1. An apparatus including one or more processors, the one or more processors comprising: Accessing the block to be encoded forming a prediction for the block as a weighted sum of two predictors; configured to encode an index to indicate each weighting factor used to weight the two predictors when forming the weighted sum; the index is binarized into a plurality of binary symbols using a binarization scheme; the first binary symbol of the plurality of binary symbols is entropy coded using a context-based mode; An apparatus, wherein each binary symbol following the first binary symbol is entropy coded in bypass mode.

23. 23. The apparatus of claim 22, wherein the binarization scheme is a truncated Rice binarization scheme.

24. 24. The apparatus of claim 22 or 23, wherein the index indicates a weighting factor from a set of weighting factors for weighting one of the two predictors when forming the weighted sum.

25. 25. The apparatus of claim 24, wherein a different weighting factor is obtained in response to the weighting factor, the different weighting factor being used to weight a different one of the two predictors when forming the weighted sum.

26. An apparatus as claimed in any one of claims 22 to 25, wherein the first binary symbol indicates whether or not equal weights are applied to the two predictors when forming the weighted sum.

27. 27. The apparatus of claim 22, wherein the second binary symbol of the plurality of binary symbols indicates whether a weighting factor of 5 is applied to one of the two predictors when forming the weighted sum.

28. 28. The apparatus of claim 22, wherein the third binary symbol of the plurality of binary symbols indicates whether a weighting factor of three is applied to one of the two predictors when forming the weighted sum.

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