Display device

Abstract

To provide a display device including more uniformly aligned light-emitting elements.SOLUTION: A pixel circuit layer of a display device is arranged on a base layer and includes conductive patterns configuring at least one of a transistor, a capacitor, and a signal line. A first electrode and a second electrode are arranged on the pixel circuit layer and are spaced from each other. A bank is arranged on the first electrode and the second electrode, and includes an opening. A light emitting element is arranged between the first electrode and the second electrode in the opening of the bank. In the opening of the bank, a space between the first electrode and the second electrode spaced apart from each other by a distance corresponding to a length of the light emitting element is defined as a lane where the light emitting element is arranged. In a plan view, the lane is arranged spaced apart from all the conductive patterns of the pixel circuit layer, and is spaced apart from by half or more of the length of the light emitting element from the conductive pattern.SELECTED DRAWING: Figure 10

Description

[Technical field]

[0001] The present invention relates to a display device. [Background technology]

[0002] 2. Description of the Related Art As interest in information displays increases and the demand for portable information media increases, the demand for display devices increases and commercialization of display devices is attracting attention. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Korean Patent Publication No. 2018-0011404 [Patent Document 2] Korean Patent Publication No. 2017-0141305 Summary of the Invention [Problem to be solved by the invention]

[0004] It is an object of the present invention to provide a display device that includes more uniformly aligned light emitting elements. [Means for solving the problem]

[0005] A display device according to an embodiment of the present invention includes a pixel circuit layer disposed on a base layer and including a conductive pattern constituting at least one of a transistor, a capacitor, and a signal line, a first electrode and a second electrode disposed on the pixel circuit layer and spaced apart from each other, a bank disposed on the first electrode and the second electrode and including an opening, and a light-emitting element disposed between the first electrode and the second electrode in the opening of the bank. A space between the first electrode and the second electrode, which are spaced apart from each other by a distance corresponding to the length of the light-emitting element, in the opening of the bank is defined as a lane in which the light-emitting element is disposed. In a plan view, the lane is disposed apart from all conductive patterns of the pixel circuit layer and is spaced apart from the conductive pattern by at least half the length of the light-emitting element.

[0006] The length of the light emitting element may be 10 μm or less, and in a plan view, the lane may be spaced apart from the conductive pattern by a distance of 6 μm or more.

[0007] In the display device, the pixel circuit layer may further include an insulating layer, and portions of the conductive patterns may be connected to each other via contact holes penetrating a portion of the insulating layer, and in a planar view, the lanes may be spaced apart from all of the contact holes by a distance equal to or greater than half the length of the light-emitting element.

[0008] The display device may further include sub-pixels each including the lane, the conductive pattern may include a first line extending in a second direction, and a first sub-pixel and a second sub-pixel adjacent to each other in the first direction across the first line may have structures symmetrical to each other with respect to the first line in a planar view.

[0009] The first sub-pixel and the second sub-pixel may share the first line.

[0010] The first lines may be repeatedly arranged along the first direction at intervals corresponding to two of the sub-pixels.

[0011] The conductive pattern may include a first power line and a second power line extending in the first direction, the light emitting element may be electrically connected between the first power line and the second power line, the first power line and the second power line may be spaced apart from each other at a distance corresponding to two of the sub-pixels, and the first power line and the second power line may be repeatedly arranged along the first direction at a distance corresponding to four of the sub-pixels.

[0012] Each of the first power line and the second power line may include three conductive layers spaced apart by insulating layers.

[0013] The conductive pattern may further include a first auxiliary power line and a second auxiliary power line extending in the first direction, the first auxiliary power line being electrically connected to the first power line, and the second auxiliary power line being electrically connected to the second power line.

[0014] The first electrodes and the second electrodes may extend in the second direction and be arranged alternately and repeatedly along the first direction, and the first electrodes may be electrically connected to the first power line via a first connection line and a first contact hole extending in the first direction.

[0015] The conductive pattern may include a first auxiliary power line extending in a first direction, and a first capacitor and a second capacitor spaced apart in a second direction across the first auxiliary power line in a planar view, and the first capacitor and the second capacitor may be electrically connected in parallel.

[0016] The display device may further include a connecting electrode arranged on the light-emitting elements, the lanes including a first lane, a second lane, a third lane, and a fourth lane spaced apart from one another within the opening of the bank, the light-emitting elements including a first light-emitting element located in the first lane, a second light-emitting element located in the second lane, a third light-emitting element located in the third lane, and a fourth light-emitting element located in the fourth lane, and the first to fourth light-emitting elements may be electrically connected in series via the connecting electrode.

[0017] A portion of the connecting electrodes may include a closed loop.

[0018] The display device may further include color conversion particles disposed on the light emitting element for converting a wavelength of light from the light emitting element and diffusing the converted light, and a color filter disposed on the color conversion particles.

[0019] The conductive pattern may include a first auxiliary power line extending in a first direction, and in a planar view, the lane of a subpixel may be arranged in a region different from the transistor and capacitor of the pixel circuit layer of the subpixel relative to the first auxiliary power line.

[0020] The display device may further include first sub-pixels and second sub-pixels each including the lane, the conductive pattern may include first lines extending in a second direction, and the first sub-pixels and second sub-pixels adjacent to each other across two of the first lines may have structures symmetrical to each other in a planar view.

[0021] Three of the first lines may be coupled to one pad.

[0022] The display device may further include sub-pixels each including the lane, the conductive pattern may include first lines extending in a second direction, a first sub-pixel and a second sub-pixel adjacent to each other across one of the first lines may have structures symmetrical to each other with respect to the first line in a planar view, and at least two of the first lines may be connected to one pad.

[0023] A display device according to an embodiment of the present invention includes sub-pixels arranged along a first direction, and a signal line extending in a second direction between a pair of adjacent sub-pixels among the sub-pixels. Each of the sub-pixels includes a pixel circuit including a transistor and a capacitor, a first electrode and a second electrode electrically connected to the pixel circuit and spaced apart from each other in a plan view, and a light emitting element disposed in a lane between the first electrode and the second electrode. A conductive pattern may not be disposed in the lane. The pair of sub-pixels may be commonly connected to the signal line and have a structure symmetrical to each other with respect to the signal line.

[0024] In a planar view, with respect to a first line extending in a first direction, the lanes are arranged in a region different from the transistors, and the pixel circuit includes a first capacitor and a second capacitor spaced apart in a second direction across the first line, and the first capacitor and the second capacitor may be electrically connected in parallel. Effect of the Invention

[0025] In a display device according to an embodiment of the present invention, a conductive pattern (e.g., a transistor, a capacitor, a contact hole) of a pixel circuit layer may be disposed at a certain distance from a lane in which a light emitting device is disposed. Therefore, the influence of the conductive pattern on an electrical signal (e.g., an electric field, etc.) for aligning the light emitting device LD may be reduced, and the alignment of the light emitting device may be improved. That is, the display device may include light emitting devices that are more uniformly aligned.

[0026] The effects of one embodiment of the present invention are not limited to the above-mentioned examples, and various other effects are included in this specification. [Brief description of the drawings]

[0027] [Figure 1] 1 is a perspective view showing a light emitting device according to an embodiment of the present invention; [Diagram 2] 1 is a cross-sectional view showing a light emitting device according to an embodiment of the present invention. [Diagram 3] 1 is a plan view showing a display device according to an embodiment of the present invention; [Figure 4] 4 is a circuit diagram showing an embodiment of a sub-pixel included in the display device of FIG. 3. [Diagram 5] FIG. 4 is a cross-sectional view showing an embodiment of the display device of FIG. [Figure 6] 4 is a plan view illustrating an embodiment of a sub-pixel included in the display device of FIG. 3. [Figure 7] 7 is a cross-sectional view showing an embodiment of a sub-pixel taken along line II' in FIG. 6. [Figure 8] 7 is a cross-sectional view showing an embodiment of a sub-pixel taken along line II' in FIG. 6. [Figure 9] 4 is a cross-sectional view showing an embodiment of a pixel included in the display device of FIG. 3. [Figure 10] 2 is a schematic cross-sectional view illustrating a positional relationship between an alignment electrode layer and a lower line according to an embodiment of the present invention; [Figure 11] FIG. 4 is a plan view showing an embodiment of the display device of FIG. [Figure 12] 12 is a layout diagram showing an embodiment of first and second sub-pixels included in the display device of FIG. 11. FIG. [Figure 13] 13 is a cross-sectional view showing an embodiment of a storage capacitor taken along line II-II' in FIG. 12. [Figure 14] 12 is a layout diagram showing an embodiment of first and second sub-pixels included in the display device of FIG. 11. FIG. [Figure 15] 12 is a layout diagram showing an embodiment of first and second sub-pixels included in the display device of FIG. 11. FIG. [Figure 16] 12 is a layout diagram showing an embodiment of first and second sub-pixels included in the display device of FIG. 11. FIG. [Figure 17] 12 is a layout diagram showing another embodiment of the first and second sub-pixels included in the display device of FIG. 11. FIG. [Figure 18] 4 is a layout diagram showing an embodiment of first and second sub-pixels included in the display device of FIG. 3. [Figure 19] 4 is a layout diagram showing an embodiment of first and second sub-pixels included in the display device of FIG. 3. [Figure 20] FIG. 4 is a plan view showing an embodiment of the display device of FIG. [Figure 21] FIG. 4 is a plan view showing an embodiment of the display device of FIG. [Figure 22] FIG. 4 is a plan view showing an embodiment of the display device of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] Although the present invention can be modified in various ways and can be implemented in various forms, only specific examples are illustrated in the drawings and the present invention will be described based on them. However, the present invention is not limited to such specific disclosure, and it is understood that the present invention includes all modifications, equivalents, or alternatives included in the spirit and technical scope of the present disclosure.

[0029] Terms such as first and second are used to describe various components, but the components are not limited by the terms. The terms are used to distinguish one component from another component. For example, the first component may be called the second component without departing from the scope of the present invention. Similarly, the second component may be called the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0030] In this application, the terms "comprise" or "have" refer to features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, and do not preclude the possibility of one or more other features, numbers, steps, operations, components, parts, or combinations thereof or additional features. In addition, when a layer, film, region, plate, or other part is described as being "on" another part, this includes not only the case where it is "directly on" the other part, but also the case where another part is located between them. In addition, in this specification, when a layer, film, region, plate, or other part is described as being formed on another part, the formed direction is not limited to the upper direction, but also includes the case where it is formed on the side or lower direction. In addition, when a layer, film, region, plate, or other part is described as being "under" another part, this includes not only the case where it is "directly under" the other part, but also the case where another part is located between them.

[0031] In the following description, when a part is said to be connected to another part, this includes not only a direct connection but also an electrical connection with another element therebetween. In one embodiment of the present invention, the "connection" between two components can be used to mean both an electrical connection and a physical connection.

[0032] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a display device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0033] Fig. 1 is a perspective view of a light emitting device according to an embodiment of the present invention, and Fig. 2 is a cross-sectional view of a light emitting device according to an embodiment of the present invention.

[0034] 1 and 2, the light emitting element LD is configured to emit light. The light emitting element LD may include a first semiconductor layer SCL1, a second semiconductor layer SCL2, and an active layer AL disposed between the first semiconductor layer SCL1 and the second semiconductor layer SCL2. According to an embodiment of the present invention, the first semiconductor layer SCL1, the active layer AL, and the second semiconductor layer SCL2 may be sequentially stacked along a length L direction of the light emitting element LD. According to an embodiment of the present invention, the light emitting element LD may further include an electrode layer ELL and an insulating film INF.

[0035] The light emitting element LD can have various shapes. For example, the light emitting element LD can have a columnar shape extending in one direction. The columnar shape can include a rod-like shape or a bar-like shape that is long in the length L direction (for example, the aspect ratio is greater than 1), such as a circular cylinder or a polygonal prism, and the shape of the cross section is not particularly limited.

[0036] The light emitting element LD may have a first end EP1 and a second end EP2. According to an embodiment of the present invention, the first end EP1 of the light emitting element LD may be adjacent to a first semiconductor layer SCL1, and the second end EP2 may be adjacent to a second semiconductor layer SCL2. According to an embodiment of the present invention, the first end EP1 may be adjacent to an electrode layer ELL.

[0037] The light emitting element LD can be manufactured by etching the semiconductor layers that are sequentially stacked. The light emitting element LD can have a size on the nanoscale to the microscale. For example, the diameter D (or width) of the light emitting element LD and the length L of the light emitting element LD can each have a size on the nanoscale to the microscale. For example, the diameter D of the light emitting element LD can be about 0.2 μm to about 5 μm, and the length of the light emitting element LD can be about 1 μm to about 10 μm. For example, the diameter D of the light emitting element LD can be about 0.5 μm to about 0.6 μm, and the length of the light emitting element LD can be about 3.5 μm to about 4 μm. However, the light emitting element LD is not limited thereto.

[0038] The first semiconductor layer SCL1 may include a semiconductor of a first conductive type. The first semiconductor layer SCL1 may be disposed on the active layer AL and may include a semiconductor layer of a different type from the second semiconductor layer SCL2. For example, the first semiconductor layer SCL1 may include a p-type semiconductor layer. For example, the first semiconductor layer SCL1 may include one or more semiconductor materials selected from the group of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a first conductive type dopant such as Ga, B, and Mg. However, the present disclosure is not limited to the above examples. The first semiconductor layer SCL1 may include various materials.

[0039] The active layer AL may be disposed between the first semiconductor layer SCL1 and the second semiconductor layer SCL2. The active layer AL may include a single-quantum well or a multi-quantum well structure. The position of the active layer AL is not limited to a specific example and may be variously changed according to the type of the light emitting device LD.

[0040] A cladding layer doped with a conductive dopant may be formed on one side and / or the other side of the active layer AL. For example, the cladding layer may include one or more of AlGaN and InAlGaN. However, the present disclosure is not necessarily limited to the above examples.

[0041] The second semiconductor layer SCL2 may include a semiconductor of a second conductive type. The second semiconductor layer SCL2 may be disposed on the active layer AL and may include a semiconductor layer of a different type from the first semiconductor layer SCL1. For example, the second semiconductor layer SCL2 may include an n-type semiconductor layer. For example, the second semiconductor layer SCL2 may include one or more selected from the group of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include an n-type semiconductor layer doped with a second conductive type dopant such as Si, Ge, and Sn. However, the present disclosure is not limited to the above examples. The second semiconductor layer SCL2 may include various materials.

[0042] When a voltage equal to or greater than a threshold voltage is applied to the first end EP1 and the second end EP2 of the light emitting device LD, electron-hole pairs in the active layer AL can be combined with each other, and the light emitting device LD can emit light. By controlling the emission of the light emitting device LD using this principle, the light emitting device LD can be used as a light source in various devices.

[0043] The insulating film INF may be disposed on one surface of the light emitting element LD. The insulating film INF may surround the outer surface of the active layer AL and may further surround a portion of each of the first semiconductor layer SCL1 and the second semiconductor layer SCL2. The insulating film INF may have a single layer or a multi-layer structure.

[0044] The insulating film INF can expose the first end EP1 and the second end EP2 of the light emitting element LD having different polarities. For example, the insulating film INF can expose one end of each of the electrode layer ELL and the second semiconductor layer SCL2 adjacent to the first end EP1 and the second end EP2 of the light emitting element LD. The insulating film INF can ensure the electrical stability of the light emitting element LD. In addition, the insulating film INF can minimize surface defects of the light emitting element LD to improve its lifespan and efficiency. In addition, when a large number of light emitting elements LD are arranged closely to each other, the insulating film INF can prevent a short circuit (e.g., a short circuit) between the light emitting elements LD.

[0045] According to an embodiment of the present invention, the insulating film INF may include an inorganic material. For example, the inorganic material may be silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), and titanium oxide (TiO x ), but the inorganic material may include, but is not limited to, one or more of the following group:

[0046] The electrode layer ELL may be disposed on the first semiconductor layer SCL1. The electrode layer ELL may be adjacent to the first end EP1. The electrode layer ELL may be electrically connected to the first semiconductor layer SCL1. A portion of the electrode layer ELL may be exposed. For example, the insulating film INF may expose one surface of the electrode layer ELL. The electrode layer ELL may be exposed in a region corresponding to the first end EP1. According to an embodiment of the present invention, a side surface of the electrode layer ELL may be exposed. For example, the insulating film INF may not cover at least a portion of the side surface of the electrode layer ELL while covering each of the side surfaces of the first semiconductor layer SCL1, the active layer AL, and the second semiconductor layer SCL2. In this case, electrical connection to other components of the electrode layer ELL adjacent to the first end EP1 may be easy. According to an embodiment of the present invention, the insulating film INF may expose not only the side surface of the electrode layer ELL but also a portion of the side surface of the first semiconductor layer SCL1 and / or the second semiconductor layer SCL2.

[0047] According to an embodiment of the present invention, the electrode layer ELL may be an ohmic contact electrode. However, the electrode layer ELL is not limited thereto. For example, the electrode layer ELL may be a Schottky contact electrode.

[0048] According to an embodiment of the present invention, the electrode layer ELL may include one or more of the group consisting of chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), oxides thereof, and alloys thereof. However, the present disclosure is not necessarily limited to the above examples. According to an embodiment of the present invention, the electrode layer ELL may be substantially transparent. For example, the electrode layer ELL may include indium tin oxide (ITO). This allows the electrode layer ELL to transmit the emitted light.

[0049] The structure and shape of the light emitting element LD are not limited to the above embodiment, and the light emitting element LD may have various structures and shapes according to an embodiment of the present invention. For example, the light emitting element LD may further include an additional electrode layer disposed on one surface of the second semiconductor layer SCL2 and adjacent to the second end EP2. For example, the light emitting element LD may be formed in a core-shell structure having a polygonal pyramid shape.

[0050] The light emitting device including the light emitting element LD described above can be used in various types of devices that require a light source, including a display device. For example, a plurality of light emitting elements LD can be arranged in each pixel of a display panel, and the light emitting elements LD can be used as a light source for each pixel. However, the application field of the light emitting element LD is not limited to the above example. For example, the light emitting element LD can be used in other types of devices that require a light source, such as a lighting device.

[0051] Fig. 3 is a plan view showing a display device according to an embodiment of the present invention, in particular, a display panel PNL provided in the display device, as an example of an electronic device that can use the light emitting element LD described in the embodiment of Fig. 1 and Fig. 2 as a light source.

[0052] For convenience of explanation, the structure of the display panel PNL is simply illustrated with a display area DA at the center in Fig. 3. According to an embodiment of the present invention, at least one driving circuit unit (for example, at least one of a scan driving unit and a data driving unit), wiring and / or pads may be further disposed on the display panel PNL.

[0053] The present invention can be applied to any electronic device having at least one display surface, such as a smartphone, television, tablet PC, mobile phone, video phone, e-book reader, desktop PC, laptop PC, netbook computer, workstation, server, PDA, portable multimedia player (PMP), MP3 player, medical equipment, camera, or wearable device.

[0054] Referring to FIG. 3, the display panel PNL may include a base layer BSL and pixels PXL disposed on the base layer BSL.

[0055] The base layer BSL (or substrate) constitutes a base member of the display panel PNL and may be a hard or soft substrate or film. For example, the base layer BSL may be a hard substrate made of glass or tempered glass, a soft substrate (or thin film) made of plastic or metal, or at least one insulating layer. The material and / or physical properties of the base layer BSL are not particularly limited.

[0056] In one embodiment of the present invention, the base layer BSL may be substantially transparent. Here, being substantially transparent may mean that light can be transmitted at a certain transmittance or more. In other embodiments, the base layer BSL may be semi-transparent or opaque. The base layer BSL may also include a reflective material depending on the embodiment.

[0057] The display panel PNL and the base layer BSL for forming the display panel PNL can include a display area DA for displaying an image and a non-display area NDA excluding the display area DA.

[0058] The pixels PXL may be arranged in the display area DA, and various wirings, pads and / or built-in circuit units connected to the pixels PXL of the display area DA may be arranged in the non-display area NDA.

[0059] The pixel PXL includes sub-pixels SPXL1 to SPXL3, and for example, the pixel PXL may include a first sub-pixel SPXL1, a second sub-pixel SPXL2, and a third sub-pixel SPXL3.

[0060] The sub-pixels SPXL1 to SPXL3 may each emit light of a predetermined color. According to an embodiment of the present invention, the sub-pixels SPXL1 to SPXL3 may emit light of different colors. As an example, the first sub-pixel SPXL1 may emit light of a first color, the second sub-pixel SPXL2 may emit light of a second color, and the third sub-pixel SPXL3 may emit light of a third color. For example, the first sub-pixel SPXL1 may be a red pixel that emits red light, the second sub-pixel SPXL2 may be a green pixel that emits green light, and the third sub-pixel SPXL3 may be a blue pixel that emits blue light, but is not limited thereto.

[0061] In one embodiment of the present invention, the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 each include a first color light-emitting element, a second color light-emitting element, and a third color light-emitting element as a light source, and can emit light of the first color, the second color, and the third color, respectively. In another embodiment, the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 each include a light-emitting element that emits light of the same color, and can also emit light of the first color, the second color, and the third color, respectively, by including color conversion layers and / or color filters of different colors disposed on each light-emitting element. However, the colors, types, and / or numbers of the sub-pixels SPXL1 to SPXL3 constituting each pixel PXL are not particularly limited. That is, the color of light emitted by each pixel PXL can be changed in various ways.

[0062] The sub-pixels SPXL1 to SPXL3 may be regularly arranged in a stripe or PENTILE™ arrangement structure. For example, the first, second and third sub-pixels SPXL1, SPXL2 and SPXL3 may be sequentially and repeatedly arranged along a first direction DR1 and may also be repeatedly arranged along a second direction DR2. At least one of the first, second and third sub-pixels SPXL1, SPXL2 and SPXL3 arranged adjacent to each other may constitute one pixel PXL capable of emitting light of various colors. However, the arrangement structure of the sub-pixels SPXL1 to SPXL3 is not limited thereto, and the sub-pixels SPXL1 to SPXL3 may be arranged in various structures and / or manners in the display area DA.

[0063] In one embodiment of the present invention, each of the sub-pixels SPXL1 to SPXL3 may be configured as an active pixel. For example, each of the sub-pixels SPXL1 to SPXL3 may include at least one light source (e.g., a light-emitting element) driven by a predetermined control signal (e.g., a scanning signal and a data signal) and / or a predetermined power supply (e.g., a first power supply and a second power supply). However, the type, structure and / or driving method of the sub-pixels SPXL1 to SPXL3 that can be applied to the display device are not particularly limited.

[0064] Fig. 4 is a circuit diagram showing an embodiment of a sub-pixel included in the display device of Fig. 3. The sub-pixels SPXL1 to SPXL3 of Fig. 3 are collectively referred to as sub-pixel SPXL.

[0065] 4, the sub-pixel SPXL may include a light emitting unit EMU (or light emitting unit) that generates light having a luminance corresponding to a data signal. The sub-pixel SPXL may further include a pixel circuit PXC for driving the light emitting unit EMU.

[0066] According to an embodiment of the present invention, the light emitting unit EMU may include a plurality of light emitting elements LD connected in parallel between a first power line PL1 and a second power line PL2. A voltage of a first driving power supply VDD may be applied to the first power line PL1, and a voltage of a second driving power supply VSS may be applied to the second power line PL2.

[0067] For example, the light emitting unit EMU may include a first pixel electrode PE1 (or a first electrode) connected to a first driving power supply VDD via a pixel circuit PXC and a first power supply line PL1, a second pixel electrode PE2 (or a second electrode) connected to a second driving power supply VSS via a second power supply line PL2, and a plurality of light emitting elements LD connected in parallel in the same direction between the first pixel electrode PE1 and the second pixel electrode PE2. For example, the first pixel electrode PE1 may be an anode electrode of the light emitting unit EMU, and the second pixel electrode PE2 may be a cathode electrode of the light emitting unit EMU, but is not limited thereto.

[0068] Each of the light emitting elements LD included in the light emitting unit EMU may include a first end connected to a first driving power supply VDD via a first pixel electrode PE1 and a second end connected to a second driving power supply VSS via a second pixel electrode PE2. The first driving power supply VDD and the second driving power supply VSS may have different potentials. For example, the first driving power supply VDD may be set to a high potential power supply, and the second driving power supply VSS may be set to a low potential power supply. At this time, the potential difference between the first and second driving power supplies VDD and VSS may be set to be equal to or higher than a threshold voltage of the light emitting element LD during the light emitting period of each sub-pixel SPXL. Each of the first driving power supply VDD and the second driving power supply VSS may have a constant voltage, but is not limited thereto.

[0069] As described above, each light emitting element LD connected in parallel in the same direction (for example, the forward direction) between the first pixel electrode PE1 and the second pixel electrode PE2 to which different power supply voltages are supplied can constitute a respective effective light source.

[0070] The light emitting element LD of the light emitting unit EMU can emit light with a luminance corresponding to a driving current supplied via a corresponding pixel circuit PXC. For example, the pixel circuit PXC can supply a driving current corresponding to a gray scale value of the corresponding frame data of the pixel circuit PXC to the light emitting unit EMU during each frame period. The driving current supplied to the light emitting unit EMU can flow separately to each light emitting element LD. As a result, each light emitting element LD can emit light with a luminance corresponding to the current flowing through the light emitting unit LD, and the light emitting unit EMU can emit light with a luminance corresponding to the driving current.

[0071] In the above embodiment, both ends of the light emitting element LD are connected in the same direction between the first and second driving power sources VDD and VSS, but the present invention is not limited thereto. According to an embodiment of the present invention, the light emitting unit EMU may further include at least one non-effective light source, for example, a backward light emitting element, in addition to the light emitting element LD constituting each effective light source. Such a backward light emitting element may be connected in parallel between the first and second pixel electrodes PE1 and PE2 together with the light emitting element LD constituting the effective light source, and may be connected between the first and second pixel electrodes PE1 and PE2 in the opposite direction to the light emitting element LD. Such a backward light emitting element maintains an inactive state even when a predetermined driving voltage (for example, a forward driving voltage) is applied between the first and second connecting electrodes CNE1 and CNE2, so that substantially no current flows through the backward light emitting element.

[0072] According to an embodiment of the present invention, the light emitting unit EMU may be configured with a series / parallel mixed structure. For example, when the light emitting element LD connected in parallel between the first pixel electrode PE1 and the second pixel electrode PE2 shown in FIG. 4 is defined as one series stage, the light emitting unit EMU may include a plurality of series stages connected in series between the second node N2 and the second power line PL2. For example, the light emitting unit EMU may include two, three, four or more series stages. The number of series stages included in the light emitting unit EMU may be changed in various ways. The light emitting unit EMU including the series stages connected in a series / parallel structure may easily adjust the driving current / voltage conditions according to the applied product specifications. The more the number of series stages, the more the driving current may be reduced. In other words, the more the number of series stages, the higher the luminance the light emitting unit EMU may emit light for the same driving current. Also, the less the number of series stages, the more the driving voltage applied to both ends of the light emitting unit EMU may be reduced.

[0073] The pixel circuit PXC may be connected to the scan line SL (or the first gate line) and the data line DL of the sub-pixel SPXL. Also, the pixel circuit PXC may be connected to the sensing scan line SSL (or the second gate line) and the sensing line SENL (or the readout line) of the sub-pixel SPXL. According to an embodiment of the present invention, the sensing scan line SSL may be connected to the scan line SL or may be the scan line SL.

[0074] The pixel circuit PXC may include transistors M1 to M3 and a storage capacitor CST (or a capacitor).

[0075] The first transistor M1 is a driving transistor for controlling a driving current applied to the light emitting unit EMU, and may be connected between a first driving power supply VDD and the light emitting unit EMU. Specifically, a first terminal (or a first transistor electrode) of the first transistor M1 may be electrically connected to a first driving power supply VDD via a first power supply line PL1, a second terminal (or a second transistor electrode) of the first transistor M1 may be electrically connected to a second node N2, and a gate electrode of the first transistor M1 may be electrically connected to the first node N1. The first transistor M1 may control the amount of driving current applied to the light emitting unit EMU from the first driving power supply VDD via the second node N2 according to a voltage applied to the first node N1. In the embodiment, the first terminal of the first transistor M1 may be a drain electrode, and the second terminal of the first transistor M1 may be a source electrode, but is not limited thereto. According to an embodiment of the present invention, the first terminal may be a source electrode, and the second terminal may be a drain electrode.

[0076] According to an embodiment of the present invention, a bottom electrode BGE may be disposed under the first transistor M1. In this case, a back-bias technique may be applied to apply a back-bias voltage to the bottom electrode BGE when driving the sub-pixel SPXL, thereby shifting the threshold voltage of the first transistor M1 in a negative or positive direction.

[0077] The second transistor M2 may be connected between the data line DL and the first node N1 as a switching transistor for selecting the sub-pixel SPXL in response to a scan signal and activating the sub-pixel SPXL. A first terminal of the second transistor M2 may be connected to the data line DL, a second terminal of the second transistor M2 may be connected to the first node N1, and a gate electrode of the second transistor M2 may be connected to the scan line SL. The first and second terminals of the second transistor M2 may be different terminals, for example, the first terminal may be a source electrode and the second terminal may be a drain electrode.

[0078] The second transistor M2 is turned on when a scan signal having a gate-on voltage (for example, a high level voltage) is supplied from the scan line SL, and can electrically connect the data line DL to the first node N1. The first node N1 is a point where the second terminal of the second transistor M2 and the gate electrode of the first transistor M1 are connected, and the second transistor M2 can transmit a data signal to the gate electrode of the first transistor M1.

[0079] A first terminal of the third transistor M3 is connected to the sensing line SENL, a second terminal of the third transistor M3 is connected to the second terminal of the first transistor M1, and a gate electrode of the third transistor M3 is connected to the sensing scan line SSL. An initialization power supply may be applied to the sensing line SENL. The third transistor M3 is an initialization transistor capable of initializing the second node N2, and is turned on when a sensing control signal is supplied from the sensing scan line SSL, and may transmit a voltage of the initialization power supply to the second node N2. Thus, a second storage electrode of the storage capacitor CST electrically connected to the second node N2 may be initialized. According to an embodiment of the present invention, the third transistor M3 may detect characteristics of the sub-pixel SPXL, including a threshold voltage of the first transistor M1, by connecting the first transistor M1 to the sensing line SENL, so that a sensing signal is output via the sensing line SENL. Information regarding the characteristics of the sub-pixel SPXL may be used to convert image data so that characteristic deviations between the sub-pixels SPXL may be compensated for.

[0080] The storage capacitor CST may be electrically connected between the first node N1 and the second node N2 or may be formed between the first node N1 and the second node N2. The storage capacitor CST charges a data voltage corresponding to a data signal supplied to the first node N1 during one frame period. Thus, the storage capacitor CST may store a voltage corresponding to a voltage difference between the gate electrode voltage of the first transistor M1 and the second node N2.

[0081] 4, the transistors M1 to M3 included in the pixel circuit PXC are all n-type transistors, but the present invention is not limited to this. For example, at least one of the transistors M1 to M3 may be changed to a p-type transistor.

[0082] In addition, the structure and driving method of the sub-pixel SPXL may be modified in various ways. As an example, the pixel circuit PXC may not include the third transistor M3. As another example, the pixel circuit PXC may further include other circuit elements such as a compensation transistor for compensating for the threshold voltage of the first transistor M1, an initialization transistor for initializing the voltage of the first node N1 and / or the first pixel electrode PE1, an emission control transistor for controlling a period during which a driving current is supplied to the emission unit EMU, and / or a boost capacitor for boosting the voltage of the first node N1.

[0083] Fig. 5 is a cross-sectional view showing one embodiment of the display device of Fig. 3. Fig. 5 shows a schematic diagram of a laminated structure of a display panel PNL provided in the display device.

[0084] Referring to FIG. 5, the display panel PNL may include a lower electrode layer BML (or auxiliary electrode layer), a buffer layer BFL, an active layer ACT (or semiconductor layer), a gate insulating layer GI, a first conductive layer ICL1, an interlayer insulating layer ILD, a second conductive layer ICL2, a protective layer PSV, a via layer VIA, an alignment electrode layer ELT (or first electrode layer), and a connecting electrode layer CNE (or second electrode layer), which are sequentially stacked on a base layer BSL.

[0085] According to an embodiment of the present invention, the lower electrode layer BML, the buffer layer BFL, the active layer ACT, the gate insulating layer GI, the first conductive layer ICL1, the interlayer insulating layer ILD, the second conductive layer ICL2, the protective layer PSV, and the via layer VIA may form a pixel circuit layer PCL including a pixel circuit PXC. According to an embodiment of the present invention, the lower electrode layer BML, the first conductive layer ICL1, and the second conductive layer ICL2 may form a lower line BPL (and a transistor, a capacitor). Here, the lower line BPL is a line (e.g., a wiring and an electrode) forming the pixel circuit layer PCL, and may include a conductive pattern (or a component including a conductive material) formed below the alignment electrode layer ELT.

[0086] The buffer layer BFL can prevent diffusion of impurities into the active layer ACT and moisture permeation. According to an embodiment of the present invention, the buffer layer BFL can include, but is not limited to, an inorganic material. The buffer layer BFL may be omitted depending on the material and process conditions of the base layer BSL.

[0087] The active layer ACT may include a semiconductor. For example, the active layer ACT may include one or more of the group consisting of polysilicon, LTPS (Low Temperature Polycrystalline Silicon), amorphous silicon, and oxide semiconductor. According to an embodiment of the present invention, the active layer ACT may form channels of the first transistor M1, the second transistor M2, and the third transistor M3, and may be doped with impurities in a portion in contact with a source / drain electrode (e.g., the first source electrode SE1 and the first drain electrode DE1 in FIG. 7).

[0088] Each of the bottom electrode layer BML, the first conductive layer ICL1, and the second conductive layer ICL2 may include a conductive material. For example, the conductive material may include one or more of the following group: gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and platinum (Pt). At least one of the bottom electrode layer BML, the first conductive layer ICL1, and the second conductive layer ICL2 may include one or more conductive layers.

[0089] The gate insulating layer GI, the interlayer insulating layer ILD, the protective layer PSV, and the via layer VIA may be disposed between the active layer ACT, the first conductive layer ICL1, the second conductive layer ICL2, and the alignment electrode layer ELT to electrically isolate them from each other. According to an embodiment of the present invention, the aforementioned conductive layers may be electrically connected to each other through contact holes formed in one or more of the gate insulating layer GI, the interlayer insulating layer ILD, the protective layer PSV, and the via layer VIA.

[0090] According to an embodiment of the present invention, the gate insulating layer GI, the interlayer insulating layer ILD, and the protective layer PSV may include an inorganic material. However, without being limited thereto, the gate insulating layer GI, the interlayer insulating layer ILD, and the protective layer PSV may include an organic material. According to an embodiment of the present invention, the via layer VIA may include an organic material. For example, the organic material may include one or more of the following group: acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, polyester resin, polyphenylenesulfide resin, and benzocyclobutene (BCB). However, the organic material is not limited thereto.

[0091] According to an embodiment of the present invention, the alignment electrode layer ELT can include a conductive material, for example, the alignment electrode layer ELT can include one or more of the following group: molybdenum (Mo), magnesium (Mg), silver (Ag), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), copper (Cu), and aluminum (Al).

[0092] According to an embodiment of the present invention, the connecting electrode layer CNE may include a conductive material. The connecting electrode layer CNE may be electrically connected to the light emitting device LD. According to an embodiment of the present invention, the connecting electrode layer CNE may include a transparent conductive material. For example, the transparent conductive material may include one or more of the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnOx), and indium gallium zinc oxide (IGZO). A first insulating layer INS1 (see FIG. 7) may be disposed between the alignment electrode layer ELT and the connecting electrode layer CNE.

[0093] Fig. 6 is a plan view showing an embodiment of a sub-pixel included in the display device of Fig. 3. Fig. 6 shows a sub-pixel SPXL in a simplified manner with respect to the alignment electrode layer ELT and the connection electrode layer CNE of Fig. 4 as a center.

[0094] The sub-pixel SPXL may include a light-emitting region EMA and a non-light-emitting region NEA. The sub-pixel SPXL may include a first bank BNK1, an alignment electrode layer ELT, a light-emitting element LD, and a connecting electrode layer CNE.

[0095] In a plan view, the light emitting region EMA may be defined by the first bank BNK1. For example, the light emitting region EMA may overlap with the opening portion OPN (or the opening region OPA) of the first bank BNK1. The light emitting element LD may be arranged in the light emitting region EMA. The light emitting element LD may not be arranged in the non-light emitting region NEA.

[0096] The first bank BNK1 may have a shape protruding in the third direction DR3 and may surround the light emitting region EMA. According to an embodiment of the present invention, ink containing the light emitting element LD may be supplied to the opening portion OPN (or the opening area OPA) of the first bank BNK1, and the light emitting element LD may be disposed in the opening portion OPN. The first bank BNK1 may include an organic material.

[0097] The alignment electrode layer ELT may include an electrode for aligning the light-emitting element LD. According to an embodiment of the present invention, the alignment electrode layer ELT may include a first electrode ELT1 (or a first alignment electrode, a first reflective electrode) and a second electrode ELT2 (or a second alignment electrode, a second reflective electrode). The first electrode ELT1 and the second electrode ELT2 may be spaced apart from each other in a first direction DR1 in the light-emitting area EMA (or in the opening OPN of the first bank BNK1). For example, the first electrode ELT1 and the second electrode ELT2 may be spaced apart from each other by the length L (see FIG. 1) of the light-emitting element LD or an interval corresponding thereto. For example, the first electrode ELT1 and the second electrode ELT2 may be spaced apart from each other by about 4 μm. In the light-emitting region EMA (or within the opening OPN of the first bank BNK1), the space between the first electrode ELT1 and the second electrode ELT2, which are spaced apart by the length L (see FIG. 1) of the light-emitting element LD or a distance corresponding thereto, can be defined as a lane (or passage) (or alignment region) in which the light-emitting element LD can be arranged.

[0098] In a process step in which the light emitting element LD is aligned, a first alignment signal and a second alignment signal may be applied to the first electrode ELT1 and the second electrode ELT2, respectively. For example, ink including the light emitting element LD may be supplied to the opening part OPN, and the first alignment signal may be applied to the first electrode ELT1, and the second alignment signal may be applied to the second electrode ELT2. In this case, the first alignment signal and the second alignment signal may have different waveforms, potentials, and / or phases. For example, the first alignment signal may be an AC signal, and the second alignment signal may be a ground signal. However, the present invention is not limited thereto. An electric field is formed between (or on) the first electrode ELT1 and the second electrode ELT2, and the light emitting element LD may be aligned between the first electrode ELT1 and the second electrode ELT2 based on the electric field. For example, the light emitting element LD may be moved (or rotated) by a force (e.g., a DEP (dielectrophoresis) force) due to the electric field, and aligned (or disposed) on the first electrode ELT1 and the second electrode ELT2.

[0099] The light-emitting element LD may be disposed (or aligned) on the alignment electrode layer ELT. According to an embodiment of the present invention, the light-emitting element LD may be aligned between a first electrode ELT1 and a second electrode ELT2 in a plan view. A first end EP1 of the light-emitting element LD may be disposed adjacent to the first electrode ELT1, and a second end EP2 of the light-emitting element LD may be disposed adjacent to the second electrode ELT2. The light-emitting element LD may form (or configure) a light-emitting unit EMU (see FIG. 4).

[0100] The light emitting element LD can emit light based on the provided electrical signal. For example, the light emitting element LD can provide light based on a first electrical signal (e.g., an anode signal) provided from the first connecting electrode CNE1 and a second electrical signal (e.g., a cathode signal) provided from the second connecting electrode CNE2.

[0101] The connecting electrode layer CNE may be disposed on the first end EP1 and the second end EP2 of the light emitting element LD. According to an embodiment of the present invention, the connecting electrode layer CNE may include a first connecting electrode CNE1 and a second connecting electrode CNE2. The first connecting electrode CNE1 may be a first pixel electrode PE1 (or an anode electrode), and the second connecting electrode CNE2 may be a second pixel electrode PE2 (or a cathode electrode). The first connecting electrode CNE1 may be disposed on the first end EP1 to be electrically connected to the first end EP1 of the light emitting element LD. The second connecting electrode CNE2 may be disposed on the second end EP2 to be electrically connected to the second end EP2 of the light emitting element LD.

[0102] Fig. 7 is a cross-sectional view showing an embodiment of a sub-pixel taken along line II' in Fig. 6. Fig. 7 shows a first transistor M1 (see Fig. 4) and first and second power supply lines PL1, PL2 as an example of circuit elements that can be arranged in the pixel circuit layer PCL.

[0103] Referring to FIG. 7, the sub-pixel SPXL (or display device) may include a pixel circuit layer PCL and a display element layer DPL (or light-emitting element layer) disposed on a base layer BSL.

[0104] The pixel circuit layer PCL may include a first transistor M1, a first power line PL1, a second power line PL2, and a plurality of insulating layers BFL, ILD, GI, ILD, PSV, VIA. The first transistor M1 may include a bottom electrode BGE, a first semiconductor pattern ACT1, a first gate electrode GE1, a first source electrode SE1 (or a second transistor electrode, a second terminal), and a first drain electrode DE1 (or a first transistor electrode, a first terminal).

[0105] The bottom electrode layer BML may include a bottom electrode BGE, a first power line PL1, and a second power line PL2. The bottom electrode BGE and the gate electrode GE of the first transistor M1 may overlap each other with a buffer layer BFL interposed therebetween. The bottom electrode BGE may be disposed under the first semiconductor pattern ACT1 of the first transistor M1. At this time, the bottom electrode BGE may function as a light blocking pattern to stabilize the operating characteristics of the first transistor M1.

[0106] According to an embodiment of the present invention, the first transistor M1 may not include the bottom electrode layer BML. In this case, the buffer layer BFL may be located directly on the base layer BSL. Also, the bottom electrode layer BML may be physically and / or electrically connected to the first source electrode SE1 of the first transistor M1 through a contact hole of the insulating layer. As a result, the threshold voltage of the first transistor M1 may be shifted in a negative or positive direction.

[0107] A buffer layer BFL (or a first insulating layer) covers the bottom electrode layer BML and may be located on the base layer BSL.

[0108] The first semiconductor pattern ACT1 may be located on the buffer layer BFL. The first semiconductor pattern ACT1 may include a first region (e.g., a source region) connected to the first source electrode SE1, a second region (e.g., a drain region) connected to the first drain electrode DE1, and a channel region between the first and second regions. The channel region may overlap with the first gate electrode GE1 of the first transistor M1.

[0109] A gate insulating layer GI (or a second insulating layer) may be disposed on the first semiconductor pattern ACT1. The gate insulating layer GI may be disposed only partially on the first semiconductor pattern ACT1, or may be disposed entirely on the base layer BSL.

[0110] A first conductive layer ICL1 may be disposed on the gate insulating layer GI. The first conductive layer ICL1 may include a first gate electrode GE1, an eleventh connecting pattern CP11, and a twenty-first connecting pattern CP21.

[0111] The first gate electrode GE1 may be disposed on the gate insulating layer GI to overlap a channel region of the first semiconductor pattern ACT1. The eleventh connecting pattern CP11 may overlap the first power line PL1, and the twenty-first connecting pattern CP21 may overlap the second power line PL2.

[0112] An interlayer insulating layer ILD (or a first interlayer insulating layer, a third insulating layer) may cover the first conductive layer ICL1 and be disposed entirely on the base layer BSL.

[0113] A second conductive layer ICL2 may be disposed on the interlayer insulating layer ILD. The second conductive layer ICL2 may include a first source electrode SE1, a first drain electrode DE1, a twelfth connecting pattern CP12, and a twenty-second connecting pattern CP22.

[0114] The first source electrode SE1 may be in contact with or connected to a first region of the first semiconductor pattern ACT1 through a contact hole penetrating the interlayer insulating layer ILD, and may be in contact with or connected to the bottom electrode BGE through a contact hole penetrating the interlayer insulating layer ILD and the buffer layer BFL. The first drain electrode DE1 may be in contact with or connected to a second region of the first semiconductor pattern ACT1 through a contact hole penetrating the interlayer insulating layer ILD. Like the first source electrode SE1, the twelfth connecting pattern CP12 may be in contact with or connected to the first power line PL1 and the eleventh connecting pattern CP11, and the twenty-second connecting pattern CP22 may be in contact with or connected to the second power line PL2 and the twenty-first connecting pattern CP21. The eleventh connecting pattern CP11 and the twelfth connecting pattern CP12 are connected to the first power line PL1, and may reduce the resistance of the first power line PL1. Similarly, the twenty-first connecting pattern CP21 and the twenty-second connecting pattern CP22 are connected to the second power line PL2, and can reduce the resistance of the second power line PL2.

[0115] A protective layer PSV (or a second interlayer insulating layer) can be disposed entirely on the base layer BSL so as to cover the third conductive layer.

[0116] A via layer VIA (or a passivation layer) may be disposed on the protective layer PSV. The via layer VIA may be disposed entirely on the base layer BSL. The via layer VIA may provide a flat surface on the top.

[0117] The display element layer DPL may be located on the via layer VIA.

[0118] The display element layer DPL can include first and second bank patterns BNP1, ​​BNP2, first and second electrodes ELT1, ELT2 (or alignment electrodes, reflective electrodes), a first bank BNK1, a light-emitting element LD, first and second connecting electrodes CNE1, CNE2 (or contact electrodes), and multiple insulating layers INS1 to INS3.

[0119] The first and second bank patterns BNP1, ​​BNP2 can be disposed on the via layer VIA.

[0120] Each of the first and second bank patterns BNP1 and BNP2 may have a trapezoidal cross section that narrows from one surface (for example, an upper surface) of the via layer VIA toward the upper side in the third direction DR3. According to an embodiment of the present invention, each of the first and second bank patterns BNP1 and BNP2 may include a curved surface having a semi-elliptical, semicircular (or hemispherical) cross section that narrows from one surface of the via layer VIA toward the upper side in the third direction DR3. The shapes of each of the first and second bank patterns BNP1 and BNP2 in cross section are not limited to those of the above embodiment and may be variously changed within a range that can improve the efficiency of light emitted from each light emitting element LD.

[0121] The first and second bank patterns BNP1 and BNP2 may include inorganic and / or organic materials and may be composed of a single layer or multiple layers. According to an embodiment of the present invention, the first and second bank patterns BNP1 and BNP2 may be omitted. For example, a structure corresponding to the first and second bank patterns BNP1 and BNP2 may be formed in the via layer VIA.

[0122] The first and second electrodes ELT1, ELT2 can be disposed on the via layer VIA and the first and second bank patterns BNP1, ​​BNP2.

[0123] The first electrode ELT1 may be arranged on the first bank pattern BNP1, ​​and the second electrode ELT2 may be arranged on the second bank pattern BNP2. Viewed in cross section, the first and second electrodes ELT1, ELT2 may have surface profiles that correspond to the shapes of the first and second bank patterns BNP1, ​​BNP2, respectively.

[0124] The first and second electrodes ELT1 and ELT2 may include a conductive material having a certain reflectance so as to propagate light emitted from the light emitting element LD in an image display direction (for example, a third direction DR3) of the display device. The first and second electrodes ELT1 and ELT2 may be formed of a single layer or multiple layers.

[0125] The second electrode ELT2 (or the first electrode ELT1) may contact or be connected to the twelfth connecting pattern CP12 through a first contact hole CNT1 penetrating the via layer VIA and the protective layer PSV. The second electrode ELT2 (or the first electrode ELT1) may be electrically connected to the first power line PL1. The second electrode ELT2 may be directly connected to the twelfth connecting pattern CP12, but is not limited thereto, and for example, the second electrode ELT2 may be connected to the twelfth connecting pattern CP12 (or the eleventh connecting pattern CP11, the first power line PL1) through a bridge electrode.

[0126] The first insulating layer INS1 may be disposed on the via layer VIA so as to cover at least a portion of the first and second electrodes ELT1 and ELT2. The first insulating layer INS1 may be located between the first electrode ELT1 and the second electrode ELT2, and may prevent a short circuit (e.g., a short circuit) between the first electrode ELT1 and the second electrode ELT2. The first insulating layer INS1 may include an inorganic material or an organic material.

[0127] A light-emitting element LD may be disposed on the first insulating layer INS1. The light-emitting element LD may be aligned between the first electrode ELT1 and the second electrode ELT2 such that a first end EP1 of the light-emitting element LD faces the first electrode ELT1 and a second end EP2 of the light-emitting element LD faces the second electrode ELT2.

[0128] The first end EP1 of the light emitting element LD can partially overlap with the first electrode ELT1 in the third direction DR3, and the second end EP2 of the light emitting element LD can partially overlap with the second electrode ELT2 in the third direction DR3, but is not limited thereto.

[0129] The first bank BNK1 may be disposed on the first insulating layer INS1. The first bank BNK1 may be a dam structure that prevents a solution containing the light emitting element LD from flowing into an adjacent sub-pixel SPXL or controls a constant amount of solution to be supplied to each sub-pixel SPXL in the step of supplying the light emitting element LD onto the first insulating layer INS1. The first bank BNK1 may also define a light emitting region EMA. For example, the light emitting region EMA may correspond to an opening OPN of the first bank BNK1.

[0130] The first bank BNK1 may include an organic material. According to an embodiment of the present invention, the first bank BNK1 may include a light blocking material and / or a reflective material. In this case, the first bank BNK1 may prevent a light leakage defect in which light leaks between the sub-pixel SPXL and an adjacent sub-pixel. For example, the first bank BNK1 may include a color filter material or a black matrix material. As another example, a reflective material layer may be separately provided and / or formed on the first bank BNK1 in order to further improve the efficiency of light emitted from the sub-pixel SPXL to the outside.

[0131] A second insulating layer INS2 (or a second insulating pattern) may be disposed on the light emitting element LD. The second insulating layer INS2 may be located on a portion of the upper surface of the light emitting element LD such that the first end EP1 and the second end EP2 of the light emitting element LD are exposed to the outside. According to an embodiment of the present invention, the second insulating layer INS2 may also be disposed on the first insulating layer INS1 and the first bank BNK1.

[0132] The second insulating layer INS2 may include an inorganic material or an organic material depending on design conditions of the display device including the light emitting device LD. After the alignment of the light emitting device LD on the first insulating layer INS1 is completed, the second insulating layer INS2 is positioned on the light emitting device LD to prevent the light emitting device LD from moving away from the aligned position. If there is a gap (or space) between the first insulating layer INS1 and the light emitting device LD before the formation of the second insulating layer INS2, the gap may be filled with the second insulating layer INS2 during the process of forming the second insulating layer INS2.

[0133] The first connecting electrode CNE1 may be disposed on the first electrode ELT1. The first connecting electrode CNE1 may be in direct contact with the first end EP1 of the light emitting element LD. The first connecting electrode CNE1 may be in contact with or connected to the first source electrode SE1 of the first transistor M1 through the second insulating layer INS2, the first insulating layer INS1, the via layer VIA, and the second contact hole CNT2 penetrating the protective layer PSV. That is, the first connecting electrode CNE1 may electrically connect the first end EP1 of the light emitting element LD and the first source electrode SE1 of the first transistor M1.

[0134] The third insulating layer INS3 may be located on the second insulating layer INS2 and the first connecting electrode CNE1 to cover the second insulating layer INS2 and the first connecting electrode CNE1. The third insulating layer INS3 may be located such that an edge of the third insulating layer INS3 abuts against one end of the second insulating layer INS2 so that the second end EP2 of the light emitting element LD is exposed.

[0135] The third insulating layer INS3 may include an inorganic material or an organic material.

[0136] The second connecting electrode CNE2 may be disposed on the second electrode ELT2. The second connecting electrode CNE2 may be in direct contact with the second end EP2 of the light emitting element LD. The second connecting electrode CNE2 may be in contact with or connected to the twenty-second connecting pattern CP22 through a third contact hole CNT3 penetrating the third insulating layer INS3, the second insulating layer INS2, the first insulating layer INS1, the via layer VIA, and the protective layer PSV. That is, the second connecting electrode CNE2 may electrically connect the second end EP2 of the light emitting element LD to the second power line PL2.

[0137] A transparent conductive material (e.g., ITO) may have a better binding force with a conductive layer (e.g., the first source electrode SE1, the 22nd connecting pattern CP22) in the pixel circuit layer PCL and a lower contact resistance than a conductive material (or a metal material) having a certain reflectance. Therefore, the first and second connecting electrodes CNE1 and CNE2 may be directly connected to the components in the pixel circuit layer PCL without going through the first and second electrodes ELT1 and ELT2. However, the present invention is not limited thereto.

[0138] 7, the first connecting electrode CNE1 and the second connecting electrode CNE2 are described as being located on different layers with the third insulating layer INS3 interposed therebetween, but the present invention is not limited thereto. For example, the first connecting electrode CNE1 and the second connecting electrode CNE2 may be disposed on the same layer (for example, the second insulating layer INS2) through the same process.

[0139] Fig. 8 is a cross-sectional view showing an embodiment of a sub-pixel taken along line II' in Fig. 6. Fig. 9 is a cross-sectional view showing an embodiment of a pixel included in the display device of Fig. 3.

[0140] 7 and 8, the sub-pixel SPXL (or the display device) may further include a light conversion layer LCPL disposed on the display element layer DPL.

[0141] The light conversion layer LCPL may further include a second bank BNK2, a color conversion layer CCL, and color filters CF1 to CF3.

[0142] The second bank BNK2 may be disposed on the display element layer DPL. The second bank BNK2 may be a structure that is located in the non-light-emitting area NEA (FIG. 6) and defines a position where the color conversion layer CCL should be provided. The second bank BNK2 may overlap the first bank BNK1 in the third direction DR3.

[0143] The second bank BNK2 may include an organic material. According to an embodiment of the present invention, the second bank BNK2 may include a light-shielding material. As an example, the second bank BNK2 may be a black matrix. According to an embodiment of the present invention, the second bank BNK2 is configured to include at least one light-shielding material and / or a reflective material, and may further advance light emitted from the color conversion layer CCL in the image display direction (or the third direction DR3) of the display device, thereby improving the light output efficiency of the color conversion layer CCL.

[0144] The color conversion layer CCL can be disposed on the display element layer DPL (or the light-emitting element LD) in a region surrounded by the second bank BNK2.

[0145] The color conversion layer CCL can include color conversion particles QD (or wavelength conversion particles) corresponding to a specific color. As an example, the color conversion layer CCL can include color conversion particles QD that convert light of a first color (or a first wavelength band) incident from the light emitting element LD into light of a second color (or a specific color, a second wavelength band) and dissipate the converted light.

[0146] Referring to FIG. 9, when the first subpixel SPXL1 is a red pixel (or a red subpixel), the first color conversion layer CCL1 of the first subpixel SPXL1 may include first color conversion particles QDr of red quantum dots that convert the first color light emitted from the light-emitting element LD into a second color light, for example, red light.

[0147] When the second subpixel SPXL2 is a green pixel (or a green subpixel), the second color conversion layer CCL2 of the second subpixel SPXL2 may include second color conversion particles QDg of green quantum dots that convert the first color light emitted from the light-emitting element LD into a third color light, for example, green light.

[0148] When the third subpixel SPXL3 is a blue pixel (or a blue subpixel), the third color conversion layer CCL3 of the third subpixel SPXL3 may include color conversion particles of blue quantum dots that convert the first color light emitted from the light-emitting element LD into a fourth color light, for example, blue light.

[0149] According to one embodiment of the present invention, when the third sub-pixel SPXL3 is a blue pixel (or a blue sub-pixel) and the light-emitting element LD emits blue series light, the third sub-pixel SPXL3 may include a light scattering layer including light scattering particles SCT. The first sub-pixel SPXL1 and the second sub-pixel SPXL2 may also include a light scattering layer including light scattering particles SCT. The above-mentioned light scattering layer may be omitted depending on the embodiment. According to another embodiment, when the third sub-pixel SPXL3 is a blue pixel (or a blue sub-pixel), a transparent polymer may be provided instead of the third color conversion layer CCL3.

[0150] Referring again to FIG. 8, a fourth insulating layer INS4 may be disposed on the color conversion layer CCL and the second bank BNK2.

[0151] The fourth insulating layer INS4 may be provided on the entire surface of the base layer BSL to cover the second bank BNK2 and the color conversion layer CCL. The fourth insulating layer INS4 may include an inorganic material or an organic material. According to an embodiment of the present invention, the fourth insulating layer INS4 may totally reflect light (e.g., light traveling in a diagonal direction) emitted from the color conversion layer CCL by utilizing a refractive index difference with an adjacent structure, thereby improving the light output efficiency of the sub-pixel SPXL. For this reason, the fourth insulating layer INS4 may have a relatively low refractive index compared to the color conversion layer CCL.

[0152] According to an embodiment of the present invention, the fourth insulating layer INS4 can reduce steps caused by components disposed thereunder and have a flat surface.

[0153] In one embodiment of the present invention, first and second cap layers CAP1, CPA2 may be disposed on the upper and lower parts of the fourth insulating layer INS4. The first and second cap layers CAP1, CPA2 may include an inorganic material. The first cap layer CAP1 is disposed on the color conversion layer CCL and can prevent moisture (or a solution used in a subsequent process) from penetrating into the lower color conversion layer CCL. The second cap layer CAP2 is disposed on the fourth insulating layer INS4 and can prevent moisture from penetrating into the fourth insulating layer INS4. According to one embodiment of the present invention, the second cap layer CAP2 can improve the adhesion between the fourth insulating layer INS4 and the color filter layer.

[0154] A color filter layer may be disposed on the fourth insulating layer INS4.

[0155] Referring to FIG. 9, the color filter layer may include color filters CF corresponding to the colors of the adjacent sub-pixels. For example, a first color filter CF1 may be disposed on the first color conversion layer CCL1 of the first sub-pixel SPXL1, a second color filter CF2 may be disposed on the second color conversion layer CCL2 of the second sub-pixel SPXL2, and a third color filter may be disposed on the third color conversion layer CCL3 of the third sub-pixel SPXL3. Each of the first, second, and third color filters CF1, CF2, and CF3 may include a color filter material that selectively transmits light of a specific color converted by the color conversion layer CCL. For example, the first color filter CF1 may be a red color filter, the second color filter CF2 may be a green color filter, and the third color filter CF3 may be a blue color filter. The color filters CF may be provided on one surface of the fourth insulating layer INS4 to correspond to the color conversion layer CCL.

[0156] The first, second, and third color filters CF1, CF2, and CF3 are arranged to overlap each other in the non-emitting area NEA to block optical interference between adjacent sub-pixels. According to an embodiment of the present invention, a separate light-shielding pattern may be arranged in the non-emitting area NEA instead of the stacked structure of the first, second, and third color filters CF1, CF2, and CF3.

[0157] A fifth insulating layer INS5 may be disposed on the color filter layer. The fifth insulating layer INS5 may include an inorganic material or an organic material. The fifth insulating layer INS5 may entirely cover the underlying structure to prevent moisture or humidity from entering the color filter layer and the display element layer DPL from the outside. In one embodiment of the present invention, the fifth insulating layer INS5 may be formed of multiple layers. For example, the fifth insulating layer INS5 may include at least two inorganic layers and at least one organic layer interposed between the at least two inorganic layers. However, the constituent material and / or structure of the fifth insulating layer INS5 may be variously changed. In addition, at least one overcoat layer, a filler layer, and / or an upper substrate may be further disposed on the fifth insulating layer INS5 depending on the embodiment.

[0158] In the above embodiment, the color conversion layer CCL is directly formed on the display element layer DPL, but the present invention is not limited to this. According to an embodiment of the present invention, the color conversion layer CCL may be formed on a separate substrate and coupled to the display element layer DPL via an adhesive material.

[0159] When the subpixel SPXL includes a light conversion layer LCPL on the display element layer DPL, i.e., when it includes a color conversion layer CCL and a color filter CF arranged on the light emitting element LD, light having excellent color reproducibility is emitted through the color conversion layer CCL and the color filter CF, thereby improving the light emission efficiency of the subpixel SPXL.

[0160] FIG. 10 is a schematic cross-sectional view illustrating a positional relationship between an alignment electrode layer and a lower line according to an embodiment of the present invention.

[0161] 10, the sub-pixel SPXL (or the display device) may include a first region A1 and a second region A2. The first region A1 may be a region set to be larger than the lane EA by a certain distance D0. The first region A1 may be set to be larger than the lane EA in all directions, up, down, left and right, by the certain distance D0 in a plan view (see FIG. 12). The certain distance D0 may be half or more of the length L of the light-emitting element LD (see FIG. 1), and for example, the certain distance D0 may be about 6 μm or more.

[0162] According to an embodiment of the present invention, the bottom line BPL (or conductive pattern) may be disposed (or patterned) in one region in the pixel circuit layer PCL. For example, the bottom line BPL may be disposed in the second region A2 and may not be disposed in the first region A1. For example, one or more of the bottom electrode layer BML, the first conductive layer ICL1, and the second conductive layer ICL2 may be disposed in the second region A2. Parts of the bottom line BPL may be connected to each other through contact holes penetrating parts of the insulating layer, or may be connected to other components (e.g., the first electrode ELT1 or the second electrode ELT2). The contact holes may be disposed in the second region A2 and may not be disposed in the first region A1.

[0163] The lower line BPL is selectively disposed only in a part of the region, and the pixel circuit layer PCL may include a line-free region BFA in which the lower line BPL is not disposed. For example, in a plan view, the line-free region BFA may overlap with the first region A1 and not overlap with the lower line BPL and the second region A2. As a result, in a plan view, the lane EA may not overlap with any of the lower lines BPL (and contact holes) of the pixel circuit layer PCL, and the lane EA may be separated from all of the lower lines BPL (and contact holes) by a distance equal to or greater than half the length L of the light-emitting element LD. In the line-free region BFA, only an insulating layer (e.g., one or more of the buffer layer BFL, the gate insulating layer GI, the interlayer insulating layer ILD, the protective layer PSV, and the via layer VIA) may be disposed on the base layer BSL in the pixel circuit layer PCL.

[0164] The alignment electrode layer ELT may be disposed (or patterned) in one region in the display element layer DPL. For example, the alignment electrode layer ELT may be disposed in the second region A2. For example, the first electrode ELT1 and the second electrode ELT2 may be disposed in the second region A2. In the first region A1, the first electrode ELT1 and the second electrode ELT2 may be spaced apart from each other.

[0165] The first electrode ELT1 and the second electrode ELT2 may be selectively disposed in only a part of the first region A1 to form an electrode-free region EFA. For example, the electrode-free region EFA may be a region in which the first electrode ELT1 and the second electrode ELT2 are defined to be spaced apart from each other. According to an embodiment of the present invention, the electrode-free region EFA may be entirely covered by the line-free region BFA when viewed in a plan view.

[0166] In plan view, the electrode-free area EFA may overlap the light-emitting element LD. According to one embodiment of the present invention, the electrode-free area EFA may overlap the active layer AL of the light-emitting element LD. For example, the electrode-free area EFA may correspond to a lane EA (or an alignment area) in which the light-emitting element LD is arranged between the first electrode ELT1 and the second electrode ELT2.

[0167] According to an embodiment of the present invention, the light emitting element LD may be aligned based on an electric field formed between the first electrode ELT1 and the second electrode ELT2. Experimentally, when the bottom line BPL (and contact hole) is formed in the lane EA, the electric field formed between the first electrode ELT1 and the second electrode ELT2 may be interfered with by the bottom line BPL, and the degree of alignment of the light emitting element LD and the reliability of the alignment may be reduced. For example, the light emitting element LD may not be aligned in the center of the lane EA, but may be biased toward one of the first electrode ELT1 and the second electrode ELT2. In addition, when the bottom line BPL is formed in the first region A1, for example, when the bottom line BPL is adjacent to the lane EA by about the length L (see FIG. 1) of the light emitting element LD, the electric field may be interfered with by the bottom line BPL. Therefore, in this case, the lower line BPL (and contact hole) is not disposed in the first region A1 (the first region A1 and the lower line BPL (and contact hole) are disposed apart), so that the influence on the electrical signal (e.g., electric field, etc.) for aligning the light emitting element LD is reduced, and as a result, the alignment degree of the light emitting element LD can be substantially improved. That is, the light emitting element LD can be arranged more uniformly.

[0168] Fig. 11 is a plan view showing one embodiment of the display device of Fig. 3. Fig. 11 shows the arrangement of the lanes EA of the sub-pixels SPXL1 to SPXL3 and the wirings DL1 to DL3, PL1, PL2, SENL, and SL in the display area DA.

[0169] 11, the sub-pixels SPXL1 to SPLX3 may be sequentially and repeatedly arranged along a first direction DR1. The first sub-pixel SPXL1 may be a red pixel R, the second sub-pixel SPXL2 may be a green pixel G, and the third sub-pixel SPXL3 may be a blue pixel B, but is not limited thereto. The sub-pixels SPXL1 to SPXL3 may be repeatedly arranged along a second direction DR2.

[0170] The wirings DL1 to DL3, PL1, PL2, SENL, and SL may be disposed at regular distances D1 to D4 from the lanes EA of the sub-pixels SPXL1 to SPLX3, respectively. As described with reference to FIG. 10, the regular distances D1 to D4 are equal to or greater than half the length L (see FIG. 1) of the light-emitting element LD, and may be, for example, equal to or greater than about 6 μm.

[0171] The data lines DL1 to DL3 may extend in the second direction DR2 and be repeatedly arranged in sequence along the first direction DR1 corresponding to the subpixels SPXL1 to SPLX3. For example, the first data line DL1 may be arranged on the left (or right) side of the lane EA of the first subpixel SPXL1. The first data line DL1 may be spaced apart from the lane EA of the first subpixel SPXL1 by a third distance D3. The second data line DL2 may be spaced apart from the lane EA of the second subpixel SPXL2 by the third distance D3 on the right (or left) side, and the third data line DL3 may be spaced apart from the lane EA of the third subpixel SPXL3 by the third distance D3 on the left (or right) side.

[0172] The sensing line SENL (or the first line) may extend in the second direction DR2 and be repeatedly arranged along the first direction DR1 with an interval corresponding to two sub-pixels. For example, the sensing line SENL may be disposed between the first sub-pixel SPXL1 of the first column and the second sub-pixel SPXL2 of the second column, and may be spaced apart from the lane EA of the first sub-pixel SPXL1 (and the second sub-pixel SPXL2) by a fourth distance D4. The first sub-pixel SPXL1 and the second sub-pixel SPXL2 adjacent to each other across the sensing line SENL may share the sensing line SENL and have a structure symmetrical to each other with respect to the sensing line SENL. The symmetrical structure will be described later with reference to FIG. 12. Similarly, the sensing line SENL may be disposed between the third sub-pixel SPXL3 of the third column and the first sub-pixel SPXL1 of the fourth column, and the third sub-pixel SPXL3 of the third column and the first sub-pixel SPXL1 of the fourth column may have a structure symmetrical to each other.

[0173] The first power supply line PL1 may include a first horizontal power supply line PL1_H and a first vertical power supply line PL1_V. The first horizontal power supply line PL1_H and the first vertical power supply line PL1_V may cross each other and be electrically connected to each other. The first power supply line PL1 including the first horizontal power supply line PL1_H and the first vertical power supply line PL1_V may be arranged in a mesh shape over the entire display area DA. The first vertical power supply line PL1_V may be a main power supply line, and the first horizontal power supply line PL1_H may be an auxiliary power supply line, but is not limited thereto.

[0174] The first vertical power line PL1_V may extend in the second direction DR2 and be repeatedly arranged along the first direction DR1 at intervals corresponding to four sub-pixels. For example, the first vertical power line PL1_V may be disposed to the left of the first sub-pixel SPXL1 in the first column. Also, the first vertical power line PL1_V may be disposed between the first sub-pixel SPXL1 in the fourth column and the second sub-pixel SPXL2 in the fifth column.

[0175] The first horizontal power line PL1_H may extend in a first direction DR1 and be arranged in a row unit along a second direction DR2. For example, the first horizontal power line PL1_H may be disposed below the lane EA of the first sub-pixel SPXL1 in the first row by a first distance D1. Similarly, the first horizontal power line PL1_H may be disposed below the lane EA of each of the sub-pixels SPXL1 to SPXL3 in the second row.

[0176] Similar to the first power line PL1, the second power line PL2 may include a second horizontal power line PL2_H and a second vertical power line PL2_V. The second horizontal power line PL2_H and the second vertical power line PL2_V are electrically connected to each other, and the second power line PL2 may be arranged in a mesh shape over the entire display area DA. The second vertical power line PL2_V may be a main power line, and the second horizontal power line PL2_H may be an auxiliary power line, but is not limited thereto.

[0177] The second vertical power line PL2_V extends in the second direction DR2, is spaced apart from the first vertical power line PL1_V in the first direction DR1 by an interval corresponding to two sub-pixels, and may be repeatedly arranged along the first direction DR1 with an interval corresponding to four sub-pixels. For example, the second vertical power line PL2_V may be disposed between the second sub-pixel SPXL2 in the second column and the third sub-pixel SPXL3 in the third column. Also, the second vertical power line PL2_V may be disposed between the third sub-pixel SPXL3 in the sixth column and the first sub-pixel SPXL1 in the seventh column.

[0178] The second horizontal power line PL2_H may extend in the first direction DR1 and be arranged in rows along the second direction DR2. For example, the second horizontal power line PL2_H may be disposed above the lane EA of the first sub-pixel SPXL1 in the first row by a second distance D2. Similarly, the second horizontal power line PL2_H may be disposed above the lane EA of each of the sub-pixels SPXL1 to SPXL3 in the second row.

[0179] The scan lines SL (and / or the sensing scan lines SSL) may extend in a first direction DR1 and be arranged in rows along a second direction DR2.

[0180] In one row, 12 sub-pixels SPXL1 to SPXL3 form a unit block according to the arrangement of the sub-pixels SPXL1 to SPXL3 and the arrangement of the vertical wirings DL1 to DL3, PL1_V, and PL2_V, and the display device can have a structure in which the unit blocks are repeated.

[0181] As described above, the lines DL1 to DL3, PL1, PL2, SENL, and SL may be disposed at predetermined distances D1 to D4 away from the lanes EA of the sub-pixels SPXL1 to SPLX3, respectively.

[0182] FIG. 12 is a layout diagram showing an embodiment of the first and second sub-pixels included in the display device of FIG. 11. FIG. 12 shows a first sub-pixel SPXL1 in the first column and a second sub-pixel SPXL2 in the second column of FIG. 11 with reference to a pixel circuit layer PCL (see FIG. 7). FIG. 13 is a cross-sectional view showing an embodiment of a storage capacitor taken along line II-II' in FIG. 12. FIGS. 14, 15, and 16 are layout diagrams showing an embodiment of the first and second sub-pixels included in the display device of FIG. 11. FIG. 14 further shows a first electrode ELT1 and a second electrode ELT2, FIG. 15 further shows a first bank BNK1, and FIG. 16 further shows connecting electrodes CNE1 to CNE5.

[0183] 11 to 16, the second subpixel SPXL2 may have a symmetrical structure to the first subpixel SPXL1 with respect to the sensing line SENL. That is, the transistors and capacitors of the second subpixel SPXL2 may be arranged symmetrically to the transistors and capacitors of the first subpixel SPXL1 with respect to the sensing line SENL. Meanwhile, the third subpixel SPXL3 in the third column and the first subpixel SPXL1 in the fourth column in FIG. 11 may have a symmetrical structure to the second subpixel SPXL2 and the first subpixel SPXL1 in FIG. 12 with respect to the second vertical power line PL2_V. Therefore, the common configuration of the subpixels SPXL1 to SPXL3 in FIG. 11 will be described mainly with respect to the first subpixel SPXL1, and a duplicated description will be omitted.

[0184] The first vertical power line PL1_V, the first data line DL1, the sensing line SEN, the second data line DL2, and the second vertical power line PL2_V may extend approximately in the second direction DR2 and be arranged along the first direction DR1. The first vertical power line PL1_V, the first data line DL1, the sensing line SEN, the second data line DL2, and the second vertical power line PL2_V may be included in the bottom electrode layer BML described with reference to FIGS. 5 and 7, and may be disposed in the same layer through the same process.

[0185] The second horizontal power line PL2_H, the first horizontal power line PL1_H, and the scan line SL may extend approximately in the first direction DR1 and be arranged along the second direction DR2. The second horizontal power line PL2_H, the first horizontal power line PL1_H, and the scan line SL may be included in the second conductive layer ICL2 described with reference to Figures 5 and 7, and may be disposed in the same layer through the same process.

[0186] The first vertical power line PL1_V and the first horizontal power line PL1_H may constitute the first power line PL1. Similarly, the second vertical power line PL2_V and the second horizontal power line PL2_H may constitute the second power line PL2. The first power line PL1 and the second power line PL2 are arranged in a mesh shape, and in this case, the first power line PL1 and the second power line PL2 may be reduced.

[0187] Also, each of the first power line PL1 and the second power line PL2 may have a three-layer structure (i.e., a structure including three conductive layers). The eleventh connecting pattern CP11 may overlap the first vertical power line PL1_V in a region between the second horizontal power line PL2_H and the scan line SL, and may be connected to the first vertical power line PL1_V through a contact hole CH. The twelfth connecting pattern CP12 may spread or extend from the first horizontal power line PL1_H in the first direction DR1, overlap the first vertical power line PL1_V, and be connected to the first vertical power line PL1_V through a contact hole CH. Similarly, the twenty-first connecting pattern CP21 and the twenty-second connecting pattern CP22 may overlap the second vertical power line PL2_V, and be connected to the second vertical power line PL2_V through a contact hole CH. In this case, the resistance of each of the first power line PL1 and the second power line PL2 may be further reduced.

[0188] The sensing line SENL may have a two-layer structure. The 32nd connecting pattern CP32 may overlap the sensing line SENL and be connected to the sensing line SENL through a contact hole CH. However, the present invention is not limited thereto, and for example, the sensing line SENL may have a three-layer structure.

[0189] The first region A1 may be located in a region (or pixel region) defined by the data line DL1 or DL2, the sensing line SENL (or the second storage capacitor CST2), the first horizontal power line PL1_H, and the second horizontal power line PL2_H. The first region A1 may include a lane EA (i.e., a space between the first electrode ELT1 and the second electrode ELT2 spaced apart from each other in the first bank BNK1 of FIG. 15).

[0190] The lane EA in the first region A1 may be spaced apart from the first horizontal power line PL1_H (and the contact hole CH) by a first distance D1 in the second direction DR2, spaced apart from the second horizontal power line PL2_H by a second distance D2 in the second direction DR2, spaced apart from the first data line DL1 by a third distance D3 in the first direction DR1, and spaced apart from the second storage capacitor CST2 by a fourth distance D4 in the first direction DR1. The lane EA in the first region A1 may be spaced apart from the sensing line SENL by more than the fourth distance D4 in the first direction DR1. The second storage capacitor CST2 may constitute a storage capacitor CST together with the first storage capacitor CST1. According to an embodiment of the present invention, the second storage capacitor CST2 may be omitted (see FIG. 17). According to an embodiment of the present invention, the first storage capacitor CST1 may be omitted instead of the second storage capacitor CST2.

[0191] The pixel circuit including the transistors M1 to M3 and the first storage capacitor CST1 may be located in the second direction DR2 from the first region A1. For example, the transistors M1 to M3 and the first storage capacitor CST1 may be located in a region between the first horizontal power line PL1_H and the scan line SL (and between the data line DL1 or DL2 and the sensing line SENL).

[0192] The first semiconductor pattern ACT1 may protrude from the first horizontal power line PL1_H in the second direction DR2 and extend in the first direction DR1. The first semiconductor pattern ACT1 may constitute a first transistor M1. One end of the first semiconductor pattern ACT1 may be connected to the first horizontal power line PL1_H through a contact hole CH. The other end of the first semiconductor pattern ACT1 may overlap a thirteenth capacitor electrode CE13 of the first storage capacitor CST1 and be connected to the thirteenth capacitor electrode CE13 through a contact hole CH, as shown in FIG.

[0193] Referring to FIG. 13, the eleventh capacitor electrode CE11 of the first storage capacitor CST1 may be included in the lower electrode layer BML, the twelfth capacitor electrode CE12 may be included in the active layer ACT, and the thirteenth capacitor electrode CE13 may be included in the second conductive layer ICL2. The twelfth capacitor electrode CE12 may be a semiconductor pattern doped with impurities. The eleventh capacitor electrode CE11 and the twelfth capacitor electrode CE12 may overlap to form a first sub-capacitor, and the twelfth capacitor electrode CE12 and the thirteenth capacitor electrode CE13 may overlap to form a second sub-capacitor. The thirteenth capacitor electrode CE13 is connected to the eleventh capacitor electrode CE11 through a contact hole CH, so that the first sub-capacitor and the second sub-capacitor are connected in parallel to form the first storage capacitor CST1. Therefore, the capacitance of the first storage capacitor CST1 may be more sufficiently secured within a limited space in a plan view.

[0194] 12, one end of the first gate electrode GE1 may overlap a channel region of the first semiconductor pattern ACT1, and the other end of the first gate electrode GE1 may be connected to the second drain electrode DE2 of the second transistor M2 through a contact hole CH.

[0195] The second semiconductor pattern ACT2 may extend in a first direction DR1 from the first data line DL1. The second semiconductor pattern ACT2 may constitute a second transistor M2. One end of the second semiconductor pattern ACT2 may be connected to a second source electrode SE2 through a contact hole CH, and the second source electrode SE2 may be connected to the first data line DL1 through the contact hole CH. The other end of the second semiconductor pattern ACT2 may be connected to a second drain electrode DE2 through the contact hole CH. One end of the second gate electrode GE2 may overlap a channel region of the second semiconductor pattern ACT2, and the other end of the second gate electrode GE2 may be connected to a scan line SL through the contact hole CH.

[0196] The second semiconductor pattern ACT2 may further extend in the first direction DR1 and form a twelfth capacitor electrode of the first storage capacitor CST1.

[0197] The third semiconductor pattern ACT3 may extend in the first direction DR1 from the sensing line SENL. The third semiconductor pattern ACT3 may constitute a third transistor M3. The third semiconductor pattern ACT3 may be connected to a third source electrode SE3 through a contact hole CH, and the third source electrode SE3 may be connected to the sensing line SENL through the contact hole CH. One end of the third semiconductor pattern ACT3 may be connected to a third drain electrode DE3 through a contact hole CH. The third drain electrode DE3 may be integrally formed with the thirteenth capacitor electrode CE13, but is not limited thereto. One end of the third gate electrode GE3 may overlap a channel region of the third semiconductor pattern ACT3, and the other end of the third gate electrode GE3 may be connected to a scan line SL (or a sensing scan line SSL) through a contact hole CH.

[0198] As shown in FIG. 12, the third semiconductor pattern ACT3 may constitute not only the third transistor M3 of the first subpixel SPXL1 but also the third transistor M3 of the second subpixel SPXL2. The sensing line SENL may be commonly connected to the first subpixel SPXL1 and the second subpixel SPXL2. When the first subpixel SPXL1 and the second subpixel SPXL2 share the sensing line SENL, the width or interval of each of the first subpixel SPXL1 and the second subpixel SPXL2 in the first direction DR1 may be reduced or the first area A1 may be more sufficiently secured, compared to when the first subpixel SPXL1 and the second subpixel SPXL2 are each provided with the sensing line SENL (i.e., a total of two sensing lines). In addition, as described with reference to FIG. 11, the first vertical power line PL1_V and the second vertical power line PL2_V are arranged at intervals of four subpixels SPXL1 to SPXL3, so that the first area A1 may be more sufficiently secured. In other words, the lane EA can be more sufficiently isolated from the surrounding wirings DL1, PL1, PL2, and SENL.

[0199] In an embodiment of the present invention, the storage capacitor CST may include a first storage capacitor CST1 and a second storage capacitor CST2 spaced apart in a second direction DR2 across the first horizontal power line PL1_H in a plan view. The first storage capacitor CST1 and the second storage capacitor CST2 may be electrically connected in parallel.

[0200] The twelfth capacitor electrode CE12 (or the second semiconductor pattern ACT2) may further extend in the second direction DR2 across the first horizontal power line PL1_H and be connected to a 22nd capacitor electrode CE22 of the second storage capacitor CST2. The 22nd capacitor electrode CE22 may be integrally formed with the twelfth capacitor electrode CE12.

[0201] Referring to FIG. 13, the 21st capacitor electrode CE21 of the second storage capacitor CST2 may be included in the lower electrode layer BML and may be connected to the 11th capacitor electrode CE11 via a bridge pattern BRP. The 21st capacitor electrode CE21, the bridge pattern BRP, and the 11th capacitor electrode CE11 may be integrally formed. The 22nd capacitor electrode CE22 may be included in the active layer ACT, and the 23rd capacitor electrode CE23 may be included in the second conductive layer ICL2. The 22nd capacitor electrode CE22 may be a semiconductor pattern doped with impurities. The 21st capacitor electrode CE21 and the 22nd capacitor electrode CE22 may overlap to form a third sub-capacitor, and the 22nd capacitor electrode CE22 and the 23rd capacitor electrode CE23 may overlap to form a fourth sub-capacitor. The 23rd capacitor electrode CE23 may be connected to the 21st capacitor electrode CE21 via a contact hole CH, so that the third sub-capacitor and the fourth sub-capacitor may be connected in parallel to form the second storage capacitor CST2. Since the storage capacitor CST further includes the second storage capacitor CST2 in addition to the first storage capacitor CST1, the capacitance of the storage capacitor CST can be sufficiently ensured.

[0202] Meanwhile, although the 22nd capacitor electrode CE22 has been described as being included in the active layer ACT, the present invention is not limited thereto. For example, the 22nd capacitor electrode CE22 may be included in a first conductive layer between the gate insulating layer GI and the interlayer insulating layer ILD. However, when the 22nd capacitor electrode CE22 (and a portion connected to the 12th capacitor electrode CE12) is located in the active layer ACT, a short circuit between the storage capacitor CST and the first horizontal power line PL1_H can be prevented by two insulating layers (i.e., the gate insulating layer GI and the interlayer insulating layer ILD).

[0203] In addition, in order to additionally form the second storage capacitor CST2, the scan line SL (and the second transistor M2 and the third transistor M3 connected thereto) may be disposed apart from the first region A1 (i.e., the first region A1 of the corresponding subpixel). When the first storage capacitor CST1 and the second storage capacitor CST2 are divided based on the scan line SL, it may be difficult to connect the first storage capacitor CST1 and the second storage capacitor CST2 by the third gate electrode GE3.

[0204] 14, the first electrode ELT1 and the second electrode ELT2 may extend generally in the second direction DR2 and be repeatedly arranged alternately along the first direction DR1 with the lane EA therebetween. The first electrode ELT1 may be located between two lanes EA adjacent to each other in the first direction DR1 in the first region A1. The second electrode ELT2 may be located between the first electrode ELT1 of the first subpixel SPXL1 and the first electrode ELT1 of the second subpixel SPXL2.

[0205] The first electrode ELT1 of the first sub-pixel SPXL1 and the first electrode ELT1 of the second sub-pixel SPXL2 are connected to a first connecting line CELT1 extending in a first direction DR1, and the first connecting line CELT1 may be connected to the eleventh connecting pattern CP11 (and the first vertical power line PL1_V) through a first contact hole CNT1. The first connecting line CELT1 may be integrally formed with the first electrode ELT1. That is, the first electrode ELT1 may be electrically connected to the first power line PL1 through the first connecting line CELT1 and the first contact hole CNT1. Meanwhile, since the first vertical power line PL1_V is arranged every four sub-pixels in the first direction DR1, the first contact hole CNT1 for the first electrode ELT1 may also be arranged every four sub-pixels. In addition, the first contact hole CNT1 for the first electrode ELT1 is located at a maximum distance from the first region A1, thereby reducing the influence of the first contact hole CNT1 on the first region A1.

[0206] The second electrode ELT2 of the first subpixel SPXL1 and the second electrode ELT2 of the second subpixel SPXL2 are connected to a second connecting line CELT2 extending in the first direction DR1, and the second connecting line CELT2 may be connected to the twenty-first connecting pattern CP21 (and the second vertical power line PL2_V) through a first contact hole CNT1. The second connecting line CELT2 may be integrally formed with the second electrode ELT2. That is, the second electrode ELT2 may be electrically connected to the second power line PL2 through the second connecting line CELT2 and the first contact hole CNT1. Since the second vertical power line PL2_V is arranged every four subpixels in the first direction DR1, the first contact hole CNT1 for the second electrode ELT2 may also be arranged every four subpixels.

[0207] Referring to FIG. 15, the first bank BNK1 is disposed on the first electrode ELT1 and the second electrode ELT2 and may include an aperture portion corresponding to the first region A1. The aperture portion of the first bank BNK1 may be formed larger than the first region A1. For example, in the aperture portion, the upper and lower edges of the first bank BNK1 may coincide with the edges of the first region A1, and the length of the aperture portion in the second direction DR2 may be the same as the length of the first region A1 in the second direction DR2. The width of the aperture portion in the first direction DR1 may be larger than the width of the first region A1 in the first direction DR1. However, the first bank BNK1 (or the aperture portion) is not limited thereto. The width of the first bank BNK1 in the first direction DR1 may be changed depending on the amount of the mixture (i.e., the mixture containing the light-emitting element, or the ink) poured into the aperture portion of the first bank BNK1.

[0208] The first bank BNK1 may not overlap the first connecting line CELT1 and the second connecting line CELT2. According to an embodiment of the present invention, the first connecting line CELT1 and the second connecting line CELT2 exposed by the first bank BNK1 may be at least partially removed after the light emitting element is aligned between the first electrode ELT1 and the second electrode ELT2 (or lane EA).

[0209] 16, the first light emitting element LD1 may be arranged in the lower right lane EA (or the first lane), the second light emitting element LD2 may be arranged in the upper right lane EA (or the second lane), the third light emitting element LD3 may be arranged in the upper left lane EA (or the third lane), and the fourth light emitting element LD4 may be arranged in the lower left lane EA (or the fourth lane). The first connecting electrode CNE1 may overlap the first end of the first light emitting element LD1 and the first electrode ELT1, and may be connected to the first end of the first light emitting element LD1. In addition, the first connecting electrode CNE1 may overlap the thirteenth capacitor electrode CE13, and may be connected to the thirteenth capacitor electrode CE13 (or the first storage capacitor CST3) via the second contact hole CNT2. The first connecting electrode CNE1 may be electrically isolated from the first electrode ELT1.

[0210] The second connecting electrode CNE2 may be positioned so as to overlap with the second end of the first light emitting element LD1 and the second electrode ELT2. Also, the second connecting electrode CNE2 may be positioned so as to overlap with the first end of the second light emitting element LD2 and the first electrode ELT1. Therefore, a part of the second connecting electrode CNE2 may have a curved shape. The second connecting electrode CNE2 may connect the second end of the first light emitting element LD1 and the first end of the second light emitting element LD2.

[0211] The third connecting electrode CNE3 may be positioned to overlap with the second end of the second light emitting element LD2 and the second electrode ELT2. Also, the third connecting electrode CNE3 may be positioned to overlap with the first end of the third light emitting element LD3 and the first electrode ELT1. The third connecting electrode CNE3 may have a shape that bypasses the second connecting electrode CNE2. The third connecting electrode CNE3 may connect the second end of the second light emitting element LD2 and the first end of the third light emitting element LD3.

[0212] The fourth linking electrode CNE4 may be positioned so as to overlap with the second end of the third light-emitting element LD3 and the second electrode ELT2. Also, the fourth linking electrode CNE4 may be positioned so as to overlap with the first end of the fourth light-emitting element LD4 and the first electrode ELT1. Therefore, a part of the fourth linking electrode CNE4 may have a curved shape. The fourth linking electrode CNE4 may connect the second end of the third light-emitting element LD3 and the first end of the fourth light-emitting element LD4.

[0213] The fifth connecting electrode CNE5 may be positioned to overlap the second end of the fourth light emitting element LD4 and the second electrode ELT2. The fifth connecting electrode CNE5 may be connected to the second end of the fourth light emitting element LD4. The fifth connecting electrode CNE5 may be connected to the second power line PL2 via a third contact hole CNT3 (see FIG. 7) or the like. The fifth connecting electrodes CNE5 of the first and second sub-pixels SPXL1 and SPXL2 (and all sub-pixels) may be connected to each other. For example, the fifth connecting electrode CNE5 may extend from a non-emitting region (i.e., a region excluding the opening of the first bank BNK1) in the first direction DR1 and the second direction DR2 and be generally arranged in a mesh shape. However, the arrangement of the fifth connecting electrodes CNE5 is not limited thereto.

[0214] The light emitting elements LD1 to LD4 may be connected in series via the connecting electrodes CNE1 to CNE5, that is, the first sub-pixel SPXL1 may include four series stages.

[0215] The connecting electrodes of the second sub-pixel SPXL2 may be arranged symmetrically to the connecting electrodes CNE1 to CNE5 of the first sub-pixel SPXL1 with respect to the sensing line SENL.

[0216] In one embodiment of the present invention, some of the connecting electrodes CNE1 to CNE5 may include a closed loop. For example, the second connecting electrode CNE2 may include a closed loop on the second electrode ELT2. Even if a disconnection (i.e., an open circuit) occurs in a part of the second connecting electrode CNE2 adjacent to the second end of the first light-emitting element LD1, a current can flow through a detour path formed by the closed loop. For example, the third connecting electrode CNE3 may include a closed loop on the second electrode ELT2. Similarly, each of the fourth connecting electrode CNE4 and the fifth connecting electrode CNE5 may include a closed loop on the second electrode ELT2.

[0217] As described above, the sub-pixels adjacent to each other across the sensing line SENL (eg, the first sub-pixel SPXL1 and the second sub-pixel SPXL2) may share the sensing line SENL and have symmetrical structures with respect to the sensing line SENL.

[0218] In addition, the storage capacitor CST may include a first storage capacitor CST1 and a second storage capacitor CST2 spaced apart in a second direction DR2 across the first horizontal power line PL1_H in a plan view, thereby providing the first area A1 and ensuring a sufficient capacitance of the storage capacitor CST within a limited space in a plan view.

[0219] FIG. 17 is a layout diagram showing another embodiment of the first and second sub-pixels included in the display device of FIG.

[0220] 12 and 17, except for the lane EA and the second storage capacitor CST2, the first sub-pixel SPXL1_1 and the second sub-pixel SPXL2_1 in FIG 17 may be substantially the same as or similar to the first sub-pixel SPXL1 and the second sub-pixel SPXL2 in FIG 12, respectively, and therefore, a duplicated description will be omitted.

[0221] The first sub-pixel SPXL1_1 may not include the second storage capacitor CST2 of Fig. 12. For example, if a sufficient capacitance is ensured by only the first storage capacitor CST1 of the first sub-pixel SPXL1_1, or if the first storage capacitor CST1 of the first sub-pixel SPXL1_1 is formed larger than the first storage capacitor CST1 of the first sub-pixel SPXL1 of Fig. 12, the storage capacitor CST2 of Fig. 12 may not be necessary.

[0222] In this case, all components of the pixel circuit of the first subpixel SPXL1_1, i.e., the transistors M1 to M3 and the first storage capacitor CST1, may be disposed in a region different from the first region A1 (or lane EA) with respect to the first horizontal power line PL1_H. For example, the lane EA of the first subpixel SPXL1_1 may be spaced apart in the second direction DR2 from all components of the pixel circuit of the first subpixel SPXL1_1 across the first horizontal power line PL1_H.

[0223] The first region A1 in Fig. 17 can be more sufficiently secured compared to the first region A1 in Fig. 12. For example, the width of the first region A1 in Fig. 17 in the first direction DR1 can be made larger than the width of the first region A1 in Fig. 12 in the first direction DR1.

[0224] In this case, the first subpixel SPXL1_1 may further include an additional lane EA instead of the second storage capacitor CST2 (see FIG. 12). The first subpixel SPXL1_1 may further include a light emitting element disposed in the additional lane EA. As the number of light emitting elements increases, the luminance of the first subpixel SPXL1_1 (and the display device including the same) may be increased.

[0225] According to one embodiment of the present invention, when the first storage capacitor CST1 of the first sub-pixel SPXL1_1 is formed relatively large, the length of the first region A1 in FIG. 17 in the second direction DR2 may be made smaller than the length of the first region A1 in FIG. 12 in the second direction DR2.

[0226] In this case, the lane EA may be formed relatively long in consideration of the number of light-emitting elements to be arranged in one lane EA, for example, in consideration of the fact that the length of the first region A1 in the second direction DR2 is small. For example, the first subpixel SPXL_1 may include three lanes EA (or three corresponding series stages). However, this is not limited thereto. For example, if the length of the first region A1 in the second direction DR2 is sufficiently large, two lanes EA may be arranged in one column, similar to the lane EA in FIG. 12, and the first subpixel SPXL_1 may include a total of six lanes EA (or six corresponding series stages).

[0227] As described above, the second storage capacitor CST2 (see FIG. 12) may be omitted. Also, the arrangement of the lanes EA can be freely changed in consideration of the size of the first area A1.

[0228] Fig. 18 is a layout diagram showing an embodiment of the first and second sub-pixels included in the display device of Fig. 3. Fig. 19 is a layout diagram showing an embodiment of the first and second sub-pixels included in the display device of Fig. 3.

[0229] 12 and 18, except for the sensing line SENL, the embodiment of Fig. 18 may be substantially the same as or similar to the embodiment of Fig. 12. Therefore, a duplicated description will be omitted.

[0230] A sensing line SENL may be provided for each of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 (or the sub-pixels SPXL1 to SPXL3 in FIG. 3).

[0231] The first sensing line SENL1 ​​and the second sensing line SENL2 may extend in the second direction DR2 and be located between the first sub-pixel SPXL1 and the second sub-pixel SPXL2.

[0232] The first sensing line SENL1 ​​may be connected to the third semiconductor pattern ACT3 (i.e., the third transistor M3) of the first sub-pixel SPXL1. Similarly, the second sensing line SENL2 may be connected to the third semiconductor pattern ACT3 (i.e., the third transistor M3) of the second sub-pixel SPXL2.

[0233] In this case, a sensing signal of the first sub-pixel SPXL1 (or a corresponding characteristic of the first sub-pixel SPXL1, such as a threshold voltage of the first transistor M1) can be independently acquired or detected via the first sensing line SENL1. Similarly, a sensing signal of the second sub-pixel SPXL2 (or a corresponding characteristic of the second sub-pixel SPXL2) can be independently acquired or detected via the second sensing line SENL2.

[0234] In addition, in the embodiment of FIG. 12, when the first sub-pixel SPXL1 and the second sub-pixel SPXL2 share one sensing line SENL, the sensing signal of the first sub-pixel SPXL1 and the sensing signal of the second sub-pixel SPXL2 can be acquired through one sensing line SENL. In order to acquire only the sensing signal of the first sub-pixel SPXL1 or the second sub-pixel SPXL2, the first sub-pixel SPXL1 or the second sub-pixel SPXL2 must be driven in a time division manner, and in this case, the sensing time for acquiring the sensing signals of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 (and all sub-pixels) may increase. Meanwhile, in the embodiment of FIG. 18, the sensing signals of the first sub-pixel SPXL1 and the second sub-pixel SPXL2 can be simultaneously and independently acquired through the first and second sensing lines SENL1 ​​and SENL2, thereby shortening the sensing time. For example, when it is difficult to sufficiently secure the first area A1 due to the second storage capacitor CST2, one sensing line SENL may be provided to the first sub-pixel SPXL1 and the second sub-pixel SPXL2 according to the embodiment of Fig. 12. Alternatively, when the second storage capacitor CST2 is omitted and the first area A1 is sufficiently secured, the first and second sensing lines SENL1 ​​and SENL2 may be provided to the first sub-pixel SPXL1 and the second sub-pixel SPXL2, respectively.

[0235] 18 and 19, the second sub-pixel SPXL2 according to the embodiment of Fig. 18 has a symmetrical structure with the first sub-pixel SPXL1, and the second sub-pixel SPXL2 according to the embodiment of Fig. 19 may have the same structure as the first sub-pixel SPXL1. That is, in the embodiment of Fig. 19, the transistors and capacitors of the second sub-pixel SPXL2 may be arranged in the same manner as the transistors and capacitors of the first sub-pixel SPXL1.

[0236] As mentioned above, a sensing line SENL may be provided for each sub-pixel, and the sub-pixels may have the same structure instead of a symmetric structure.

[0237] 20, 21 and 22 are plan views showing an embodiment of the display device of FIG.

[0238] 11, 20, and 21, except for the connection configuration of the pad PD and the sensing line SENL, the display devices of FIGS. 20 and 21 may be substantially the same as or similar to the display device of FIG. 11. Therefore, a duplicated description will be omitted.

[0239] The pads PD are disposed in the non-display area NDA (see FIG. 3) and can be connected to a driver (eg, a driver integrated circuit) or the like.

[0240] In one embodiment of the present invention, at least two sensing lines SENL may be connected to one pad PD, i.e., more sub-pixels SPXL1 to SPXL3 may substantially share one sensing line SENL, similar to the first and second sub-pixels SPXL1 and SPXL2 sharing one sensing line SENL as described with reference to FIG.

[0241] For example, as shown in Fig. 20, two sensing lines SENL may be connected to one pad PD. In this case, four sub-pixels SPXL1 to SPXL3 included in one row may be connected to one pad PD.

[0242] As another example, three sensing lines SENL may be connected to one pad PD as shown in Fig. 21. In this case, six sub-pixels SPXL1 to SPXL3 included in one row may be connected to one pad PD.

[0243] 18, 20 and 22, two sensing lines SENL may be disposed between two adjacent sub-pixels among the sub-pixels SPXL1 to SPXL3. In this case, at least two sensing lines SENL may be connected to one pad PD.

[0244] For example, a total of three sensing lines SENL for the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3 may be connected to one pad PD, that is, three sub-pixels SPXL1 to SPXL3 constituting one pixel may be connected to one pad PD.

[0245] As described above, at least two sensing lines SENL may be connected to one pad PD, and at least three sub-pixels SPXL1 to SPXL3 may be connected to one pad PD, that is, at least three sub-pixels SPXL1 to SPXL3 may substantially share one sensing line SENL.

[0246] Although each embodiment of the present invention has been described above with reference to the drawings, a person skilled in the art or having ordinary knowledge in the art can modify and change the present invention in various ways without departing from the concept and technical scope of the present invention described in the claims below.

[0247] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims. [Explanation of symbols]

[0248] BNK Bank BSL Base Layer CF Color Filter CE capacitor electrode CNE connection electrode CNT1, CNT2 First and second contact holes CELT Connecting Line CST Storage Capacitor EA Lane ELT electrode INS Insulating layer LD light emitting element OPN hole PCL Pixel circuit layer PD Pad PL power line PNL display panel PXL Pixel PXC pixel circuit SPXL Subpixel T transistor QD color conversion particles

Claims

1. a pixel circuit layer disposed on the base layer and including a conductive pattern constituting at least one of a transistor, a capacitor, and a signal line; a first electrode and a second electrode spaced apart from each other and disposed on the pixel circuit layer; a bank disposed on the first electrode and the second electrode and including an aperture; a light emitting element disposed between the first electrode and the second electrode within the opening of the bank, a space between the first electrode and the second electrode spaced apart from each other by a distance corresponding to a length of the light emitting device in the opening of the bank is defined as a lane in which the light emitting device is disposed; A display device characterized in that, in a plan view, the lane is arranged apart from all conductive patterns of the pixel circuit layer and is separated from the conductive patterns by more than half the length of the light-emitting element.

2. The length of the light emitting element is 10 μm or less, The display device according to claim 1 , wherein the lane is spaced from the conductive pattern by 6 μm or more in a plan view.

3. The pixel circuit layer further includes an insulating layer, the conductive patterns are connected to each other through contact holes penetrating a portion of the insulating layer; The display device according to claim 1 , wherein the lane is spaced apart from all the contact holes by at least half the length of the light emitting element in a plan view.

4. further comprising sub-pixels each including said lane; The conductive pattern includes a first line extending in a second direction, a first sub-pixel and a second sub-pixel adjacent to each other in a first direction with the first line interposed therebetween have structures symmetrical to each other with respect to the first line in a plan view; the first sub-pixel and the second sub-pixel share the first line; The display device of claim 1 , wherein the first lines are repeatedly arranged along the first direction at intervals corresponding to two of the sub-pixels.

5. the conductive pattern includes a first power supply line and a second power supply line extending in the first direction; the light emitting device is electrically connected between the first power line and the second power line, the first power line and the second power line are spaced apart from each other by a distance corresponding to two of the sub-pixels; the first power supply lines and the second power supply lines are repeatedly arranged along the first direction at intervals corresponding to four of the sub-pixels; each of the first power line and the second power line includes three conductive layers spaced apart with an insulating layer therebetween; the conductive pattern further includes a first auxiliary power line and a second auxiliary power line extending in the first direction; the first auxiliary power line is electrically connected to the first power line, The display device of claim 4, wherein the second auxiliary power line is electrically connected to the second power line.

6. the first electrodes and the second electrodes extend in the second direction and are alternately and repeatedly arranged along the first direction; 6. The display device of claim 5, wherein the first electrode is electrically connected to the first power line through a first connection line and a first contact hole extending in the first direction.

7. The conductive pattern is a first auxiliary power line extending in a first direction; a first capacitor and a second capacitor spaced apart in a second direction across the first auxiliary power line in a plan view; 2. The display device of claim 1, wherein the first capacitor and the second capacitor are electrically connected in parallel.

8. The light emitting device further includes a connection electrode disposed on the light emitting device, the lanes include a first lane, a second lane, a third lane, and a fourth lane spaced apart from one another within the opening of the bank; The light emitting device includes a first light emitting device located in the first lane, a second light emitting device located in the second lane, a third light emitting device located in the third lane, and a fourth light emitting device located in the fourth lane, the first to fourth light emitting elements are electrically connected in series via the connection electrode, The display device according to claim 1 , wherein a portion of the connecting electrode includes a closed loop.

9. the conductive pattern includes a first auxiliary power line extending in a first direction, 2. The display device according to claim 1, wherein, in a plan view, the lane of a subpixel is arranged in a region different from the transistor and the capacitor of the pixel circuit layer of the subpixel with respect to the first auxiliary power line.

10. further comprising a first sub-pixel and a second sub-pixel each including the lane; The conductive pattern includes a first line extending in a second direction, the first sub-pixel and the second sub-pixel adjacent to each other across two of the first lines have structures symmetrical to each other in a plane; The display device of claim 1 , wherein three of the first lines are connected to one pad.

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