Method for forming air gap spacer for semiconductor device and semiconductor device

Abstract

To provide semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices, and methods for fabricating such air gap spacers.SOLUTION: For example, a method includes forming a first metallic structure and a second metallic structure on a substrate, the first metallic structure and the second metallic structure being disposed adjacent to each other with insulating material disposed therebetween. The insulating material is etched to form a space between the first metallic structure and the second metallic structure. A layer of dielectric material is deposited over the first metallic structure and the second metallic structure using a pinch-off deposition process to form an air gap in the space between the first metallic structure and the second metallic structure. A portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The field relates generally to semiconductor fabrication, and more particularly to techniques for fabricating air gap spacers for semiconductor devices. [Background technology]

[0002] Semiconductor manufacturing technology continues to advance with ever-decreasing design rules and higher integration densities, resulting in increasingly finer separations between adjacent structures within integrated circuits. Therefore, undesired capacitive coupling can occur between adjacent structures within an integrated circuit, such as adjacent metal lines in back-end-of-line (BEOL) interconnect structures and adjacent contacts in front-end-of-line (FEOL) devices (e.g., middle-of-the-line (MOL) device contacts). The parasitic capacitance associated with these structures can degrade the performance of semiconductor devices. For example, capacitive coupling between transistor contacts can lead to increased gate-to-source or gate-to-drain parasitic capacitance, which can adversely affect the transistor's operating speed and increase the energy consumption of the integrated circuit. Furthermore, undesired capacitive coupling between adjacent metal lines in BEOL structures can lead to increased resistive-capacitive delay (or latency), crosstalk, and increased dynamic power dissipation in the interconnect stack.

[0003] To reduce parasitic coupling between adjacent conductive structures, the semiconductor industry has adopted the use of low-k dielectrics and ultra-low-k (ULK) dielectrics (instead of conventional SiO2 (k = 4.0)) as insulating materials in the MOL and BEOL layers of ultra-large-scale integrated circuits (ULSI). However, the emergence of low-k dielectrics associated with rapid miniaturization has created significant challenges in terms of the long-term reliability of these low-k materials. For example, low-k materials generally have lower intrinsic dielectric breakdown strength than conventional SiO2 dielectrics, so low-k TDDB (time-dependent dielectric breakdown) is generally considered a significant issue. TDDB generally refers to the loss of dielectric insulating properties over time when a dielectric is subjected to voltage / current bias and temperature stress. TDDB causes increased leakage current, thereby degrading the performance of nanoscale integrated circuits. Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device having an air gap spacer formed as part of a BEOL layer or MOL layer of the semiconductor device, and a method for making such an air gap spacer, are provided. [Means for solving the problem]

[0005] Embodiments of the present invention include semiconductor devices having air gap spacers formed as part of the BEOL or MOL layers of the semiconductor device, and methods of making air gap spacers as part of the BEOL and MOL layers of a semiconductor device.

[0006] For example, a method for fabricating a semiconductor device includes forming a first metal structure and a second metal structure on a substrate, the first metal structure and the second metal structure being adjacent to each other with an insulating material therebetween, etching the insulating material to form a space between the first metal structure and the second metal structure, and depositing a layer of dielectric material over the first metal structure and the second metal structure to form a void in the space between the first metal structure and the second metal structure, a portion of the void extending above a top surface of at least one of the first metal structure and the second metal structure.

[0007] In one embodiment, the first metal structure includes a first metal line formed in an interlevel dielectric layer of the BEOL interconnect structure, and the second metal structure includes a second metal line formed in an ILD layer of the BEOL interconnect structure.

[0008] In another embodiment, the first metal structure includes a device contact and the second metal structure includes a gate structure of a transistor, hi one embodiment, the device contact is higher than the gate structure and the portion of the air gap extends above the gate structure and below an upper surface of the device contact.

[0009] Other embodiments are described in the following detailed description, which should be read in connection with the accompanying drawings. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic diagram illustrating a semiconductor device with air gap spacers integrally formed within a BEOL structure of the semiconductor device according to an embodiment of the present invention. [Figure 2] 1 is a schematic diagram illustrating a semiconductor device with air gap spacers integrally formed within a BEOL structure of the semiconductor device according to an embodiment of the present invention. [Figure 3]FIG. 10 is a diagram illustrating the improved TDDB reliability and reduced capacitive coupling between metal lines in BEOL structures achieved using an air gap structure formed using a pinch-off deposition method according to an embodiment of the present invention compared to an air gap structure formed using a conventional method. [Figure 4] FIG. 10 is a schematic illustrating improved TDDB reliability and reduced capacitive coupling between metal lines in BEOL structures achieved using an air gap structure formed using a pinch-off deposition method according to an embodiment of the present invention compared to an air gap structure formed using a conventional method. [Figure 5] 2 is a schematic cross-sectional view illustrating a semiconductor device with an air gap spacer integrally formed within a BEOL structure of the semiconductor device according to another embodiment of the present invention. [Figure 6] 2A-2C are schematic cross-sectional views illustrating a semiconductor device at an intermediate fabrication stage in which a pattern of openings is formed in an ILD (interlayer dielectric) layer, illustrating a method of fabricating the semiconductor device of FIG. 1 according to an embodiment of the present invention. [Figure 7] 6 is a schematic cross-sectional view of the semiconductor device of FIG. 6 after depositing a conformal layer of liner material and depositing a layer of metal material to fill the opening in the ILD layer, illustrating a method of fabricating the semiconductor device of FIG. 1 according to an embodiment of the present invention. [Figure 8] 7 is a schematic cross-sectional view of the semiconductor device of FIG. 7 after planarizing the surface of the semiconductor structure down to the ILD layer and forming a metal wiring layer, illustrating a method of fabricating the semiconductor device of FIG. 1 according to an embodiment of the present invention. [Figure 9] 8 is a schematic cross-sectional view of the semiconductor device of FIG. 8 after forming protective caps on the metal lines of the metal wiring layer, illustrating a method of fabricating the semiconductor device of FIG. 1 according to an embodiment of the present invention. [Figure 10]9 is a schematic cross-sectional view of the semiconductor device of FIG. 9 after etching the ILD layer to form spaces between the metal lines of the metal wiring layer, illustrating a method of fabricating the semiconductor device of FIG. 1 according to an embodiment of the present invention. [Figure 11] 10 is a schematic cross-sectional view of the semiconductor device of FIG. 10 after depositing a conformal layer of insulating material to form an insulating liner covering the exposed surfaces of the metal wiring layer and the ILD layer. [Figure 12] 11 is a schematic cross-sectional view of the semiconductor device of FIG. 11 illustrating a process for depositing a dielectric material using a non-conformal deposition process to initiate the formation of pinch-off regions in the deposited dielectric material over spaces between metal lines of a metal wiring layer, which is a schematic illustration of a method for fabricating the semiconductor device of FIG. 1 according to an embodiment of the present invention. [Figure 13] 1 is a schematic cross-sectional view illustrating a semiconductor device with an air gap spacer integrally formed within the FEOL / MOL structure of the semiconductor device according to another embodiment of the present invention. [Figure 14] 14A-14C are schematic cross-sectional views illustrating a method of fabricating the semiconductor device of FIG. 13 according to an embodiment of the present invention, showing the semiconductor device at an intermediate fabrication stage in which a vertical transistor structure is formed on a semiconductor substrate. [Figure 15] FIG. 15 is a schematic cross-sectional view of the semiconductor device of FIG. 14 after patterning the premetal dielectric layer to form contact openings between gate structures of the vertical transistor structure, illustrating a method of fabricating the semiconductor device of FIG. 13 according to an embodiment of the present invention. [Figure 16] 15 is a schematic cross-sectional view of the semiconductor device of FIG. 15 after forming a conformal liner layer on the surface of the semiconductor device to line the contact openings with the liner material, illustrating a method of fabricating the semiconductor device of FIG. 13 according to an embodiment of the present invention. [Figure 17]FIG. 16 is a schematic cross-sectional view of the semiconductor device of FIG. 16 after depositing a layer of metal material to fill the contact openings and planarizing the surface of the semiconductor device to form MOL device contacts. [Figure 18] 17 is a schematic cross-sectional view of the semiconductor device of FIG. 17 after recessing the gate capping layer and sidewall spacers of the gate structure of the vertical transistor structure, which is a schematic illustration of a method of fabricating the semiconductor device of FIG. 13 according to an embodiment of the present invention. [Figure 19] FIG. 18 is a schematic cross-sectional view of the semiconductor device of FIG. 18 after depositing a conformal layer of insulating material to form an insulating liner lining the exposed surfaces of the gate structure and MOL device contacts, illustrating a method of fabricating the semiconductor device of FIG. 13 according to an embodiment of the present invention. [Figure 20] 19A is a schematic cross-sectional view of the semiconductor device of FIG. 19 after a dielectric material has been deposited using a non-conformal deposition process to create a pinch-off region that forms a void in the space between the gate structure and the MOL device contact;

[0033] FIG. 19B is a schematic cross-sectional view of the semiconductor device of FIG. 19 after a dielectric material has been deposited using a non-conformal deposition process to create a pinch-off region that forms a void in the space between the gate structure and the MOL device contact; [Figure 21] 20A is a schematic cross-sectional view of the semiconductor device of FIG. 20 after planarizing the surface of the semiconductor device down to the MOL device contacts and depositing an ILD layer as part of the first interconnect level of the BEOL structure. DETAILED DESCRIPTION OF THE INVENTION

[0011] Embodiments will now be described in further detail with respect to semiconductor integrated circuit devices having air gap spacers formed as part of the back-end of line (BEOL) and / or MOL layers, and methods of fabricating air gap spacers as part of the back-end of line (BEOL) and / or MOL layers of semiconductor integrated circuit devices. In particular, as described in further detail below, embodiments of the present invention include methods of fabricating air gap spacers using a "pinch-off" deposition technique that utilizes specific dielectric materials and deposition techniques to control the size and shape of the formed air gap spacers, thereby optimizing the air gap spacer formation for a target application. The exemplary pinch-off deposition methods described herein for forming air gap spacers result in improved TDDB reliability and optimal capacitance drop in the back-end of line (BEOL) and MOL layers of semiconductor integrated circuit devices.

[0012] It should be understood that the various layers, structures, and regions illustrated in the accompanying figures are represented diagrammatically and are not necessarily drawn to scale. Moreover, for ease of explanation, in a given figure, one or more layers, structures, and regions of the type typically used to form semiconductor devices or structures may not be explicitly shown. However, the fact that layers, structures, and regions are not explicitly shown does not mean that they are omitted in an actual semiconductor structure.

[0013] Furthermore, it should be understood that the embodiments described herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is emphasized that the descriptions provided herein are not intended to encompass all processing steps that may be required to form a working semiconductor integrated circuit device. Rather, certain processing steps commonly used in forming semiconductor devices, such as wet cleaning steps and annealing steps, have not been described herein to avoid redundant description.

[0014] Furthermore, the same or similar features, elements, or structures are referred to by the same or similar reference numerals throughout the drawings, and detailed descriptions of these same or similar features, elements, or structures will not be repeated in each drawing. It should be understood that the terms "about" or "substantially" used in this specification in connection with thickness, width, ratio, range, etc., do not mean exact, but rather mean close or approximate. For example, the terms "about" or "substantially" used in this specification mean that there is a small margin of error, such as less than 1% of the stated amount.

[0015] 1 and 2 are schematic diagrams illustrating a semiconductor device 100 including an air gap spacer integrally formed within a BEOL structure of the semiconductor device, according to an embodiment of the present invention. FIG. 1 is a schematic cross-sectional view of the semiconductor device 100 taken along line 1A-1A in FIG. 2, and FIG. 2 is a schematic plan view of the semiconductor device 100 along a plane including line 1B-1B shown in FIG. 1. More specifically, FIG. 1 is a schematic cross-sectional view of the semiconductor device 100 in the XZ plane, and FIG. 2 is a plan view illustrating the layout of various elements in the XY plane, as shown in XYZ Cartesian coordinates shown in FIGS. 1 and 2. It should be understood that the terms "vertical" or "vertical direction" as used herein refer to the Z direction of the Cartesian coordinate system shown in the drawings, and the terms "horizontal" or "horizontal direction" as used herein refer to the X and / or Y directions of the Cartesian coordinate system shown in the drawings.

[0016] In particular, FIG. 1 schematically illustrates a semiconductor device 100 including a substrate 110, a FEOL / MOL structure 120, and a BEOL structure 130. In one embodiment, the substrate 110 comprises a bulk semiconductor substrate composed of, for example, silicon or other types of semiconductor substrate materials commonly used in bulk semiconductor fabrication processes, such as germanium, silicon-germanium alloys, silicon carbide, silicon-germanium carbide alloys, or compound semiconductor materials (e.g., III-V and II-VI). Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide. The thickness of the substrate 110 varies depending on the application. In another embodiment, the substrate 110 is a silicon-on-insulator (SOI) substrate comprising an insulating layer (e.g., an oxide layer) disposed between a base semiconductor substrate (e.g., a silicon substrate) and an active semiconductor layer (e.g., an active silicon layer) in which active circuit components (e.g., field-effect transistors) are formed as part of the FEOL layers.

[0017] In particular, the FEOL / MOL structure 120 comprises FEOL layers formed on the substrate 110. The FEOL layers comprise various semiconductor devices and components formed in or on the active surface of the semiconductor substrate 110 to form integrated circuits for a target application. For example, the FEOL layers comprise FET devices (e.g., FinFET devices, planar MOSFET devices), bipolar transistors, diodes, capacitors, inductors, resistors, isolation devices, etc., formed in or on the active surface of the semiconductor substrate 110. In general, FEOL processes typically include preparing the substrate 110 (or wafer), forming isolation structures (e.g., shallow trench isolation), forming device wells, patterning gate structures, forming spacers, forming source / drain regions (e.g., by implantation), forming silicide contacts on the source / drain regions, forming stress liners, etc.

[0018] The FEOL / MOL structure 120 further includes a MOL layer formed on the FEOL layer. Typically, the MOL layer includes a PMD (pre-metal dielectric) layer and conductive contacts (e.g., via contacts) formed within the PMD layer. The PMD layer is formed over the components and devices of the FEOL layer. A pattern of openings is formed in the PMD layer, and the openings are filled with a conductive material, such as tungsten, to form conductive via contacts that electrically contact device terminals (e.g., source / drain regions, gate contacts, etc.) of the integrated circuits in the FEOL layer. The conductive via contacts in the MOL layer provide electrical connection between the integrated circuits in the FEOL layer and the first metallization level of the BEOL structure 130.

[0019] BEOL structures 130 are formed on FEOL / MOL structures 120 to connect various integrated circuit components in the FEOL layers. As is known in the art, BEOL structures comprise multiple levels of dielectric material and multiple levels of metallization embedded in the dielectric material. BEOL metallization includes horizontal wiring, interconnects, pads, etc., as well as vertical wiring in the form of conductive vias that form connections between different interconnect levels of the BEOL structures. BEOL fabrication processes involve the sequential deposition and patterning of multiple layers of dielectric and metallic materials to form a network of electrical connections between FEOL devices and to provide I / O connections with external components.

[0020] In the exemplary embodiment of FIG. 1 , the BEOL structure 130 includes a first interconnect level 140 and a second interconnect level 150. The first interconnect level 140 is illustrated schematically but may include one or more low-k interlevel dielectric (ILD) layers and metal via and wiring levels (e.g., copper damascene structures). A capping layer 148 is formed between the first interconnect level 140 and the second interconnect level 150. The capping layer 148 serves to insulate the metallization of the first interconnect level 140 from the dielectric material of the ILD layer 151. For example, the capping layer 148 serves to improve interconnect reliability and prevent copper metallization from diffusing out of the ILD layer 151 of the second interconnect level 150. Capping layer 148 may comprise any suitable insulating or dielectric material, including, but not limited to, silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), hydrogenated silicon carbide (SiCH), multi-layer stacks comprising homogeneous or heterogeneous dielectric materials, etc. Capping layer 148 may be deposited using standard deposition techniques, such as, for example, chemical vapor deposition. Capping layer 148 may be formed to a thickness ranging from about 2 nm to about 60 nm.

[0021] The second interconnect level 150 includes an ILD layer 151 and a metal wiring layer 152 formed within the ILD layer 151. The ILD layer 151 can be formed using any suitable dielectric material, including, but not limited to, silicon oxide (e.g., SiO), SiN (e.g., SiN), hydrogenated silicon carbonate (SiCOH), silicon-based low-k dielectrics, porous dielectrics, or other known ULK (ultra-low-k) dielectric materials. The ILD layer 151 can be deposited using known deposition techniques, such as ALD (atomic layer deposition), CVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), or PVD (physical vapor deposition). The thickness of the ILD layer 151 varies depending on the application and can range, for example, from about 30 nm to about 200 nm.

[0022] Metal wiring layer 152 includes a plurality of closely spaced metal lines 152-1, 152-2, 152-3, 152-4, 152-5, and 152-6, which are formed by filling trenches / openings patterned in ILD layer 151 with a metal material. The trenches / openings are lined with a conformal liner layer 153, which acts as a diffusion barrier layer to prevent migration of the metal material (e.g., Cu) into ILD layer 151, as well as an adhesion layer to provide good adhesion to the metal material (e.g., Cu) being used to fill the trenches / openings in ILD layer 151 to form metal lines 152-1, ..., 152-6.

[0023] As further shown in FIG. 1 , second interconnect level 150 further comprises protective caps 154 selectively formed on the upper surfaces of metal lines 152-1, 152-2, 152-3, 152-4, 152-5, and 152-6, a conformal insulating liner 155 conformally covering metal wiring layer 152, and a dielectric capping layer 156 deposited using a pinch-off deposition technique to form gap spacers 158 between metal lines 152-1, 152-2, 152-3, 152-4, 152-5, and 152-6. Protective caps 154 and conformal insulating liner 155 serve to protect metal wiring 152 from potential structural damage or contamination that may result from subsequent processing steps and environmental conditions. Exemplary materials and methods for forming protective caps 154 and conformal insulating liner 155 are described in further detail below with reference to FIGS. 9 through 11 .

[0024] Air gap spacers 158 are formed in the spaces between metal lines 152-1, 152-2, 152-3, 152-4, 152-5, and 152-6 of metal wiring layer 152 as a means of reducing parasitic capacitive coupling between adjacent metal lines in metal wiring layer 152. As described in further detail below, a dielectric air gap integration process is performed as part of the BEOL fabrication process, in which portions of the dielectric material of ILD layer 151 are etched away to form spaces between metal lines 152-1, 152-2, 152-3, 152-4, 152-5, and 152-6 of wiring layer 152. Dielectric capping layer 156 is formed using a non-conformal deposition process (e.g., chemical vapor deposition) that deposits a dielectric material that forms a "pinch-off" region 156-1 above upper portions of the spaces between the metal lines of wiring layer 152, thereby forming air gap spacers 158. 1, in one embodiment of the present invention, pinch-off region 156-1 is formed above the top surfaces of metal lines 152-1, ..., 152-6 of metal wiring layer 152, as indicated by dashed line 1B-1B. In this regard, air gap spacers 158 formed between metal lines 152-1, ..., 152-6 extend vertically into dielectric capping layer 156 above metal lines 152-1, ..., 152-6.

[0025] Furthermore, in one embodiment of the present invention, as shown in FIG. 2 , the air gap spacers 158 formed between the metal lines 152-1, ..., 152-6 extend horizontally (e.g., in the Y direction) beyond the ends of adjacent metal lines. In particular, FIG. 2 illustrates an exemplary interdigitated layout pattern of the metal wiring layer 152. In this layout pattern, the metal lines 152-1, 152-3, and 152-5 each have one end connected to the elongated metal line 152-7, and the metal lines 152-2, 152-4, and 152-6 each have one end connected to the elongated metal line 152-8. As shown in FIG. 2 , the air gap spacers 158 extend horizontally beyond the open (unconnected) ends of the metal lines 152-1, ..., 152-6. Compared to conventional air gap structures, the size and shape of the air gap spacers 158 illustrated in FIGS. 1 and 2 result in improved TDDB reliability and reduced capacitive coupling between the metal lines. The reason for this will now be explained in more detail with reference to FIGS.

[0026] 3 and 4 are diagrams illustrating the improved TDDB reliability and reduced capacitive coupling between metal lines in BEOL structures achieved using an air gap structure formed using pinch-off deposition according to an embodiment of the present invention, as compared to an air gap structure formed using conventional methods. In particular, FIG. 3 illustrates a portion of metal wiring layer 152 of FIG. 1, including metal lines 152-1 and 152-2 and an air gap 158 formed between the metal lines by forming a dielectric capping layer 156 using a pinch-off deposition process according to an embodiment of the present invention. As shown in FIG. 3, metal line 152-1 and its associated liner 153 and metal line 152-2 and its associated liner 153 are formed to have width W and are spaced apart by a distance S. Additionally, FIG. 4 schematically illustrates a semiconductor structure similar to FIG. 3, but with an air gap 168 disposed between the same two metal lines 152-1 and 152-2 having the same width W and spacing S, but where the air gap 168 is formed by forming a dielectric capping layer 166 using a conventional pinch-off deposition process.

[0027] As shown in FIG. 3, a "pinch-off" region 156-1 is formed in dielectric capping layer 156 such that void 158 extends above the top surfaces of metal lines 152-1 and 152-2. In contrast, as shown in FIG. 4, a conventional pinch-off deposition process forms pinch-off region 166-1 in dielectric capping layer 166 below the top surfaces of metal lines 152-1 and 152-2 such that the resulting void 168 does not extend above metal lines 152-1 and 152-2. Furthermore, as shown in FIGS. 3 and 4 for comparison, the amount of dielectric material deposited on the sidewalls and bottom of the space between metal lines 152-1 and 152-2, as shown in FIG. 4, using a conventional pinch-off deposition process is significantly greater than the amount of dielectric material deposited on the sidewalls and bottom of the space between metal lines 152-1 and 152-2, as shown in FIG. 3, using a pinch-off deposition process according to an embodiment of the present invention. As a result, the volume V1 of the resulting void 158 shown in FIG. 3 is significantly larger than the volume V2 of the resulting void 168 shown in FIG.

[0028] The structure of Figure 3 has various associated advantages over the conventional structure shown in Figure 4. For example, the larger volume V1 of air gap 158 (less dielectric material deposited in the space between the metal lines) reduces the parasitic capacitance between metal lines 152-1 and 152-2 (compared to the structure of Figure 4). In fact, the smaller dielectric material and larger volume V1 of air (k=1) in the space between metal lines 152-1 and 152-2 in Figure 3 reduces the effective dielectric constant in the space between metal lines 152-1 and 152-2 in Figure 3 compared to Figure 4.

[0029] Furthermore, the structure of FIG. 3 provides improved TDDB reliability compared to the structure of FIG. 4. In particular, because the air gap 158 extends above the metal lines 152-1 and 152-2 as shown in FIG. 3, there is a long diffusion / conduction path P1 between the critical interface of the metal line 152-1 and the critical interface of the metal line 152-2 (the critical interface being the interface between the dielectric capping layer 156 and the top surfaces of the metal lines 152-1 and 152-2). This contrasts with the short diffusion / conduction path P2 in the dielectric capping layer 166 between the critical interface of the metal line 152-1 and the critical interface of the metal line 152-2 in the structure shown in FIG. 4. If a TDDB failure mechanism occurs in the structure of FIG. 3 or FIG. 4, it occurs due to breakdown of the dielectric material and the formation of a conductive path in the dielectric material between the top surfaces of the metal lines 152-1 and 152-2 due to electron tunneling current. The long diffusion path P1 of the structure shown in FIG. 3, optionally in conjunction with a dense dielectric liner 155 material with superior dielectric breakdown strength, will result in improved TDDB reliability of the structure of FIG. 3 compared to the structure shown in FIG. 4.

[0030] Furthermore, extending the air gap spacers 158 horizontally beyond the ends of the metal lines as shown in Figure 2 further improves TDDB reliability and further reduces capacitive coupling for the same reasons as described with reference to Figure 3. In particular, extending the air gaps 158 beyond the ends of, for example, metal line 152-1 as shown in Figure 2 creates a long diffusion / conduction path between the critical interface at the open ends of metal line 152-1 and adjacent metal line 152-2. In an alternative embodiment of Figure 2, air gap spacers may be formed between elongated metal line 152-8 and adjacent open ends of metal lines 152-1, 152-3, and 152-5, and between elongated metal line 152-7 and adjacent open ends of metal lines 152-2, 152-4, and 152-6, thereby further optimizing TDDB reliability and reducing capacitive coupling between the interdigitated comb structures.

[0031] FIG. 5 is a schematic cross-sectional view illustrating a semiconductor device having void spacers integrally formed within its BEOL structure in accordance with another embodiment of the present invention. In particular, FIG. 5 schematically illustrates a semiconductor device 100′ having a structure similar to that of the semiconductor device 100 shown in FIGS. 1 / 2 , except that the void spacers 158 shown in FIG. 5 do not extend beyond the bottom surfaces of the metal lines in the metal wiring layer 152. In this structure, the ILD layer 151 is recessed to the level of the bottom of the metal lines (as compared to being recessed below the bottom of the metal lines, as shown in FIG. 10 , forming long void spacers as shown in FIG. 1 ). In other embodiments of the present invention, although FIGS. 1 and 5 illustrate a BEOL structure 130 having first and second interconnect levels 140 and 150, the BEOL structure 130 may also have one or more additional interconnect levels formed above the second interconnect level 150. Such additional interconnect levels may be formed to include void spacers using the techniques and materials described herein.

[0032] A method of fabricating the semiconductor device 100 of FIG. 1 (and FIG. 5) will now be described in more detail with reference to FIGS. 6 through 12, which schematically illustrate the semiconductor device 100 at various stages of fabrication. For example, FIG. 6 is a schematic cross-sectional view illustrating the semiconductor device 100 at an intermediate fabrication stage after forming a pattern of openings 151-1 (e.g., damascene openings including trench and via openings) in the ILD layer 151, in accordance with an embodiment of the present invention. In particular, FIG. 6 schematically illustrates the semiconductor device 100 of FIG. 1 at an intermediate fabrication stage after sequentially forming the FEOL / MOL structure 120, the first interconnect level 140, the capping layer 148, and the ILD layer 151 on the substrate 110, and patterning the ILD layer 151 to form the openings 151-1 in the ILD layer 151. After the ILD layer 151 is deposited, standard photolithography and etching processes can be performed to etch openings 151-1 in the ILD layer 151, which are then filled with a metal material to form the metal wiring layer 152 of Figure 1. Note that although vertical vias are not shown in the ILD layer 151, vertical vias are present in the second interconnect level 150 to provide vertical connections to the metallization of the underlying interconnect level 140.

[0033] 6, openings 151-1 are shown as having a width W and spaced apart by a distance S. In one embodiment of the invention, in situations where a pinch-off deposition method is used to form air gap spacers between adjacent metal lines, the width W of the openings (in which the metal lines are formed) can range from about 2 nm to about 25 nm, with a preferred range being about 6 nm to about 10 nm. Further, in one embodiment, the spacing S between the metal lines can range from about 2 nm to about 25 nm, with a preferred range being about 6 nm to about 10 nm.

[0034] The next process module of the exemplary fabrication process involves forming the metal interconnect layer 152 shown in FIG. 1 using the process flows generally illustrated in FIGS. 7 and 8. In particular, FIG. 7 is a schematic cross-sectional view of the semiconductor device of FIG. 6 after depositing a conformal layer of liner material 153A and depositing a layer of metal material 152A over the conformal layer of liner material 153A to fill opening 151-1 in ILD layer 151. Additionally, FIG. 8 is a schematic cross-sectional view of the semiconductor device of FIG. 7 after planarizing the surface of the semiconductor structure down to ILD layer 151 to form metal interconnect layer 152. Metal interconnect layer 152 can be formed using known materials and techniques.

[0035] For example, the conformal layer of liner material 153A is preferably deposited to line the sidewalls and bottom of the opening 151-1 in the ILD layer 151 with a thin liner layer. This thin liner layer can be formed by conformally depositing one or more thin layers of material such as tantalum nitride (TaN), cobalt (Co), ruthenium (Ru), manganese (Mn), or manganese nitride (MnN), or other liner materials (or combinations of liner materials such as Ta / TaN, TiN, CoWP, NiMoP, or NiMoB) suitable for a given application. This thin liner layer serves multiple purposes. For example, this thin liner layer functions as a diffusion barrier layer to prevent migration / diffusion of metallic materials (e.g., Cu) into the ILD layer 151. Additionally, this thin liner layer functions as an adhesion layer to provide good adhesion of the metallic material (e.g., Cu) used to fill the opening 151-1 in the ILD layer 151 to the layer 152A.

[0036] In one embodiment, the layer of metallic material 152A comprises a metallic material, such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), or ruthenium (Ru), deposited using known techniques, such as electroplating, electroless plating, CVD, PVD, or a combination of these methods. Prior to filling the openings 151-1 in the ILD layer 151 with a conductive material, a thin seed layer (e.g., a Cu seed layer) can optionally be deposited (on the conformal liner layer 153A) using a suitable deposition technique, such as ALD, CVD, or PVD. The seed layer can be composed of a material that improves adhesion between the metallic material and the underlying material and acts as a catalytic material during a subsequent plating process. For example, the Cu metallization layer 152 can be formed by depositing a thin conformal Cu seed layer on the surface of the substrate using PVD, followed by electroplating Cu to fill the openings 151-1 (e.g., trenches and vias) formed in the ILD layer 151. A chemical mechanical polishing process (CMP) is then performed to remove excess liner, seed, and metallization material and planarize the surface of the semiconductor structure down to the ILD layer 151, resulting in the intermediate structure shown in FIG.

[0037] In one embodiment of the present invention, after the CMP process, a protective layer may be formed over the exposed surfaces of the metal lines 152-1, ..., 152-6 to protect the metallization from potential damage due to subsequent processing conditions and the environment. For example, FIG. 9 is a schematic cross-sectional view illustrating the semiconductor device of FIG. 8 after protective caps 154 have been formed over the metal lines 152-1, ..., 152-6 in accordance with an embodiment of the present invention. In one embodiment, for copper metallization, the protective caps 154 may be formed using a selective Co deposition process that selectively deposits a thin capping layer of Co over the exposed surfaces of the metal lines 152-1, ..., 152-6. In other embodiments of the present invention, the protective caps 154 may be composed of other materials, such as tantalum (Ta) or ruthenium (Ru). The protective caps 154 over the metal lines 152-1, ..., 152-6 are optional features that may be utilized, if desired, to allow for more aggressive etching conditions, etc., when forming air gap spacers and other structures using the techniques described herein below.

[0038] The next step in the fabrication process involves forming gap spacers in second interconnect level 150 using the process flows generally illustrated in FIGS. 10, 11, and 12. In particular, FIG. 10 is a schematic cross-sectional view illustrating the semiconductor device of FIG. 9 after etching exposed portions of ILD layer 151 to form spaces 151-2 between metal lines 152-1, ..., 152-6, in accordance with an embodiment of the present invention. In one embodiment, any suitable masking technique (e.g., a photoresist mask) and etching technique (e.g., RIE (reactive ion etching)) can be used to recess portions of ILD layer 151 to form spaces 151-2, as shown in FIG. 10. For example, in one embodiment, a dry etching technique using a fluorine-based etchant can be used to remove dielectric material in ILD layer 151 to form spaces 151-2. In one embodiment, spaces 151-2 are formed such that the recessed surfaces of ILD layer 151 are below the bottom surfaces of metal lines 152-1, ..., 152-6, as shown in FIG. In another embodiment, the etching process can be performed such that the spaces 151-2 are recessed to the level of the bottom surfaces of the metal lines 152 (see FIG. 5). In areas of the metal lines 152 where the metal lines are relatively far apart, the ILD layer 151 is not removed because the inter-line capacitance between widely spaced metal lines can be assumed to be negligible.

[0039] The next step in this process involves depositing a conformal layer of insulating material over the semiconductor structure of FIG. 8 to form conformal insulating liner 155, as shown in FIG. 11. Conformal insulating liner 155 is an optional protective feature and can also be formed before the pinch-off deposition process to provide additional protection to the exposed surfaces of ILD layer 151 and metal wiring layer 152. For example, in the exemplary embodiment of FIG. 11, conformal liner layer 153 provides some protection to the sidewalls of metal lines 152-1, ..., 152-6, but conformal insulating liner 155 can provide additional protection against oxidation of metal lines 152-1, ..., 152-6 when the metal lines are composed of copper and liner layer 153 is insufficient to prevent oxygen diffusion from subsequently formed void spacers 158 into the metal lines. In practice, although the void spacer 158 is later formed to have a near-vacuum environment, there is still some oxygen present within the void spacer 158, which may lead to oxidation of the copper metal line if the liner layer 153 allows the residual oxygen within the void spacer 158 to diffuse through the liner layer 153 and into the metal line.

[0040] Furthermore, the conformal insulating liner 155 can be formed with one or more robust, ultra-thin dielectric material layers that have desirable electrical and mechanical characteristics, such as low leakage, high dielectric breakdown, and hydrophobicity, resulting in reduced damage during subsequent semiconductor processing steps. For example, the conformal insulating liner 155 can be composed of a dielectric material such as SiN, SiCN, SiNO, SiCNO, SiBN, SiCBN, SiC, or other dielectric materials having the desired electrical and mechanical properties described above. In one embodiment, the conformal insulating liner 155 is formed to a thickness ranging from about 0.5 nm to about 5 nm. The conformal insulating liner 155 can also be composed of multiple conformal layers of the same or different dielectric materials deposited using a cyclic deposition process. For example, in one embodiment, the conformal insulating liner 155 can be composed of multiple thin conformal layers of SiN (e.g., 0.1 nm to 0.2 nm thick SiN layers) deposited sequentially to form a SiN liner layer having a desired overall thickness.

[0041] 11 , after forming conformal insulating liner 155, spaces 151-2 between metal lines in metal wiring layer 152 are shown as having an initial volume V i . In particular, in one embodiment that forms conformal insulating liner 155, this volume V i is defined by the sidewalls and bottom surface of conformal insulating liner 155 and dashed line L, which indicates the top surface of conformal insulating liner 155 on metal wiring layer 152. In another embodiment of the invention, when conformal insulating liner 155 is not formed, initial volume V i would be defined by the exposed surface of liner layer 153, the recessed surface of ILD layer 151, and the top surfaces of the metal lines in metal wiring layer 152. As described below, after forming void spacers 158 using a pinch-off deposition process according to an embodiment of the invention, a significant portion of initial volume V i remains within spaces 151-2 between the metal lines.

[0042] The next step in this fabrication process involves depositing a dielectric material over the semiconductor structure of FIG. 11 using a pinch-off deposition process to form gap spacers 158 in the spaces 151-2 between the metal lines of the metal wiring layer 152. For example, FIG. 12 is a schematic diagram illustrating a process for depositing a layer of dielectric material 156A using a non-conformal deposition process (e.g., PECVD or PVD) that initiates the formation of pinch-off regions in the deposited dielectric material 156A over the spaces 151-2 between the metal lines of the metal wiring layer 152, in accordance with an embodiment of the present invention. FIG. 1 illustrates the semiconductor device 100 upon completion of the pinch-off deposition process that forms the dielectric capping layer 156 with pinch-off regions 156-1 in the dielectric capping layer and gap spacers 158 formed in the spaces 151-2 between the metal lines of the metal wiring layer 152.

[0043] According to embodiments of the present invention, the structural characteristics (e.g., size, shape, volume, etc.) of the void spacer formed by the pinch-off volume can be controlled based on, for example, (i) the type of dielectric material used to form the dielectric capping layer 156, or (ii) the deposition process and associated deposition parameters (e.g., gas flow rate, RF power, pressure, deposition rate, etc.) used to perform the pinch-off deposition, or both. For example, in one embodiment of the present invention, the capping layer 158 is formed by PECVD deposition of a low-k dielectric material (e.g., k in the range of about 2.0 to about 5.0). Such low-k dielectric materials include, but are not limited to, SiCOH, porous p-SiCOH, SiCN, carbon-rich SiCNH, p-SiCNH, SiN, SiC, etc. SiCOH dielectric materials have a dielectric constant k=2.7, and porous SiCOH materials have a dielectric constant of about 2.3 to 2.4. In one exemplary embodiment of the present invention, the pinch-off deposition process is carried out by depositing a SiCN dielectric film by a plasma enhanced chemical vapor deposition process using an industrial parallel plate single wafer 300 mm CVD tool with deposition parameters of trimethylsilane (200 to 500 standard cubic centimeters per minute (sccm)) and ammonia (300 to 800 sccm) as gases, RF power of 300 to 600 Watts, pressure of 2 to 6 Torr, and deposition rate of 0.5 to 5 nm / sec.

[0044] Additionally, the conformality level of PECVD-deposited dielectric materials can be controlled to achieve "pinch-off" of the dielectric capping layer above or below the surface of adjacent metal lines. The term "conformality level" for an insulating / dielectric film deposited over a trench with an aspect ratio R (R = trench depth / trench opening) of 2 is defined herein as the ratio of the thickness of the insulating / dielectric film deposited on the sidewalls at the center of the trench to the thickness of the insulating / dielectric film at the top of the trench. For example, a 3-nm-thick insulating / dielectric film deposited over a trench structure with a 12-nm opening and a 24-nm depth (aspect ratio of 2) has a conformality level of 33%, which means that the film has a thickness of approximately 1 nm on the sidewalls at the center of the trench and a thickness of approximately 3 nm at the top of the trench (conformality level = 1 nm / 3 nm ~ 33%).

[0045] For example, if the conformality level is about 40% or less, the "pinch-off" region 156-1 shown in FIG. 1 will be formed in the dielectric capping layer 156 above the metal lines of the metal wiring layer 152. This will result in the formation of void spacers 158 that extend above the metal lines of the metal wiring layer 152. On the other hand, if the conformality level is greater than about 40%, the "pinch-off" region will be formed in the dielectric capping layer below the top surfaces of the metal lines of the metal wiring layer 152. This will result in the formation of void spacers that do not extend above the metal lines of the metal wiring layer 152.

[0046] Depending on the given application and the dimensions of the void / air spacer structure, the desired level of conformality for the PECVD-deposited dielectric material can be achieved by adjusting deposition process parameters. For example, for PECVD dielectric materials such as SiN, SiCN, SiCOH, porous p-SiCOH, and other ULK dielectric materials, lower conformality levels can be achieved by increasing RF power, increasing pressure, or increasing the deposition rate (e.g., increasing the precursor flow rate), or a combination thereof. As the conformality level decreases, "pinch-off" regions form above the metal lines, minimizing the volume of dielectric material on the exposed sidewalls and bottom surfaces within the spaces 151-2. This results in the formation of large, high-volume void spacers 158 extending above the metal lines of the metal wiring layer 152, as shown in Figures 1 and 5.

[0047] It should be noted that experimental BEOL test structures, such as those shown in Figures 1 and 5, have been fabricated using the "pinch-off" deposition method described herein to form nonconformal capping layers (conformalities less than 40%) comprising ULK materials (e.g., SiCOH, porous p-SiCOH) to achieve large, high-volume air gap spacers between adjacent metal lines, with the air gap spacers extending above the metal lines as shown in Figures 1 and 5. Furthermore, experimental results have shown that pinch-off deposition of such nonconformal capping layers results in very little dielectric material being deposited on the sidewalls and bottom of the air spaces between the metal lines. In particular, experimental BEOL test structures have been fabricated in which, assuming the spaces 151-2 between the metal lines have an initial volume V i before forming the capping layer (as shown in Figure 9), a volume of approximately n V i (where n ranges from about 0.70 to about 1.0) is achieved after forming the air gap spacers using the nonconformal pinch-off deposition process described herein.

[0048] The dielectric constant of air is approximately 1, which is much less than the dielectric constant of the dielectric material used to form the conformal insulating liner 155 and the dielectric capping layer 156. In this regard, the ability to tightly control and minimize the amount of dielectric material deposited in the spaces 151-2 between adjacent metal lines in the metal wiring layer 152 using the techniques described herein enables optimizing the electrical performance of BEOL structures by lowering the effective dielectric constant (and thereby the parasitic capacitance) between adjacent metal lines in the metal wiring layer 152. Furthermore, pinch-off deposition can be performed using ULK dielectric materials to form the low-k dielectric capping layer 156 and the large, high-volume air gap spacers 158, thereby lowering the effective dielectric constant (and thereby the parasitic capacitance) of the BEOL structures as a whole.

[0049] While the exemplary embodiments of the present invention described above describe the formation of air gap spacers as part of BEOL structures, similar techniques can be applied to form air gap spacers as part of FEOL / MOL structures to reduce parasitic coupling between adjacent FEOL / MOL structures. For example, the techniques described in more detail below with reference to Figures 13 through 21 can be used to form air gap spacers between MOL device contacts of FEOL / MOL structures and metal gate structures of vertical transistor devices.

[0050] 13 is a schematic cross-sectional view illustrating a semiconductor device including an air gap spacer integrally formed within the FEOL / MOL structure of the semiconductor device according to another embodiment of the present invention. In particular, FIG. 13 schematically illustrates a semiconductor device 200 including a substrate 210 / 215 including a bulk substrate layer 210 and an insulating layer 215 (e.g., a buried oxide layer of an SOI substrate), and multiple vertical transistor structures M1, M2, and M3 (see FIG. 14) formed on the substrate 210 / 215. The vertical transistor structures M1, M2, and M3 have a standard structural framework including a semiconductor fin 220 (extending in the X-direction along the substrate), epitaxially grown source (S) / drain (D) regions 225, and respective metal gate structures 230-1, 230-2, and 230-3. The semiconductor fin 220 serves as a vertical channel for vertical transistor structures M1, M2, and M3 in the regions of the semiconductor fin 220 surrounded by the metal gate structures 230-1, 230-2, and 230-3, respectively. The semiconductor fin 220 may be formed by etching / patterning an active silicon layer (e.g., an SOI layer of an SOI substrate) formed on the insulating layer 215. The semiconductor fin 220 is not shown in detail in FIG. 13, but the top surface of the semiconductor fin 220 is also shown in FIG. 13 with a dashed line (i.e., the channel portions of the semiconductor fin 220 are covered by the gate structures 230-1, 230-2, and 230-3, and the portions of the semiconductor fin 220 extending from the gate structures are encapsulated by epitaxial material grown on the exposed surfaces of the semiconductor fin 220).

[0051] In one embodiment, metal gate structures 230-1, 230-2, and 230-3 each comprise a conformal high-k metal gate stack structure formed on the vertical sidewalls and top surface of semiconductor fin 220 and a gate electrode formed on the high-k metal gate stack structure. Each conformal high-k metal gate stack structure comprises a conformal layer of gate dielectric material (e.g., a high-k dielectric material such as HfO2 or Al2O3) formed on the sidewalls and top surface of semiconductor fin 220 and a conformal layer of a metal work function metal material (e.g., Zr, W, Ta, Hf, Ti, Al, Ru, Pa, TaN, TiN, etc.) formed on the conformal layer of gate dielectric material. The gate electrode material formed on the high-k metal gate stack structure includes a low-resistivity conductive material, including, but not limited to, tungsten, aluminum, or any metal or conductive material commonly used to form gate electrode structures.

[0052] The epitaxial source (S) / drain (D) regions 225 comprise an epitaxial semiconductor material (e.g., SiGe, III-V compound semiconductor material, etc.) epitaxially grown on the exposed portions of the semiconductor fin structure 220 extending from the metal gate structures 230-1, 230-2, 230-3. A plurality of MOL device contacts 240 / 245 are formed as part of the MOL layer of the semiconductor device 200 to form vertical contacts to the source / drain regions 225. Each MOL device contact 240 / 245 comprises a liner / barrier layer 240 and a conductive via 245.

[0053] 13, the metal gate structures 230-1, 230-2, and 230-3 are electrically isolated from the MOL contacts 240 / 245 and other surrounding structures by insulating material layers 234, 250, and 260 and gap spacers 262. These insulating material layers include lower sidewall spacers 234, conformal insulating liner 250, and dielectric capping layer 260. The lower sidewall spacers 234 electrically isolate the metal gate structures 230-1, 230-2, and 230-3 from the adjacent source / drain regions 223. The conformal insulating liner 250 (having a composition and function similar to the conformal insulating liner 155 of the BEOL structure of FIG. 1) conformally coats the sidewall surfaces of the MOL device contacts 240 / 245 and the metal gate structures 230-1, 230-2, and 230-3. The conformal insulating liner 250 is an optional feature that can be formed to protect the MOL device contacts 240 / 245 and metal gate structures 230-1, 230-2, 230-3 from potential structural damage or contamination that may occur due to subsequent processing steps and environmental conditions.

[0054] According to an embodiment of the present invention, the dielectric capping layer 260 is formed by depositing a low-k dielectric material using a pinch-off deposition process to encapsulate the upper regions of the metal gate structures 230-1, 230-2, and 230-3 with the low-k dielectric material and form an air gap spacer 262 between the metal gate structure and the MOL device contact. The process flow for fabricating the air gap spacer 262 is described in further detail below. As shown in FIG. 13 , the air gap spacer 262 is relatively large and voluminous, extending vertically above the metal gate structures 230-1, 230-2, and 230-3. For reasons similar to those discussed above with respect to the BEOL air gap spacer 158 shown in FIG. 3 , the size and shape of the FEOL / MOL air gap spacer 262 shown in FIG. 13 provides improved TDDB reliability and reduced capacitive coupling between the MOL device contact and the metal gate structure.

[0055] For example, the large, high-volume air gap spacers 262 reduce the effective dielectric constant of the space between the metal gate structures 230-1, 230-2, 230-3 and the MOL device contacts 240 / 245. Furthermore, because the air gap spacers 262 extend above the metal gate structures 230-1, 230-2, 230-3 as shown in FIG. 13, there is a relatively long diffusion / conduction path P between the critical interfaces of the metal gate structures 230-1, 230-2, 230-3 (the critical interfaces being the interfaces between the dielectric capping layer 260 and the top surfaces of the metal gate structures 230-1, 230-2, 230-3) and the adjacent MOL device contacts 240 / 245. Therefore, the air gap spacers 262 of FIG. 13 serve to enhance the TDDB reliability of the FEOL / MOL semiconductor structure.

[0056] 13 further illustrates a first interconnect level of the BEOL structure formed above the FEOL / MOL layer, the first interconnect level comprising an ILD layer 270 and a plurality of metal lines 272 / 274 formed within the ILD layer 270 in electrical contact with respective MOL device contacts 240 / 245. The metal lines 272 / 274 are formed using known techniques by etching openings (e.g., trenches or vias) in the ILD layer 270, lining the openings with a barrier liner layer 272, and filling the openings with a metal material 274, such as copper.

[0057] The process flow for fabricating the semiconductor device 200 of FIG. 13 will now be described in more detail with reference to FIGS. 14 through 21, which schematically illustrate the semiconductor device 200 at various stages of fabrication. First, FIG. 14 is a schematic cross-sectional view illustrating the semiconductor device 200 at an intermediate fabrication stage, in which vertical transistor structures M1, M2, and M3 are formed on a semiconductor substrate 210 / 215. In one embodiment, the substrate 210 / 215 comprises an SOI (silicon-on-insulator) substrate, with the base substrate 210 being composed of silicon or other types of semiconductor substrate materials commonly used in bulk semiconductor fabrication processes, such as germanium, silicon-germanium alloy, silicon carbide, silicon-germanium carbide alloy, or compound semiconductor materials (e.g., III-V and II-VI). Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide. An insulating layer 215 (e.g., an oxide layer) is deposited between the base semiconductor substrate 210 and an active semiconductor layer (e.g., an active silicon layer), and the active semiconductor layer is patterned using known methods to create the semiconductor fin structure 220. Additionally, epitaxial source / drain regions 225 can be epitaxially grown on exposed portions of the semiconductor fin structure 220 using known methods.

[0058] 14, the metal gate structures 230-1, 230-2, 230-3 are encapsulated in an insulating / dielectric material structure including an insulating capping layer 232 and sidewall spacers 234. The capping layer 232 and sidewall spacers 234 are fabricated using known techniques and insulating materials (e.g., SiN). The metal gate structures 230-1, 230-2, 230-3 may be formed, for example, by a replacement metal gate (RMG) process in which a dummy gate structure is first formed and then replaced with the metal gate structures 230-1, 230-2, 230-3 after forming the epitaxial source / drain regions 225 and before forming the MOL device contacts. The embodiment of FIG. 14 assumes that the RMG process has already been completed to form metal gate structures 230-1, 230-2, 230-3, and that a PMD (pre-metal dielectric) layer 236 has already been deposited and planarized to result in the structure shown in FIG. 14.

[0059] PMD layer 236 is formed by depositing a layer of dielectric material on the surface of the semiconductor device and then planarizing the dielectric material to the top surface of capping layer 232. PMD layer 236 can be composed of any suitable insulating / dielectric material, such as, for example, silicon oxide, silicon nitride, hydrogenated silicon carbonate, silicon-based low-k dielectrics, porous dielectrics, or organic dielectrics, such as porous organic dielectrics. PMD layer 236 can be formed using known deposition techniques, such as, for example, ALD, CVD, PECVD, spin-on deposition, or PVD, followed by a standard planarization process (e.g., CMP).

[0060] The next process module involves forming MOL device contacts using the process flows generally depicted in Figures 15, 16, and 17. In particular, Figure 15 is a schematic cross-sectional view of the semiconductor device of Figure 14 after patterning the PMD layer 236 to form contact openings 236-1 between the gate structures 230-1, 230-2, and 230-3 of the vertical transistor structures M1, M2, and M3 down to the source / drain regions 225. The contact openings 236-1 can be formed using known etching techniques and chemistries for etching the material of the PMD layer 236 that is selective to the insulating material of the capping layer 232 and sidewall spacers 234.

[0061] Next, FIG. 16 is a schematic cross-sectional view of the semiconductor device of FIG. 15 after depositing a conformal liner layer 240A on the surface of the semiconductor device. The conformal liner layer 240A may include a material such as TaN, which acts as a diffusion barrier and / or adhesion layer for the metallic material used to fill the opening 236-1 and form the MOL device contact. Next, FIG. 17 is a schematic cross-sectional view of the semiconductor device of FIG. 16 after depositing a metallic material layer to fill the contact opening 236-1 between the metal gate structures 230-1, 230-2, and 230-3 with a conductive material 245, and forming the MOL device contacts 240 / 245 by planarizing the surface of the semiconductor device down to the gate capping layer 232 and removing excess liner and conductive material. The conductive material 245 may include copper, tungsten, cobalt, aluminum, or other conductive materials suitable for use in forming vertical MOL device contacts with the source / drain regions and gate electrode.

[0062] 17, the MOL gate contacts may be formed in openings formed in the PMD layer 236 and capping layer 232 down to the top surfaces of the metal gate structures 230-1, 230-2, 230-3. As will be appreciated by those skilled in the art, the metal gate structures 230-1, 230-2, 230-3 extend in the YY direction (into and out of the page based on the Cartesian coordinate system shown in FIG. 13), and thus the MOL gate contacts may be formed in the PMD layer 236 in alignment with the extended ends of the metal gate structures 230-1, 230-2, 230-3.

[0063] After forming the MOL device contacts, the next process module involves forming gap spacers between the metal gate structures and the MOL device contacts using the process flow generally depicted in FIGS. 18 through 21. The first step in this process involves etching the gate capping layer 232 and the sidewall spacers 234. In particular, FIG. 18 illustrates a cross-sectional view of the semiconductor device of FIG. 17 after etching away the gate capping layer 232 and recessing the sidewall spacers 234 to the top surface of the semiconductor fin structure 220, thereby forming a narrow space S between the sidewalls of the metal gate structures 230-1, 230-2, and 230-3 and the adjacent MOL device contacts 240 / 245. While the exemplary embodiment of FIG. 18 illustrates the gate capping layer 232 as being completely etched away, in alternative embodiments, the etching process can be performed such that a thin layer of the etched gate capping layer 232 remains on the top surfaces of the metal gate structures 230-1, 230-2, and 230-3.

[0064] 19 is a schematic cross-sectional view illustrating the semiconductor device of FIG. 18 after depositing a conformal layer 250A of insulating material to form an insulating liner on the exposed surfaces of metal gate structures 230-1, 230-2, 230-3 and MOL device contacts 240 / 245. Conformal insulating liner layer 250A is an optional protective feature that may be formed prior to the pinch-off deposition process to provide additional protection to the exposed surfaces of metal gate structures 230-1, 230-2, 230-3 and MOL device contacts 240 / 245 for the same or similar reasons as described above.

[0065] Furthermore, conformal insulating liner layer 250A can be composed of one or more robust, ultra-thin dielectric material layers that have desirable electrical and mechanical characteristics, such as low leakage, high dielectric breakdown, and hydrophobicity, resulting in reduced damage during subsequent semiconductor processing steps. For example, conformal insulating liner layer 250A can be composed of a dielectric material such as SiN, SiCN, SiNO, SiCNO, SiC, or other dielectric materials having the desired electrical / mechanical properties described above. In one embodiment, when spacing S ( FIG. 18 ) is in the range of about 4 nm to about 15 nm, conformal insulating liner layer 250A is formed to a thickness in the range of about 1.0 nm to about 2 nm, thereby reducing spacing S by about 2 nm to about 4 nm due to liner layer 250A on the sidewalls of adjacent structures.

[0066] Similar to the BEOL embodiment described above, conformal insulating liner layer 250A can also be composed of multiple conformal layers of the same or different dielectric materials deposited using a cyclic deposition process. For example, in one embodiment, conformal insulating liner layer 250A can be composed of multiple thin conformal layers of SiN deposited sequentially to form a SiN liner layer having a desired overall thickness (e.g., cyclically depositing 0.1 nm to 0.2 nm thick SiN layers using a plasma-enhanced CVD or CVD process with silane and NH).

[0067] The next step in this fabrication process involves depositing a dielectric material over the semiconductor structure of FIG. 19 using a pinch-off deposition process to form gap spacers between the metal gate structures and the MOL device contacts. For example, FIG. 20 is a schematic cross-sectional view illustrating the semiconductor device of FIG. 19 after depositing a layer 260A of dielectric material using a non-conformal deposition process to create pinch-off regions that form gap spacers 262 in the narrow spaces between metal gate structures 230-1, 230-2, and 230-3 and adjacent MOL device contacts 240 / 245. As described above, according to embodiments of the present invention, the structural characteristics (e.g., size, shape, volume, etc.) of the gap spacers 262 formed by pinch-off deposition can be controlled based on, for example, (i) the type of dielectric material used to form the dielectric layer 260A, or (ii) the deposition process and associated deposition parameters (e.g., gas flow rate, RF power, pressure, deposition rate, etc.) used to perform the pinch-off deposition, or both.

[0068] For example, in one embodiment of the present invention, dielectric material layer 260A is formed by PECVD deposition of a low-k dielectric material (e.g., k ranging from about 2.0 to about 5.0). Such low-k dielectric materials include, but are not limited to, SiCOH, porous p-SiCOH, SiCN, SiNO, carbon-rich SiCNH, p-SiCNH, SiN, SiC, etc. SiCOH dielectric material has a dielectric constant k=2.7, and porous SiCOH material has a dielectric constant of about 2.3 to 2.4. In one exemplary embodiment of the present invention, the pinch-off deposition process is carried out by depositing a SiN dielectric film by a plasma enhanced chemical vapor deposition process using an industrial parallel plate single wafer 300 mm CVD tool with deposition parameters of silane (100 to 500 sccm) and ammonia (200 to 1000 sccm) as gases, RF power of 200 to 600 Watts, pressure of 1 to 8 Torr, and deposition rate of 0.5 to 8 nm / sec.

[0069] FIG. 21 is a schematic cross-sectional view of the semiconductor device of FIG. 20 after planarizing the surface of the semiconductor device down to the MOL device contacts and depositing an ILD layer 270 as part of the first interconnect level of the BEOL structure. The semiconductor structure of FIG. 20 can be planarized using a standard CMP process, which removes excess dielectric material 260A and a portion of the insulating liner layer 250A deposited over the MOL device contacts, resulting in the structure shown in FIG. 21. As shown in FIG. 21, the remaining pinch-off deposited dielectric material 260A forms a separate dielectric capping structure 260 over the metal gate structures 230-1, 230-2, and 230-3 and the separate insulating liner 250. Although not shown in detail in FIGS. 13 and 21, an additional capping layer can be formed on the planarized FEOL / MOL surface prior to forming the ILD layer 270 to insulate the conductive material 245 of the MOL device contacts from the dielectric material of the ILD layer 270.

[0070] Experimental test structures have been fabricated based on the semiconductor structure shown schematically in Figure 13. In these experimental test structures, the conformal insulating liner 250 is composed of periodic SiN films with thicknesses of 1 nm, 1.5 nm, 2 nm, and 3 nm. The pinch-off deposition was performed using PECVD SiCN and PECVD ULK films with k = 2.7 and 2.4, respectively. Experimental results demonstrate that it is possible to obtain large, high-volume air gap spacers (air gap spacer 262 shown schematically in Figure 13) that extend above the metal gate structure. Furthermore, experimental results demonstrate that the size, shape, and volume of the air gap spacers can be optimized for various applications by varying the deposition process parameters or materials used for the pinch-off deposition.

[0071] It should be understood that the methods for fabricating air gap spacers in FEOL / MOL or BEOL layers described herein can be incorporated into various semiconductor process flows to fabricate semiconductor devices and integrated circuits with various analog and digital or mixed-signal circuits. In particular, integrated circuit dies can be fabricated to include various devices, such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, inductors, and the like. Integrated circuits according to the present invention can be utilized in applications, hardware, or electronic systems, or combinations thereof. Hardware and systems suitable for implementing the present invention may include, but are not limited to, personal computers, communications networks, electronic commerce systems, portable communications devices (e.g., mobile phones), solid-state media storage devices, functional circuits, and the like. Systems and hardware incorporating such integrated circuits are considered to be included in the embodiments described herein. Given the teachings of the present invention provided herein, those skilled in the art will be able to contemplate other implementations and applications of the present technology.

[0072] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the present invention is not strictly limited to these embodiments, and that various changes and modifications may be made by those skilled in the art without departing from the scope of the appended claims.

Claims

1. It is a semiconductor device, Gate structures and source / drain contacts arranged adjacent to each other on the substrate, A gap is provided between the gate structure and the source / drain contact, The gate structure and the dielectric material arranged to cover the gap, A conformal insulating liner layer comprising (i) a first portion located below the gap, (ii) a second portion located between the gate structure and the gap, and (iii) a third portion located between the source / drain contact and the gap, The upper portion of the gap is positioned above the upper surface of the gate structure and below the upper surface of the source / drain contacts. A semiconductor device in which the lower portion of the aforementioned gap is positioned below the bottom surface of the source / drain contact.

2. The aforementioned semiconductor device further comprises epitaxial source / drain regions, The source / drain contact and the epitaxial source / drain region are in contact. The semiconductor device according to claim 1, wherein the void extends above and below the upper surface of the epitaxial source / drain region.

3. The semiconductor device according to claim 2, wherein a portion of the void exists between the epitaxial source / drain region and the gate structure.

4. The semiconductor device according to claim 1, wherein the conformal insulating liner layer comprises Si and N.

5. The semiconductor device according to claim 4, wherein the conformal insulating liner layer has a thickness of approximately 1 to 3 nm.

6. The semiconductor device according to claim 4, wherein the conformal insulating liner layer is approximately 1 nm thick.

7. The semiconductor device according to claim 4, wherein the conformal insulating liner layer is approximately 1.5 nm thick.

8. The semiconductor device according to claim 1, wherein the conformal insulating liner layer comprises a plurality of layers containing Si and N, each having a thickness of about 0.1 to 0.2 nm.

9. The semiconductor device according to claim 8, wherein the conformal insulating liner layer is approximately 1 to 3 nm thick.

10. The semiconductor device according to claim 8, wherein the conformal insulating liner layer is approximately 1 nm thick.

11. The semiconductor device according to claim 8, wherein the conformal insulating liner layer is approximately 1.5 nm thick.

12. The semiconductor device according to claim 1, wherein the conformal insulating liner layer is approximately 1 to 3 nm thick.

13. The semiconductor device according to claim 1, wherein the conformal insulating liner layer is approximately 1 nm thick.

14. The semiconductor device according to claim 1, wherein the conformal insulating liner layer is approximately 1.5 nm thick.

15. The semiconductor device according to claim 1, wherein the conformal insulating liner layer includes a plurality of conformal dielectric layers.

16. The semiconductor device according to claim 15, wherein the conformal insulating liner layer has a thickness of approximately 0.5 nm to 5 nm.

17. The semiconductor device according to claim 1, wherein the source / drain contact includes a conformal liner layer containing Ta adjacent to the conformal insulating liner layer.

18. The semiconductor device according to claim 1, wherein the upper surface of the dielectric material and the upper surface of the source / drain contacts are substantially coplanar.

19. The semiconductor device according to claim 1, wherein a portion of the dielectric material is disposed between the gate structure and the source / drain contact.

20. The semiconductor device according to claim 1, wherein a semiconductor fin including an epitaxial source / drain region is formed on the substrate, and the source / drain contact is formed on the epitaxial source / drain region.

21. It is a semiconductor device, Metal gate structures and source / drain contacts arranged adjacent to each other on a substrate, A gap is disposed between the metal gate structure and the source / drain contact, A fin portion is disposed between the metal gate structure and the source / drain contact, A dielectric material is arranged to cover the metal gate structure and is pinched off to form the void, Conformal insulating liner layer, The conformal insulating liner layer comprises, A first portion located below the gap on the upper surface of the fin portion, A second portion disposed between the metal gate structure and the gap, A third portion disposed between the source / drain contact and the gap, The upper portion of the gap is positioned above the upper surface of the metal gate structure and below the upper surface of the source / drain contacts. A semiconductor device in which the lower portion of the aforementioned gap is positioned below the bottom surface of the source / drain contact.

22. The aforementioned semiconductor device further comprises epitaxial source / drain regions, The source / drain contact and the epitaxial source / drain region are in contact. The semiconductor device according to claim 21, wherein the void extends above and below the upper surface of the epitaxial source / drain region.

23. The semiconductor device according to claim 22, wherein a portion of the void exists between the epitaxial source / drain region and the metal gate structure.

24. The semiconductor device according to claim 21, wherein the conformal insulating liner layer comprises Si and N.

25. The semiconductor device according to claim 24, wherein the conformal insulating liner layer has a thickness of approximately 1 to 3 nm.

26. The semiconductor device according to claim 24, wherein the conformal insulating liner layer is approximately 1 nm thick.

27. The semiconductor device according to claim 24, wherein the conformal insulating liner layer is approximately 1.5 nm thick.

28. The semiconductor device according to claim 24, wherein a portion of the dielectric material is disposed between the metal gate structure and the source / drain contact.

29. The semiconductor device according to claim 21, wherein the conformal insulating liner layer comprises a plurality of layers containing Si and N, each having a thickness of about 0.1 to 0.2 nm.

30. The semiconductor device according to claim 29, wherein the conformal insulating liner layer is approximately 1 to 3 nm thick.

31. The semiconductor device according to claim 29, wherein the conformal insulating liner layer is approximately 1 nm thick.

32. The semiconductor device according to claim 29, wherein the conformal insulating liner layer is approximately 1.5 nm thick.

33. The semiconductor device according to claim 21, wherein the conformal insulating liner layer is approximately 1 to 3 nm thick.

34. The semiconductor device according to claim 21, wherein the conformal insulating liner layer is approximately 1 nm thick.

35. The semiconductor device according to claim 21, wherein the conformal insulating liner layer is approximately 1.5 nm thick.

36. The semiconductor device according to claim 21, wherein the conformal insulating liner layer includes a plurality of conformal dielectric layers.

37. The semiconductor device according to claim 36, wherein the conformal insulating liner layer has a thickness of approximately 0.5 nm to 5 nm.

38. The semiconductor device according to claim 21, wherein the source / drain contact includes a conformal liner layer containing Ta adjacent to the conformal insulating liner layer.

39. The semiconductor device according to claim 21, wherein the upper surface of the dielectric material and the upper surface of the source / drain contact are substantially coplanar.

40. The semiconductor device according to claim 21, wherein a portion of the dielectric material is disposed between the metal gate structure and the source / drain contact.

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