Data communication device and image formation apparatus

Abstract

To provide a mechanism that can achieve both the reliability and productivity of operations of a device.SOLUTION: A data communication device includes a master device and at least one slave device. The master device transmits first data to the slave device, determines whether a transmission error has occurred in the transmission of the first data, retransmits the first data to the slave device when it is determined that the transmission error has occurred in the transmission of the first data, transmits second data in a type different from the first data to the slave device, and does not determine whether a transmission error has occurred in the transmission of the second data.SELECTED DRAWING: Figure 15

Description

[Technical field]

[0001] The present invention relates to a data communication device and an image forming device. [Background technology]

[0002] In an electrophotographic image forming apparatus, an electrostatic latent image is formed on a photoconductor by exposing the photoconductor to light as it is rotated, and the electrostatic latent image is developed with toner to form an image. In particular, a solid-state exposure type exposure device that uses light from an array of light-emitting elements is attracting attention because it is easier to reduce the size, noise level, and cost compared to a laser scanning type exposure device.

[0003] Patent Document 1 discloses a technology for providing a light emitting element array, a driving circuit, and a register for storing control parameter values ​​on the substrate of one light emitting chip in order to promote miniaturization of a solid-state exposure type exposure apparatus using organic EL (Electro-Luminescence) elements. In the technology disclosed in Patent Document 1, image data output to the light emitting element array and parameter values ​​written to the register are output from a controller to the light emitting chip via a common signal line, thereby reducing the number of signal lines.

[0004] Patent Document 2 discloses a technique for suppressing the effects of problems caused by errors in serial communication performed inside an image forming device. In the technique disclosed in Patent Document 2, a master that transmits data to a slave compares the data returned from the slave with an expected value, and if it determines that a transmission error has occurred, it stops the operation of the slave. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2021-35765 [Patent Document 2] JP 2010-122736 A Summary of the Invention [Problem to be solved by the invention]

[0006] When transmitting and receiving data between circuits, a transmission error may occur due to the influence of noise from the external environment. A transmission error may cause misinterpretation of data, resulting in abnormalities such as malfunction of the device or deterioration of output quality. If the technology of Patent Document 2 is adopted to perform error judgment every time data is communicated, such abnormalities can be prevented, but the time required for communication increases, making it difficult to meet the demand for productivity.

[0007] An object of the present invention is to provide a mechanism that can achieve both reliability of the operation of the device and productivity. [Means for solving the problem]

[0008] According to a first aspect, there is provided a data communication apparatus including a master device and at least one slave device, in which the master device transmits first data to the slave device, determines whether a transmission error has occurred in the transmission of the first data, and if it is determined that a transmission error has occurred in the transmission of the first data, resends the first data to the slave device, transmits second data of a type different from the first data to the slave device, and does not determine whether a transmission error has occurred in the transmission of the second data.

[0009] According to a second aspect, there is provided an image forming apparatus for forming an image on a sheet, comprising a photosensitive member and an exposure head for exposing the photosensitive member, the exposure head including the data communication device of the first aspect. Effect of the Invention

[0010] According to the present invention, it is possible to achieve both reliability of the operation of the device and productivity. [Brief description of the drawings]

[0011] [Figure 1] 1 is a diagram showing a schematic configuration of an image forming apparatus according to an embodiment; [Diagram 2] FIG. 2 is an explanatory diagram of a configuration of a photoconductor and an exposure head according to the embodiment. [Diagram 3] FIG. 4 is an explanatory diagram of the configuration of a printed circuit board of an exposure head according to an embodiment. [Figure 4] 1A and 1B are explanatory diagrams of a light-emitting chip and a light-emitting element array in the light-emitting chip according to an embodiment. [Diagram 5] FIG. 1 is a plan view showing a schematic configuration of a light-emitting chip according to an embodiment. [Figure 6] FIG. 1 is a cross-sectional view showing a schematic configuration of a light-emitting chip according to an embodiment. [Figure 7] FIG. 4 is a circuit diagram showing a control configuration of an exposure apparatus according to an embodiment. [Figure 8] FIG. 2 is a functional block diagram showing a detailed configuration of a light-emitting chip according to an embodiment. [Figure 9] FIG. 4 is a circuit diagram showing a partial configuration of a current driver corresponding to one light emitting element. [Figure 10] 5 is a timing chart of image data transmission from a master to a slave. [Figure 11A] 4 is a timing chart of transmission of control data from a master to a slave. [Figure 11B] 4 is a timing diagram of the reception of control data by a master from a slave. [Figure 12] 11 is a timing chart of transmission of invalidation data from a master to a slave. [Figure 13] FIG. 4 is a state transition diagram showing constraints on transitions of the operation states of the slave interface circuit. [Figure 14] 13 is a timing diagram of data communication in a scenario in which misinterpretation of identification information occurs during transmission of image data. [Figure 15] 5 is a flowchart showing an example of the flow of a data communication process according to the first embodiment. [Figure 16A] 11 is a timing chart of transmission of dummy data for turning off lights from a master to a slave. [Figure 16B] 11 is a timing chart showing the return of dummy data from a slave to a master. [Figure 17] 10 is a flowchart showing an example of the flow of a data communication process according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0013] <1. Schematic configuration of image forming apparatus> 1 shows an example of a schematic configuration of an image forming apparatus 1 according to an embodiment. The image forming apparatus 1 includes a reading unit 100, an image creating unit 103, a fixing unit 104, and a conveying unit 105. The reading unit 100 optically reads an original placed on a platen and generates read image data. The image creating unit 103 forms an image on a sheet based on the read image data generated by the reading unit 100, or based on print image data received from an external device via a network, for example.

[0014] The image forming unit 103 includes image forming units 101a, 101b, 101c, and 101d. The image forming units 101a, 101b, 101c, and 101d form black, yellow, magenta, and cyan toner images, respectively. The image forming units 101a, 101b, 101c, and 101d have the same configuration, and are collectively referred to as the image forming unit 101 below. The photoconductor 102 of the image forming unit 101 is rotated clockwise in the figure during image formation. The charger 107 charges the photoconductor 102. The exposure head 106 exposes the photoconductor 102 to light to form an electrostatic latent image on the surface of the photoconductor 102. The developer 108 develops the electrostatic latent image on the photoconductor 102 with toner to form a toner image. The toner image formed on the surface of the photoconductor 102 is transferred to a sheet transported on a transfer belt 111. By transferring the toner images of the four photoconductors 102 onto a sheet in an overlapping manner, a color image containing four color components, namely black, yellow, magenta, and cyan, can be formed.

[0015] The conveying unit 105 controls the feeding and conveying of the sheet. Specifically, the conveying unit 105 feeds the sheet from a designated unit among the internal storage units 109a and 109b, the external storage unit 109c, and the manual feed unit 109d to the conveying path of the image forming apparatus 1. The fed sheet is conveyed to the registration roller 110. The registration roller 110 conveys the sheet onto the transfer belt 111 at an appropriate timing so that the toner image of each photoconductor 102 is transferred onto the sheet. As described above, the toner image is transferred onto the sheet while the sheet is being conveyed on the transfer belt 111. The fixing unit 104 fixes the toner image onto the sheet by heating and pressing the sheet onto which the toner image has been transferred. After the toner image is fixed, the sheet is discharged to the outside of the image forming apparatus 1 by the discharge roller 112. An optical sensor 113 is disposed at a position opposite the transfer belt 111. Optical sensor 113 optically reads the test chart formed on transfer belt 111 by image forming unit 101. When an error in the image formation range is detected for the test chart read by optical sensor 113, image controller 700 (described later) performs control to compensate for the error when a subsequent job is executed.

[0016] Although an example in which a toner image is directly transferred from each photoconductor 102 to a sheet on the transfer belt 111 has been described here, the toner image may be indirectly transferred from each photoconductor 102 to a sheet via an intermediate transfer body. Also, although an example in which a color image is formed using toners of multiple colors has been described here, the technology according to the present disclosure is also applicable to an image forming apparatus that forms a monochrome image using toners of a single color.

[0017] <2. Basic structure of the exposure head> 2(A) and 2(B) show the photoconductor 102 and the exposure head 106. The exposure head 106 has a light emitting element array 201, a printed circuit board 202 on which the light emitting element array 201 is mounted, a rod lens array 203, and a housing 204 that supports the printed circuit board 202 and the rod lens array 203. The photoconductor 102 has a cylindrical shape. The exposure head 106 is disposed such that its longitudinal direction is parallel to the axial direction D1 of the photoconductor 102, and the surface on which the rod lens array 203 is attached faces the surface of the photoconductor 102. While the photoconductor 102 rotates in the circumferential direction D2, the light emitting element array 201 of the exposure head 106 emits light, and the rod lens array 203 focuses the light on the surface of the photoconductor 102.

[0018] Fig. 3(A) and Fig. 3(B) show an example of the configuration of the printed circuit board 202. Fig. 3(A) shows the surface on which the connector 305 is mounted, and Fig. 3(B) shows the surface on which the light-emitting element array 201 is mounted (the surface opposite to the surface on which the connector 305 is mounted). Fig. 4 shows a schematic diagram of the light-emitting chip 400 and the array of the light-emitting elements 602 in the light-emitting chip 400.

[0019] In this embodiment, the light emitting element array 201 has a plurality of light emitting elements arranged two-dimensionally. The light emitting element array 201 includes, as a whole, N columns of light emitting elements in the axial direction D1 of the photoconductor and M rows of light emitting elements in the circumferential direction D2, where M and N are integers. In the example of FIG. 3(B), the light emitting element array 201 is divided into 20 light emitting chips 400-1 to 400-20, each including a subset of the entire plurality of light emitting elements, and the light emitting chips 400-1 to 400-20 are arranged in a staggered pattern along the axial direction D1. The light emitting chips 400-1 to 400-20 are also collectively referred to as light emitting chips 400. As shown in FIG. 3(B), the range occupied by all the light emitting elements of the 20 light emitting chips in the axial direction D1 is equal to or larger than the maximum width W of the input image data. 0is wider than the range occupied by the light emitting chip 400. Therefore, some light emitting elements located at both ends in the axial direction D1 may not be used to expose the photoconductor 102 unless an error in the image formation range is detected. Each light emitting chip 400 on the printed circuit board 202 is connected to the image controller 700 (FIG. 7) via a connector 305. For convenience of explanation, the side with the smaller branch number of the light emitting chips 400-1 to 400-20 aligned along the axial direction D1 may be referred to as the "left" and the side with the larger branch number as the "right". For example, the light emitting chip 400-1 is the leftmost light emitting chip 400, and the light emitting chip 400-20 is the rightmost light emitting chip.

[0020] The number J (J=N / 20) of the light-emitting elements 602 arranged in each row of one light-emitting chip 400 may be equal to, for example, 748 (J=748, N=14960). Meanwhile, the number M of the light-emitting elements 602 arranged in each column of one light-emitting chip 400 may be equal to, for example, 4 (M=4). That is, in the exemplary embodiment, each light-emitting chip 400 has a total of 2992 (=748×4) light-emitting elements 602, with 748 in the axial direction D1 and 4 in the circumferential direction D2. The interval P between the center points of the light-emitting elements 602 adjacent to each other in the circumferential direction D2 is C may be, for example, about 21.16 μm corresponding to a resolution of 1200 dpi. The interval between the center points of adjacent light-emitting elements 602 in the axial direction D1 may also be about 21.16 μm, in which case 748 light-emitting elements 602 occupy a length of about 15.8 mm in the axial direction D1, which corresponds to the width in the axial direction D1 of the light-emitting element array of one light-emitting chip 400. The width in the axial direction D1 of the light-emitting element array of the 20 light-emitting chips 400-1 to 400-20 is about 316 mm.

[0021] In one embodiment, M>1, and in each light-emitting chip 400, the light-emitting elements 602 may be completely arranged in a lattice as shown in FIG. 4. In another embodiment, M=1, and in each light-emitting chip 400, the light-emitting elements 602 form a simple one-dimensional array. In yet another embodiment, M>1, and in each light-emitting chip 400, the M light-emitting elements 602 in each column may be arranged in a stepped manner (i.e., shifted from each other by 1 / M of the pixel pitch in the axial direction) or in a partially stepped manner. When the number of rows M of the light-emitting element array is greater than 1, pixel areas (also called spots) corresponding to each pixel of each line on the surface of the photoconductor 102 are exposed multiple times by the M light-emitting elements 602. This makes it possible to increase the amount of light for exposure and form a high-density image.

[0022] 5 is a plan view showing a schematic configuration of the light emitting chip 400. The light emitting elements 602 of each light emitting chip 400 are formed on a light emitting substrate 402, which is, for example, a silicon substrate. A circuit section 406 for driving the light emitting elements 602 is provided on the light emitting substrate 402. Signal lines for communicating with the image controller 700, power lines for connecting to a power source, and ground lines for connecting to a ground are connected to the pads 408-1 to 408-8. The signal lines, power lines, and ground lines may be wires made of, for example, gold.

[0023] FIG. 6 shows a part of the cross section taken along line AA in FIG. 5. A plurality of lower electrodes 504 are formed on the light emitting substrate 402. A gap of length d is provided between two adjacent lower electrodes 504. A light emitting layer 506 is provided on the lower electrode 504, and an upper electrode 508 is provided on the light emitting layer 506. The upper electrode 508 is a common electrode for the plurality of lower electrodes 504. When a voltage is applied between the lower electrode 504 and the upper electrode 508, a current flows from the lower electrode 504 to the upper electrode 508, causing the light emitting layer 506 to emit light. Therefore, one lower electrode 504 and a partial region of the light emitting layer 506 and the upper electrode 508 corresponding to the lower electrode 504 constitute one light emitting element 602. That is, in this embodiment, the light emitting substrate 402 includes a plurality of light emitting elements 602.

[0024] For example, an organic EL film can be used for the light-emitting layer 506. The upper electrode 508 is composed of a transparent electrode such as indium tin oxide (ITO) so as to transmit the emission wavelength of the light-emitting layer 506. Note that in this embodiment, the entire upper electrode 508 transmits the emission wavelength of the light-emitting layer 506, but it is not necessary for the entire upper electrode 508 to transmit the emission wavelength. Specifically, it is sufficient that a partial region through which light from each light-emitting element 602 passes transmits the emission wavelength.

[0025] In FIG. 6, one continuous light-emitting layer 506 is formed, but a plurality of light-emitting layers 506 each having a width equivalent to the width W of the lower electrode 504 may be formed on the lower electrode 504. In FIG. 6, the upper electrode 508 is formed as one common electrode for the plurality of lower electrodes 504, but a plurality of upper electrodes 508 each having a width equivalent to the width W of the lower electrode 504 may be formed corresponding to each of the lower electrodes 504. In addition, the first plurality of lower electrodes 504 of the lower electrodes 504 of each light-emitting chip 400 may be covered by the first light-emitting layer 506, and the second plurality of lower electrodes 504 may be covered by the second light-emitting layer 506. Similarly, the first upper electrode 508 may be commonly formed corresponding to the first plurality of lower electrodes 504 of the lower electrodes 504 of each light-emitting chip 400, and the second upper electrode 508 may be commonly formed corresponding to the second plurality of lower electrodes 504. In such a configuration, one lower electrode 504 and the region of the light emitting layer 506 and upper electrode 508 corresponding to the lower electrode 504 constitute one light emitting element 602 .

[0026] <3. Configuration of the circuit for controlling light emission> This section describes some examples of the configuration of the circuit for controlling light emission in the exposure head 106. For simplicity of explanation, only the configuration for a single color component will be described here, but similar configurations may exist for multiple color components, and some of the configurations described may be common to multiple color components.

[0027] FIG. 7 is a circuit diagram related to a control configuration for controlling the light-emitting chip 400. The image controller 700 is a control circuit that communicates with the printed circuit board 202 via a plurality of signal lines (wires). The image controller 700 has a CPU 701, a clock generating unit 702, an image data processing unit 703, a communication data processing unit 704, and a light-emitting control unit 705. The light-emitting control unit 705 terminates the signal line between the image controller 700 and the printed circuit board 202. The n-th light-emitting chip 400-n (n is an integer from 1 to 20) on the printed circuit board 202 is connected to the light-emitting control unit 705 via signal lines DATAn, READn, CLK, and SYNC. The signal line DATAn is a signal line commonly used to transmit a plurality of types of data from the image controller 700 to the light-emitting chip 400-n. The signal line READn is a signal line for the image controller 700 to read data from the light-emitting chip 400-n. The signal line CLK is a clock signal line that carries a clock signal generated by the light emission control unit 705 based on a reference clock signal from the clock generation unit 702. The signal line SYNC is a synchronization signal line that carries a line synchronization signal that indicates the periodic exposure timing of each line on the photoconductor 102.

[0028] The CPU 701 controls the entire image forming apparatus 1. The image data processing unit 703 performs image processing on image data received from the reading unit 100 or an external device, and generates binary bitmap image data for controlling the on / off of light emission of the light emitting element 602 of the light emitting chip 400 on the printed circuit board 202. The image processing here may include, for example, raster conversion, gradation correction, color conversion, and halftone processing. The image data processing unit 703 outputs the generated image data to the light emission control unit 705 as input image data.

[0029] The communication data processing unit 704 acquires control data to be written to a register in each light-emitting chip 400 (described later) from the CPU 701, and outputs the control data to the light-emitting control unit 705. In addition, the communication data processing unit 704 receives control data read from a register in each light-emitting chip 400 via the light-emitting control unit 705. The control data received by the communication data processing unit 704 is output to the CPU 701.

[0030] The light emission control unit 705 controls light emission from each light emitting chip 400 of the exposure head 106 based on the input image data input from the image data processing unit 703. In particular, in this embodiment, the light emission control unit 705 functions as a master device that controls communication between the image controller 700 and each light emitting chip 400. Meanwhile, each light emitting chip 400 is a slave device that is mounted on the printed circuit board 202 as an integrated circuit chip connected to the light emission control unit 705 via the above-mentioned signal line. The slave device transmits and receives data to and from the master device under the control of the master device. It can be said that such a master device and at least one slave device constitute a data communication device.

[0031] FIG. 8 illustrates an example of a detailed configuration of one light-emitting chip 400 (n-th light-emitting chip 400-n) as a slave device. Referring to FIG. 8, the light-emitting chip 400 includes a circuit unit 406, a light-emitting element array 1005, and eight pads 408-1 to 408-8 also illustrated in FIG. 5. The circuit unit 406 has an interface (I / F) circuit 1001, a register 1002, a data holding unit 1003, and a current driving unit 1004. The I / F circuit 1001, the register 1002, and the data holding unit 1003 are digital circuits, and the current driving unit 1004 is an analog circuit. The light-emitting element array 1005 is a one-dimensional or two-dimensional array of light-emitting elements 602 used for forming an image. The pads 408-1 and 408-2 are connected to a power supply voltage VCC by a power supply line. Each circuit of the circuit unit 406 of the light-emitting chip 400 is supplied with power from this power supply voltage VCC. The pads 408-3 and 408-4 are connected to the ground by a ground line. Each circuit of the circuit section 406 and the upper electrode 508 are connected to the ground via the pads 408-3 and 408-4. The signal lines CLK, SYNC, DATAn, and READn are connected to the I / F circuit 1001 via the pads 408-5, 408-6, 408-7, and 408-8, respectively.

[0032] The I / F circuit 1001 is an interface for each light-emitting chip 400 as a slave device to transmit and receive data to and from the light-emitting control unit 705 as a master device. The register 1002 is a storage unit (e.g., a semiconductor memory) that stores control parameters for controlling the light-emitting elements 602 included in the light-emitting element array 1005. The control parameters stored by the register 1002 include, for example, parameters indicating the desired light-emitting intensity of the light-emitting elements 602 (for each light-emitting element, for each light-emitting element group, or commonly for all light-emitting elements). The data holding unit 1003 includes a set of latch circuits that hold J×M signal values ​​of image data input from the light-emitting control unit 705 via the I / F circuit 1001. The data holding unit 1003 outputs drive signals indicating the respective signal values ​​in parallel to the current driving unit 1004 at the timing indicated by the line synchronization signal.

[0033] The current driver 1004 is supplied with a value of the light emission intensity indicated by the control parameter stored in the register 1002 in addition to the drive signal. FIG. 9 shows an example of a partial configuration of the current driver 1004 corresponding to one light emitting element 602. Referring to FIG. 9, the current driver 1004 includes a digital-to-analog converter (DAC) 1101, a first transistor 1102, and a second transistor 1103. The DAC 1101 performs digital-to-analog conversion on the digital value (current setting value) of the light emission intensity stored in the register 1002, and outputs a corresponding analog signal to the gate of the first transistor 1102. The first transistor 1102 is a current amplifier circuit, and may be, for example, a P-channel MOSFET. The source of the first transistor 1102 is connected to a power supply voltage VCC. The drain of the first transistor 1102 is connected to the source of the second transistor 1103. The first transistor 1102 draws out a current of a magnitude that depends on the current amount of the analog signal input to the gate from the source and outputs it to the drain. The second transistor 1103 is a switching circuit, and may be, for example, a P-channel MOSFET. A drive signal (indicating ON or OFF of light emission) from the data storage unit 1003 is input to the gate of the second transistor 1103. The drain of the second transistor 1103 is connected to the lower electrode 504 of the light-emitting element 602. When the drive signal input to the gate of the second transistor 1103 indicates that light emission is ON (for example, high level), the second transistor 1103 outputs a current input to the source to the light-emitting element 602 via the drain. Therefore, during the period when the drive signal indicates that light emission is ON, a current having a magnitude corresponding to the parameter value stored in the register 1002 is supplied to the light-emitting element 602, and each light-emitting element 602 emits light with a designated light emission intensity.

[0034] 9 shows only a portion corresponding to one light emitting element 602, the current driving unit 1004 may actually have the same circuits as the number of light emitting elements 602 (for example, 748×4=2992). However, the DAC 1101 may be shared across multiple light emitting elements 602.

[0035] In this embodiment, the I / F circuit 1001 may receive at least two of the following types of data from the light emission control unit 705: Image data Control Data Disabling Data The image data is a sequence of signal values ​​indicating the on or off state of the drive signal output to each light-emitting element as described above. The control data indicates the value of at least one control parameter to be written to the register 1002 and the address of the corresponding register. The invalidation data is data transmitted from the light emission control unit 705 to the I / F circuit 1001 in order to switch the operating state of the I / F circuit 1001. Both types of data are transmitted serially on the signal line DATAn in accordance with the clock indicated by the clock signal.

[0036] The I / F circuit 1001 determines the type of data received from the light emission control unit 705 based on the identification information added to the beginning of each data. The identification information may be composed of two clocks worth of bits from the rising edge of the synchronization signal, for example. Table 1 below shows an example of the correspondence between the signal levels of the two bits (also called identification bits) of the identification information and the data type.

[0037] [Table 1]

[0038] According to the example of Table 1, when the first bit of the identification information is at a high level and the second bit is also at a high level, image data is transmitted after the identification information. When the first bit of the identification information is at a high level and the second bit is at a low level, control data is transmitted after the identification information. When the first bit of the identification information is at a low level, invalidation data is transmitted after the identification information regardless of the signal level of the second bit. Note that the correspondence between the signal level of the identification information and the data type is not limited to the example of Table 1. For example, a correspondence in which the high level and the low level are interchanged may be adopted.

[0039] The I / F circuit 1001 switches the output destination of the subsequent data between the register 1002 and the data holding unit 1003 according to the data type determined based on the above-mentioned identification information. For example, when the identification information indicates image data, the I / F circuit 1001 outputs the subsequent data (together with a clock signal and a line synchronization signal) to the data holding unit 1003. When the identification information indicates control data, the I / F circuit 1001 outputs the subsequent data (together with a clock signal and a line synchronization signal) to the register 1002 (writes the value of the control parameter to a specified address of the register 1002). When the identification information indicates invalid data, the I / F circuit 1001 may ignore the subsequent data.

[0040] Furthermore, when the identification information indicates control data, the I / F circuit 1001 switches between writing data to the register 1002 and reading data from the register 1002 in accordance with access control information received following the identification information. The access control information may be configured with one clock's worth of bits (also called an access control bit) following the identification information. For example, the access control bit may indicate a data write instruction by a low level and a data read instruction by a high level, or vice versa.

[0041] 10 is a timing chart when image data is transmitted from a master device to a slave device, i.e., from the light-emitting control unit 705 to the light-emitting chip 400. From the top to the bottom in the figure, changes in signal level along the time axis of a clock signal (CLK), a line synchronization signal (SYNC), and data signals on signal lines DATA1, DATA2, ..., DATA19, and DATA20 are shown. The clock signal and the line synchronization signal are common signals across multiple light-emitting chips 400.

[0042] The clock signal (CLK) provides a clock for distinguishing each bit of the signal. The frequency of the clock signal may be, for example, 30 MHz. The light emission control unit 705 may generate a clock signal of a desired frequency by frequency-converting the reference clock generated by the clock generation unit 702.

[0043] The line synchronization signal (SYNC) indicates the start timing of each line cycle in which the photoconductor 102 rotates by an angle of one pixel in the circumferential direction D2 by a rising edge of the signal level. For example, when the resolution is 1200 dpi (pixel pitch about 21.16 um) and the moving speed of the surface of the photoconductor 102 is 200 mm / s, the length of one line cycle is about 105.8 us.

[0044] The data signals (DATA1 to DATA20) are output in parallel to the 20 light-emitting chips 400-1 to 400-20. Starting from the rising edge of the line synchronization signal, the first two bits of each data signal are identification information indicating a high level. Valid pixel values ​​follow from the third bit onwards, and pixel values ​​corresponding to 2992 (=748×4) light-emitting elements 602 are serially transmitted to each light-emitting chip 400 by the end of a line cycle of approximately 105.8 us.

[0045] 11A is a timing chart when control data is transmitted from the master device to the slave device (i.e., when the value of a control parameter is written to the register 1002). From the top of the figure, changes in signal level along the time axis of a clock signal (CLK), a synchronization signal (SYNC), a data signal on a signal line DATAn, and a data signal on a signal line READn are shown. The data signal on the signal line DATAn is a signal transmitted to the light-emitting chip 400-n, and the data signal on the signal line READn is a signal returned from the light-emitting chip 400-n.

[0046] The frequency of the clock signal (CLK) for transmitting and receiving the control data may be different from the frequency of the clock signal for transmitting and receiving the image data, and may be, for example, 3 MHz. The light emission control unit 705 can generate a clock signal of a desired frequency by converting the frequency of the reference clock generated by the clock generation unit 702. The synchronization signal (SYNC) here serves as an enable signal indicating the period during which the communication of the control data is enabled, and is at a high level during the communication period.

[0047] The data signal (DATAn, n=1,...,20) is transmitted in synchronization with the clock signal, starting from the rising edge of the synchronization signal. The first two bits of each data signal are identification information for identifying control data, and consist of a first bit at a high level followed by a second bit at a low level. The third bit following the identification information is an access control bit, and indicates, for example, a write (W) to the register 1002 by a low level, i.e., data transmission from the master device to the slave device. The fourth to seventh bits indicate the address of the register 1002. When the identification information indicates control data and the access control bit indicates a write (W), the I / F circuit 1001 writes data (control parameter value) indicated by the eighth to fifteenth bits of the data signal to a specified address in the register 1002. Naturally, the address and the size of the data are not limited to the example shown in the figure.

[0048] FIG. 11B is a timing chart when the master device receives control data from the slave device (that is, when the value of the control parameter is read from the register 1002).

[0049] The frequency of the clock signal (CLK) for transmitting and receiving the control data may be, for example, 3 MHz, as in the example of Fig. 11A. The synchronization signal (SYNC) also serves as an enable signal indicating the period during which the communication of the control data is enabled, and is at a high level during the communication period.

[0050] Data signals (DATAn, n=1,...,20) are transmitted in sync with the clock signal, starting from the rising edge of the synchronization signal. The first two bits of each data signal are identification information for identifying control data, consisting of a first bit at high level followed by a second bit at low level. The third bit following the identification information is an access control bit, and when high level, indicates, for example, a read (R) from register 1002, i.e., the master device receiving data from a slave device. The fourth to seventh bits indicate the address of register 1002. When the identification information indicates control data and the access control bit indicates a read (R), I / F circuit 1001 reads out the data stored at the specified address in register 1002 and outputs the eighth to fifteenth bits (D) on signal line READn. 7 ~D 0 ) and return it.

[0051] 12 is a timing chart showing the case where invalidation data is transmitted from a master device to a slave device. From the top of the figure, the changes in signal levels along the time axis of a clock signal (CLK), a synchronization signal (SYNC), and data signals on signal lines DATA1, DATA2, ..., DATA19, and DATA20 are shown.

[0052] The frequency of the clock signal (CLK) may be, for example, 30 MHz. The synchronization signal (SYNC) triggers the transmission of the invalidation data by rising to a high level.

[0053] The data signals (DATA1 to DATA20) indicate that invalidation data is to be transmitted by making the first bit of the first two bits of identification information low level, starting from the rising edge of the synchronization signal. In the example of FIG. 12, the second bit is high level, but the second bit may be low level. The third bit and subsequent bits of the data signal may all be low level.

[0054] As can be understood from the above description, in this embodiment, the I / F circuit 1001 operates in one of a number of operating states, including the following two states: First state: writing control data received from the master device to register 1002 (or transmitting control data read from register 1002 to the master device) Second state: outputting image data received from the master device to the light-emitting element array

[0055] However, if the I / F circuit 1001 can directly transition between the first state and the second state, there is a risk that the I / F circuit 1001 may enter an erroneous operating state when an identification information transmission error (e.g., misinterpretation of bits) occurs due to disturbances such as noise or static electricity. As one example, if the identification information is misinterpreted as indicating control data while image data is being transmitted sequentially, the bit string of the subsequent image data may be written to an unexpected address in the register 1002. As another example, if the identification information is misinterpreted as indicating image data even though control data is intended to be transmitted, the subsequent control data may not be written to the correct address, and instead a light-emitting element that does not need to emit light may emit light.

[0056] The invalidation data described above is incorporated to prevent such irregular transitions of the operating state. That is, when the master device switches the operating state of the I / F circuit 1001 between the first state and the second state, the master device transmits invalidation data (third data) different from the control data (first data) and the image data (second data) to the slave device. When the slave device receives the invalidation data, the slave device transitions to an intermediate state between the first state and the second state, and then transitions to the first state or the second state based on the identification information given to the data received thereafter. In other words, while the I / F circuit 1001 is operating in the first state, if image data is received from the master device without receiving the invalidation data, the I / F circuit 1001 maintains operation in the first state. Also, while the I / F circuit 1001 is operating in the second state, if control data is received from the master device without receiving the invalidation data, the I / F circuit 1001 also maintains operation in the second state.

[0057] 13 is a state transition diagram showing constraints on transition of the operation state of the I / F circuit 1001. The I / F circuit 1001 has three operation states, a first state S1, a second state S2, and an intermediate state S3, in addition to a power-off state S0.

[0058] When the power supply voltage VCC is applied, the I / F circuit 1001 transitions from the power-off state S0 to the intermediate state S3. The intermediate state S3 is a state in which invalidation data was received immediately before (or the power was turned on immediately before). When the I / F circuit 1001 receives identification bits "High+Low" indicating control data in the intermediate state S3, the I / F circuit transitions to the first state (transition T31). When the I / F circuit 1001 receives identification bits "High+High" indicating image data in the intermediate state S3, the I / F circuit transitions to the second state (transition T32). When the I / F circuit 1001 receives identification bits "Low+Any" indicating invalidation data in the intermediate state S3, the I / F circuit 1001 maintains the intermediate state (transition T33). Note that "Any" means that either "High" or "Low" is acceptable.

[0059] When the I / F circuit 1001 receives identification bits "High+Low" indicating control data in the first state S1, it maintains the first state (transition T11). Even if the I / F circuit 1001 receives identification bits "High+High" indicating image data in the first state S1, the I / F circuit 1001 ignores the subsequent data and maintains the first state because transition T12 to the second state is prohibited. When the I / F circuit 1001 receives identification bits "Low+Any" indicating invalid data in the first state S1, it transitions to the intermediate state (transition T13).

[0060] Even if the I / F circuit 1001 receives identification bits "High+Low" indicating control data in the second state S2, transition to the first state T21 is prohibited, so the I / F circuit 1001 ignores the subsequent data and maintains the second state. When the I / F circuit 1001 receives identification bits "High+High" indicating image data in the second state S2, it maintains the second state (transition T22). When the I / F circuit 1001 receives identification bits "Low+Any" indicating invalid data in the second state S2, it transitions to the intermediate state (transition T23).

[0061] By thus interposing an intermediate state between the first state and the second state, even if an error in transmitting the identification bit occurs due to an external disturbance, it is possible to avoid a situation in which invalid data is written to the register 1002 or output to the light-emitting element 602.

[0062] FIG. 14 is a timing chart of data communication in a scenario in which an error in interpretation of identification information occurs during transmission of image data. In FIG. 14, the transmission of image data from the kth line to the k+3th line, which is sent to the signal line DATA1 toward the light-emitting chip 400-1, is shown together with a clock signal (CLK) and a line synchronization signal (SYNC). First, since the identification information of the kth line is "High+High", the I / F circuit 1001 of the light-emitting chip 400-1 operates in the second state, sequentially receives image data for the 2992 light-emitting elements of the kth line, and outputs the image data to the data holding unit 1003. Next, since the identification information of the k+1th line is also "High+High", the I / F circuit 1001 of the light-emitting chip 400-1 maintains the second state, sequentially receives image data of the k+1th line, and outputs the image data to the data holding unit 1003. After that, an error occurs in the second bit of the identification information of the k+2th line, and the identification information is interpreted as "High+Low" meaning control data. However, since the I / F circuit 1001 of the light-emitting chip 400-1 has not received the invalidation data and is in the second state rather than the intermediate state, it does not transition to the first state and ignores the bit string received following the invalid identification information. As a result, the driving signals based on the image data of the k+1th line continue to be supplied to the 2992 light-emitting elements without being updated, and the image of the k+2th line becomes the same as the image of the k+1th line. Next, since the identification information of the k+3th line is "High+High", the I / F circuit 1001 of the light-emitting chip 400-1 maintains the second state, sequentially receives image data of the k+3th line, and outputs it to the data holding unit 1003.

[0063] Here, assume that the first bit of the identification information of the k+2th line is erroneously interpreted as "Low" (i.e., invalidation data), and the second bit of the identification information of the k+3th line is erroneously interpreted as "Low" (i.e., control data). In this case, the I / F circuit 1001 transitions to an intermediate state in response to reception of the invalidation data, and then erroneously transitions to the first state for receiving control data. However, the probability that such a transmission error occurs consecutively by chance at the timing when two pieces of identification information are received is extremely low. Normally, even if the identification information that should originally indicate image data is erroneously interpreted as indicating invalidation data, the next identification information again indicates image data, so the I / F circuit 1001 can properly return to the second state.

[0064] <4. Retransmission control> In the data communication between the master device and the slave device as described above, in order to prevent abnormalities such as malfunction of the device or deterioration of output quality due to transmission errors, there is a method in which the master device compares the data returned from the slave device with an expected value. If the returned data differs from the expected value, the error can be corrected by resending the data from the master device to the slave device. However, if such a comparison or resending procedure is uniformly adopted for all data communications from the master device to the slave device, the time required for communication will increase, making it difficult to meet productivity requirements.

[0065] Therefore, in this embodiment, the light-emitting control unit 705, which is a master device, selectively switches whether or not to perform retransmission control for data transmitted to the light-emitting chip 400, which is a slave device, depending on the type of data. In this section, two examples of such an embodiment will be described. Note that, although the following two examples are described in a form in which the light-emitting control unit 705 determines a transmission error and controls retransmission, any of the processes may be performed by the CPU 701 or the communication data processing unit 704 instead of the light-emitting control unit 705.

[0066] <4-1. First Example> The exposure head 106 as a data communication device includes a light-emitting control unit 705 which is a master device, and at least one light-emitting chip 400 which is a slave device. In the first embodiment, the number of the light-emitting chips 400 is 20. The light-emitting control unit 705 transmits corresponding control data to each of the light-emitting chips 400, and determines whether a transmission error has occurred in the transmission of the control data. Then, the light-emitting control unit 705 retransmits the corresponding control data to each of the light-emitting chips 400 in which it is determined that a transmission error has occurred. On the other hand, when transmitting image data corresponding to each of the light-emitting chips 400, the light-emitting control unit 705 does not determine whether a transmission error has occurred in the transmission of the image data. Similarly, when transmitting invalidation data to each of the light-emitting chips 400, the light-emitting control unit 705 does not determine whether a transmission error has occurred in the transmission of the invalidation data.

[0067] Fig. 15 is a flowchart showing an example of the flow of data communication processing according to the first embodiment. The data communication processing in Fig. 15 is started, for example, in response to acceptance of a print job from a user, and can be executed by the light-emitting control unit 705 under the control of the CPU 701. The light-emitting control unit 705 is connected to the 20 light-emitting chips 400-1 to 400-20 via the above-mentioned signal lines.

[0068] First, in S101, the light-emission control unit 705 transmits control data to the i-th light-emitting chip 400-i to write a control parameter value to the register (the initial value of index i is 1). The control data transmitted here may include, for example, a digital value of light-emission intensity (current setting value) determined in an adjustment process at a factory before shipment. Next, in S102, the light-emission control unit 705 reads the control data written to the register of the i-th light-emitting chip 400-i from the light-emitting chip. Next, in S103, the light-emission control unit 705 verifies whether the control data received from the i-th light-emitting chip 400-i in S102 matches the control data transmitted in S101, thereby determining whether a transmission error has occurred.

[0069] If the control data do not match, it is determined that a transmission error has occurred, and the process returns to S101, where the light-emitting control unit 705 retransmits the control data to the i-th light-emitting chip 400-i. This retransmission is repeated until it is determined in S103 that no transmission error has occurred.

[0070] If the control data matches, it is determined that the control data has been properly written to the register of the i-th light-emitting chip 400-i, and the process proceeds to S104. In S1004, the light-emitting control unit 705 determines whether the index i has reached 20. If the index i has not reached 20, the process returns to S101 after i is incremented in S105. In this case, the transmission of the control data to the next light-emitting chip 400-i, the reading of the data from the register, and the verification of the match (and retransmission of the control data as necessary) are repeated. If the index i has reached 20, the process proceeds to S106.

[0071] In S106, the light emission control unit 705 transmits disable data to all the light emitting chips 400-1 to 400-20 in order to switch the operation states of the I / F circuits 1001 of these light emitting chips from the first state to the second state. Next, in S107, the exposure head 106 waits until the sheet is transported to a predetermined position. When the timing to start printing (light emission control) arrives, the process proceeds to S108.

[0072] In S108, the light emission control unit 705 starts light emission control based on the input image data, and transmits the image data to the light emitting chips 400-1 to 400-20 on a line-by-line basis. At this time, the light emission control unit 705 does not perform retransmission control of the image data. Even if a transmission error occurs in the identification information added to the image data for a certain light emitting chip 400 in a certain line, the I / F circuit 1001 of the light emitting chip 400 can resume receiving the image data in the second state in the next line without transitioning to the first state. The transmission of the image data to the light emitting chips 400-1 to 400-20 is repeated until it is determined in S109 that the data transmission of the final line of the input image data has been completed. When it is determined that the data transmission of the final line has been completed, the process proceeds to S110. Note that, when printing of multiple copies is instructed, the data transmission in S108 and the end determination in S109 may be repeated until printing of all copies is completed.

[0073] In S110, the light-emitting control unit 705 transmits disable data to the light-emitting chips 400-1 to 400-20 in order to switch the operation states of the I / F circuits 1001 of all the light-emitting chips 400-1 to 400-20 to the intermediate state.

[0074] In the above-described first embodiment, the light-emitting control unit 705 performs retransmission control based on error determination only when writing control data to the register of each light-emitting chip 400, and omits retransmission control when transmitting image data for light-emitting control. Therefore, it is possible to prevent malfunctions caused by writing erroneous control data and ensure high reliability, while also avoiding an increase in the time required for communication of image data and achieving high productivity.

[0075] Furthermore, in the first embodiment, the corresponding control data can be retransmitted only to the light-emitting chip 400 in which it is determined that a transmission error has occurred among the multiple light-emitting chips 400. By such retransmission control in units of light-emitting chips (or slave devices), the time required for retransmission of the control data can be reduced.

[0076] <4-2. Second Example> Also in the second embodiment, the number of the light-emitting chips 400 may be, for example, 20. Each of the light-emitting chips 400, which is a slave device, includes one or more light-emitting elements 602 used for forming an image. When transmitting corresponding image data to each of the light-emitting chips 400 for controlling the light emission of the one or more light-emitting elements 602, the light-emission control unit 705 does not determine whether a transmission error has occurred in transmitting the image data.

[0077] After the print job is completed, the light-emitting control unit 705 transmits dummy image data (hereinafter, referred to as dummy data for turning off) which is a set of signal values ​​indicating light emission off, to each light-emitting chip 400 after the image data of the last line in order to turn off all the light-emitting elements 602. The I / F circuit 1001 of each light-emitting chip 400 outputs a drive signal based on the dummy data for turning off received from the light-emitting control unit 705 to the light-emitting elements 602 to turn off the light-emitting elements 602. If a transmission error occurs with respect to the dummy data for turning off, there is a risk that some of the light-emitting elements 602 will remain lit after the print job is completed. Turning on the light-emitting elements 602 for an excessively long period of time may cause afterimages or other image defects as a result of abnormal exposure of the photoconductor 102.

[0078] Therefore, the light-emission control unit 705 determines whether a transmission error has occurred in the transmission of the dummy data for turning off when the dummy data for turning off is transmitted to each light-emitting chip 400. Then, the light-emission control unit 705 retransmits the dummy data for turning off to each of the light-emitting chips 400 for which it is determined that a transmission error has occurred.

[0079] In the second embodiment, the image controller 700 and each light-emitting chip 400 may have the same circuit configuration as that described with reference to FIG. 7 and FIG. 8. In the first embodiment, the data return path from the data holding unit 1003 of each light-emitting chip 400 to the I / F circuit 1001 is not used. In contrast, in the second embodiment, this data return path may be used for the purpose of determining a transmission error of the dummy data for turning off. That is, the light-emitting control unit 705 transmits the dummy data for turning off to the light-emitting chip 400 after completing the transmission of image data for all lines of the image, and then receives the return of the data from the light-emitting chip 400. If the returned data is not the dummy data for turning off, the light-emitting control unit 705 determines that the turning off of the light-emitting element 602 has failed, and retransmits the dummy data for turning off to the light-emitting chip 400.

[0080] 16A and 16B are timing charts of the transmission of dummy data for turning off from the master device to the slave device, and the subsequent return of the dummy data from the slave device to the master device. From the top of the figure, the signal level changes along the time axis of the clock signal (CLK), the line synchronization signal (SYNC), and the data signals on the signal lines DATA1, READ1, ..., DATA20 and READ20 are shown. The clock signal and the line synchronization signal may be common signals across multiple light-emitting chips 400, similar to those described in relation to the first embodiment.

[0081] In the first half of the two line periods shown in FIG. 16A, the light emission control unit 705 transmits image data of the last line of the input image data in parallel to the 20 light emitting chips 400-1 to 400-20 on the signal lines DATA1 to DATA20. Starting from the rising edge of the line synchronization signal, the first two bits of each data signal are identification information indicating a high level. In this embodiment, the following third bit is further used as an access control bit. In this line period, the access control bit indicates write (W), which means that image data is transmitted from the master device to the slave device. Then, valid pixel values ​​follow from the fourth bit onwards, and pixel values ​​of the last line corresponding to 2992 (=748×4) light emitting elements 602 are serially transmitted to each light emitting chip 400.

[0082] In the latter half of the two line periods shown in FIG. 16A, the light-emitting control unit 705 transmits dummy data for turning off in parallel to the 20 light-emitting chips 400-1 to 400-20 on the signal lines DATA1 to DATA20. Starting from the rising edge of the line synchronization signal, the first two bits of each data signal are identification information indicating a high level. The third bit, which is an access control bit, also indicates write (W) in this line period, which means that image data (dummy data simulating image data) is transmitted from the master device to the slave device. Then, the actual dummy data follows from the fourth bit onwards, and a pixel value instructing 2992 (=748×4) light-emitting elements 602 to turn off light emission is serially transmitted to each light-emitting chip 400.

[0083] In the subsequent line period shown in FIG. 16B, the light-emitting control unit 705 requests each light-emitting chip 400 to return dummy data for turning off. Specifically, the light-emitting control unit 705 sets both of the first two bits of the identification information of each data signal to a high level to indicate image data, and further sets the subsequent access control bit to a high level meaning read (R). In response to receiving the identification information and the access control bit, the I / F circuit 1001 of each light-emitting chip 400 returns the image data received in the immediately preceding line period (held by the data holding unit 1003) from the fourth bit onwards on the signal line READn. Here, the returned image data should be dummy data for turning off. The light-emitting control unit 705 verifies whether the image data returned from each light-emitting chip 400 is dummy data for turning off, and when it is determined that a transmission error has occurred, retransmits the dummy data for turning off to the light-emitting chip 400 in which the transmission error has occurred.

[0084] Fig. 17 is a flowchart showing an example of the flow of data communication processing according to the second embodiment. The data communication processing in Fig. 17 is started, for example, in response to acceptance of a print job from a user, and can be executed by the light-emitting control unit 705 under the control of the CPU 701. The light-emitting control unit 705 is connected to the 20 light-emitting chips 400-1 to 400-20 via the above-mentioned signal lines.

[0085] S101 to S109 in Fig. 17 are the same processing steps as S101 to S109 in the data communication processing according to the first embodiment shown in Fig. 15, and therefore the description thereof will be omitted here. When it is determined in S109 that data transmission of the final line of the input image data has ended, the process proceeds to S111.

[0086] In S111, the light-emission control unit 705 transmits dummy data for turning off to the j-th light-emitting chip 400-j (the initial value of index j is 1). Next, in S112, the light-emission control unit 705 causes the I / F circuit 1001 of the j-th light-emitting chip 400-j to return the image data received immediately before. Next, in S113, the light-emission control unit 705 verifies whether the image data returned from the j-th light-emitting chip 400-j in S112 is dummy data for turning off, thereby determining whether or not a transmission error has occurred.

[0087] If the returned image data is not the dummy data for turning off, it is determined that a transmission error has occurred, and the process returns to S111, where the light-emission control unit 705 retransmits the dummy data for turning off to the j-th light-emitting chip 400-j. This retransmission is repeated until it is determined in S113 that no transmission error has occurred.

[0088] If the returned image data is dummy data for turning off, all the light-emitting elements 602 of the j-th light-emitting chip 400-j are properly turned off, and the process proceeds to S114. In S1104, the light-emitting control unit 705 determines whether the index j has reached 20. If the index j has not reached 20, j is incremented in S115, and then the process returns to S111. In this case, the transmission of dummy data for turning off to the next light-emitting chip 400-j, the return of the image data, and the determination of a communication error (and retransmission of the dummy data if necessary) are repeated. If the index j has reached 20, the process proceeds to S120.

[0089] In S120, the light-emitting control unit 705 transmits disable data to the light-emitting chips 400-1 to 400-20 in order to switch the operation states of the I / F circuits 1001 of all the light-emitting chips 400-1 to 400-20 to the intermediate state.

[0090] In the above-mentioned second embodiment, the I / F circuit 1001 of each light-emitting chip 400 receives both the dummy data for turning off (first data) and the image data for normal light-emitting control (second data) via a common signal line. The light-emitting control unit 705 omits retransmission control when transmitting image data for normal light-emitting control, and performs retransmission control based on error determination when transmitting the dummy data for turning off. Therefore, it is possible to achieve both prevention of image defects caused by abnormal lighting of the light-emitting element and printing productivity. In particular, the second embodiment is suitable for the case where a hold-type light-emitting element that continues to emit light once it starts emitting light until a drive signal for turning it off is supplied is used.

[0091] In addition, since the dummy data for turning off the light is transmitted after image data for all lines of the image to be printed is transmitted to each light-emitting chip 400, even if the dummy data for turning off the light is retransmitted, the retransmission does not reduce the productivity of the print job.

[0092] Furthermore, in the second embodiment, the corresponding dummy data for turning off can be retransmitted only to the light-emitting chip 400 in which it is determined that a transmission error has occurred among the multiple light-emitting chips 400. By such retransmission control in units of light-emitting chips (or slave devices), the time required for retransmitting the dummy data for turning off can be reduced.

[0093] The first and second embodiments may be combined in any manner. For example, in the second embodiment, when writing control data to a register, retransmission control based on an error determination may be performed, or the retransmission control may be omitted.

[0094] In this specification, specific numerical values ​​are used for explanation, but these specific numerical values ​​are merely examples, and the present invention is not limited to the specific numerical values ​​used in the embodiments. Specifically, the number of light-emitting chips provided on one printed circuit board is not limited to 20, and may be any number equal to or greater than 1. In addition, the size of the light-emitting element array of each light-emitting chip 400 is not limited to 4 rows and 748 columns, and may be any other size. In addition, the circumferential pitch and axial pitch of the light-emitting elements are not limited to about 21.16 μm and about 5 μm, and may be any other value.

[0095] <5. Other embodiments> The above-mentioned embodiment can be realized in the form of a process in which a program for realizing one or more functions is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., ASKC) for realizing one or more functions.

[0096] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0097] 1: image forming apparatus, 102: photoconductor, 106: exposure head, 400: light emitting chip (slave), 406: circuit section, 602: light emitting element, 701: CPU, 705: light emitting control section (master), 1001: interface circuit, 1002: register (storage section), 1003: data holding section, 1004: current driving section

Claims

1. A data communication apparatus comprising a master device and at least one slave device, The master device is Transmitting first data to the slave device; determining whether a transmission error occurred in the transmission of the first data; retransmitting the first data to the slave device when it is determined that a transmission error has occurred in the transmission of the first data; Transmitting second data to the slave device, the second data being a different type than the first data; not determining whether a transmission error has occurred in the transmission of the second data; Data communications equipment.

2. The slave device is one or more light emitting elements used to form an image; a storage unit configured to store control parameters for controlling the one or more light-emitting elements; Including, the first data includes a parameter value to be written to the storage unit; the second data includes image data to be output to the one or more light-emitting elements; 2. The data communication device according to claim 1.

3. The slave device includes one or more light emitting elements used to form an image; the second data includes image data to be output to the one or more light-emitting elements; The first data includes a signal value to be output to the one or more light-emitting elements after the second data in order to turn off the one or more light-emitting elements.

2. The data communication device according to claim 1.

4. The master device is transmitting the first data including the signal values ​​to the slave device after transmitting the second data for all lines of the image to the slave device; determining whether a transmission error occurred in the transmission of the first data including the signal value; 4. The data communication device according to claim 3.

5. The data communication apparatus includes a plurality of the slave devices, The master device is Transmitting the first data corresponding to each of the plurality of slave devices; determining whether a transmission error occurred in the transmission of the corresponding first data to each slave device; retransmitting the corresponding first data to each of the slave devices in which it is determined that the transmission error has occurred; 2. The data communication device according to claim 1.

6. 3. The data communication apparatus according to claim 2, wherein the slave device is implemented on a substrate as an integrated circuit chip connected to the master device via a signal line, and includes an interface circuit for receiving both the first data and the second data.

7. the interface circuit operates in one of a plurality of operating states including a first state for writing the first data received from the master device to the storage unit, and a second state for outputting the second data received from the master device to the one or more light-emitting elements; the master device transmits third data different from the first data and the second data to the slave device when switching an operation state of the interface circuit between the first state and the second state; 7. A data communication device according to claim 6.

8. The interface circuit includes: while operating in the first state, if the second data is received from the master device without the third data being received, maintain operation in the first state; if the first data is received from the master device without the third data being received while operating in the second state, maintaining operation in the second state.

8. A data communication device according to claim 7.

9. 9. The data communication apparatus according to claim 8, wherein the interface circuit determines a type of data received from the master device based on identification information added to a beginning of each of the first data, the second data, and the third data.

10. An image forming apparatus for forming an image on a sheet, A photoconductor; an exposure head for exposing the photoconductor; Equipped with The exposure head includes a data communication device according to any one of claims 1 to 9. Image forming device.

Images