System and method for displaying signal based on signal characteristics

Abstract

To provide an electrophysiologic (EP) signal processing technique.SOLUTION: A system, method, and computer product embodiment which display a signal based on signal characteristics, such as delay electric potential or early excitation, are disclosed. One embodiment operates by a first digital signal processor (DSP) of a first signal module by matching a heartbeat in a first packet relevant to first cardiac signals with a known signal characteristic. By a second DSP of a second signal module, the embodiment responds to matching and searches for a signal characteristic in a second packet relevant to second cardiac signals. The embodiment displays a part of the first cardiac signals with a display module combined with the first signal module and the second signal module. Subsequently, the embodiment displays a part of the second cardiac signals including the signal characteristic in time synchronization with the portion where the first cardiac signals are displayed with the display module based on search.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] Technical Field FIELD OF THE DISCLOSURE

[0001] Embodiments contained herein relate generally to cardiac electrophysiology (EP) signal acquisition and recording systems. More particularly, system, device and method embodiments are disclosed for communicating biomedical signals between a patient and monitoring and therapy devices. [Background technology]

[0002] background

[0002] Catheter ablation is a procedure to treat arrhythmias such as atrial fibrillation, a disease of the heart muscle characterized by abnormal conduction. Depending on the severity of the problem, multiple ablation procedures may be required to achieve effective results. This is because current electrophysiology (EP) techniques are limited in accurately identifying the location of the tissue causing the abnormality and to be ablated.

[0003]

[0003] A conventional diagnostic process begins with an electrocardiogram (ECG) recorded from electrodes attached to the surface of a subject's (e.g., patient's) skin. A medical team evaluates the ECG signal to determine whether a need for drug therapy and / or ablation is indicated. If ablation is indicated, an EP test is performed. A catheter is inserted into the heart via the patient's neck or groin and the heart's electrical activity is recorded. Based on this EP test, ablation is performed in areas of the heart that the medical team suspects are causing the abnormal heart rhythm.

[0004]

[0004] An ablation catheter is inserted into the patient's blood vessels and guided to the site of tissue causing abnormal electrical propagation in the heart. The catheter can scar tissue using different energy sources (most commonly heat or cold) to reduce the tissue's ability to trigger and / or transmit abnormal electrical pulses, thereby eliminating the abnormal heart rhythm. ECG signals are recorded from surface electrodes on the patient's skin, and intracardiac (IC) signals can be obtained from a catheter inside the patient's heart and recorded as electrograms (EGMs). Both ECG and IC (EGM) signals are small signals that require accurate assessment of conditioning and amplification.

[0005]

[0005] In conventional EP systems, to determine whether ablation treatment of a particular tissue site is successful, the medical team must often stop the ablation process and collect physiological signals (e.g., cardiac signals) from a monitoring device (e.g., an ECG monitor). This is because current systems do not allow for accurate simultaneous detection, collection, and isolation of small cardiac signals (with amplitudes ranging from 0.1 to 5 mV and frequencies ranging from DC to 1 kHz) in near real time during application of large ablation signals (on the order of hundreds of volts at frequencies of about 450 kHz).

[0006]

[0006] Specifically, Francischelli et al., U.S. Patent Application Publication No. 2006 / 014275 The 3A1 determines the completeness or transmurality of the ablation by monitoring the ablation and the depolarizing ECG signal from the electrodes adjacent to the tissue to be ablated. proposed a system and method for evaluating the ablation They point out that in order to minimize noise detection problems during measurement of the ECG signal from the electrodes of the ablation device, the measurements are preferably performed during interruptions in the delivery of ablation energy to the ablation electrodes.

[0007]

[0007] In general, some current EP recording systems can effectively aid in the treatment of arrhythmias such as atrial flutter and supraventricular tachycardia, which manifest as large amplitude, low frequency signals. However, more complex and prevalent arrhythmias such as atrial fibrillation and ventricular tachycardia, which are characterized as low amplitude, high frequency signals, have not found effective assessment of all relevant signals.

[0008]

[0008] This signal detection, acquisition and feature extraction can be further complicated by device power line noise and pacing signals. To reduce noise and artifacts from various electrical signal information, current EP recorders use low pass, high pass and notch filters. Unfortunately, conventional filtering techniques can alter the signal and make it difficult or impossible to see low amplitude, high frequency signals that may be inherent in cardiac monitoring, the visualization of which can aid in the treatment of atrial fibrillation and ventricular tachycardia. It has been recognized in recent years that certainty of waveform integrity, such as for low noise acquisition of IC and ECG signals in the EP environment, was not previously achieved due to contamination by artifacts and noise.

[0009]

[0009] Specifically, in a paper entitled Waveform Integrity in Atrial Fibrillation: The Forgotten Issue of Cardiac Electrophysiology (Annals of Biomedical Engineering, April 18, 2017), Martinez-Iniesta et al. point out that during signal acquisition, high-frequency and broadband instrument noise is "unavoidably recorded" and that further complications of acquisition come from a variety of other signals, including 50 or 60 Hz mains voltage, high-frequency patient muscle activity, and low-frequency baseline fluctuations from respiration or catheter movement or unstable catheter contact. Martinez-Iniesta et al. further point out that regular filtering results in insufficient noise reduction with significant changes in waveform and spectral characteristics. However, aggressive filtering from 30 to 300 Hz remains routine EP practice.

[0010]

[0010] Conventional practices distort morphological features in the resulting signal, resulting in the loss of relevant (interesting) signal information, affecting signal validity. Martinez-Iniesta et al. propose a partial software solution for only mid- and high-frequency noise reduction using pre-processing and noise reduction methods, but no solution exists that combines low-frequency noise reduction components in software with noise reduction components in hardware. A desirable feature of an EP system is that it can maintain the integrity of the original signal information using a combination of hardware and software that can reduce noise from the signal (or promote a high signal-to-noise ratio) while minimizing hardware filtering that would otherwise remove the interest of the signal content. Summary of the Invention [Problem to be solved by the invention]

[0011]

[0011] Currently, the predominant approach to ablation treatment of paroxysmal and persistent atrial fibrillation is pulmonary vein isolation (PVI), where a medical team uses a cardiac mapping system to reconstruct the cardiac geometry in 3D and perform ablation at the anatomical location where atrial fibrillation occurs, such as the pulmonary veins. The procedure takes 2-8 hours, and the physician may not achieve a durable lesion / scar to isolate the potentially problematic tissue from the left atrium. Thus, the patient often needs to be returned for an additional ablation procedure to complete the treatment. However, the additional ablation procedure and possible complications can be minimized by being able to clearly visualize the cardiac signal during ablation and determine whether the lesion is transmural or not.

[0012]

[0012] Conventional EP systems may have several other limitations. First, users often want to process and display multiple features of a signal in near real time. For example, a medical team may want to simultaneously display various and multiple versions of ECG, IC, and other physiological signals in near real time to evaluate different signal attributes, however, conventional EP systems often are not capable of processing and displaying multiple versions of the signals simultaneously in near real time.

[0013]

[0013] Second, users often want to dynamically apply new digital signal processing functions to a signal without interfering with other digital signal processing functions already applied to the signal. However, conventional solutions do not allow a user to dynamically apply new digital signal processing functions to a signal without stopping the acquisition of the signal or interfering with other digital signal processing functions already applied to the signal.

[0014]

[0014] Finally, users often want to synchronize the processing and display of multiple signals in near real time. For example, a user may want to synchronize the display of multiple processed versions of the same signal. Furthermore, a medical team may want to synchronize the display of multiple processed versions of ECG, IC, and other physiological signals, since the medical team's ability to make a valid clinical diagnosis depends on comparing multiple signals at the same time. However, conventional solutions may not be able to process and synchronize the display of multiple processed signals in near real time. [Means for solving the problem]

[0015] Overview of the embodiment

[0015] Apparatus, systems and methods for EP signal acquisition and recording are disclosed that include numerous improvements with respect to noise and artifact reduction in a variety of biomedical applications.

[0016]

[0016] The disclosed EP system embodiments can record raw (unaltered) cardiac and other physiological signals with multiple display options, and with low noise and large input signal dynamic range. The raw signals collected by the acquisition module are filtered and processed in accompanying software using a digital processing module with minimal use of hardware filters (e.g., hardware filters are used only for AC coupling, anti-aliasing, and high frequency suppression). The use of software-based digital signal processing algorithms allows the signals to be displayed in real time as raw signals, or as a combination of raw and processed signals simultaneously in a single window or in real time in multiple windows. Furthermore, the visualization and review capabilities of the disclosed EP system allow the user to mark features specified in the algorithm on the real time tracing.

[0017]

[0017] The disclosed EP system allows the simultaneous display of signals with more than one signal processing algorithm applied, a feature not found in conventional systems. This allows the user to view signals that have been filtered in multiple ways for a given reason. In the real-time window, the waveform of interest can be displayed as a raw signal or any combination of raw and filtered signals, allowing for better visualization of the signal in the presence of noise and artifacts.

[0018]

[0018] All of the displayed signals are time-synchronous, and the user has the option to open multiple review windows as well as display the results of various signal processing algorithms independent of real-time tracing.

[0019] From a clinical perspective, the disclosed EP system can greatly aid medical teams in decision making for patients undergoing various medical therapies (such as ablation), with benefits including, but not limited to, clearer and more reliable recording of intracardiac signals; These include: reduced baseline drift and suppressed RF energy to reduce noise; improved dynamic range for better visualization, especially of very low amplitude signals that are temporarily located within larger amplitude signals; real-time digital processing and recording of the raw signal to facilitate signal filtering and reduce artifacts and noise without affecting the original information; high quality unipolar signals to aid in determination of tissue type and catheter location; improved waveform integrity and reduced artifacts, which are by-products of signal processing, enabling medical teams to improve procedural outcomes; and improved signal information to enable medical teams to provide more precise catheter tip location for ablation and other treatment levels and durations for treatment efficacy.

[0020] In some embodiments of a system for visualizing signals using late potentials, the memory includes a first signal module including a first digital signal processor (DSP) configured to match heart beats in a first packet associated with a first cardiac signal with known signal characteristics, and a second signal module including a second DSP configured to search for late potentials in a second packet associated with a second cardiac signal in response to the matching. The memory also includes a display module coupled to the first signal module and the second signal module, the display module configured to display a portion of the first cardiac signal and display a portion of the second cardiac signal including the late potential in time synchronization with the displayed portion of the first cardiac signal based on the searching. The system also includes at least one processor coupled to the memory and configured to execute the first signal module, the second signal module, and the display module. Execution of the system components by the computer system implements various method embodiments for visualizing signals using late potentials. The computer system includes a non-transitory computer-readable device having instructions stored thereon that, when executed by at least one computing device, cause the at least one computing device to perform operations implementing the method steps.

[0021]

[0021] In some embodiments of a system for visualization of signals using early activation, the memory includes a first signal module including a first DSP configured to match a heart beat in a first packet associated with the first cardiac signal with a known signal characteristic, and a second signal module including a second DSP configured to search for an early activation in a period of time before a matching heart beat in the second cardiac signal. The memory also includes a display module coupled to the first signal module and the second signal module, the display module configured to display a portion of the first cardiac signal and, based on the search, display a portion of the second cardiac signal including the early activation in time synchronization with the displayed portion of the first cardiac signal. The system also includes at least one processor coupled to the memory and configured to execute the first signal module, the second signal module, and the display module. Some method embodiments and non-transitory computer-readable device embodiments for visualization of signals using early activation are also disclosed.

[0022]

[0022] Some method and non-transitory computer readable device embodiments perform steps including accessing a first cardiac signal associated with a body surface lead, matching a heart beat of the first cardiac signal with a known signal pattern, and searching for early excitation or late potentials in the second cardiac signal for a period of time before and after the matching heart beat.

[0023] Another method and non-transitory computer readable device embodiment for filtering noise from an input signal using notch filtering includes accessing an input signal having a first harmonic frequency and having noise; determining a first high-order noise component from the input signal; storing samples of noise of the input signal in a buffer during a quiet period; and subtracting samples from a single cycle of noise in the buffer from the input signal to generate a filtered signal, the subtraction removing a first high-order noise component from the input signal. A subtraction step is performed in which harmonic and superharmonic frequencies are removed and the introduction of transient responses in the filtered signal is avoided, and a step of refining the filtered signal by repeated determining, storing and subtracting is performed.

[0024] Some method and non-transitory computer readable device embodiments for filtering noise from an input signal using high frequency filtering include the steps of accessing an input signal including noise and a high frequency signal of interest; high pass filtering the input signal to generate a filtered signal; isolating noise related artifacts in the filtered signal from the high frequency signal of interest; optionally selecting a filter based on the isolated artifacts; and blanking the filtered signal for a period of time before and after the isolated artifact. ) where disabling removes the isolated artifacts and allows high frequency signals of interest to pass.

[0025]

[0025] Some method and non-transitory computer readable device embodiments of pattern matching implement the steps of accessing an input cardiac signal, matching a portion of the input cardiac signal with a known signal pattern, and displaying an indication of the degree of match. Other embodiments of pattern matching match a portion of the input cardiac signal with a known signal pattern based on a detection threshold and display a highlighted portion of the input cardiac signal based on the match.

[0026]

[0026] A system embodiment for generating a clean unipolar signal, comprising: Also disclosed is a system embodiment comprising an ECG circuit board configured to process an ECG signal, and a plurality of intracardiac (IC) circuit boards, each configured to process a corresponding IC signal, wherein the ECG circuit board and the plurality of IC circuit boards share substantially the same circuitry and components, and wherein the ECG circuit board processes the ECG signal using substantially the same path as each IC circuit board uses to process its corresponding IC signal.

[0027]

[0027] Other system embodiments for performing electrophysiology (EP) processing are also disclosed, the system embodiments comprising an ECG circuit board configured to process ECG signals, a plurality of IC circuit boards, each configured to process a corresponding IC signal, a communication interface communicatively coupled to a remote device, and a processor coupled to the ECG circuit board, the plurality of IC circuit boards, and the communication interface. Such system embodiments receive feedback from the remote device via the communication interface, and control the remote device based on the ECG signal, the IC signal, and the feedback from the remote device via the communication interface.

[0028] BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are incorporated in this specification and form a part of this specification, illustrate this embodiment and, together with the description, further serve to explain the principles of this embodiment and enable those skilled in the art to make and use this embodiment. [Brief description of the drawings]

[0029] [Figure 1]

[0029] A block diagram of a conventional electrophysiology (EP) environment including patient connections and interference sources is shown. [Diagram 2]

[0030] 1 illustrates a hardware system block diagram of the disclosed EP hardware system, according to some embodiments. [Diagram 3]

[0031] FIG. 2 illustrates a block diagram of a multi-channel analog-to-digital input / output of an EP hardware system input stage according to some embodiments. [Figure 4]

[0032] FIG. 2 illustrates a block diagram of a single channel of an EP hardware system input stage according to some embodiments. [Figure 5A]

[0033] 1 shows a block diagram of an overall EP system, according to some embodiments. [Figure 5B]

[0034] 1 shows a high level summary of the overall EP system hardware and software, according to some embodiments. [Figure 6A]

[0035] 1 illustrates a schematic diagram of a large signal input protection portion of an input protection circuit of an EP hardware system according to some embodiments. [Figure 6B]

[0036] 1 illustrates a schematic diagram of an electrostatic discharge (ESD) protection portion of an input protection circuit of an EP hardware system according to some embodiments. [Figure 7]

[0037] 1 illustrates a schematic diagram of a radio frequency (RF) filtering portion of an input protection circuit of an EP hardware system according to some embodiments. [Figure 8A]

[0038] 4 illustrates a voltage signal plot of a typical defibrillation signal at an input to an input protection circuit in accordance with an exemplary embodiment. [Figure 8B] 4 illustrates a voltage signal plot of a typical defibrillation signal at the input to an input protection circuit, according to an exemplary embodiment. [Figure 8C] 4 illustrates a voltage signal plot of a typical defibrillation signal at the input to an input protection circuit, according to an exemplary embodiment. [Figure 8D] 4 illustrates a voltage signal plot of a typical defibrillation signal at the input to an input protection circuit, according to an exemplary embodiment. [Figure 8E] 4 illustrates a voltage signal plot of a typical defibrillation signal at the input to an input protection circuit, according to an exemplary embodiment. [Figure 9A]

[0039] 1 illustrates a voltage signal plot of a typical ablation signal at the input to an input protection circuit, according to an exemplary embodiment. [Figure 9B] 4 illustrates a voltage signal plot of a typical ablation signal at the input to an input protection circuit according to an exemplary embodiment. [Figure 9C] 4 illustrates a voltage signal plot of a typical ablation signal at the input to an input protection circuit according to an exemplary embodiment. [Figure 9D] 4 illustrates a voltage signal plot of a typical ablation signal at the input to an input protection circuit according to an exemplary embodiment. [Figure 9E] 4 illustrates a voltage signal plot of a typical ablation signal at the input to an input protection circuit according to an exemplary embodiment. [Figure 10]

[0040] FIG. 1 shows a schematic diagram of the instrumentation and gain stages of an EP hardware system, according to some embodiments. [Figure 11]

[0041] 1 illustrates a schematic diagram of a large signal detection / fast recovery circuit for an EP hardware system according to some embodiments. [Figure 12]

[0042] 1 illustrates a voltage signal plot showing the slow recovery that occurs after a large undesirable signal gets through the input protection, instrumentation and gain stages of an EP hardware system circuit when the large signal detection / fast recovery circuit is disconnected, according to an exemplary embodiment. [Figure 13A]

[0043] 1 illustrates a voltage signal plot showing the fast recovery that occurs after a large undesirable signal is presented to the input protection, instrumentation and gain stages of an EP hardware system circuit when a large signal detection / fast recovery circuit is connected, in accordance with an exemplary embodiment. [Figure 13B]

[0043] A voltage signal plot showing the fast recovery that occurs after a large undesirable signal is presented to the input protection stage, instrumentation stage and gain stage of an EP hardware system circuit when a large signal detection / fast recovery circuit is connected according to an exemplary embodiment. [Figure 13C]

[0043] A voltage signal plot showing the fast recovery that occurs after a large undesirable signal is presented to the input protection stage, instrumentation stage and gain stage of an EP hardware system circuit when a large signal detection / fast recovery circuit is connected according to an exemplary embodiment. [Figure 14A]

[0044] 1 illustrates signal plots for voltage signals at various internal nodes passing through a large signal detection / fast recovery circuit when the large signal detection / fast recovery circuit is connected, according to an exemplary embodiment. [Figure 14B] 4 shows signal plots for voltage signals at various internal nodes passing through a large signal detection / fast recovery circuit when the large signal detection / fast recovery circuit is connected, according to an exemplary embodiment. [Figure 14C] 4 shows signal plots for voltage signals at various internal nodes passing through a large signal detection / fast recovery circuit when the large signal detection / fast recovery circuit is connected, according to an exemplary embodiment. [Figure 14D] 4 shows signal plots for voltage signals at various internal nodes passing through a large signal detection / fast recovery circuit when the large signal detection / fast recovery circuit is connected, according to an exemplary embodiment. [Figure 15A]

[0045] 1 illustrates a signal plot for a current signal across a resistor at the output of a connected large signal detection / fast recovery circuit in accordance with an exemplary embodiment. [Figure 15B] 4 illustrates a signal plot for a current signal across a resistor at the output of a connected large signal detection / fast recovery circuit, according to an exemplary embodiment. [Figure 16]

[0046] FIG. 1 illustrates a schematic diagram of a low-frequency feedback circuit that acts as a dynamic current source for an EP hardware system, according to some embodiments. [Figure 17A]

[0047] 1 illustrates a signal plot for a typical in-band voltage differential input signal affected by 60 Hz common mode noise to an EP hardware system, according to an exemplary embodiment. [Figure 17B] 4 shows a signal plot for a typical in-band voltage differential input signal affected by 60 Hz common mode noise to an EP hardware system, according to an exemplary embodiment. [Figure 17C] 4 shows a signal plot for a typical in-band voltage differential input signal affected by 60 Hz common mode noise to an EP hardware system, according to an exemplary embodiment. [Figure 17D] 4 shows a signal plot for a typical in-band voltage differential input signal affected by 60 Hz common mode noise to an EP hardware system, according to an exemplary embodiment. [Figure 18A]

[0048] 1 illustrates a signal plot of a typical differential voltage signal affected by 60 Hz common mode noise passing through an EP hardware system, according to an exemplary embodiment. [Figure 18B] 4 shows a signal plot of a typical differential voltage signal affected by 60 Hz common mode noise passing through an EP hardware system, according to an exemplary embodiment. [Figure 18C] 4 shows a signal plot of a typical differential voltage signal affected by 60 Hz common mode noise passing through an EP hardware system, according to an exemplary embodiment. [Figure 18D] 4 shows a signal plot of a typical differential voltage signal affected by 60 Hz common mode noise passing through an EP hardware system, according to an exemplary embodiment. [Figure 19A]

[0049] 13 shows a signal plot of a typical 500 kHz ablation input system in a frequency range attenuated by an RF filter in an EP hardware system, according to an exemplary embodiment. [Figure 19B] 4 shows a signal plot of a typical 500 kHz ablation input system in a frequency range attenuated by an RF filter in an EP hardware system, according to an exemplary embodiment. [Figure 19C] 4 shows a signal plot of a typical 500 kHz ablation input system in a frequency range attenuated by an RF filter in an EP hardware system, according to an exemplary embodiment. [Figure 19D] 4 shows a signal plot of a typical 500 kHz ablation input system in a frequency range attenuated by an RF filter in an EP hardware system, according to an exemplary embodiment. [Figure 20A]

[0050] 1 shows a signal plot of a typical 500 kHz ablation input signal at the shield input allowing an RF filter to attenuate the input signal to the EP hardware system in accordance with an exemplary embodiment. [Figure 20B] 13 shows a signal plot of a typical 500 kHz ablation input signal at the shield input that enables an RF filter to attenuate the input signal to the EP hardware system, according to an exemplary embodiment. [Figure 21A]

[0051] 1 shows a signal plot of a typical 500 kHz ablation input signal attenuated after passing through an instrumentation amplifier and after passing through a fully differential operational amplifier of the EP hardware system in accordance with an exemplary embodiment. [Figure 21B]

[0051] Figure 1 shows a signal plot of a typical 500 kHz ablation input signal attenuated after passing through an instrumentation amplifier and after passing through a fully differential operational amplifier of an EP hardware system, according to an exemplary embodiment. [Figure 21C]

[0051] Figure 1 shows a signal plot of a typical 500 kHz ablation input signal attenuated after passing through an instrumentation amplifier and after passing through a fully differential operational amplifier of an EP hardware system, according to an exemplary embodiment. [Figure 21D]

[0051] Figure 1 shows a signal plot of a typical 500 kHz ablation input signal attenuated after passing through an instrumentation amplifier and after passing through a fully differential operational amplifier of an EP hardware system, according to an exemplary embodiment. [Figure 22A]

[0052] 1 illustrates an improvement in visualization of ECG or IC signals according to an exemplary embodiment. [Figure 22B]

[0053] We show that an EP system, according to an exemplary embodiment, can reveal low amplitude cardiac signals and small components of EP signal artifacts in the presence of noise and large signal procedures. [Figure 22C]

[0054] We show that an EP system, according to an exemplary embodiment, can remove 60 Hz noise without saturation or delayed recovery, while preserving the components of the 60 Hz signal that belong to the original waveform. [Diagram 23]

[0055] FIG. 1 shows a schematic diagram of an improved Wilson Central Terminal-Right Leg Drive (WCT-RLD) circuit, according to some embodiments. [Figure 24]

[0056] FIG. 1 shows a schematic diagram of a Twin-T feedback network interfaced with the RLD circuit of a WCT-RLD circuit, according to some embodiments. [Diagram 25]

[0057] 13 illustrates a signal plot of an output of a Twin-T feedback network of a WCT-RLD circuit in accordance with an exemplary embodiment. [Figure 26]

[0058] FIG. 1 is a block diagram of a system for processing and displaying multiple signals in near real-time according to some embodiments. [Figure 27]

[0059] FIG. 2 is a block diagram of a queuing module that stores generated packets associated with different base signals, according to some embodiments. [Figure 28]

[0060] FIG. 2 is a block diagram of a configuration path module that generates time-allocated signals at run time that are processed from a set of base signals, according to some embodiments. [Figure 29]

[0061] 4 is a block diagram of a signal module generated by a signal factory module according to some embodiments. [Diagram 30]

[0062] FIG. 2 is a block diagram of a display module for displaying one or more signals according to some embodiments. [Diagram 31]

[0063] FIG. 2 is a block diagram of a monitoring module that performs error checking, according to some embodiments. [Diagram 32]

[0064] 13 illustrates an example of adjusting a sweep speed for a display module according to some embodiments. [Diagram 33]

[0065] 1 illustrates signal management for a display module according to some embodiments. [Diagram 34]

[0066] 4 illustrates example zoom and clip factor adjustments for a display module according to some embodiments. [Diagram 35]

[0067] 1 illustrates pattern search management for a display module according to some embodiments. [Diagram 36]

[0068] 13 shows late potential search results highlighted in a display of a display module according to some embodiments. [Figure 37A]

[0069] 1 illustrates the use of a display module configured as a waterfall view, according to some embodiments. [Figure 37B]

[0070] 1 illustrates the correspondence between signals in a normal display module and in a display module configured as a waterfall view, according to some embodiments. [Figure 37C]

[0071] 1 illustrates the use of a display module configured as a dynamic view, according to some embodiments. [Figure 37D]

[0072] 1 illustrates the use of a display module configured as a trigger view, according to some embodiments. [Figure 38]

[0073] 1 illustrates the capture of a signal in a display of a display module configured as a review window, according to some embodiments. [Figure 39]

[0074] 13 illustrates an amplitude measurement performed on a display of a display module configured as a review window, according to some embodiments. [Diagram 40]

[0075] 1 is a flow chart of a method for processing and displaying multiple signals in near real-time, according to one embodiment. [Diagram 41]

[0076] 1 is a flowchart of a method for configuring one or more signal modules, according to some embodiments. [Diagram 42]

[0077] 1 is a flowchart of a method for generating a signal module from a signal processing specification according to some embodiments. [Diagram 43]

[0078] 1 is a flowchart of a method for equalizing processing delays associated with each DSP of one or more signal modules according to some embodiments. [Diagram 44]

[0079] 1 is a flowchart of a method for receiving one or more signal samples for one or more signals using an input module, according to some embodiments. [Diagram 45]

[0080] 1 is a flowchart of a method for converting one or more signal samples into one or more packets using a packetizer according to some embodiments. [Figure 46]

[0081] 1 is a flowchart of a method for dispatching a packet including one or more signal samples to a queuing module according to some embodiments. [Figure 47]

[0082] 1 is a flowchart of a method for dispatching a packet from a queuing module to an associated signaling module of the packet, according to some embodiments. [Figure 48]

[0083] 4 is a flowchart of a method for processing a packet using an associated signal module of the packet, according to some embodiments. [Figure 49]

[0084] 1 is a flowchart of a method for displaying processed packets on a display screen using a display module according to some embodiments. [Figure 50]

[0085] 1 illustrates an example of a signal with superimposed noise, according to some embodiments. [Figure 51]

[0086] 1 illustrates an example of a conventional approach to removing noise using a notch filter, according to some embodiments. [Figure 52]

[0087] 52 illustrates an example of the results of applying the conventional filter of FIG. 51 according to some embodiments. [Figure 53]

[0088] 52 illustrates an example of the 180 Hz harmonic still present in the output of the conventional filter of FIG. 51 according to some embodiments. [Figure 54]

[0089] 1 illustrates an example of notch filtering for a signal containing 60 Hz and 180 Hz noise, according to some embodiments. [Figure 55]

[0090] 1 shows an example of a notch filter that uses 100 samples and stores exactly 3 cycles of 60 Hz, according to some embodiments. [Figure 56]

[0091] 1 illustrates an example of a notch filter for calculating quiet time, according to some embodiments. [Figure 57]

[0092] 1 illustrates an example of a notch filter that accumulates a replica of noise and subtracts it from a noisy signal, according to some embodiments. [Figure 58]

[0093] 13 illustrates an example of a notch filter result, according to some embodiments. [Figure 59]

[0094] 1 is a flowchart of a process for notch filtering noise from an input signal in accordance with some embodiments. [Figure 60]

[0095] 1 illustrates an example of a conventional high-pass filter, according to some embodiments. [Figure 61]

[0096] 1 shows an example of a signal that includes both high frequency signals from conductive regions of the heart and sharp local spikes from various sources, according to some embodiments. [Figure 62]

[0097] 62 shows an example of the output that results from filtering the signal of FIG. 61 using the high pass filter of FIG. 60 according to some embodiments. [Figure 63]

[0098] 62 shows an example of the output that results from filtering the signal of FIG. 61 using a high-pass filter to remove impulses while allowing high frequency signals of interest to pass, according to some embodiments. [Figure 64]

[0099] 1 is a flowchart of a process for high-pass filtering noise from an input signal in accordance with some embodiments. [Figure 65]

[0100] 1 shows an example of a review window using vertical calipers to select a range of data, according to some embodiments. [Figure 66]

[0101] 13 illustrates an example of saving a selected pattern as a reference heart beat, according to some embodiments. [Figure 67]

[0102] 1 shows an example of a window of selectable patterns to search for, according to some embodiments. [Figure 68]

[0103] FIG. 66 shows an example of a pattern search summary view in the review window of FIG. 65 with multiple matching patterns displayed, according to some embodiments. [Figure 69]

[0104] FIG. 69 illustrates an example of a pattern search summary view in the review window of FIG. 68 with a single matching pattern displayed and other patterns hidden, according to some embodiments. [Figure 70]

[0105] 66 shows an example of a detailed view of the review window of FIG. 65 according to some embodiments. [Figure 71]

[0106] 13 illustrates an example of pattern matching confidence values ​​provided by guidance, according to some embodiments. [Figure 72]

[0107] 1 is a flowchart of a process of pattern matching, according to some embodiments. [Figure 73]

[0108] 1 is a flowchart of a process of pattern matching, according to some embodiments. [Figure 74]

[0109] 1 illustrates an example of a search definition window for creating and managing late potential and pre-excitation searches, according to some embodiments. [Figure 75]

[0110] 1 illustrates an example of a late potential detection configuration window that defines various search parameters for late potentials, according to some embodiments. [Figure 76]

[0111] 1 shows an example showing the locations of late potentials along with their detection confidence, according to some embodiments. [Figure 77]

[0112] 1 illustrates an example of a pre-excitation detection configuration window that defines various search parameters for pre-excitation, according to some embodiments. [Figure 78]

[0113] 1 illustrates an example showing locations of pre-excitation along with their detection confidence, according to some embodiments. [Figure 79]

[0114] 1 illustrates an example of a search definition window for managing previously defined late potential and pre-excitation searches, according to some embodiments. [Figure 80]

[0115] 1 is a flowchart of a process for detecting early excitation or late potentials, according to some embodiments. [Figure 81]

[0116] 1 illustrates an example of a waterfall view configuration window, according to some embodiments. [Figure 82]

[0117] 1 illustrates an example of a waterfall view using time mode, according to some embodiments. [Figure 83]

[0118] 1 illustrates an example of a waterfall using heart rate mode, according to some embodiments. [Figure 84]

[0119] 1 illustrates an example of a display parameters window, according to some embodiments. [Figure 85]

[0120] 1 illustrates an example computer system according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030]

[0121] Features and advantages of the present embodiments will become more apparent from the detailed description set forth below in conjunction with the drawings, in which like reference numbers identify corresponding elements throughout the drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) of the corresponding reference number. Detailed Description of the Invention

[0031]

[0122] In particular, devices, systems and methods associated with unique amplifier topologies are disclosed that condition cardiac (e.g., ECG and IC) and other physiological signals to clearly define and record low amplitude, low frequency information that may be collected during ablation and other similar large signal disturbances, such as pacing and stimulation. During a procedure, the tip (or other electrode) of the catheter can be connected to a pacing, ablation and stimulation device system to allow visualization, pacing, ablation and stimulation without mode switching. For example, the disclosed devices, systems and methods can effectively isolate ablation signals from cardiac signals during ablation while simultaneously providing input protection against high voltages from defibrillation signals and the like. Similarly, the disclosed devices, systems and methods can effectively isolate stimulation signals from physiological signals during stimulation.

[0032]

[0123] Because different system recording requirements for each signal type cannot be met simultaneously, each block or module of the system can be optimized in performance to achieve the multiple signal conditioning requirements desired by the clinician. Various embodiments allow the system to simultaneously process cardiac, pacing, ablation, defibrillation, stimulator and other physiological signal types by detecting, conditioning and displaying the signals of interest, for example, to monitor the effect of an ongoing treatment on the cardiac signals.

[0033]

[0124] Furthermore, various embodiments can ensure collection of multiple low amplitude cardiac signals in the presence of multiple electrical noise sources and environmental interferences, apart from large signals injected during ablation and stimulation procedures, pacing or defibrillation. The cardiac signals of interest can be displayed in an uncomplicated and clinically relevant manner by processing the signals in real-time or near real-time to display a comprehensive causal relationship between physician-initiated procedures and resulting cardiac signals, while simultaneously identifying signal artifacts and removing undesirable noise. This disclosure discloses both hardware and software embodiments to achieve these objectives.

[0034]

[0125] This disclosure refers to both "unipolar signals" and "bipolar signals," both of which are commonly used in EP recordings, but for complementary purposes. Both unipolar and bipolar signals require a single unipolar or bipolar signal to be applied to the patient's body, particularly the patient's extremities and chest, for example, to measure an ECG signal. To measure the IC signal, for example, it is obtained from the potential difference recorded at two (or more) different isolated electrodes placed directly on the cardiac tissue, or, as another example, at two (or more) different isolated electrodes placed directly on the cardiac tissue.

[0035]

[0126] Conventionally, a 12-lead ECG system is used, consisting of connections to each of the four limbs, i.e., right arm (RA), left arm (LA), right leg (RL) and left leg (LL), and six precordial connections V1-V6 from six separate electrodes placed at various locations on the patient's chest. The individual ECG electrode wires are connected to a terminal block at the end of the patient table, from which they are routed to a data acquisition system. All leads are conventionally connected to a protection circuit that prevents damage to the measurement equipment caused by defibrillation potentials or static electricity from the environment.

[0036]

[0127] Bipolar signals are standard for some ECG measurements (Leads I, II, III), but can also be obtained directly from the heart surface to collect IC signals. Bipolar signals can be obtained by attaching two (or more) electrodes in close proximity to a given region of the heart or cardiac tissue and measuring the potential difference between the electrodes, providing information about local electrical activity, such as late potentials caused by damaged myocardium. However, bipolar IC signals do not provide information about the electrical impulse propagation direction. For example, currently, one of the challenges of bipolar mapping is that it is not possible to know whether the signal of interest is originating from the distal or proximal electrode. This is important because pacing and energy delivery are provided by the distal electrode.

[0037]

[0128] A unipolar signal is generated from a point source by placing one IC electrode on the surface of the patient's heart and the other electrode spaced apart from the first electrode to serve as a reference signal so that the IC potential can be derived. The unipolar leads from the IC electrodes are connected such that one lead serves as the active lead while the other is at a non-active location or the result of a calculated non-active location (WCT, described below). In this way, electrodes flowing towards the active electrode result in a positive deflection and electrodes flowing away from the active electrode result in a negative deflection. This provides information regarding the cardiac signal propagation direction. Unipolar recordings are particularly useful when directional information is desired, such as in determining the depolarization and repolarization pathways in the endocardium and epicardium. Methods are disclosed herein that use the first derivative of both unipolar signals.

[0038]

[0129] Leads can also be connected to the limbs, creating a virtual triangle called "Einthoven's triangle." Thus, true bipolar leads can be obtained by referencing each connection to one of the other two (e.g. LA referenced to RA is Lead I, LL referenced to RA is Lead II, and finally LA referenced to LL is Lead III). The average of the three limb cords RA, LA and LL then approximates the zero potential point and provides the reference electrode (WCT, described below), where the vector sum of Leads I and III is Lead II.

[0039]

[0130] Using the concept of Einthoven's triangle, the Wilson Coupling Electrode (WCT) is an electrical circuit concept used in the art (and further discussed in this disclosure) that can be used as an indifferent electrode acting as the electrical center of the heart as a reference. The WCT can be used when it is desired that the IC signal be displayed in a unipolar manner. When using the WCT as a reference for the unipolar signal, the unipolar signal can approximate widely separated bipolar signals for consistent unipolar recording. The WCT can eliminate the need for an additional catheter to be used as a reference for unipolar recording of the IC signal.

[0040]

[0131] In this disclosure, "near real-time" means that the signals passing through the EP system are displayed on the EP system display monitor from the time they occur at the inputs of the hardware circuits of the EP system. "Near real-time" refers to the collection and visualization of signals passing through an EP system, either in raw (unprocessed) form or after being processed by an EP system main processing unit (MPU) and one or more digital signal processing (DSP) modules, up to the point where they are first displayed. For raw signals, "near real-time" may be on the order of less than 5 milliseconds, and for processed signals, on the order of less than 50 milliseconds.

[0041]

[0132] FIG. 1 is a block diagram depicting a conventional EP environment 100 including patient connections and interference sources. As will be appreciated by those skilled in the art, a patient 118 may be connected to a pulse oximeter 104, one or more ECG units 106, an infusion pump 108, an electroanatomical mapping system 110, a data collection system 112 such as the EP system disclosed herein, an ablation generator 114, a neurostimulator 128, other diagnostic equipment such as an external defibrillator, and several IC catheters. Such diagnostic equipment may be connected to and powered by a 120-240V, 50 / 60Hz AC power source 102. The laboratory diagnostic equipment may be connected to ground 120 through its power connections.

[0042]

[0133] As the number of connections to the patient 118 increases, the leakage current 122 from all patient connections through the patient 118 to ground 120 increases, increasing the potential for interference and adverse effects. The total leakage current 122 when such devices are connected and operating simultaneously can be safely and tolerably up to tens of microamps at a fundamental power frequency of 50 or 60 Hz, but harmonics extend to thousands of Hertz. This leakage current 122 can substantially interfere with the processing of ECG and IC signals. Additionally, the patient 118 can be capacitively coupled 124 as well as inductively coupled 126 to the 120 / 240 AC power source 102. The patient 118 can also pick up RF interference 116 from devices in close proximity to the EP environment, such as wireless headsets, cell phones, and wireless monitors.

[0043]

[0134] For reference, Table 1 outlines signals, both desirable and undesirable, that may be found in a conventional medical device / EP environment and their signal characteristics.

[0044] [Table 1]

[0045]

[0135] As a result of equipment noise and other EP environmental interferences, measured voltages at the patient's body can be higher than 1-3 V RMS (root mean square) across a frequency spectrum ranging from 50 Hz to tens of megahertz. However, measured cardiac signal amplitudes can range from 25 microvolts to 5 mV. To display these signals in a noisy environment, cardiac signals are conventionally amplified and displayed without loss of detail (e.g., so as not to miss relevant information) and with minimal addition of noise (e.g., so as not to obscure signal details), while delivering, for example, RF ablation energy at about 70 V RMS at 500 kHz or cardiac stimulation at up to 25 mA.

[0046]

[0136] To adequately acquire and identify cardiac signals of interest in such an environment, a very high signal-to-noise (SNR) ratio (on the order of 30 dB) is desirable, but there are no methods to minimize or eliminate sources of electrical interference before they must be electrically processed by software methods. is not achievable. Traditional hardware techniques used to condition signals in such noisy environments include cable shielding, equipment grounding, input and output balancing, differential amplification, filtering, circuit impedance reduction, electrical isolation or signal enhancement techniques. These traditional methods have only been limited in their effectiveness in achieving a sufficient SNR.

[0047]

[0137] The disclosed hardware embodiments can apply novel electrical circuit topologies to minimize noise, isolate and condition the IC and ECG signals of interest, and reduce interference while removing undesirable artifacts. This can be done before the signals are passed to processing software that provides the electrophysiologist with near real-time visualization and comprehensive signal review capabilities. The EP system embodiments described herein can achieve substantial SNR improvements.

[0048]

[0138] 2 is a hardware system block diagram illustrating a disclosed EP hardware system 200 including, for example, an EP workstation 201 and an EP console 214, according to some embodiments. The system can include an EP console 214 with an optical interface 216 for EP measurement hardware from a user input, visualization and review workstation (herein, "EP workstation 201"). The EP workstation 201 can include, for example, a conventional lab PC 208 with a keyboard / mouse 210 and a monitor distributor 206 that facilitates multiple monitors 202 to provide multi-signal, multi-context display capabilities to the EP signal visualization and review software. The EP workstation 201 can also include an additional optical interface 212 for electrically isolated data transmission from the EP console 214, for example, via USB 2.0.

[0049]

[0139] The EP console 214 may include one or more ECG amplifiers 218, one or more unipolar amplifiers 220 to process monopolar signals, and a bipolar amplifier 222 to process bipolar signals from the ECG and EGM monitoring unit 224. The EP console 214 may also include a dedicated AC input filter 234, an AC / DC power supply 236, and a DC / DC power supply 238 that condition and convert mains 120 / 240V, 50 / 60Hz power supply power to DC power for use by the diagnostic equipment. The ECG and EGM electrode inputs 232 may enter the EP console 214 through a yoke 226 that provides additional input impedance for protection. Junction boxes (1 and 2) 228, 230 may provide a convenient plug-in interface for an IC catheter input (not shown) for subsequent processing by the EGM monitoring unit 224.

[0050]

[0140] FIG. 3 is a block diagram illustrating a multi-channel analog-to-digital input / output module 300 of an EP hardware system input stage, including an ECG board 302 and an IC board 316, according to some embodiments. The ECG board 302 and IC board 316 represent portions of the ECG amplifier 218, unipolar amplifier 220, and bipolar amplifier 222 of FIG. 2. The ECG board 302 and IC board 316 include multiple EP hardware system input stages 400, described below (see FIG. 4). FIG. 3 illustrates one 8-channel ECG board and one multi-channel IC board, according to an exemplary embodiment. Some embodiments have at least 16 channels. Other embodiments may include more or fewer channels.

[0051]

[0141] In Figure 3, analog inputs V1-V6 304 represent six separate ECG (precordial) electrodes that may be placed at various locations on the patient's chest. Analog inputs LL, RA, and LA 306 represent the limb leads for the left leg, right arm, and left arm, respectively. The output RL 308 represents the patient return line driving the right leg, as discussed later in this disclosure. The WCT 314 on the ECG board 302, also discussed later in this disclosure, is a Wilson coupling electrode, which also uses analog inputs LL, RA, and LA 306. The output of the WCT 314 can then be input to each channel of the EP hardware system input stage 400 corresponding to the analog inputs V1-V6 304. Each of the digital outputs V1-V6 310 represents a rectified and digitized version of the respective analog input V1-V6 304. In an exemplary embodiment, the digital outputs I, II 312 can include LA referenced to RA as Lead I, and LL referenced to RA as Lead II, in rectified and digitized form. The average of the three limb cords LL, RA, and LA 306 can then approximate the zero potential point and provide the reference level for the generation of RL 308.

[0052]

[0142] In FIG. 3, multiple analog inputs to IC board 316 represent possible connections and channels from the intracardiac catheter through EP hardware system input stage 400 (see FIG. 4). IC board 316 can accept IC signals that are either unipolar or bipolar. INDIF 318 represents an indifferent electrode that provides a reference for multiple unipolar indifferent leads. ICUniWCT1,2-N signal 320 represents a unipolar IC signal referenced to WCT. ICUniINDIF1,2-N signal 322 represents the active electrode for each IC unipolar signal. ICDiff1,2-N signal 324 represents multiple bipolar differential signals from the IC catheter. Multiple digital outputs represent conditioned and digitized versions of the analog inputs, specifically ICUniWCT1,2-N signal 326, ICUniINDIF1,2-N signal 328, and ICDiff1,2-N signal 330.

[0053]

[0143] 4 is a block diagram illustrating a single channel of an EP hardware system input stage 400 having input protection, signal filtering, detection, feedback and amplification circuitry, according to some embodiments. The circuitry is illustrated in the block diagram by numbered blocks 1-11, each representing a portion of the hardware functionality. This division and labeling of the blocks is for ease of explanation and is not intended to limit the scope of protection provided by the appended claims. The input protection and signal filtering section of the EP hardware system input stage 400 includes symmetrical positive and negative circuits that generate a differential version of each input signal for the differential signal amplifier stage 532, described below.

[0054]

[0144] Figure 5A is a block diagram 500 of an overall EP system disclosed herein, according to some embodiments, generally illustrating an interface from a main system unit (MSU) (hardware component) 504 to a main processing unit (MPU) (software component) 514. Figure 5A is discussed in more detail later in this disclosure.

[0055]

[0145] Figure 5B is a block diagram 524 representing the main sections of the EP hardware system input stage 400, and sections 530, 532, 534 are cross-referenced with the sections shown in the EP hardware system input stage 400.

[0056]

[0146] In Figure 5B, the analog input protection / filtering stage 530 includes block 1 - input protection 402a, block 2 - RF filter 404a, block 3 - buffer 406a, block 4 - DC block 408a, block 10 - low frequency feedback 420a, and block 11 - shield drive 422a. The symmetric negative circuit includes block 1 - input protection 402b, block 2 - RF filter 404b, block 3 - buffer 406b, block 4 - DC block 408b, block 10 - low frequency feedback 420b, and block 11 - shield drive 422b. The signal amplification stage 532 includes a differential circuit including block 5 - instrumentation amplifier / filter 410, block 6 - differential amplifier 1 / filter 412, block 7 - differential amplifier 2 / filter 414, and block 9 - large signal detection / high speed recovery 418. The A / D converter stage 534 includes block 8 - A / D converter 416. The A / D converter stage 534 also includes a communication module 510 (shown in Figure 5A) that can format the signal for transmission via the optical fiber link 512 to the digital processing stage 528, which is represented by the MPU 514 in some embodiments.

[0057]

[0147] The functionality of the predetermined blocks 1 to 11 in Figure 4, that is, for a single channel of the EP hardware system input stage 400, will be described in the following paragraphs.

[0058] Analog input protection / filtering stage

[0148] The analog input protection / filtering stage 530 of the EP system shown in Figure 5B includes block 1 - input protection 402a, 420b, block 2 - RF filters 404a, 404b, block 3 - buffers 406a, 406b, block 4 - DC blocks 408a, 408b, block 10 - low frequency feedback 420a, 420b, and block 11 - shield drive 422a, 422b. These elements according to some embodiments are described in more detail in the following paragraphs.

[0059] Input Protection Circuit

[0149] Figures 6A, 7, and 6B show circuits including an analog input protection / filtering stage 530 of the disclosed EP system, according to some embodiments. Figure 6A shows an overvoltage protection circuit 600 (represented by block 1 (402a, 402b) in Figure 4) that can protect other EP hardware system input stage 400 circuitry from large transient voltages, specifically, for example, from defibrillation pulses. The analog input protection / filtering stage 530 can protect against input voltages that are outside the range that the circuitry can actually handle.

[0060]

[0150] Specifically, analog input protection / filtering circuit 530 can reduce high voltage transients at ECG, IC and other electrode induced inputs connected to the patient's body, for example to less than 10 volts at the input to the EP system buffer. Analog input protection / filtering circuit 530 can suppress large signals, for example from a defibrillator, from damaging other parts of the system. Moreover, analog input protection / filtering circuit 530 can perform these functions without reducing the energy of the applied defibrillation pulse by more than, for example, 10%, and without clamping or adding nonlinearity in the case of an ablation signal being applied.

[0061]

[0151] FIG. 6A shows an exemplary embodiment of an overvoltage protection circuit 600 of block 1, including a commercially available gas discharge tube (GDT) 608 that can be triggered at very high voltages, such as over 300V, to provide high voltage surge protection. The GDT 608 is coupled to two stages of diodes 610, 612 (and resistors 602, 604) designed to sequentially clip the signal, for example, to 18V, to eliminate defibrillation signals of up to 5000V. Diode 610 represents a commercially available electrostatic discharge (ESD) voltage suppressor device that can assist the GDT 608 until it is fully on. Diode 612 represents a commercially available bidirectional ESD protection diode that can limit the In2 input of the RF filter (block 2) to 18V at the node labeled (a) in FIG. 6A and FIG. 7.

[0062]

[0152] Traditionally, defibrillation signals of approximately 5000V are clamped to ±5V to prevent damage. In the present disclosure, the defibrillation signal may be clamped in a similar manner, but an ablation signal having, for example, an ablation voltage of approximately 200V at 500kHz may be linearly passed through input resistors RCable, 602, 604 and block 2 (FIGS. 4, 4 04a, 404b), i.e., can be attenuated by RF filter 702.

[0063]

[0153] Figure 7 shows an RF filter / shield drive 700 including an RF filter 702 and a shield drive 730. The RF filter / shield drive 700 connects to the overvoltage protection circuit 600 of Figure 6A at a node labeled (a) for routing the signal In12 through the analog input protection / filtering stage 530. The RF filter 702 of the RF filter / shield drive 700 is described in more detail below. The shield drive 730 of the RF filter / shield drive 700 is also described below.

[0064]

[0154] The input overvoltage protection circuit 600 does not clamp the ablation signal, but rather the ablation signal is linearly attenuated (e.g., reduced in direct proportion by the input resistors RCable, 602, 604 and RF filter 702) so that it is not inadvertently altered. For example, if the ablation signal is clamped by the input overvoltage protection circuit 600, the content of that signal above the clamping cannot be accessed any more. Advantageously, the linear attenuation of the ablation signal by the disclosed EP system allows cardiac signals as small as a few millivolts to be recorded during ablation. Those skilled in the art will appreciate that the devices, systems, and methods disclosed herein apply equally well to other high frequency signals that need to pass through a protection circuit (e.g., are not clamped) to prevent the generation of nonlinearities that affect the signal of interest.

[0065]

[0155] Figure 6B depicts an ESD input protection circuit 620 in the final section of the analog input protection / filtering stage 530. The ESD input protection circuit 620 is coupled to an RF filter / shield drive 700 at a node labeled (b) in Figure 7. An ESD protection chip 622 can provide up to 30 kV of ESD protection for the data lines and can respond to overvoltage conditions in nanoseconds. Any number of commercially available ESD protection devices can be used for this purpose.

[0066]

[0156] Transient voltage suppressor (TVS) diodes 628, 630 can provide ESD protection of over 16 kV by shunting excessive current when induced voltages exceed their breakdown voltage. TVS diodes 628, 630 can function as "clamping" or limiting devices that suppress overvoltages that exceed their breakdown voltage, and can automatically reset once the overvoltage subsides. TVS diodes 622, 630 can also respond to overvoltages faster than other common overvoltage protection components, for example, "clamping" occurs in about 1 millisecond. TVS diodes can generally be advantageous for protecting against very fast, potentially damaging voltage transients.

[0067]

[0157] 8A-8E and 9A-9E show sample signal plots that demonstrate how a front-end input protection circuit handles high voltage transients and ESD, according to an exemplary embodiment. FIG. 8A shows the voltage of a representative defibrillator signal, V(Defib), applied to the input of the input protection circuit, labeled "EP Signal" in FIG. 6A. In a laboratory environment, the defibrillator signal can be derived by applying 5000 volts to a 32 μF capacitor and then discharging the capacitor into connected electrodes on the patient. Due to inductance and resistance, the amplitude received at the electrodes is approximately 4500 volts and lasts for tens of milliseconds.

[0068]

[0158] 8B-8E show different voltage levels as a defibrillation signal travels through the circuit. V(In) in FIG. 8B is the voltage at the GDT 608 in FIG. 6A. The GDT has very low capacitance (e.g., less than 1 pF) and high impedance (e.g., The GDT acts as a gap between the two electrodes. Once the GDT ionizes and turns on, it can have a very low resistance (e.g., a few ohms) due to its large current carrying capacity (e.g., carrying tens of amps) and therefore acts as a short circuit. The disadvantage of the GDT is that it can take some time to turn on, as the plot of V(In) in FIG. 8B shows. The GDT should trigger at 230V, but the voltage rises to a much higher level before it effectively turns on and starts conducting. The turn-on time can be hundreds of nanoseconds. Resistor RCable in FIG. 6A limits the current going to the GDT 608. This can reduce the power dissipated in the system and also ensure that the analog input protection / filtering stage 530 does not shunt significant power intended for the patient.

[0069]

[0159] The ESD voltage suppressor diodes 610 in Figure 6A turn on much faster, e.g., within nanoseconds, but can have a lower power / energy capacity so that they can become active quickly. They can hold up to about 30V at P1 while the GDT 608 is fully on, as shown in the signal plot of V(P1) in Figure 8C. Once the GDT 608 is fully on, the ESD voltage suppressor diodes 610 are no longer active.

[0070]

[0160] The next stage in Figure 6A is a bidirectional pair of ESD protection diodes 612 that can limit the signal at In12, the input to the RF filter (Block 2), to approximately 18V, as shown in the signal plot vs. V(In12) in Figure 8D. Signal passing through the RF filter is discussed further below in the RF Filter (Block 2) section.

[0071]

[0161] Finally, as shown in FIG. 6B, at In13, after the signal is filtered by the RF filter of block 1, the ESD protection chip 622 can clip the signal at VDD±diode drops (e.g., ±5.7 volts), as shown in the signal plot versus V(In13) in FIG. 8E.

[0072]

[0162] Those skilled in the art will appreciate that the combination of the input protection circuitry shown in Figures 6A and 6B, including the GDT 608, diode 610, diode 612, ESD protection chip 622, and TVS diodes 628, 630, protects the circuitry of the EP recording system. However, this circuitry alone may be detrimental to achieving high quality EP recording during ablation. For example, if the ablation signal is clipped, the induced nonlinearity may introduce noise and mask the cardiac signal of interest. Because medical teams may want to see the cardiac signal during ablation, integrating the Block 2 RF filter with the input protection circuitry is an improvement over conventional solutions. The disclosed embodiments allow for linear filtering of the ablation signal and attenuation of undesired disruptive or potentially damaging signals while monitoring the ECG and IC signals.

[0073]

[0163] 9A-9E are signal plots showing the propagation of an ablation signal through the input protection circuit of FIGS. 6A, 7 and 6B. The ablation input is 400 Vpp at the sensor electrode, as shown by plot V(Defib) in FIG. 9A. As the signal progresses through the stages of the input protection circuit, it is attenuated by resistor RCable (shown as plot V(In) in FIG. 9B), by resistor 602 (shown as plot V(P1) in FIG. 9C), by resistor 604 (shown as plot V(In12) in FIG. 9D), and by capacitor 716 (shown as plot V(In13) in FIG. 9E). The ablation signal voltage level is 100 Vpp at node In in FIG. 6A. 6A and 12 Vpp at node In12 and, after the RF filter in FIG. 7, 60 mV at node In13. The ablation signal does not trigger a protection device but is linearly attenuated, allowing observation and / or recording of the cardiac signal during ablation. The ablation signal can be further filtered in each of blocks 5, 6 and 7 of the signal amplification stage 532 (see FIGS. 4, 5B and 10) and in the A / D converter (block 8 in FIG. 4) with a 100 dB low pass filter at 950 Hz.

[0074] RF filter circuitry including low frequency feedback and shield drive

[0164] In addition to contributing to the input protection circuitry that filters and linearly attenuates the ablation signal at the EP system input, the RF filter 702, in conjunction with the low frequency feedback of block 10 (see FIG. 4, 420a and 420b, and FIG. 16, 1600), can enable the entire circuit to, for example, pass small cardiac signals (e.g., having a frequency range of about 0.01 Hz to about 500 Hz) while continuing to linearly attenuate the ablation signal (e.g., having a voltage amplitude of about 200 V in a frequency range of about 300 kHz to about 600 kHz) in near real time during cardiac monitoring.

[0075]

[0165] The RF filter 702 can be designed to linearly attenuate the amplitude of the ablation signal, for example, by at least 75% in some embodiments, or even at least 90% in other embodiments. The RF filter 702 can be designed to provide substantially no attenuation to input signals having frequencies below 5 kHz, for example. This RF filter 702 can also work in conjunction with the shield drive 730 of block 11 (see FIG. 4, 422a and 422b and FIG. 7), which can work with the input capacitors 706, 714, 716 of the RF filter 702 to help maintain a high input impedance of the entire circuit. This high input impedance can help minimize input loss of the target cardiac signal. The shield drive 730 is discussed further below.

[0076] Low Frequency Feedback Circuit

[0166] Block 10 (see FIG. 4, 420a and 420b), i.e., low frequency feedback circuit 1600, can provide positive feedback to the block 2 RF filter (see FIG. 4, 404a and 404b and FIG. 7, 702) to increase the input impedance to the EP system and therefore reduce signal attenuation. This is advantageous because the input impedance of the EP system in the frequency range of cardiac signals can be compromised by the RF filter 702.

[0077]

[0167] Specifically, the high input impedance of instrumentation amplifier 1001 of Figure 10 can be significantly reduced depending on the frequency of the input signal (e.g., by a factor of 100 at 60 Hz) by the presence of RLC network elements 706, 708, 714, 716 of RF filter 702. While RF filter 702 is advantageous at ablation frequencies, the reduced impedance at lower frequencies can reduce the amplitude of cardiac signals and affect common mode rejection. Without mitigating the effect of RF filter 702, the benefits of instrumentation amplifier 1001 are lost.

[0078]

[0168] To mitigate that loss and maintain high common mode rejection (e.g., on the order of 100 dB), it is desirable to maintain a high impedance at power line frequencies so that variations in source impedance do not convert the common mode signal to a differential signal. The block 10 low frequency feedback circuit 1600 shown in FIG. 16 receives a buffered version of the signal of interest from block 3 buffers 406a, 406b as Buf1 1602. The low frequency feedback circuit 1600 then applies an operational amplifier 1606 to the bases of the capacitors 706, 714, 716 of the RF filter 702 (i.e., the lower preamplifier). 1728 at its input (output). Specifically, the operational amplifier 1606 acts as a driver circuit that eliminates loading effects and maintains a high input impedance of the analog input protection / filtering stage 530 to the signal amplification stage 532.

[0079]

[0169] When the block 10 low frequency feedback circuit 1600 drives the RF filter 702 at low frequencies, there is little or no voltage variation across the capacitors 714, 716. Thus, at low frequencies, the capacitors 706, 714, 716 act as open circuits and a high input impedance is maintained. However, at higher frequencies, the feedback from the block 10 low frequency feedback circuit 1600 is reduced due to the low pass filtering functionality of block 10.

[0080]

[0170] Specifically, the combination of capacitor 1666 and resistor 1693 at the inverting input to operational amplifier 1606 filters high frequencies. The output of this circuit does not track the input, keeping Shield1 728 (which is also the reference node of RF filter 702) at a constant level with respect to high frequency signals. This allows the passive RLC networks 706, 708, 710, 712, 714, 716 of RF filter 702 to attenuate high frequency signals.

[0081]

[0171] Specifically, the block 10 low frequency feedback circuit 1600 (see also FIG. 4, 420a and 420b) takes the buffered signal from the block 3 buffer circuit (see FIG. 4, 406a and 406b) and generates a correction signal at Shield1 728 in FIG. 7, i.e., an equivalent signal of the input as a feedback signal at capacitors 706, 714, 716 of the block 2 (see FIG. 4, 404a and 404b) RF filter 702. This feedback to capacitors 706, 714, 716 is provided as a dynamic current source for the circuit.

[0082]

[0172] The RF filter 702 in block 2 404a, 404b is effective at filtering at high frequencies, but is ineffective at low frequencies when it receives feedback from the low frequency feedback circuit 1600 in block 10 420a, 420b. At high frequencies, the capacitors 706, 714, 716 in the RF filter 702 act as shunt capacitors that effectively short out the signal at RF frequencies. The impedance of the capacitors 706, 714, 716 decreases linearly with increasing frequency. The low frequency feedback circuit 1600 has no effect on the EP system at high frequencies.

[0083]

[0173] At low frequencies, the low frequency feedback correction signal, i.e., Shield1 728 from block 10 (see FIG. 16) to block 11 (Shield Drive 730 in FIG. 7), drives the bottom plates of capacitors 706, 714, 716 so that they mimic the input signal. This controls the reference node of RF filter 702. Specifically, the voltages at the plates of capacitors 706, 714, 716 vary in sync with each other, and low frequency feedback circuit 1600 drives the bottom plates of capacitors 706, 714, 716 of RF filter 702 to be at the same voltage as the top plates, so that the voltage difference between the plates of capacitors 706, 714, 716 is zero and capacitors 706, 714, 716 act as open circuits.

[0084]

[0174] The purpose of the low frequency feedback is to make the difference between Shield1 728 and Buf1 1602 zero, so that Shield1 728 is equal to Buf1 1602. When this occurs, the input capacitance can be eliminated. At high frequencies, the positive feedback from the operational amplifier 1606 reduces to zero. Furthermore, at high frequencies, the capacitor 722 (which may be, for example, 30 times larger than the other capacitors in the circuit) acts as a short between Shield1 728 and ground. This reduces the RF filter 702 The reference node of is effectively grounded and the RF filter 702 completely attenuates the RF frequencies. Thus, the block 10 low frequency feedback circuit 1600 works in conjunction with the unique configuration of elements in the block 2 RF filter 702 to remove the loading effects of the RF filter 702 before passing the signal to the block 5 instrumentation amplifier 1001.

[0085]

[0175] In this way, the instrumentation amplifier 1001 can condition the cardiac signal without the ablation signal overlapping it. As a result, the input to the entire circuit at low frequencies still has a very high input impedance (e.g., on the order of tens of megohms) that is advantageous for visualizing high fidelity cardiac signals in an EP environment. Furthermore, block 10 is a symmetrical (e.g., mirror image) circuit, so common mode noise is reduced as the signal propagates through the circuit. Another advantage of the low frequency feedback circuit 1600 is that its output Shield1 728 can be used to drive the outer shield of an input cable, for example, at OutS1 of the shield drive 730 in FIG. 7.

[0086] Shield Drive Circuit

[0176] Block 11 (see FIG. 4, 422a and 422b), specifically the shield drive 730 shown in FIG. 7, receives the output (Shield1 728 in FIG. 16) of the low frequency feedback circuit 1600 of block 10 (see FIG. 4, 420a and 420b) and provides positive feedback to the cable shield at OutS1, thus reducing the effective input capacitance of the input cable. Thus, the path from the bottom plate of the input capacitor 714, 716 in the RF filter 702 of block 2 (see FIG. 4, 404a and 404b) to the shield of the input cable further contributes to making the input impedance as large as possible. This high input impedance minimizes input losses of the subject's cardiac signal. In some embodiments, the shield drive connection is grounded when shield drive is not desired.

[0087] Signal Buffering and DC Blocking Circuits

[0177] Block 3 (FIG. 4, 406a and 406b) is a low noise unity gain driver that helps minimize input losses for the cardiac signal. Specifically, block 3 can provide a high input impedance that minimizes the loading of the input stage on the cardiac signal and drives the signal amplification stage 532. In block 3, two operational amplifiers (circuitry not shown) form two buffers that act as unity gain followers, buffering the input and presenting a high input impedance to the input.

[0088]

[0178] Block 4, the DC block (FIG. 4, 408a, 408b), is a high pass module (circuit not shown) that prevents input offsets from the sensor / tissue interface in the patient's body from entering the amplifier gain stage. In block 4, two DC blocking capacitors (not shown) ensure that the input is not affected by large offsets from the catheter.

[0089] Heart Amplification Stage

[0179] The signal amplification stage 532 of the EP system (see FIG. 5B) includes differential circuits: block 5—instrumentation amplifier / filter 410, block 6—differential amplifier 1 / filter 412, block 7—differential amplifier 2 / filter 414, and block 9—large signal detection / fast recovery circuit 418. These circuits are described in more detail in the following paragraphs.

[0090] Instrumentation amplifier / filter circuit

[0180] Block 5 (see FIG. 4, 410) provides amplification for the differential signal and suppression of unwanted signals from the instrument laboratory or medical environment, specifically power line noise and associated harmonics. Block 5, detailed in FIG. 10, has a gain stage 1001 with a differential gain of about 20 at its output and provides further filtering of RF attenuation through its RC networks 1008, 1010, 1012, 1014. For example, two operational amplifiers 1006, 1016 are low noise devices designed to receive the cardiac signal at the input to the instrumentation amplifier 1001 before it is amplified. The differential signal from block 5 instrumentation amplifier 1001 then goes into a precision resistor block 1018 of block 6 differential amplifier 1 1017.

[0091] Differential amplifier / filter circuit

[0181] Block 6 (see FIG. 4, 412) has a differential amplifier 1020 that produces a fully differential output that is unity gain, referenced to the common mode voltage. Block 6 Differential Amplifier 1 1017 can provide further filtering for RF attenuation. Maintaining a fully differential signal path helps reduce noise from the digital portion of the system. Such noise appears primarily as common mode noise and is rejected. This portion of the signal amplifier stage 532 also shifts the DC bias of the cardiac signal from 0 to 2.5V and limits its output to 0-5V.

[0092]

[0182] At the output of block 6 with a first fully differential amplifier 1020 referenced to common mode, the common mode level is set to 2.5V as the signal enters block 7 differential amplifier 2 1021. This circuit continues low pass filtering of the ablation signal to the outputs of block 7 (B2OutP, B2OutN). Block 7 with a second fully differential amplifier 1034 similar to differential amplifier 1020 of block 6 has a gain of about 0.5, and further filtering for RF attenuation is provided by circuit elements 1022, 1024, 1026, 1028, 1030, 1032, 1036, 1038, 1040, 1042. This portion of the signal amplification stage 532 maintains a fully differential signal path to continue noise rejection.

[0093]

[0183] The gain introduced by block 7 allows the circuit to clip the signal to the input limits of the A / D converter, i.e., block 8 (see FIG. 4, 416), which may be, for example, a delta-sigma converter (not shown). As described above, block 6 differential amplifier 1 1017 clips each output signal to ±2.5 volts for a bias level of 2.5 volts. With a gain of 0.5, the output of block 7 differential amplifier 2 1021 produces a signal biased at 2.5 volts, or a peak-to-peak differential voltage of 2.5 volts, in a range of ±1.25 volts for each output. This represents the limits of, for example, a 24-bit A / D converter 416 in some embodiments. By clipping and matching the output limits, the input of the A / D converter 416 is prevented from being overdriven. It is advantageous that this embodiment allows but does not exceed the full range of the input to the A / D converter, since delta-sigma converters can behave erratically when overdriven, which can result in spurious results.

[0094]

[0184] The overall gain of the signal amplification stage 532 of the disclosed EP system can be, for example, 20 or less in some embodiments, or 50 or less in other embodiments. For example, in some embodiments, a gain of about 20 at the output of instrumentation amplifier 1001, unity gain at the output of differential amplifier 1 1017, and a gain of about 0.5 at the output of differential amplifier 2 1021 produces a system gain of about 10 at the input of the A / D converter 416. In general, signal amplification stage 532 can include instrumentation amplifier 1001 with a gain greater than 1 at its output, differential amplifier 1 1017 with a gain of about 1 at its output, and differential amplifier 2 1021 with a gain less than 1 at its output.

[0095]

[0185] Improved system noise rejection capability resulting in overall system performance improvement. The gain provides further improvement over conventional systems. In conventional systems with 16-bit A / D converters, high gain is required to visualize small signals that become obscured in the presence of higher amplitude signals. Conventional systems may have a gain of, for example, up to 5000, where signal saturation occurs quickly. Furthermore, if a lower gain is used with a 16-bit converter, quantization noise may adversely affect the output result. The disclosed system with a low gain of about 10 coupled to a 24-bit A / D converter prevents saturation and avoids quantization noise, for example down to small signal inputs of at least 250 mV.

[0096] Large signal detection / fast recovery circuit

[0186] In addition to being passed to block 7 differential amplifier 2 1021, the output from block 6 differential amplifier 1 1017 is also passed to block 9 (see Figures 4, 418 and 10), i.e., large signal detection / fast recovery circuit 1100 of Figure 11. Large signal detection / fast recovery circuit 1100 is able to reject large signals and recover quickly from large transient events. Thus, this circuit is referred to as a "fast recovery" circuit because of its improved ability to recover from saturation much faster than previously achieved.

[0097]

[0187] Specifically, the large signal detection / fast recovery circuit 1100 can detect when the differential input signal exceeds, for example, 100 mV for a duration of at least 10 ms, which is identified as an abnormal operating range. When this condition is detected, the large signal detection / fast recovery circuit 1100 can decrease the time constant after the block 4 DC blocking stage (see FIG. 4, 408a and 408b) to ensure that the cardiac signal does not remain saturated. However, the large signal detection / fast recovery circuit 1100 may have only a negligible effect under normal operation. For example, the large signal detection / fast recovery circuit 1100 cannot have any effect on fast transient events caused by pacing, which may be signals of interest to be monitored and recorded in an EP environment, and which may generally have transient events lasting less than 10 ms.

[0098]

[0188] In one embodiment, the first stage of the large signal detection / fast recovery circuit 1100 includes, for example, two operational amplifiers 1108, 1112. The gain of the operational amplifier 1108 (e.g., about 40) determines the activation threshold, i.e., the signal amplitude at which the large signal detection / fast recovery circuit 1100 can act to limit (or "soft clamp") the signal. This activation threshold determines how large the signal must be before the large signal detection / fast recovery circuit 1100 becomes active and begins pulling the voltages at nodes In14 and In24 towards the common mode level. For example, an operational amplifier 1108 with a gain of about 80 may activate the large signal detection / fast recovery circuit 1100 at about 50 mV, an operational amplifier 1108 with a gain of about 40 may activate the large signal detection / fast recovery circuit 1100 at about 100 mV, and an operational amplifier 1108 with a gain of about 20 may activate the large signal detection / fast recovery circuit 1100 at about 200 mV. When the signal amplitude reaches a set amplitude level determined by the gain, the voltage will be sufficient to exceed the activation threshold of the first pair of diode stages 1114, 1116 to activate the large signal detection / fast recovery circuit 1100.

[0099]

[0189] The operational amplifier 1112 creates unity gain to buffer the common mode (CM) signal, which provides a common mode reference for the signal through the operational amplifier 1108. The operational amplifier 1108 receives the U4Out1 and U4Out2 signals from block 6 (see FIG. 10). The average of the U4Out1 and U4Out2 signals is therefore referenced to the common mode node (CMB in FIG. 11). The signal output from the operational amplifier 1108 passes through a first pair of diode stages 1114, 1116 which limit the charging of the following capacitors 1120, 1124, 1128, 1132. The buffering These capacitors 1120, 1124, 1128, 1132, which store charge from the inverted U4Out1 and U4Out2 signals, generate a maximum positive (+) and maximum negative (-) charge for both the inverted and non-inverted versions of the signals U4Out1 and U4Out2.

[0100]

[0190] Capacitors 1120, 1124, 1128, 1132 along with resistors 1118, 1122, 1126, 1130 form an RC network at nodes C, D, E, and F, which together act as a timing network that determines a time constant. The time constant determines how long the signals can be at their maximum amplitude before the large signal detection / fast recovery circuit 1100 pulls the voltage at nodes In14 and In24 toward CM. This RC network is hereafter referred to as a "timing bank" 1158. Some embodiments of the timing bank 1158 can be designed to produce a time constant of at least 10 ms, for example, to prevent activation of the large signal detection / fast recovery circuit 1100 during pacing signals of duration between 2 ms and 10 ms. Other embodiments can be designed to produce a time constant of at least 5 ms.

[0101]

[0191] When the capacitors 1120, 1124, 1128, 1132 charge, the difference is detected and the signal passes through a second pair of diode stages 1146, 1148 which limits (or "soft clamps") the input to, for example, between about ±100 mV. This prevents the system from saturating for any significant amount of time (e.g., less than 100 ms). The second pair of diode stages 1146, 1148 also ensures that there is no interaction between the large signal detection / fast recovery circuit 1100 and the EP system when the signal is not large / long enough to require limiting. In other words, when the large signal detection / fast recovery circuit 1100 is not beneficial, the second pair of diode stages 1146, 1148 disconnects the large signal detection / fast recovery circuit 1100. The Block 9 Large Signal Detect / Fast Recovery Circuit 1100 ensures that the EP system is not affected by large signal spikes and allows a steady-state response when, for example, the operational amplifier 1108 has a gain of about 40 and the difference between the inverted U4Out1 and non-inverted U4Out2 signals is, for example, about 100 mV.

[0102]

[0192] Block 9 Large Signal Detect / Fast Recovery Circuit 1100 is placed in the EP system at a location where it removes large signal voltage offsets. Those skilled in the art will appreciate that the Large Signal Detect / Fast Recovery Circuit 1100 can be placed in other locations in the EP system where possible large signal spikes may occur and are undesirable. Those skilled in the art will also appreciate that electronic components such as capacitors 1120, 1124, 1128, 1132 and resistors 1118, 1122, 1126, 1130 of timing bank 1158 can be replaced in the Large Signal Detect / Fast Recovery Circuit 1100 to change circuit activation levels and times. The Large Signal Detect / Fast Recovery Circuit 1100 can be used in various embodiments of other signal acquisition and processing systems to remove large signal voltage offsets from other types of electrical signals, as will be appreciated by those skilled in the art.

[0103]

[0193] In some embodiments, the outputs In14, In24 of the block 9 large signal detection / fast recovery circuit 1100 (see FIG. 4, 418) are fed back to block 4, i.e., the DC block (FIG. 4, 408a and 408b). A DC blocking capacitor (not shown) in block 4 again adds additional bias (e.g., correction bias) to the input signal. Thus, the signal from the block 9 large signal detection / fast recovery circuit 1100 is not fed back to the block 4 DC block unless the signal provided to block 9 is large (e.g., has an amplitude on the order of 100 mV or more). In other words, the output signal of block 9 does not enter block 4 unless a large signal event occurs. Nodes In14 and In24 is normally disconnected.

[0104]

[0194] An exemplary embodiment of the large signal detection / fast recovery circuit 1100 of FIG. 11 will now be described in detail with respect to the signal plots of FIG. 12, FIG. 13A-13C, FIG. 14A-14D, and FIG. 15A-15B. A sample signal is applied to the input of the EP system and is described at various points throughout the circuit. In this example, the signal used to demonstrate the large signal detection / fast recovery circuit 1100 is generated by applying a 20 mVpp signal at node In12 of FIG. 6A and FIG. 7 and applying a zero input at node In22 (symmetric negative node, not shown), specifically the input of the RF filter 702. At time 10 msec, a 200 mV step is added to the signal at node In12. This becomes a 200 mV differential signal as it traverses the EP system, which may cause the signal to be outside the display range of most conventional monitoring devices. Such a 200 mV signal should generally be removed so that the signal can be viewed in the EP environment.

[0105]

[0195] 12 shows what happens to such an input signal if the Large Signal Detect / Fast Recovery Circuit 1100 is not connected. After a sample input 20 mVpp signal with an unwanted 200 mV step-up passes through the Analog Input Protection / Filtering Stage 530, the Instrumentation Amplifier 1001, and the Differential Amplifier 1 1017 to the Large Signal Detect / Fast Recovery Circuit 1100, the EP hardware system will not be able to recover quickly from the 200 mV step signal if the Large Signal Detect / Fast Recovery Circuit 1100 is not connected. Such a slow recovery complicates identification of the cardiac signal.

[0106]

[0196] Resistors 1002 and 1004 in front of the instrumentation amplifier 1001 in FIG. 10 eventually pull the offset signal back to ground, but the product of the DC blocking capacitor (not shown) in block 4 and resistor 1002 creates a time constant of about 2.7 seconds. This introduced delay is too long to recover off-screen or saturated signals. FIG. 12 shows that the signal at input node In14 moves very slightly downward in about 100 msec and only a few millivolts in about 400 msec (not shown). Without the large signal detection / fast recovery circuit 1100, such large transient signals can adversely affect the operation of the EP system because the large transient events push the monitored signal into saturation, causing the signal's waveform details to be lost.

[0107]

[0197] 13A-13C show the same 200 mV large transient signal with Large Signal Detect / Fast Recovery Circuit 1100 connected. In this example, as shown in FIGS. 13A and 13B, both input nodes of Large Signal Detect / Fast Recovery Circuit 1100, namely In14 and In24 (shown in FIG. 11), are pulled (biased) toward a common mode signal V(CMB) (see FIG. 13C) that is approximately 100 mV in amplitude. In14, the positive input node of Large Signal Detect / Fast Recovery Circuit 1100, is pulled down and In24, the negative input node of Large Signal Detect / Fast Recovery Circuit 1100, is pulled up. V(CMB) is the average of the voltages at nodes In14 and In22 (the symmetrical negative input to the entire circuit). The desired bias levels are applied directly to the differential amplifiers in blocks 6 and 7 (1020 and 1034, respectively), thereby setting the common mode voltages at those differential amplifiers 1020, 1034, so that the actual common mode levels at nodes In14 and In24 have no effect.

[0108]

[0198] The plots of Figures 13A and 13B show that the voltages at nodes In14 and In24 are pulled into the monitoring range after about 50 milliseconds. Thus, the limiting or "soft clamping" is performed gradually to avoid discontinuities in signal collection and visualization. Other embodiments may allow for gradual "clamping" of about 100 milliseconds. Cut.

[0109]

[0199] Figures 14A-14D demonstrate how large transient signals are conditioned as they traverse various internal nodes of large signal detection / fast recovery circuit 1100. Signal plot V(A) of Figure 14A and signal plot (B) of Figure 14B represent the output of operational amplifier 1108 of large signal detection / fast recovery circuit 1100 in Figure 11. In this example, operational amplifier 1108 has a gain of approximately 40 relative to its input and produces a differential signal of (40 x 200 mV =) 8 volts across nodes A and B in Figure 11.

[0110]

[0200] As shown in plot V(C) of FIG. 14C, the negative signal following node B of FIG. 11 pulls down the voltage at node C of FIG. 11. Here, the signal has been filtered to remove the in-band signal occurring at node B, leaving the low frequency control voltage at node C. The negative voltage at node C is connected to In14 through resistor 1140, diode 1150, and resistor 1144. This creates a current that pulls In14 down toward the common mode voltage as shown in FIG. 13A. Similarly, node A pulls In24 up toward the common mode voltage through nodes E and J of FIG. 11, as shown in plot V(E) of FIG. 14D.

[0111]

[0201] The diodes in the large signal detect / fast recovery circuit 1100 of Figure 11 control the direction of the current. The first pair of diode stages 1114, 1116 (limiting diodes) allow different time constants for charging and discharging nodes C, D, E and F. They also provide a non-operating range where nodes C, D, E and F do not charge if outputs A and B are less than a diode forward voltage drop. The "clamping" diodes 1150, 1152, 1154, 1156 of the second pair of diode stages 1146, 1148 ensure that input nodes In14 and In24 are pulled in the correct direction.

[0112]

[0202] 15A and 15B show signal plots of the current through resistors 1144, 1142 at outputs In14 and In24, respectively, of the large signal detection / fast recovery circuit 1100 of FIG. 11. During normal operation, the current is zero and the instrumentation amplifier / filter 410 circuit is unaffected. If the differential level is too high (i.e., if a large signal of more than 100 mV is detected for several milliseconds, for example), the current in those two resistors 1144, 1142 serves to pull the signal back towards the common mode voltage V(CMB).

[0113] A / D Converter

[0203] The A / D converter 416, block 8 (see FIG. 4), is a fully differential A / D converter designed to accept differential signals from the rest of the circuit. In some embodiments, each of the EP system circuit modules is replicated eight times to feed as differential pairs into eight separate channels of the A / D converter 416. For example, a TI ADS1278 24-bit, 8-channel delta-sigma converter can be used. One skilled in the art may select other A / D converters with similar specifications.

[0114]

[0204] In some embodiments, the A / D converter 416 is highly linear, characterizing it as a delta-sigma converter. The high degree of linearity allows precise digital signal processing to be implemented in software, as described below. This configuration minimizes hardware filtering in favor of RF attenuation and anti-aliasing, allowing more flexibility in filtering and signal processing in software. An advantage of selecting a fully differential A / D converter is that common mode noise signals from any digital circuitry (e.g., digital clock signals) are rejected.

[0115] Wilson Coupled Electrode-Right Leg Drive (WCT-RLD) Circuit

[0205] The input common mode signal can be any frequency, but the predominant signal is generally the power line frequency, e.g., 60 Hz in the United States. In a conventional EP environment, ECG (and similar) equipment attenuates a large amount of 60 Hz noise that can be up to 100 times louder than the signal of interest. Additionally, due to distortion in the power line signal, there is often a strong third harmonic at 180 Hz, which is generally the most noisy masking harmonic. Higher harmonics and other common mode signals are generally smaller and / or above the frequency band of interest for ECG and IC signals.

[0116]

[0206] In some embodiments, a Wilson Coupled Electrode-Right Leg Drive (WCT-RLD) circuit is used to eliminate noise, particularly at 60 Hz and 180 Hz, through common mode rejection, i.e., by enhancing the first and third harmonic frequencies of the power line signal and selectively feeding those signals back to the patient to cancel them. Figure 23 shows a schematic diagram of an improved WCT-RLD circuit, according to some embodiments.

[0117]

[0207] For example, the WCT circuit 2332 of FIG. 23 provides a virtual ground by summing and averaging two or three limb electrodes (e.g., right arm 2304 and left arm 2306, or right arm 2304, left arm 2306 and left leg 2308) connected to a combined electrode (center electrode) 2336 through two or three large resistors 2334 (e.g., 20 kilohms in each electrode). Those skilled in the art will appreciate that an average of the right arm (RA) 2304, left arm (LA) 2306 and left leg 2308 provides a more accurate estimate of the common mode signal in the patient 2302 than an average of the right arm (RA) 2304 and left arm (LA) 2306. As will be appreciated by those skilled in the art, the RA and LA signals are alternatively buffered (see buffer 2312) versions of the RL positive (RLP) signal 2338 and RL negative (RLN) signal 2340. WCTs are conventionally designed to reduce the overall 60 Hz common-mode noise signal by forcing these limb-induced net potential differences closer to zero.

[0118]

[0208] By applying active current to the WCT circuit 2332 via the right leg, or "right leg drive" (RLD) circuit 2330, the patient 2302 can be driven to the same voltage as the common amplifier, thus reducing the common mode voltage at the inputs of the ECG electrodes (LA, RA, LL and V1-V6). This can be done by generating an inversion of the common mode signal and applying it as an output to the right leg. Specifically, the right leg drive is represented by the limb electrode RL. Through the RL electrode, the patient 2302 receives the RLD output 2310, i.e., a summed and inverted version of other IC catheter signals or ECG electrode signals, which cancels out interference present in the patient's body. This, in combination with the common mode rejection properties of the signal amplification stage 532, can reduce common mode low frequency interference to an acceptable level (e.g., as specified by standard IEC 60601-2-25).

[0119]

[0209] However, common mode rejection alone cannot reject all of the noise because 60Hz and 180Hz noises are not equal in all parts of the body. The WCT-RLD circuit 2300 of FIG. 23 provides a reference signal approximately equal to the power line frequency coming into the system, which further reduces the overall common mode signal. Thus, the combination of the disclosed WCT-RLD circuit 2300 and conventional common mode rejection advantageously improves the reduction of the common mode signal.

[0120]

[0210] In an exemplary embodiment using WCT, the WCT input in the EP system can provide an optional unipolar input to the Block 3 buffer circuit (see FIG. 4, 406a and 406b) to replace the bipolar positive (+) or negative (-) catheter input. Specifically, the WCT-RLD circuit 2300 includes a right arm 2304, a left arm 2306 and a left leg 2308. The electrode signals are averaged. The result is buffered by an operational amplifier 2314 and the output WCTBuf 2316 is sent as a unipolar feedback signal whenever desired in an EP system, specifically used in an embodiment whenever a patient is connected. The WCT-RLD disclosed herein enhances traditional unipolar WCT solutions with a novel approach to generating the RLD signal.

[0121]

[0211] In some embodiments, a novel approach in the WCT-RLD circuit 2300 is to provide an additional filter circuit, called the "Twin-T" feedback network 2440 (see Figures 23 and 24), which can generate a stronger RLD at the 60Hz power line frequency or the third harmonic frequency of 180Hz. This is particularly useful during ablation. The Twin-T feedback network 2440 resonates at both 60Hz and 180Hz, but advantageously prevents phase oscillations by reducing feedback at other frequencies.

[0122]

[0212] FIG. 24 shows a schematic diagram of a Twin-T feedback network 2440 interfacing with the RLD circuit 2330 of the WCT-RLD circuit 2300 according to some embodiments. The Twin-T feedback network 2440 of FIG. 24 acts as an improved notch filter. Resistors 2406, 2407, 2408, 2409, 2410, 2411 and capacitors 2401, 2402, 2403, 2404 form a single Twin-T network that generates a notch at 60 Hz. The next stage, i.e. resistors 2412, 2413, 2414, 2417, 2418, 2419 and capacitors 2415, 2416, 2420, 2421, similarly generates a notch at 180 Hz. However, when the network is in the operational amplifier feedback path, the inverse function is obtained.

[0123]

[0213] For example, as shown in plot 2500 of FIG. 25, the RLD output of the Twin-T feedback network 2440 in the operational amplifier 2425 produces two peaks, a peak 2510 at 60 Hz and a peak 2520 at 180 Hz. At higher frequencies, such as 10 kHz and above, the phase change approaches zero. This prevents phase changes in the RLD circuit 2330 at these higher frequencies that could result in oscillations. The minimal phase change at these higher frequencies can prevent oscillations near the ablation frequency, which is otherwise more difficult to filter out.

[0124]

[0214] Twin-T circuits are used in electronic designs, but not previously in WCT-RLD circuits as disclosed herein. The Twin-T feedback network 2440 removes the power line signal that is traditionally passed by known circuits when generating RLD signals so that the power line signal does not affect the phase response at higher frequencies. Thus, the Twin-T feedback network 2440 has advantageous applications for generating RLD signals from electrode leads.

[0125]

[0215] In the embodiment of FIG. 23, the RLD circuit 2330 tracks the power line by providing the RLD output 2310 back to the patient 2302 as a separate signal. In this circuit, the differential input signals of right leg positive (+) (RLP) 2338 and right leg negative (-) (RLN) 2340, which may alternatively be the RA and LA signals, are buffered 2312. A Twin-T feedback network 2440 then boosts / amplifies the buffered right leg signal at 60 Hz and 180 Hz, which is inverted and buffered again by the RLD circuit 2330. This RLD circuit 2330 includes an operational amplifier 2328, resistors 2320, 2324, 2326 and capacitors 2318, 2322. After passing through the RLD circuit 2330, the signal is output as an RLD in the patient's right leg surface lead. This is output as output 2310 (RLDrv). The effect of this is that the entire circuit tracks the power line and the common mode of the circuit filters out power line noise. Additionally, the Right Leg Drive circuit protects against any signals greater than approximately 1 microamp from returning to the patient.

[0126]

[0216] In some embodiments, the first derivative of both unipolar signals can be used to tell the physician whether the signal of interest is coming from the distal or proximal electrode. The bipolar signal can be displayed in a color-coded format to identify which component of the bipolar signal is coming from the anode versus the cathode. The physician can then move to the proximal electrode if the predominant signal of interest is coming from that electrode. The system can also be automated with a robotic system providing the movement as part of a closed feedback loop.

[0127] Examples

[0217] The following examples show how the disclosed hardware circuitry conditions signals found in the EP environment to enable improved cardiac monitoring among equipment and environmental noise, and during procedures that introduce potentially significant interfering signals into the monitoring environment.

[0128] Signal Example 1 - Common mode 60Hz and in-band 500Hz differential signal

[0218] Signal Case 1 presents a typical common mode 60 Hz noise signal with an in-band (<1000 Hz) differential signal such as that found from conventional IC induction. In this example, an example signal plot is shown that represents the signals at example nodes of the disclosed circuit. The circuit amplifies the differential signal and rejects the common mode signal.

[0129]

[0219] 17A and 17B show input signals of 2Vpp 60Hz sine (power line) signals applied to input nodes In12 (see FIG. 6A) and In22 (negative, lower branch of the circuit, not shown), respectively. At In12, a 0.2Vpp, 500Hz sine wave signal is superimposed (see plot V(In12) in FIG. 17A), and at In22, a -0.2V, 500Hz sine wave signal is superimposed (see plot V(In22) in FIG. 17B). This results in a 2Vpp, 60Hz common mode signal and a 0.4V, 500Hz differential signal. These signals may be too low in frequency to be affected by the RF filter 702 in block 2, so the same signals appear at the output of block 3 (buffers 406a, 406b) and after block 4 (DC blocks 408a, 408b).

[0130]

[0220] 17C and 17D also show shield input signals (Shield1, Shield2) that are the same as the corresponding input signals shown in FIGS. 17A and 17B. These signals are fed back from block 10 (low frequency feedback circuit 1600) to RF filter 702 to unload RF filter 702 (Shield1 in FIG. 7). (See 728; Shield2, the negative lower branch of the circuit, not shown.) The voltage changes across capacitors 714, 716, 706 in the upper branch of RF filter 702 in FIG. 7, along with the corresponding capacitors in the symmetrical lower branch of the RF filter (not shown), are close to zero, effectively removing them from the circuit at low frequencies.

[0131]

[0221] 18A and 18B show Out1 and Out2, the outputs of block 5 (instrumentation amplifier 1001 of FIG. 10) with a differential gain of 20. The common mode signal has a gain of 1 and the differential signal has a gain of 20. The signal at this point is a 2 Vpp, 60 Hz sine wave at each output, superimposed with a 4 Vpp, 500 Hz signal at Out1 (see FIG. 18A) and a -4 Vpp, 500 Hz signal at Out2 (see FIG. 18B). ) and provides an 8 Vpp differential signal.

[0132]

[0222] 18C and 18D show the outputs B2OutP and B2OutN of FIG. 10, respectively. At B2OutP and B2OutN, the signal passes through the fully differential operational amplifiers of FIG. 10 (blocks 6 and 7, 1017, 1021) to eliminate the common mode signal and reference the common mode output voltage, output, to VOCM (2.5V bias level). The gain of 0.5 in amplifier 1034 of block 7 results in a final set of 2Vpp 500Hz signal at B2OutP (see FIG. 18C) and -2Vpp at B2OutN (see FIG. 18D), which is equivalent to a 4Vpp differential 500Hz signal. From input to output, the common mode gain is 0 and the differential gain is 10. Thus, the common mode signal can be eliminated through the combined response of the instrumentation amplifier (block 5) and the fully differential operational amplifiers (blocks 6 and 7).

[0133] Signal Example 2 - 500kHz Ablation Signal

[0223] Signal Case 2 presents a typical 500 kHz ablation signal applied to the EP system input with cardiac monitoring continuing during the ablation procedure. Unwanted ablation signals are filtered and attenuated before reaching the A / D converter (see FIG. 4, block 8, 416) of the disclosed circuit.

[0134]

[0224] As shown in Figures 19A and 19B, the ablation signal input is a 0.2 Vpp, 500 kHz sine wave applied to In12 (Figure 19A) and a -0.2 Vpp, 500 kHz sine wave applied to In22 (Figure 19B). This results in a 0.4 V, 500 kHz differential signal. This signal is in the frequency range that should be attenuated by RF filter 702 of block 2 (Figure 4, 404a and 404b).

[0135]

[0225] Figures 19C and 19D show plots of the output of RF filter 702 (block 2) In13 (and the symmetrical lower branch RF filter output In23) when the circuit receives an ablation signal. Plot V(In13) in Figure 19C and plot V(In23) in Figure 19D are shown to the same scale as the input. It can be seen that the signal has attenuated to a few millivolts.

[0136]

[0226] The plots of V(Shield1) and V(Shield2) shown in Figures 20A and 20B, respectively, show that the same signal across the shield input (see, e.g., Shield1 in Figure 7) is also significantly attenuated, effectively grounding the bottom plates of capacitors 714, 716, 706 in the upper branch of RF filter 702 in Figure 7 and the corresponding capacitors (not shown) in the symmetrical lower branch of the RF filter, allowing the RF filter to attenuate the 500 kHz ablation signal.

[0137]

[0227] Figures 21A and 21B show plots of the signals V(Out1) and V(Out2), respectively, at the output of block 5 (instrumentation amplifier 1001 in Figure 10) with a gain of 20. The remaining 500 kHz signal passes through this 20x gain stage, but filtering in this stage (from capacitors 1010 and 1012) limits the gain at 500 kHz to approximately 1x.

[0138]

[0228] As shown in Figures 21C and 21D, the successive fully differential operational amplifiers 1017, 1021 (and their negative lower branch equalizers) in blocks 6 and 7 of Figure 10 continue to filter the 500 kHz signal until it is less than 0.5 mV at B2OutP (Figure 21C) and B2OutN (Figure 21D). The remaining signal is removed by a filter in block 8 A / D converter (see Figure 4, 416) which provides 100 dB attenuation above 1000 Hz. Thus, the ablation signal is filtered out by the RF filter (block The input signal is eliminated through the combined response of an instrumentation amplifier (block 5) and a fully differential operational amplifier (blocks 6 and 7).

[0139] Hardware / Software Interface

[0229] FIG. 5A illustrates the relationship between hardware and software of the disclosed EP recording system, according to some embodiments. A main system unit (MSU) 504 includes the hardware circuitry of the EP recording system. In FIG. 5A, an ECG board 506 including a WCT 507 corresponds to the ECG board 302 and the WCT 314 shown in FIG. 3 (for cross reference, the digital signal outputs of the ECG boards 302, 506 are V1-V6 310 and I-II 312). Similarly, an IC board 508 corresponds to the IC board 316 in FIG. 3 (for cross reference, the digital signal outputs IC1...ICN of the IC boards 316, 508 are ICUniWCT1-ICUniWCT2 326, ICUniINDIF1-ICUniINDIF2 328, and ICDiff1...ICDiffN 330). A communications module 510 and fiber optic link 512 are provided for communicating the digital signals output from the ECG board 506 and the IC board 508 to software in a main processing unit (MPU) 514 .

[0140]

[0230] According to some embodiments, the communications module 510 of the MSU 504 transmits independent digital signals from the A / D converters 416, 534 of the ECG board 506 and the IC board 508 over the fiber optic link 512 to the MPU 514 for digital signal processing. The communications module 510 samples the output channels from the A / D converters 416, 534, converts them to serial format, and transmits the data over the fiber optic link 512. The signals are converted back to parallel format at the receiving end of the fiber optic link 512 at the MPU 514.

[0141]

[0231] The ECG boards 302, 506 and IC boards 316, 508 are so named herein for convenience. As will be appreciated by those skilled in the art, the circuitry of the ECG boards 302, 506 and IC boards 316, 508 can accept other physiological signals from various types of electrodes other than ECG and IC electrodes.

[0142] EP Recording System Software Description

[0232] Provided herein are system, apparatus, device, method and / or computer program product embodiments, and / or combinations and subcombinations thereof, for processing and displaying multiple signals in near real-time. For example, embodiments may include processing and displaying multiple biomedical signals (e.g., EP signals) in near real-time. Before describing further details of these embodiments, a brief overview of digital signal processing is provided.

[0143]

[0233] In overview, digital signal processing is the use of digital processing to identify specific features in a signal or to generate a signal of higher quality than the original signal (e.g., by removing noise from the signal). Digital signal processing can be performed on digitized electrocardiography (ECG) signals or intracardiac (IC) signals that represent the electrical activity of the heart over a period of time.

[0144]

[0234] In order to perform digital signal processing on an analog signal, the analog signal needs to be converted to a digital form. As is well known to those skilled in the art, an analog-to-digital (AD) converter, such as A / D converter 416, can convert the analog signal to a digital signal.

[0145]

[0235] Digital signal processing is the process of converting digital signal processing functions into a sequence of signal samples of a signal. A digital signal processing function may include applying a digital signal processing function (DSP) to one or more signal samples in a sequence. A digital signal processing function may be a sequence of mathematical operations and computational algorithms. A digital signal processing function may, for example, measure, filter, compress, or optimize the signal samples.

[0146]

[0236] Digital signal processing may use different digital signal processing functions depending on the type of analysis and the type of signal being processed. For example, digital signal processing may use different digital signal processing functions to identify specific words in an audio signal or to remove motion blur from a video signal.

[0147]

[0237] Digital signal processing systems have many applications, such as audio signal processing, audio compression, digital image processing, video compression, voice processing, speech recognition, digital communications, digital synthesizers, radar, sonar, financial signal processing, and seismology. However, conventional digital signal processing systems are often unable to be used in some applications, such as biomedical signal processing. This is because conventional digital signal processing systems, including current EP solutions, often cannot simultaneously display multiple signals in near real time. Furthermore, conventional solutions do not allow a user to dynamically apply new digital signal processing functions to a base signal. Also, conventional solutions often do not allow for synchronized processing and display of multiple signals in near real time. This is often problematic in clinical environments, where a physician's ability to make a valid clinical diagnosis may depend on comparing multiple signals at the same point in time. Finally, conventional EP systems that use analog filters often cannot fully utilize digital signal processing. This is because the options are greatly limited when the functions are implemented in hardware. For example, functions cannot be removed, and therefore the full potential of digital signal processing cannot be obtained.

[0148]

[0238] The digital signal processing (DSP) disclosed herein goes further to solve these problems of conventional systems. In addition to using multiple simultaneous DSP filters to process, time-align, and display multiple signals in near real-time, the system also provides clear operational endpoints for biomedical procedures such as ablation so that the operator's job is more efficient. For example, the present disclosure provides high fidelity surface ECG signals to automate and create averaged, late potential electrocardiograms. Ablation procedures use internal cardiac maps so that the operator can visualize the cardiac tissue for ablation. Once an internal cardiac map is created, the adequacy of the map is judged by a percentage map relative to the surface averaged, late potential ECG. In other words, if a complete map is created, all intracardiac signals, including late potentials, when summed, should reproduce both the timing and amplitude of the averaged, late potential map from the high fidelity ECG. A score is displayed that represents the adequacy of the map. For example, a score of 50% means that the mapping catheter has not reached the site where some of the delayed signal must be present to account for the high fidelity averaged, late potential map data. Following ablation of the late potentials, a real-time high fidelity averaged, late potential ECG will determine whether the abnormal late potentials have, in fact, improved. If not, further ablation of the previously tabbed late potentials can be performed using a late potential filter and dynamic window for guidance. The disclosed system provides data that directs the operator to the exact late potential region in the map, reducing the need for further ablation.

[0149]

[0239] 26 is a block diagram of a system 2600 for processing and displaying multiple signals in near real-time, according to some embodiments. System 2600 may represent MPU (software) 514 of FIG. 5A and may implement digital processing stage 528 of FIG. 5B. The system 2600 includes a signal path module 2602, a configuration path module 2620, and a monitoring module 2622. The signal path module 2602, the configuration path module 2620, and the monitoring module 2622 may be software modules that may be executed by a processor (or multiple processors), such as the processor 8504 of Figure 85. Alternatively, multiple processors may be used.

[0150]

[0240] The signal path module 2602 includes an input module 2604, a timer 2605, a packetizer 2606, a queuing module 2608, a packet dispatcher 2610, a global signal table 2612, and an output module 2616. The input module 2604, the timer 2605, the packetizer 2606, the queuing module 2608, the packet dispatcher 2610, the global signal table 2612, and the output module 2616 may be software modules that can be executed by a processor (or multiple processors), such as the processor 5004. The signal path module 2602 solves at least the technical problem of how to synchronize the processing and display of multiple signals in near real time. The signal path module 2602 solves this technical problem using a novel multi-stage process that includes packetization, queuing, and processing delay equalization, as described below.

[0151]

[0241] In the first stage, the input module 2604 can receive signal samples for one or more base signals. The base signal can be a signal before any digital signal processing is applied. For example, the base signal can be a biomedical signal such as an ECG signal or an IC signal. As will be appreciated by those skilled in the art, the base signal can be various other types of signals. The input module 2604 can receive signal samples for multiple base signals. For example, the input module 2604 can receive a signal sample of an IC signal and a signal sample of an ECG signal.

[0152]

[0242] The input module 2604 can receive signal samples of the base signal from a hardware device associated with the MSU (hardware) 504 of Figure 5. For example, the input module 2604 can receive signal samples from a hardware device such as the EGG board 302 or the IC board 316 of Figure 3. The input module 2604 can also receive signal samples from data stored in a computer file. For example, the computer file can include previously recorded signal samples received from a hardware device.

[0153]

[0243] The input module 2604 can receive signal samples from a hardware device via the A / D converter stage 534. For example, the input module 2604 can receive signal samples of the base signal from the EGG board 302.

[0154]

[0244] The input module 2604 can receive signal samples of the base signal from electrodes attached to a hardware device. For example, the input module 2604 can receive signal samples from each of the eight electrodes attached to the ECG board 302. As will be appreciated by one of ordinary skill in the art, the input module 2604 can receive more or fewer signal samples depending on the number of hardware devices connected to the input module 2604 and the number of electrodes attached to each hardware device.

[0155]

[0245] The input module 2604 may store one or more signal samples for each base signal in a computer storage device for later analysis by the review module 2624. For example, the input module 2604 may store one or more signal samples in the main memory 8508 or hard disk drive 8512 of FIG. This allows a user (e.g., a physician) to review one or more signal samples for each base signal after they have been collected.

[0156]

[0246] The input module 2604 can dispatch one or more signal samples for each base signal to the packetizer 2606. The packetizer 2606 can perform pre-processing on the received signal samples. The packetizer 2606 performs pre-processing on the received signal samples to ensure that the resulting signal is compatible with subsequent stages in the signal path module 2602. As will be appreciated by those skilled in the art, the type of pre-processing that the packetizer 2606 performs can depend on the type of the base signal. For example, the packetizer 2606 can convert the binary values ​​of the received signal samples to their corresponding physical values, for example, to represent the base signal.

[0157]

[0247] After pre-processing the received signal samples, the packetizer 2606 can store one or more signal samples of the base signal in a packet. A packet can be a continuous sequence of N signal samples belonging to the same base signal. The storage of signal samples in packets by the packetizer 2606 allows the signal path module 2602 to synchronize the processing and display of multiple signals in near real time, especially in a non-real time operating system. In other words, a packet is a unit of processing in the signal path module 2602.

[0158]

[0248] Packetizer 2606 can store one or more signal samples in a packet based on timer 2605. Timer 2605 can be a high-resolution timer. For example, timer 2605 can be a Microsoft Windows® 8.1.x timer with 1 millisecond resolution. The timer 2605 may be a high-resolution timer (e.g., a standard high-resolution timer). The timer 2605 may be set to an amount of time for receiving a certain number of signal samples (e.g., N signal samples) from a hardware device or from a computer file. The certain number of signal samples may correspond to the number of signal samples that can be stored in a packet.

[0159]

[0249] Packetizer 2606 may use timer 2605 to ensure that each packet contains the same number of signal samples. Specifically, packetizer 2606 may set timer 2605 to an amount of time associated with receiving a given number of signal samples of a base signal. In other words, packetizer 2606 may expect to receive a particular number of signal samples when timer 2605 is triggered.

[0160]

[0250] The packetizer 2606 may start a timer 2605. The packetizer 2606 may then store the signal samples received from the input module 2604 in a packet until the timer 2605 is triggered. The packetizer may then dispatch the packet to the queuing module 2608. The packetizer 2606 may then restart the timer 2605. The packetizer 2606 may then store a new set of signal samples received from the input module 2604 in a new packet until the timer 2605 is triggered again.

[0161]

[0251] The packetizer 2606 can assign a tag to each packet. The packetizer 2606 can assign the same tag to each packet associated with different base signals for the same time period. This assignment allows the signal path module 2602 to synchronize the processing and display of packets for different base signals for the same time period. The assigned tag can be used by the display module 2618 to synchronize the output of the different signals. In other words, the display module 2618 can work with the same tag at any given time.

[0162]

[0252] The assigned tag may correspond to the period during which the signal samples in the corresponding packet were received. Specifically, the tag may correspond to the sample number of the first signal sample in the corresponding packet. For example, the packetizer 2606 may store 16 signal samples in each packet. In this case, the packetizer 2606 may store a first set of signal samples in the packet with a tag of 0. The packetizer 2606 may store a second set of signal samples in the packet with a tag of 15. The packetizer 2606 may store subsequent sets of signal samples in the packet with tags of 31, 47, 64, etc. As will be appreciated by those skilled in the art, other tag assignment conventions may be employed.

[0163]

[0253] After packetization, the packetizer 2606 can store each generated packet associated with a given base signal in a queuing module 2608. The queuing module 2608 is shown in FIG.

[0164]

[0254] Fig. 27 is a block diagram of a queuing module 2608 that stores each generated packet associated with a different base signal according to some embodiments. The queuing module 2608 solves at least the technical problem of how to dynamically apply multiple different digital signal processing functions to the same base signal. The queuing module 2608 solves this technical problem by storing the generated packets associated with each base signal in a separate queue that can be dynamically processed by different signal modules 2614. Fig. 27 is described with reference to Fig. 26.

[0165]

[0255] The queuing module 2608 includes one or more queues 2702. For example, in FIG. 27, the queuing module 2608 includes queue 2702-1, queue 2702-2, and queue 2702-N. Each queue 2702 can be associated with a given base signal. The queue 2702 can be a queue data structure that stores elements in the order in which they are inserted. For example, the first element inserted into the queue 2702 is the first element removed from the queue 2702. In other words, the queue 2702 is a first-in, first-out (FIFO) data structure. As will be appreciated by those skilled in the art, the queue 2702 can be implemented with an array, a linked list, or a variety of other data structures.

[0166]

[0256] The packetizer 2606 can store each generated packet associated with a given base signal in a corresponding queue 2702. For example, the packetizer 2606 can store generated packets associated with an IC signal in queue 2702-1 and generated packets associated with an ECG signal in queue 2702-2.

[0167]

[0257] Packetizer 2606 can store each packet in queue 2702 in the order in which it was generated, thereby ensuring that the signal samples in the generated packets are processed in the order in which they were received from the hardware device or from the computer file.

[0168]

[0258] Returning to Figure 26, the packet dispatcher 2610 can dispatch the generated packets from the queue 2702 of Figure 27 to one or more signal modules 2614 in the global signal table 2612 for digital signal processing. The packet dispatcher 2610 solves at least the technical problem of how to dynamically apply multiple different digital signal processing functions to the same base signal. The packet dispatcher 2610 solves this technical problem by dynamically dispatching the generated packets associated with each base signal to the appropriate one or more signal modules 2614 for digital signal processing.

[0169]

[0259] The packet dispatcher 2610 may continuously scan one or more queues 2702 in the queuing module 2608. Whenever the packet dispatcher 2610 detects a new packet available in the queue 2702 of the queuing module 2608, the packet dispatcher 2610 may remove the new packet from the queue 2702. The packet dispatcher 2610 may then dispatch the new packet to one or more signal modules 2614 in the global signal table 2612 for digital signal processing. The packet dispatcher 2610 may dispatch the same packet to multiple signal modules 2614, thereby allowing the base signal to be processed simultaneously using different digital signal processing functions. Furthermore, the packet dispatcher 2610 may dispatch packets from different queues 2702 to different signal modules 2614, allowing the different base signals to be processed simultaneously using different digital signal processing functions.

[0170]

[0260] The packet dispatcher 2610 can dispatch new packets from the queue 2702 to one or more signal modules 2614. The packet dispatcher 2610 can dispatch new packets to one or more signal modules 2614 using a global signal table 2612. The global signal table 2612 can be a fixed size array. Each element of the array can be associated with a given base signal and therefore a given queue 2702. For example, if there are 100 base signals, the global signal table 2612 can be a fixed size array of 100 elements. Furthermore, for each element of the array, there can be one or more signal modules 2614 designed to process the corresponding base signal. In some embodiments, each element of the array can be a fixed size array itself. Each element of this sub-array can be associated with a given signal module 2614. For example, if there are 10 signal modules 2614, this sub-array can include 10 elements. Thus, by way of example and not limitation, the global signal table 2612 may be a 100x10 array.

[0171]

[0261] The packet dispatcher 2610 may dispatch a new packet to a signal module 2614 by examining a corresponding element in a sub-array associated with a base signal of the new packet. In particular, the packet dispatcher 2610 may determine whether the corresponding element in the sub-array indicates that the signal module 2614 is assigned to the base signal associated with the packet.

[0172]

[0262] In some embodiments, the global signal table 2612 may indicate whether a given signal module 2614 is assigned to a given base signal by storing a "0" or a "1" in a corresponding element in the subarray associated with the given signal module 2614. For example, the global signal table 2612 may indicate that a given signal module 2614 is not assigned to a given base signal by storing a "0" in the corresponding element in the subarray. In some other embodiments, the global signal table 2612 may indicate whether a given signal module 2614 is assigned to a given base signal by storing a reference to the given signal module 2614 in the corresponding element in the subarray. As will be appreciated by one of ordinary skill in the art, the reference may be a memory pointer, a flag, a handle, or other type of identifier.

[0173]

[0263] The packet dispatcher 2610 can also use a lookup table to dispatch new packets to one or more signal modules 2614. The lookup table can be used to assign a given queue to one or more signal modules 2614. The packet dispatcher 2610 can dynamically determine whether one or more signal modules 2614 are associated with a given queue 2702 using a lookup table. The packet dispatcher 2610 can then dispatch the packet to the one or more determined signal modules 2614 for digital signal processing.

[0174]

[0264] Before the packet dispatcher 2610 can begin dispatching packets to one or more signal modules 2614 for digital signal processing, a configure path module 2620 can configure the signal path module 2602. The configure path module 2620 can perform this configuration during initialization of the system 2600 or when a user applies a new configuration to the signal path module 2602. The configure path module 2620 is shown in FIG.

[0175]

[0265] FIG. 28 is a block diagram of a configuration path module 2620 that configures the signal path module 2602 to synchronize the processing and display of multiple signals in near real time, according to some embodiments. The configuration path module 2620 solves at least the technical problem of how to synchronize the processing and display of multiple signals related to one or more base signals in near real time. The configuration path module 2620 solves this technical problem by equalizing the processing delay of each signal module 2614 such that each signal module 2614 completes the processing of the same corresponding packet at approximately the same time. FIG. 28 will be considered with reference to FIG. 26.

[0176]

[0266] The configuration path module 2620 includes a signal configuration module 2802, a signal factory module 2804, a digital signal processor (DSP) equalizer 2806, and a DSP factory module 2808. The configuration path module 2620 is a software module that may be executed by a processor (or multiple processors), such as the processor 5004. The configuration path module 2620 controls the execution of the signal factory module 2804, the DSP equalizer 2806, and the DSP factory module 2808. The signal factory module 2804, the DSP equalizer 2806, and the DSP factory module 2808 may be software modules that may be executed by a processor (or multiple processors), such as the processor 5004.

[0177]

[0267] During initialization of the system 2600, or in response to a user applying a new configuration to the system 2600, the configuration path module 2620 can create and configure one or more signal modules 2614 in the global signal table 2612. In some embodiments, while the configuration path module 2620 is running, the execution of the signal path module 2602 and the monitoring module 2622 can be paused.

[0178]

[0268] The configuration path module 2620 includes a signal configuration module 2802. The signal configuration module 2802 can receive one or more signal processing specifications. The signal processing specifications can be used to generate and configure the signal module 2614. The signal processing specifications can specify a base signal to be processed, input and output packet queue lengths for the signal module 2614, and digital signal processing functions to be used to process the base signal. The signal configuration module 2802 can receive one or more signal processing specifications from a computer file. The file can contain one or more signal processing specifications previously specified by a user. The signal configuration module 2802 can also receive the signal processing specifications via a graphical user interface (GUI) where a user can enter the signal processing specifications using a series of computer mouse, touch, keyboard, and / or voice recognition data entry techniques, as will be appreciated by those skilled in the art.

[0179]

[0269] In response to receiving the one or more signal processing specifications, the signal configuration module 2802 may forward the one or more signal processing specifications to the signal factory module 2804. The signal factory module 2804 may generate a signal module 2614 based on the signal processing specifications. For example, the signal factory module 2804 may generate the signal module 2614 as shown in FIG.

[0180]

[0270] Figure 29 is a block diagram of a signal module 2614 generated by the signal factory module 2804, according to some embodiments. The signal module 2614 can generate a processed signal from a base signal. The signal module 2614 includes an input packet queue 2902, a digital signal processor (DSP) 2904, and an output packet queue 2906. Figure 29 can be discussed with reference to Figures 26 and 28.

[0181]

[0271] The signal module 2614 includes an input packet queue 2902, a DSP 2904, and an output packet queue 2906. The signal factory module 2804 can generate the input packet queue 2902, the DSP 2904, and the output packet queue 2906 based on the signal processing specifications from the signal configuration module 2802. The input packet queue 2902 can store one or more packets from the packet dispatcher 2610 to be processed by the DSP 2904. The input packet queue 2902 can be a queue data structure that stores elements in the order in which they are inserted. For example, the first element inserted into the input packet queue 2902 is the first element removed from the input packet queue 2902. In other words, the input packet queue 2902 can be a first-in, first-out (FIFO) data structure. As will be appreciated by those skilled in the art, the input packet queue 2902 can be implemented using a linked list, an array, or various other data structures.

[0182]

[0272] The output packet queue 2906 may store one or more packets to be processed by the DSP 2904. The output packet queue 2906 may be a queue data structure that stores elements in the order in which they are inserted. For example, the first element inserted into the output packet queue 2906 is the first element removed from the output packet queue 2906. In other words, the output packet queue 2906 may be a first-in, first-out (FIFO) data structure. As will be appreciated by those skilled in the art, the output packet queue 2906 may be implemented using a linked list, an array, or a variety of other data structures.

[0183]

[0273] The signal factory module 2804 can generate the DSP 2904 based on the signal processing specification from the signal configuration module 2802. In particular, the signal factory module 2804 can request the DSP factory module 2808 to generate the DSP 2904. The DSP factory module 2808 can generate the DSP 2904 based on a digital signal processing function specified in the signal processing specification. The DSP factory module 2808 can further generate the DSP 2904 based on one or more signal processing parameters associated with the digital processing function. For example, the DSP factory module 2808 can generate the DSP 2904 based on a low pass filter function and a cutoff frequency specified in the signal processing specification.

[0184]

[0274] The DSP 2904 is a software module that may be executed by a processor (or processors), such as the processor 8504 of FIG. 85. The DSP 2904 performs digital processing functions on one or more packets, and thus one or more signal samples. As will be appreciated by one of ordinary skill in the art, a digital processing function may be a mathematical algorithm that takes one or more signal samples as input, processes them, and generates one or more possibly modified signal samples as output. The digital processing function may be implemented using one or more mathematical operations, such as a fast Fourier transform. As will be appreciated by one of ordinary skill in the art, the DSP2904 may apply various types of digital processing functions. For example, the DSP2904 may apply a low pass filter, a high pass filter, a band pass filter, a band stop filter, a notch filter, a comb filter, an all pass filter, or various other filters, as will be appreciated by one of ordinary skill in the art.

[0185]

[0275] The DSP2904 may also apply digital processing functions that analyze the signal for various characteristics. For example, the DSP2904 may apply digital processing functions that determine whether noise anomalies or signal patterns are present in the signal. The DSP2904 may also analyze the signal by detecting repeating patterns in the signal. This may include comparing the signal to previously detected (or recorded or synthesized) signal patterns.

[0186]

[0276] For example, the DSP 2904 can determine the presence of a late potential in the signal. Specifically, the DSP 2904 can determine the presence of a noise anomaly followed by a subsequent noise anomaly occurring simultaneously with respect to the coincident heart beat. Each subsequent noise anomaly in the same relative location can increase the confidence level that a late potential was located. The display module 2618 can then display an indication of the late potential.

[0187]

[0277] For example, such determination of late potentials by the DSP2904 can be used to filter pulmonary vein potentials. Specifically, a combination of delayed post-P wave separate electrograms with filtering for rapid conduction can be used to identify pulmonary vein potentials separately from adjacent atria and other structures. These signals can be used to filter the pulmonary vein potentials after ostia ablation. The system can be used for other thoracic veins, ventricular late potentials above the semilunar valves, late potentials in diseased myocardium, as well as the coronary sinus and Marshall's veins.

[0188]

[0278] Similarly, the DSP 2904 can determine the presence of pre-excitation in the signal. Specifically, the DSP 2904 can determine the presence of an earliest steep intracardiac signal above a selected threshold occurring within a predetermined segment prior to the fiducial point of the matched heartbeat. The display module 2618 can then display an indication of pre-excitation.

[0189]

[0279] The DSP2904 can detect patterns in the signal using a correlation function. For example, the DSP2904 can detect patterns using a mean absolute deviation algorithm. As will be appreciated by those skilled in the art, the DSP2904 can use various other types of pattern matching algorithms.

[0190]

[0280] The DSP 2904 can detect patterns based on various signal characteristics (also referred to as signal patterns). For example, the DSP 2904 can detect patterns based on shape, amplitude, and time characteristics. As will be appreciated by those skilled in the art, the DSP 2904 can detect patterns based on various other types of signal characteristics.

[0191]

[0281] The DSP2904 may also include one or more signal processing parameters. The signal processing parameters may control how the DSP2904 applies its digital processing functions. For example, the DSP2904 may set thresholds for filtering, The DSP 2904 may include one or more signal processing parameters that specify a signal frequency or amplitude to be detected. The DSP 2904 may also include one or more signal processing parameters that specify a signal pattern to be detected, or a noise threshold.

[0192]

[0282] The DSP 2904 can apply its digital processing function to the packets in the input packet queue 2902. In some embodiments, the DSP 2904 can scan the input packet queue 2902 for new packets to process. In other embodiments, the DSP 2904 can get notification that a new packet is available in the input packet queue 2902. The DSP 2904 can then remove the packet from the input packet queue 2902.

[0193]

[0283] The DSP 2904 may apply its digital processing function to the retrieved packet. In other words, the DSP 2904 may apply its digital processing function to one or more signal samples in the packet. The DSP 2904 may control how to apply the digital processing function to one or more signal samples in the packet based on the one or more signal processing parameters. After processing the packet, the DSP 2904 may store the packet in an output packet queue 2906 for display by the output module 2616.

[0194]

[0284] As described below, each DSP 2904 may have an associated processing delay. The processing delay may represent the amount of time it takes to complete processing of a packet by the digital processing functions of the DSP 2904. The processing delay may vary between different DSPs 2904. This difference in processing delay between different DSPs 2904 may cause the DSPs 2904 to output packets for display at different times, as described below.

[0195]

[0285] After the signal factory module 2804 completes the generation of the input packet queue 2902, the DSP 2904, and the output packet queue 2906, it can connect the output of the input packet queue 2902 to the input of the DSP 2904 and the output of the DSP 2904 to the input of the output packet queue 2906. Once the signal factory module 2804 has completed the connections, the DSP 2904 can receive packets representing the unprocessed base signal from the input packet queue 2902. The DSP 2904 can then process the packets using its digital processing capabilities. The DSP 2904 can output the processed packets to the output packet queue 2906. The signal factory module 2804 can further configure the input packet queue 2902 to receive packets from the base signal specified in the signal processing specification.

[0196]

[0286] Once a signal module 2614 is created, the signal factory module 2804 can add it to the global signal table 2612. As mentioned above, the global signal table 2612 can be a fixed size array. Each element of the array can be associated with a given base signal. Furthermore, each element of the array can be a fixed size array itself. Each element of this subarray can be associated with a given signal module 2614.

[0197]

[0287] In some embodiments, the signal factory module 2804 can add the created signal module 2614 to the global signal table 2612 by adding a new array element to each subarray associated with the base signal. The new array element can correspond to the newly created signal module 2614. For example, if the global signal table 2612 previously contained 10 signal modules 2614, the newly created signal module 2614 can be added to, for example, array number 11 of each subarray.

[0198]

[0288] Once the created signal module 2614 is added to the global signal table 2612, a user (e.g., a physician) can assign the created signal module 2614 to a given base signal. In some embodiments, the global signal table 2612 can indicate whether the created signal module 2614 is assigned to a given base signal by storing a "0" or a "1" in the corresponding element of the subarray associated with the created signal module 2614. In some other embodiments, the global signal table 2612 can indicate whether the created signal module 2614 is assigned to a given base signal by storing a reference to the created signal module 2614 in the corresponding element in the subarray.

[0199]

[0289] The signal factory module 2804 can generate multiple signal modules 2614. Each signal module 2614 can have a DSP 2904 that applies a different digital signal processing function. As a result, each signal module 2614 can generate a different processed version of the same base signal. This allows a user to analyze the same base signal in different ways. A user may also want to analyze the time-aligned output of multiple versions of the same base signal. This allows a user to compare different versions of the same signal at the same or different points in time.

[0200]

[0290] As mentioned above, conventional digital signal processing systems often cannot synchronize the display of multiple processed signals in near real time. This may be because different digital signal processing functions have different processing delays. For example, a current EP system may apply two different digital signal processing functions to the same base signal. However, a medical team may want to synchronize the display of two processed signals. For example, a medical team may want to compare an IC signal and an ECG signal at the same time to determine a clinical diagnosis. In other words, a medical team may want to time-align the delay of a first processed signal with the delay of a second processed signal in near real time. However, this may not be possible because two different digital processing functions have different processing delays. This is because one of the digital processing functions may complete processing of the base signal more quickly than the other digital signal processing function. As a result, one processed signal may be displayed before the other processed signal.

[0201]

[0291] The processing delay associated with a digital processing function may depend on the complexity of the function. For example, a digital processing function that performs low-pass filtering on a signal may be relatively computationally intensive and use minimal memory. As a result, such a digital processing function may have a short processing delay. In contrast, another digital processing function may analyze the signal for specific signal characteristics. This type of digital processing function may be more computationally intensive, use more memory, and therefore have a longer processing delay.

[0202]

[0292] Due to different processing delays, one processed signal may be displayed before another. This synchronization shift may become large over time. For example, this synchronization shift may become large when multiple signals are being processed and displayed near real time. This is because the difference in processing delay between two digital signal processing functions may propagate to each new signal sample.

[0203]

[0293] For example, a first digital signal processing function may have a processing delay of 10 milliseconds for a given base signal. A second digital signal processing function may have a processing delay of 20 milliseconds for the same base signal. A first digital signal processing function may complete processing of a first signal sample in 10 milliseconds, and a second digital signal processing function may process the same first signal sample in 20 milliseconds. Thus, a first signal sample processed by the first digital signal processing function may be displayed in 10 milliseconds, and a first signal sample processed by the second digital signal processing function may be displayed in 20 milliseconds. In other words, a first signal sample processed by the first digital signal processing function may be displayed 10 milliseconds before a first signal sample processed by the second digital signal processing function.

[0204]

[0294] When the second signal sample is processed, this synchronization error may increase. For example, the second signal sample may be received at 10 milliseconds for processing by the first digital signal processing function, and the second signal sample may be received at 20 milliseconds for processing by the second digital signal processing function. As a result, the second signal sample processed by the first digital signal processing function may be displayed at 20 milliseconds, and the second signal sample processed by the second digital signal processing function may be displayed at 40 milliseconds. In other words, the synchronization error may increase by 10 milliseconds for the second signal sample, i.e., first the synchronization error is 10 milliseconds, and then the synchronization error is 20 milliseconds.

[0205]

[0295] This synchronization loss can be amplified when digital signal processing is implemented in a non-real-time operating system. Unlike a non-real-time operating system, a real-time operating system is a time-bound system with clear fixed time constraints. A real-time operating system can guarantee that an application task is accepted and completed in a certain amount of time. In other words, a real-time operating system can provide a level of consistency regarding the amount of time it takes to complete a task.

[0206]

[0296] In contrast, a non-real-time operating system may not provide any guarantee that an application task will complete in a certain amount of time. For example, a non-real-time operating system may not provide any guarantee that execution of a particular digital signal processing function will complete in a certain amount of time. As a result, there may be a high degree of variability regarding the amount of time it takes to complete a task. This may be problematic when attempting to synchronize the processing and display of multiple processed signals. This is because the processing delay associated with a digital processing function may vary with each execution. For example, a digital signal processing function may typically complete execution in 10 milliseconds. However, in a non-real-time operating system, there may be no guarantee that the digital signal processing function will complete execution after 10 milliseconds. For example, a digital processing function may complete execution in 30 milliseconds. This variability in processing delay may further increase synchronization loss.

[0207]

[0297] In some embodiments, this display synchronization problem is solved in a multifaceted way by using input packet queues 2902 and output packet queues 2906 of the signal module 2614 to store signal samples in packets with associated tags and to equalize processing delays between one or more DSPs 2904.

[0208]

[0298] The input packet queue 2902 and the output packet queue 2906 can solve the delay synchronization problem in three ways. First, they ensure that packets, and therefore signal samples, are processed and displayed sequentially. Second, the output packet queue 2906 can synchronize the display of packets to the same point in time by blocking the processing of further packets until the existing packets have been consumed by the output module 2616. In other words, the output packet queue 2906 prevents the DSP 2904 from consuming further packets. A feedback mechanism may be provided to the DSP 2904 to indicate when processing can stop. Finally, the input packet queue 2902 ensures that the DSP 2904 has packets to process. For example, when the input packet queue 2902 is empty, the DSP 2904 may stop processing further packets. In other words, the input packet queue 2902 may provide a feedback mechanism to the DSP 2904 to indicate that there are no packets to process.

[0209]

[0299] The DSP delay equalizer 2806 can also solve the delay synchronization problem by equalizing the processing delays across one or more DSPs 2904. As mentioned above, different digital signal processing functions have different processing delays, which may cause the processed signals to be displayed out of sync. Therefore, the configuration path module 2620 generates multiple signal modules 2614, each with a DSP 2904 having a different digital signal processing function, and each signal module 2614 can complete the processing of a packet with a different processing delay. These different processing delays may cause the processed signals to be displayed out of sync by the output module 2616. The DSP delay equalizer 2806 can solve this problem by equalizing the processing delays across the generated signal modules 2614.

[0210]

[0300] In some embodiments, after the configuration path module 2620 generates one or more signal modules 2614, the signal factory module 2804 can use a DSP delay equalizer 2806 to equalize the processing delay of each generated signal module 2614 such that each signal module 2614 outputs a processed packet to its output packet queue 2906 at the same point in time. For example, the DSP delay equalizer 2806 can determine a relative processing delay between two signal modules 2614. The DSP delay equalizer 2806 can then use the determined relative delay to configure the DSP 2904 of the first signal module 2614 to complete processing of the packet at approximately the same point in time that the DSP 2904 in the second signal module 2614 is designed to complete processing of the packet.

[0211]

[0303] In some embodiments, the DSP delay equalizer 2806 may perform the equalization by scanning each generated signal module 2614. During the scan, the DSP delay equalizer 2806 may request the processing delay associated with the DSP 2904 of each signal module 2614. The DSP delay equalizer 2806 may request the processing delay using an application programming interface (API) of each signal module 2614. In response, each signal module 2614 may return its associated processing delay.

[0212]

[0302] The signal module 2614 may store a processing delay associated with its DSP 2904. The processing delay may be a predefined value specified in the signal processing specification used to generate the DSP 2904. In some other embodiments, the DSP factory module 2808 may calculate the processing delay of the DSP 2904 based on various factors, including the digital processing functions used by the DSP 2904, the selected signal processing parameters, and hardware characteristics such as the speed, memory size, and I / O latency of a processor, such as the processor 5004.

[0213] After determining the processing delay associated with the DSP 2904 in each signal module 2614, the DSP delay equalizer 2806 can determine a maximum processing delay between the signal modules 2614. For example, the DSP delay equalizer 2806 may determine that signal module 2614-1 has a 10 millisecond processing delay, signal module 2614-2 has a 20 millisecond processing delay, and signal module 2614-N has a 50 millisecond processing delay. Based on this, the DSP delay equalizer 2806 may determine that the maximum processing delay between the signal modules 2614 is 50 milliseconds.

[0214]

[0304] After determining the maximum processing delay, the DSP delay equalizer 2806 can configure the DSP 2904 of each signal module 2614 to have the maximum processing delay. For example, the DSP delay equalizer 2806 can use an API to set the processing delay of the DSP 2904 of each signal module 2614. In response, each DSP 2904 can be designed to process a packet using its digital processing capabilities and output the processed packet to its associated output packet queue 2906 at the end of the maximum processing delay. For example, in some embodiments, the DSP 2904 can block its output to its output packet queue 2906 if processing of the packet is completed before the end of the maximum processing delay. In some other embodiments, the DSP 2904 can insert idle computation cycles while processing the packet. As will be appreciated by those skilled in the art, various other techniques can be used to cause the DSP 2904 to output the processed packet to its output packet queue 2906 at the end of the maximum processing delay.

[0215]

[0305] Packetization and assignment of tags to packets can solve the display synchronization problem. As described above, each generated packet can contain a certain number of signal samples. Each packet can also contain a tag that indicates the relative position of that packet among a sequence of packets. To synchronize the delay of multiple signals, the display module 2618 can display packets that have the same tag. In other words, the display module 2618 can use the tags to synchronize its display.

[0216]

[0306] As shown in FIG. 26, the output module 2616 may include one or more display modules 2618-1 to 2618-N and a review module 2624. The review module 2624 may be a software module that may be executed by a processor (or processors), such as the processor 5004. The review module 2624 may display one or more signals processed by the one or more signal modules 2614 at a preceding time. The display modules 2618 may each be a software module that may be executed by a processor (or processors), such as the processor 5004. The display modules 2618 may display one or more live signals processed by the one or more signal modules 2614. Each display module 2618 may operate independently of the other display modules 2618. In other words, each display module 2618 may simultaneously display one or more signals on one or more display devices, such as the input / output device 8503 in FIG. 85. In some embodiments, each display module 2618 can display its associated signal or signals in a particular GUI window on a given display device.

[0217]

[0307] Each display module 2618 can display one or more signals. Each display module 2618 can receive a packet from an associated output packet queue 2906 in a signal module 2614 in the global signal table 2612. The display module 2618 can display the signal based on the packet.

[0218]

[0308] 30 is a block diagram of the display module 2618 according to some embodiments. The display module 2618 includes a local signal table 3002, a packet index 3004, and a display setting 3006. FIG. 30 will be discussed with reference to FIG.

[0219]

[0309] As described above, the display module 2618 may The display module 2618 may receive packets from the associated output packet queue 2906 in the signal module 2614. To receive packets, the display module 2618 may maintain a reference to the associated output packet queue 2906 in the signal module 2614. If the display module 2618 is designed to display multiple signals, it may maintain a reference to the output packet queue 2906 associated with each displayed signal. The display module 2618 may store the references in its local signal table 3002. The local signal table 3002 may include a list of one or more references to the output packet queue 2906 associated with each displayed signal. The display module 2618 may remove the reference from its local signal table 3002 when the associated signal module 2614 becomes inactive.

[0220]

[0310] In some embodiments, the display module 2618 may continuously scan its associated output packet queue(s) 2906 for new packets. If the display module 2618 is associated with a single output packet queue 2906, the display module 2618 may display a new packet on a display device each time it detects the packet. However, if the display module 2618 is associated with multiple output packet queues 2906, the display module 2618 may not immediately display a new packet detected in a particular output packet queue 2906. This is because the display module 2618 may be designed to synchronize the display of multiple signals.

[0221]

[0311] In some embodiments, if a given display module 2618 is designed to synchronize the display of multiple signals, the display module 2618 may detect a new packet in a particular output packet queue 2906. The display module 2618 may then determine a tag associated with the new packet. The display module 2618 may use this determined tag to synchronize the display of new packets from other output packet queues 2906. For example, the display module 2618 may wait to display any packets on a display device until after it detects a new packet in the other output packet queue 2906 with the same determined tag. When the display module 2618 detects a new packet with the same tag in the other associated output packet queue 2906, it may simultaneously display packets from that associated output packet queue 2906. The display module 2618 may display multiple signals in a non-overlapping stacked format. Because the display module 2618 may display packets with the same tag, the resulting displayed signals may be time aligned.

[0222]

[0312] As discussed above, the type of pre-processing that the packetizer 2606 may perform on any one of the signals may depend on the type of signal. In some embodiments, the selection of signal pre-processing by the packetizer 2606 may be automated. This allows for automated placement of appropriate filters based on, for example, the ratio of far-field signals to adjacent and near-field signals with minimal filtering to minimize noise and target the signal of interest. As will be appreciated by those skilled in the art, this type of automation may be effective to minimize procedure time, for example, when there are a low or medium number of practitioners. The display module 2618 may similarly synchronize and display the signals as new packets are detected from the automated process.

[0223]

[0313] The display module 2618 may maintain the currently active tag to be displayed in the packet index 3004. Upon detecting a new packet in a particular output packet queue 2906, the display module 2618 may determine the tag of the new packet. The display module 2618 then updates the packet index 3004 with the determined tag. 04 can be set.

[0224]

[0314] In some embodiments, a high frequency rapid conduction signal filter can be applied to multiple electrodes, such as with a basket or balloon-based catheter, to identify conducting tissues, such as distal Purkinje and annular rapid conduction tissues, which can be quickly targeted for ablation due to their signal prominence. Based on dynamic tagging of packets from the packetizer 2606, the display module 2618 can continue to visualize the signal as a reference point to guide the movement of the ablation catheter and can be used to terminate local energy delivery once the pathogenic signal of interest attenuates during ablation. As shown in this example, the system's pre-processing and continuation of processing allows the physician to continue to see the signal even during ablation.

[0225]

[0315] The display module 2618 may include display settings 3006. The display settings 3006 may include one or more parameters that control how the display module 2618 displays its associated signal or signals. The display settings 3006 may specify a color in which to display the associated signal or signals. The display settings 3006 may specify a view format such as a waterfall view, a dynamic view, or a triggered view, as described below. The display settings 3006 may specify a sweep rate for the signal or signals. The display settings 3006 may include various other types of display settings as will be appreciated by those skilled in the art. The display settings 3006 may be user designed, as described below.

[0226]

[0316] The review module 2624 can display one or more signals processed by one or more signal modules 2614 at a prior time. This allows a user (e.g., a physician) to analyze one or more signals long after they have been generated and displayed. In some embodiments, the review module 2624 can capture a display of one or more signals in the display module 2618 upon command. For example, a user can click a button in the GUI to capture the current display of the display module 2618. The captured display can include a previously displayed visualization of the one or more signals at the time of capture. In some embodiments, the display module 2618 can pause the display of its new packets in response to the capture of its current display.

[0227]

[0317] In some embodiments, the review module 2624 can capture a display of one or more signals on the display module 2618 by determining a capture configuration for the display module 2618. The capture configuration can include one or more active signal modules 2614 for the display module 2618, a capture time, a selected view for the display module 2618, a color scheme for one or more displayed signals, and various other settings, as would be understood by one of ordinary skill in the art. After determining the capture configuration, the review module 2624 can apply the capture configuration to previously stored signal samples.

[0228]

[0318] As described above, the input module 2604 may store one or more signal samples for each base signal in a storage device for later analysis by the review module 2624. The review module 2624 may capture a display of the one or more signals in the display module 2618 by applying the determined capture configuration to these stored signal samples. In particular, the review module 2624 may select the stored signal samples at the time of capture in the capture configuration. The review module 2624 may then process the selected signal samples using the active signal module 2614 in the capture configuration. The review module 2624 may then process the selected signal samples using the active signal module 2614 in the capture configuration. The review module 2624 may also display selected signal samples using a selected view, color scheme, and various other settings in the capture configuration. Thus, the review module 2624 allows a user to review one or more processed signals on the display module 2618 at a particular time and according to a particular configuration.

[0229]

[0319] In some embodiments, the review module 2624 may allow a user to change the refresh interval for the display module 2618. For example, a user may "go back" to a different point in the past (e.g., 5 minutes ago). After the capture time is changed, the review module 2624 may display one or more processed signals for the display module 2618 at the new refresh time index.

[0230]

[0320] 31 is a block diagram of the monitoring module 2622, according to some embodiments. The monitoring module 2622 includes a queue monitor 3102 and a reporting module 3104. The queue monitor 3102 and the reporting module 3104 may be software that can be executed by a processor (or multiple processors), such as the processor 5004.

[0231]

[0321] The monitoring module 2622 may execute continuously while the signal path module 2602 is executing. For example, the monitoring module 2622 may execute as a separate thread of execution by a processor. The monitoring module 2622 may determine whether there is a problem in the execution of the signal path module 2602.

[0232]

[0322] In some embodiments, the queue monitor 3102 may periodically scan the queues in the signal path module 2602. For example, the queue monitor 3102 may scan the queues 2702 of the queuing module 2608. The queue monitor 3102 may also scan the input packet queues 2902 and the output packet queues 2906 in one or more signal modules 2614. The queue monitor 3102 may determine the status of each queue during the scan. For example, the queue monitor 3102 may determine the length of each queue during the scan. In some embodiments, if the queue monitor 3102 determines that a queue has an error status, it may request the reporting module 3104 to display the error status on a display device. For example, the queue monitor 3102 may determine that the length of the queue is continuously increasing. In response, the queue monitor 3102 may request the reporting module 3104 to display an error indicating that the particular queue has an incorrect length.

[0233]

[0323] 32 illustrates an example of adjusting a sweep speed for a display module 2618, according to some embodiments. FIG. 32 includes a live view display area 3202 and a sweep speed 3204. FIG. 32 will be discussed with reference to FIG.

[0234]

[0324] The live view display area 3202 may include a near real-time display of the display module 2618. In Figure 32, the live view display area 3202 includes a near real-time display of 14 different signals (eg, processed signals or base signals).

[0235]

[0325] The sweep speed 3204 may be a GUI widget that allows a user to select a sweep speed for the live view display 3202. The sweep speed may represent a time scale of one or more signals displayed in the live view display area 3202. For example, the sweep speed may range from 10 mm / sec to 1000 mm / sec. In FIG. 32, the sweep speed 3204 appears to be selected to be 50 mm / sec. As will be appreciated by those skilled in the art, the selection of the sweep speed can affect the level of detail displayed and therefore may be set based on the size of the display screen.

[0236]

[0326] 33 illustrates signal management for the display module 2618, according to some embodiments. FIG 33 includes a signal management window 3302. FIG 33 will be discussed with reference to FIG 26.

[0237]

[0327] The signal management window 3302 may include available signals 3304 and signal settings 3306. The available signals 3304 may include one or more signals that may be selected for display by the display module 2618. For example, in FIG. 33, the available signals 3304 includes 14 signals that may be selected for display by the display module 2618. The available signals 3304 may display various information around each signal. For example, the available signals 3304 may display the name of the signal and whether or not the signal is processed by a particular signal module 2614.

[0238]

[0328] Signal settings 3306 may display various settings that may be set for each signal. For example, in FIG. 33, signal settings 3306 may allow a user to rename each signal or assign a specific color to each signal. These settings may be stored in display settings 3006 of display module 2618. Signal settings 3306 also allows a user to change various processing parameters associated with each signal. These processing parameters may be stored in one or more signal processing parameters of DSP 2904 of signal module 2614 associated with a given signal.

[0239]

[0329] 34 illustrates an example of adjusting the zoom and clip factors for a display module 2618, according to some embodiments. FIG. 34 includes a live view display area 3402 and a display settings window 3404. FIG. 34 will be discussed with reference to FIG.

[0240]

[0330] The live view display area 3402 may include a near real-time display of the display module 2618. In Figure 34, the live view display area 3402 includes a near real-time display of 14 different signals (eg, processed signals or base signals).

[0241]

[0331] The display settings window 3404 may include a zoom factor 3406 and a clip factor 3408. The zoom factor 3406 may be a GUI widget to select a zoom factor for a particular signal in the live view display area 3402. The selected zoom factor may increase or decrease the size of the particular signal. For example, the zoom factor 3406 may increase the size of the particular signal from 0.02 to 40 times.

[0242]

[0332] Clip rate 3408 may be a GUI widget that allows a user to select a clip rate for a particular signal in the live view display area 3402. The selected clip rate may control how much the signal overshoots across the display screen. For example, a user may adjust the clip rate to reduce the actual area in which a particular signal is displayed so that it does not extend beyond the entire display screen such that it is partially invisible if it is large.

[0243]

[0333] 35 illustrates pattern search management for the display module 2618, according to some embodiments. FIG. 35 includes a live view display area 3502 and a pattern search window 3504. FIG. 35 will be discussed with reference to FIG.

[0244]

[0334] The live view display area 3502 may include a near real-time display of the display module 2618. The pattern search window 3504 may be a GUI window that allows a user to load or specify a signal pattern to search for. For example, in FIG. 35, a user may create or load a search for late potentials or pre-excitation in one or more signals. The user may also specify various parameters for the search, such as a search interval, a beat detection confidence percentage, a detection confidence percentage, or other parameters, as will be appreciated by those skilled in the art. The signal pattern to search for may be stored in one or more signal processing parameters of the DSP 2904 of the signal module 2614 associated with a given signal.

[0245]

[0335] 36 shows late potential search results highlighted in a display of the display module 2618, according to some embodiments. FIG 36 includes a live view display area 3602. FIG 36 will be discussed with reference to FIG 26.

[0246]

[0336] The live view display area 3602 may include a near real-time display of the display module 2618 following a late potential search. A user may create or load a search for late potentials as previously shown in FIG. 35. Once a search is started, the live view display area 3602 may display the late potentials found in one or more signals. The live view display area 3602 may display the found late potentials along with a detection confidence percentage. For example, in FIG. 36, a found late potential 3604 is shown with a detection confidence of 83%. The live view display area 3602 may also display a tally of the total found late potentials.

[0247]

[0337] 37A illustrates the use of a display module 3618 configured as a waterfall view, according to some embodiments. FIG. 37A includes a live view display area 3702. FIG. 37A is discussed with reference to FIG.

[0248]

[0338] The live view display area 3702 can include a near real-time display of the display module 2618. The live view display area 3702 can display the near real-time display of the display module 2618 using a waterfall view. In a waterfall view, signals can be displayed side-by-side and stacked vertically as patterns match. Specifically, a user can select a matching pattern (e.g., a predefined heartbeat pattern) in a first signal. When that pattern is detected in the first signal, the display module 2618 can display the portion of the first signal that matches the pattern next to a corresponding portion of a second signal (e.g., an IC signal). A user can select the size of the portion of the first signal and the size of the portion of the second signal to display. For example, a user can select the size of the portion of the first signal using a time interval (e.g., 150 milliseconds).

[0249]

[0339] In a waterfall view, each time a pattern is detected in the first signal, the display module 2618 may display each new portion of the first signal that matches the pattern vertically with the corresponding portion of the second signal, In other words, in a waterfall view, the display module 2618 may display the signals along a vertical time axis.

[0250]

[0340] In FIG. 37A, live view display area 3702 shows a near real-time display of two different signals (e.g., V2[P1] and AB1.d) in a waterfall view. In FIG. 37A, signals V2[P1] and AB1.d are displayed side-by-side, stacked. For example, at about the 10 second time point, signal portion 3704 is displayed side-by-side with signal portion 3706. Signal portion 3704 shows the approximate real-time display of two different signals (e.g., V2[P1] and AB1.d) in a waterfall view. Signal portion 3706 may represent a corresponding portion of signal AB1.d at the time that a given pattern matches signal V2[P1].

[0251]

[0341] Users (e.g., physicians) find the waterfall view advantageous. First, the waterfall view allows the user to compare corresponding portions of two signals side-by-side. Second, the waterfall view allows the signals to be displayed longer on the display screen because the signals are stacked vertically. In contrast, when signals are displayed from left to right, it is often difficult for the user to analyze the signals because after a short period of time the signals are no longer visible on the display screen.

[0252]

[0342] Figure 37B illustrates the correspondence between signals for a normal display module 2618 and a display module 2618 configured as a waterfall view, according to some embodiments. Figure 37B includes a live view display area 3708 and a waterfall view 3710. Figure 37B is discussed with reference to Figure 26.

[0253]

[0343] 37B, the live view display area 3708 shows a near real-time display of two different signals (e.g., V2[P] and AB1.d). The waterfall view 3710 shows a near real-time display of the same two signals, except that signals V2[P] and AB1.d are displayed side-by-side to appear stacked. In the waterfall view 3710, each time a signal pattern in a signal is detected, the display module 2618 can vertically display the portion of the signal that matches the signal pattern along with the corresponding portion of a second signal.

[0254]

[0344] For example, in FIG. 37B, signal portion 3712 of signal V2[P1] includes a signal pattern. Corresponding signal portion 3714 of signal AB1.d corresponds to signal portion 3712 at the time of detection. In FIG. 37B, waterfall view 3710 displays signal portion 3712 and corresponding signal portion 3714 side-by-side (e.g., together) each time the signal pattern is detected in signal V2[P1]. In FIG. 37B, waterfall view 3710 displays the portions of signal V2[P1] that match the signal pattern along with the corresponding portions of signal AB1.d from oldest to newest. In other words, in FIG. 37B, waterfall view 3710 displays heart beats that scroll up with the oldest heart beat at the top and the newest heart beat at the bottom. As will be appreciated by those skilled in the art, waterfall view 3710 can display heart beats in a variety of other ways, such as the newest heart beat at the top and the oldest heart beat at the bottom.

[0255]

[0345] 37C illustrates the use of a display module 2618 configured as a dynamic view, according to some embodiments. FIG. 37C includes a live view display area 3716. FIG. 37C is discussed with reference to FIG.

[0256]

[0346] The live view display area 3716 can include a near real-time display of the display module 2618. The live view display area 3716 can display a near real-time display of the display module 2618 using a dynamic view. In the dynamic view, the user can select a trigger for the signal (e.g., coincidence with a stored heartbeat). The user can select a trigger from multiple trigger types. The trigger type can be a signal characteristic of interest that is related to a secondary event of interest. Once a trigger occurs, the display module 2618 can dynamically adjust the offset of the signal to be pinned to the baseline. This can prevent the signal from progressing off the display screen. This can be useful in a clinical environment, for example, where the height of a signal peak can indicate a particular type of lesion and a signal plateau can indicate the effectiveness of an ablation lesion. and are often important.

[0257]

[0347] In FIG. 37C, the live view display area 3716 shows a reference heartbeat measured with a unipolar signal (e.g., Uni1) at a reference time point (e.g., reference time point 3724). For example, this may occur during ablation. In FIG. 37C, signal 3718 may be the initial heartbeat, signal 3720 may be the current heartbeat, and signal 3722 may be the maximum recorded heartbeat since signal Uni1 was acquired at reference time point 3724. As described above, in the dynamic view, the user may specify a reference location that determines the point of the signal that is pinned to the baseline. In FIG. 37C, this point is at a pin location 3726 (e.g., 0.0 mV) on the screen for signal Uni1. This allows signal Uni1 to be offset to be pinned to the pin location 3726.

[0258]

[0348] 37D illustrates the use of a display module 2618 configured as a trigger view, according to some embodiments. FIG 37D includes a live view display area 3728 and a trigger view 3730. FIG 37D is discussed with reference to FIG 26.

[0259]

[0349] The live view display area 3728 can include a near real-time display of the display module 2618. In FIG. 37D, the trigger view 3730 shows a display of the live view display area 3728 using the trigger view. In the trigger view 3730, a user can select a first signal (e.g., a pacing signal 3732) that triggers the display of other signals (e.g., an II signal 3734, a Uni Dist signal 3736, and a Uni Prox signal 3738). The user can select a particular trigger for the first signal. The user can select a trigger from multiple trigger types. The trigger type can be a signal characteristic of interest that is related to a secondary event of interest. For example, the user can select a particular voltage (e.g., 60 millivolts) for the first signal. One skilled in the art will appreciate that other signal characteristics can be selected. When a trigger occurs, the display module 2618 can display the designated signal or signals, synchronized in time and stacked vertically on the display. A user (e.g., a physician) can find the trigger view advantageous. This is because it allows a user to more easily see the events occurring relative to an event (eg, the onset of pacing signal 3732).

[0260]

[0350] In the trigger view 3730, the user can also specify a time point after the trigger occurs at which the data is pinned to the baseline. For example, in FIG. 37D, the user sets the time to approximately 70 ms after the trigger occurs. In FIG. 37D, the Uni The Dist signal 3736 and the Uni Prox signal 3738 are pinned and are always displayed in the trigger view 3730. In contrast, in Figure 37D, the Uni Dist signal 3736 and the Uni Prox signal 3738 are not displayed in the live view display area 3728 because they are not pinned to the baseline.

[0261]

[0351] Figure 38 illustrates the capture of a signal on a display of the display module 2618 configured as a review window, according to some embodiments. Figure 38 includes a live view display area 3802 and a review window 3804. Figure 38 will be discussed with reference to Figure 26.

[0262]

[0352] The live view display area 3802 may include a near real-time display of the display module 2618. The review window 3804 may include a previous display shown in the live view display area 3802. To import a file, the user can submit a request to import the file. For example, in FIG. 38, the user can click the Review button 3806. In response, the review module 2624 can determine a capture configuration for the display module 2618. The capture configuration can include one or more active signal modules 2614 for the display module 2618, a capture time, a selected view for the display module 2618, a color scheme for one or more display signals, and various other settings, as will be appreciated by those skilled in the art. After determining the capture configuration, the review module 2624 can apply the capture configuration to previously stored signal samples and display the output in the review window 3802.

[0263]

[0353] Figure 39 illustrates amplitude measurements made in a display of the display module 2618 configured as a review window, according to some implementations. Figure 39 includes a live view display area 3902 and a review window 3904. Figure 39 will be discussed with reference to Figure 26.

[0264]

[0354] The live view display area 3902 may include a near real-time display of the display module 2618. The review window 3904 may include a previously captured display shown in the live view display area 3802. In the review window 3904, a user may analyze the previously captured output using vertical and horizontal calipers. The horizontal calipers may be a GUI selection widget. A user may use the horizontal calipers to measure the amplitude in millivolts (mV) for a particular signal. For example, as shown in FIG. 39, a user may click on the top and bottom of the V1 signal to generate two horizontal lines (e.g., caliper lines 3908 and 3910). A user may then hover a cursor along the V signal to view the measured amplitude (e.g., measurement value 3906) at a particular time point. Similarly, the vertical calipers may also be a GUI selection widget. A user may use the vertical calipers to measure time in milliseconds or beats per minute (BPM). The user can click at left and right points along the signal to create two vertical lines and display the measured time or beats per minute between the two vertical lines, as shown in Figure 65. For example, the time between vertical caliper 6502 and vertical caliper 6504 is 464 msec or 129 BPM, as shown in pop-up box 6506.

[0265]

[0355] The following description of methods for processing and displaying multiple signals in near real-time is provided for embodiments related to visualization of ECG and IC signals, but those skilled in the art will appreciate that these methods are equally applicable to visualization of other small physiological signals.

[0266]

[0356] FIG. 40 is a flowchart of a method 4000 for processing and displaying multiple signals in near real-time, according to some embodiments.

[0267]

[0357] The method 4000 will be described with reference to Figure 26. However, the method 4000 is not limited to that example embodiment.

[0268]

[0358] In 4002, the configure path module 2620 configures one or more signal modules 2614. 4002 can be implemented by the method 4100 of FIG.

[0269]

[0359] At 4004, the input module 2604 receives one or more signal samples for one or more signals. For example, the input module 2604 may receive one or more signal samples for an IC signal and one or more signal samples for an ECG signal. The method 4400 of FIG. 44 may perform 4004.

[0270]

[0360] At 4006 , the input module 2604 dispatches one or more signal samples to a packetizer 2606 .

[0271]

[0361] At 4008, the packetizer 2606 converts the one or more signal samples into one or more packets. 4008 may be performed by the method 4500 of FIG.

[0272]

[0362] In 4010, the packetizer 2606 dispatches one or more packets to the queuing module 2608. 4010 may be implemented by the method of FIG.

[0273]

[0363] At 4012, a packet dispatcher 2610 dispatches the packet from the queuing module 2608 to a signaling module 2614 associated with the packet. 4012 may be implemented by the method of FIG.

[0274]

[0364] At 4014, the signal module 2614 of 4012 processes the packet using the DSP 2904. 4014 may be implemented according to the method of FIG.

[0275]

[0365] At 4016, a display module 2618 associated with the signal module 2614 of 4012 displays the processed packets on a display screen. 4016 may be implemented by the method 4900 of FIG.

[0276]

[0366] FIG. 41 is a flowchart of a method 4100 of configuring one or more signal modules 2614 according to some embodiments.

[0277]

[0367] The method 4100 will be described with reference to Figure 26. However, the method 4100 is not limited to that example embodiment.

[0278]

[0368] At 4102, the signal configuration module 2802 may receive one or more signal processing specifications. The signal processing specifications may specify a base signal to be processed, input and output packet queue lengths for the signal module 2614, a digital signal processing function by which the base signal is to be processed, and one or more associated parameters for the digital signal processing function. In some embodiments, the signal configuration module 2802 may receive the signal processing specifications from a file stored in memory. In some other embodiments, the signal configuration module 2802 may receive the signal processing specifications from a GUI that allows a user to manually input the signal processing specifications.

[0279]

[0369] At 4104 , the signal configuration module 2802 dispatches one or more signal processing specifications to the signal factory module 2804 .

[0280]

[0370] At 4106, the signal factory module 2804 generates a signal module 2614 for each signal processing specification. 4106 may be implemented by the method 4200 of FIG.

[0281]

[0371] FIG. 42 is a flowchart of a method 4200 for generating a signal module 2614 from a signal processing specification according to some embodiments.

[0282]

[0372] The method 4200 will be described with reference to Figure 26. However, the method 4200 is not limited to that example embodiment.

[0283]

[0373] In 4202, the signal factory module 2804 generates an input packet queue 2902 for the signal module 2614 based on the signal processing specification in 4106 of Figure 41. For example, the signal factory module 2804 generates the input packet queue 2902 by creating a queue data structure of a length specified in the signal processing specification.

[0284]

[0374] At 4204, the signal factory module 2804 generates an output packet queue 2906 for the signal module 2614 based on the signal processing specification. For example, the signal factory module 2804 generates the output packet queue 2806 by creating a queue data structure of a length specified in the signal processing specification.

[0285]

[0375] At 4206, the signal factory module 2804 generates a DSP 2904 for the signal module 2614 using the DSP factory module 2808 based on the signal processing specification. Specifically, the signal factory module 2804 may request the DSP module 2808 to generate the DSP 2904 based on a signal processing function and one or more signal processing parameters specified in the signal processing specification. For example, the DSP factory module 2808 may generate the DSP 2904 based on a low pass filter function and a predetermined cutoff frequency specified in the signal processing specification.

[0286]

[0376] At 4207, the signal factory module 2804 connects together the input packet queue 2902 of the signal module 2614, the generated DSP 2904, and the generated output packet queue 2906. Specifically, the signal factory module 2804 connects the output of the input packet queue 2902 to the input of the DSP 2904. The signal factory module 2804 also connects the output of the DSP 2904 to the input of the output packet queue 2906.

[0287]

[0377] At 4210, the signal factory module 2804 configures the input packet queue 2902 to receive the dispatched packets from the packet dispatcher 2610. In some embodiments, the signal factory module 2804 may add a rule to a lookup table associated with the packet dispatcher 2610. The rule may specify that packets associated with a given signal may be processed by a given signal module 2614.

[0288]

[0378] At 4212, the signal factory module 2804 uses the DSP delay equalizer 2806 to equalize the associated processing delay of each created signal module 2614 such that each signal module 2614 outputs its processed packets to its output packet queue 2906 at the same point in time. 4210 can be implemented by the method 4300 of FIG.

[0289]

[0379] FIG. 43 is a flowchart of a method 4300 for equalizing processing delays associated with each DSP 2904 of one or more signal modules 2614 according to some embodiments.

[0290]

[0380] The method 4300 will be described with reference to Figure 26. However, the method 4300 is not limited to that example embodiment.

[0291]

[0381] At 4302, the DSP delay equalizer 2806 requests a processing delay associated with each DSP 2904 of one or more signal modules 2614. The DSP delay equalizer 2806 can request a processing delay of a DSP 2904 using the API of its associated signal module 2614.

[0292]

[0382] At 4304 , the DSP delay equalizer 2806 receives the processing delays of the DSP 2904 from each of the one or more signal modules 2614 .

[0293]

[0383] At 4306, the DSP delay equalizer 2806 determines a maximum processing delay among the one or more received processing delays.

[0294]

[0384] At 4308, the DSP delay equalizer 2806 sets the DSP 2904 of each of the one or more signal modules 2614 to a maximum processing delay. For example, the DSP delay equalizer 2806 can use an API to set the processing delay of the DSP 2904 of each signal module 2614. In response, each DSP 2904 can be designed to process a packet using its digital processing capabilities and output the processed packet to the output packet queue 2906 at the end of the maximum processing delay. In some embodiments, if the DSP 2904 completes processing of the packet using its digital processing capabilities before the end of the maximum processing delay, it can block its output to the output packet queue 2906.

[0295]

[0385] FIG. 44 is a flowchart of a method 4400 of receiving one or more signal samples for one or more signals using the input module 2604 according to some embodiments.

[0296]

[0386] The method 4400 is described with reference to Figure 26. However, the method 4400 is not limited to that example embodiment.

[0297]

[0387] At 4402, the input module 2604 receives signal samples for a base signal from a hardware device (e.g., electrodes attached to the patient) or from data stored in a computer file. For example, the computer file may contain a previously recorded session of signal samples received from the hardware device. As will be appreciated by those skilled in the art, the input module 2604 may receive signal samples for multiple base signals simultaneously.

[0298]

[0388] At 4404 , the input module 2604 dispatches the received signal samples to a packetizer 2606 .

[0299]

[0389] FIG. 45 is a flowchart of a method 4500 of converting one or more signal samples into one or more packets using a packetizer 2606 according to some embodiments.

[0300]

[0390] The method 4500 will be described with reference to Figure 26. However, the method 4500 is not limited to that example embodiment.

[0301]

[0391] At 4502 , a packetizer 2606 receives one or more signal samples from an input module 2604 .

[0302]

[0392] At 4504, the packetizer 2606 can optionally pre-process one or more signal samples. For example, the packetizer 2606 can The binary values ​​of the signal samples may be converted to their corresponding physical values. As will be appreciated by those skilled in the art, the packetizer 2606 may perform various other types of pre-processing.

[0303]

[0393] At 4506, the packetizer 2606 generates a packet including one or more signal samples for a given base signal. The packetizer 2606 may store a predefined number of signal samples in the packet. In some embodiments, the packetizer 2606 may use a timer 2605 to ensure that each packet includes the same number of signal samples. Specifically, the packetizer 2606 may store signal samples received from the input module 2604 in the packet until the timer 2605 is triggered.

[0304]

[0394] At 4508, the packetizer 2606 assigns a tag to the generated packet. The tag may correspond to a period during which one or more signal samples in the packet were received. The packetizer 2606 may assign a new tag to each subsequent packet. For example, the packetizer 2606 may initially generate a packet containing 16 signal samples for a given base signal. In this case, the packetizer 2606 may store a first set of signal samples in the packet with a tag of 0. The packetizer 2606 may store a second set of signal samples in the packet with a tag of 15. The packetizer 2606 may store subsequent sets of signal samples in the packet with tags of 31, 47, 64, etc.

[0305]

[0395] FIG. 46 is a flow chart of a method 4600 of dispatching a packet including one or more signal samples to a queuing module 2608 according to some embodiments.

[0306]

[0396] The method 4600 is described with reference to Figure 26. However, the method 4600 is not limited to that example embodiment.

[0307]

[0397] At 4602, the packetizer 2606 determines a base signal associated with the newly generated packet.

[0308]

[0398] At 4604, the packetizer 2606 determines a queue 2702 of the queuing module 2608 associated with the determined base signal. The packetizer 2606 can use a lookup table to determine that the queue 2702 is associated with the determined base signal.

[0309]

[0399] At 4606 , the packetizer 2606 dispatches a packet containing one or more signal samples to the determined queue 2702 .

[0310]

[0400] FIG. 47 is a flowchart of a method 4700 of dispatching a packet from the queuing module 2608 to the signaling module 2614 associated with the packet, according to some embodiments.

[0311]

[0404] The method 4700 is described with reference to Figure 26. However, the method 4700 is not limited to that example embodiment.

[0312]

[0402] At 4702 , the packet dispatcher 2610 continuously scans the queues 2702 in the queuing module 2608 .

[0313]

[0403] At 4704 , the packet dispatcher 2610 detects a new packet in the queue 2702 .

[0314] At 4706, the packet dispatcher 2610 determines which one or more signal modules 2614 in the global signal table 2612 are designed to process the new packet. Because the new packet can be dispatched to multiple signal modules 2614 (e.g., multiple copies or "instances" of the packet), the base signal associated with the packet can be processed simultaneously using different digital processing capabilities of the signal modules 2614.

[0315]

[0405] In some embodiments, the packet dispatcher 2610 can use the global signal table 2612 to determine one or more signal modules 2614 that are designed to process an instance of a new packet. For example, the global signal table 2612 can be a fixed size array. Each element of the array can be associated with a given base signal and therefore a given queue 2702. Furthermore, each element of the array can be a fixed size array itself. Each element of this sub-array can be associated with a given signal module 2614. Thus, the packet dispatcher 2610 can determine one or more signal modules 2614 that are designed to process a new packet by examining the corresponding element in the sub-array that is associated with the base signal of the new packet.

[0316]

[0406] In some other embodiments, the packet dispatcher 2610 may use a lookup table to determine one or more signal modules 2614 that are designed to process a new packet. In particular, the lookup table may map queues 2702 to one or more signal modules 2614.

[0317]

[0407] At 4706, the packet dispatcher 2610 dispatches the new packet for processing to the determined signal module(s) 2614 in the global signal table 2612. Specifically, the packet dispatcher 2610 inserts the new packet into the input packet queue 2902 of the determined signal module(s) 2614.

[0318]

[0408] FIG. 48 is a flow chart of a method 4800 of processing a packet using a packet-associated signal module 2614 according to some embodiments.

[0319]

[0409] The method 4800 is described with reference to Figure 26. However, the method 4800 is not limited to that example embodiment.

[0320]

[0410] At 4802, the DSP 2904 detects whether a new packet is available in the input packet queue 2902 of the signal module 2614. In some embodiments, the DSP 2904 can scan the input packet queue 2902 for a new packet to process. In other embodiments, the DSP 2904 can get notification that a new packet is available in the input packet queue 2902.

[0321]

[0411] At 4804 , the DSP 2904 gets a new packet from the input packet queue 2902 of the signal module 2614 .

[0322]

[0412] In the 4806, the DSP2904 performs the associated digital signal processing functions. In some embodiments, DSP 2904 may use its digital processing function to process a new packet. Specifically, DSP 2904 may apply its digital processing function to one or more signal samples in the packet. In some embodiments, DSP 2904 may control how it uses its digital processing function to process a packet based on one or more signal processing parameters designed for DSP 2904.

[0323]

[0413] At 4808, the DSP 2904 outputs the processed packets to the output packet queue 2906. In some embodiments, the DSP 2904 may output the processed packets to the output packet queue 2906 based on its designed maximum processing delay.

[0324]

[0414] FIG. 49 is a flowchart of a method 4900 for displaying processed packets on a display screen using the display module 2618 according to some embodiments.

[0325]

[0415] The method 4900 will be described with reference to Figure 26. However, the method 4900 is not limited to that example embodiment.

[0326]

[0416] At 4902, the display module 2618 determines one or more signal modules 2614 for which to display the processed packets. In some embodiments, the display module 2618 may determine one or more signal modules 2614 for which to display the processed packets by maintaining a reference to the output packet queue 2906 of the one or more signal modules 2614. The display module 2618 may store the reference in a local signal table 3002.

[0327]

[0417] At 4904 , the display module 2618 detects that a new packet is available in the output packet queue 2906 of one of the determined signal modules 2614 .

[0328]

[0418] At 4906 , the display module 2618 receives a new packet from the output packet queue 2906 of one of the determined signal modules 2614 .

[0329]

[0419] In 4908, the display module 2618 determines a tag associated with the new packet.

[0330]

[0420] At 4910, the display module 2618 receives a new packet from the other output packet queue 2906 that matches the determined tag.

[0331]

[0421] At 4912, the display module 2618 simultaneously displays the received new packets for one or more determined signal modules on a display screen. The display module 2618 synchronizes the display of the signal associated with the new packets to display new packets having the same tag.

[0332]

[0422] Methods 4000, 4100, 4200, 4300, 4400, 4500, 4600, 4700, 4800, 4900 may be performed by processing logic that may include hardware (e.g., circuits, dedicated logic circuitry, programmable logic circuitry, microcode, etc.), software (e.g., instructions executing on a processing device), or a combination thereof. It should be understood that not all steps may be required to practice the disclosure provided herein. Furthermore, as will be appreciated by one of ordinary skill in the art, some of the steps may be performed simultaneously or in a different order than that shown in Figures 40-49.

[0333]

[0423] In some embodiments, the DSP2904 can be based on a notch filter. Electrophysiology laboratories with a large amount of equipment can tend to have substantial power line frequencies and harmonics (e.g., noise) that interfere with cardiac recordings. In North America, this can be primarily 60 Hz plus harmonics. Figure 50 shows an example of a signal (e.g., triangular spike 5002) with 60 Hz noise 5004 superimposed, according to some embodiments.

[0334]

[0424] To obtain accurate cardiac recordings, it is often desirable to remove noise while preserving the signal of interest. A conventional approach to removing 60 Hz noise involves using a notch filter with zero transmission at 60 Hz. Figure 51 shows an example of a conventional approach to removing 60 Hz noise using a notch filter with zero transmission (single notch) 5102 at 60 Hz, according to some embodiments.

[0335]

[0425] FIG. 52 shows an example of the results of applying the conventional filter of FIG. 51, according to some embodiments. As shown in FIG. 52, the 60 Hz signal is removed from the input signal 5202 to generate a filtered signal 5204. However, conventional filters can have several problems. For example, after a large spike 5206, the conventional filter can introduce overshoot and ringing (e.g., transient response) into the signal. This overshoot and ringing may be artifacts of the filter and not part of the original input signal. This can result in a less accurate signal recording.

[0336]

[0426] Furthermore, a conventional 60Hz notch filter may not reduce any harmonics of 60Hz. For example, as shown in Figure 53, if the interference in the input signal 5302 is evaluated at both 60Hz and 180HZ, the 180Hz harmonic may still be present at the output of the conventional filter. Figure 53 shows an example of the 180Hz harmonic still present in the filtered signal 5304 at the output of the conventional filter of Figure 51 according to some embodiments.

[0337]

[0427] Thus, as shown in Figure 53, there can be two problems with a conventional notch filter. First, a conventional notch filter can introduce overshoot and ringing 5306 into the signal. Second, a conventional notch filter may not reduce any of the higher level harmonics.

[0338]

[0428] In some embodiments, the DSP2904 can apply a notch filter that does not introduce overshoot and ringing to the signal and reduces not only the first harmonic but also higher level harmonics. The DSP2904 notch filter can solve the above technical problems of conventional notch filters by extracting the interference noise and subtracting it from the noisy signal. This can remove the interference without generating artifacts (e.g., overshoot and ringing) associated with conventional notch filters. The DSP2904 notch filter can replicate one cycle of the interference signal in a separate buffer (also referred to as a cycle buffer, noise buffer, or data buffer) and subtract it from the noisy signal to extract the original data. Since the power line frequency noise can be constant or nearly constant, the DSP2904 notch filter can use some variation of averaging to refine the estimate over time. Since the frequency can be known, the buffer size can be determined in advance. Furthermore, a buffer that stores exactly one cycle can also store an integer number of higher frequency harmonics that can be subtracted from the noisy data. FIG. 54 shows an example of notch filtering of the DSP2904 for a signal containing 60 Hz and 180 Hz noise, according to some embodiments. Since power line frequency noise is constant, it replicates one cycle of interference 5402. , can be subtracted from each cycle 5404 of successive cycles in the input signal.

[0339]

[0429] For 60 Hz noise and a sample rate of 2000 samples / second, the buffer can store 33 1 / 3 samples. Since there can be an integer number of samples in the buffer, the notch filter of the DSP2904 can be selected to use 100 samples and store exactly 3 cycles of 60 Hz. Figure 55 shows an example of a notch filter of the DSP2904 that uses 100 samples of the input signal 5502 and stores exactly 3 cycles of 60 Hz 5504, according to some embodiments.

[0340]

[0430] To accumulate stationary noise in a buffer, data can be collected during the "quiet times" of the waveform. As will be appreciated by those skilled in the art, quiet times can be periods of time in the input signal where there are no large spikes or edges. Quiet times can be determined by calculating the slope of the signal. FIG. 56 shows an example of a notch filter in the DSP2904 calculating quiet times in an input signal 5602, according to some embodiments. During quiet times 5606, three cycles of noise data (interference) 5604 can be collected in a buffer. Subsequent cycles 5608, 5610, 5612 are averaged to build an exact replica of the interference 5604. Because the cycle times are constant for cycles 5606, 5608, 5610, 5612, one cycle of fundamental and harmonic frequencies accumulates. Cycles of other frequencies average to zero.

[0341]

[0431] For each new point sampled from the incoming data, a determination can be made to determine if it is in a "quiet time" of the signal. Quiet time can be determined by calculating the slope of the signal. If the slope is above a threshold, it can be determined that a quiet time has begun. If the new point is in a quiet time, it can be averaged with the previously stored data at that location in the buffer. As time progresses, this averaging process can accumulate a replica of the noise, which can be subtracted from the noisy signal. For those locations that are not in a quiet time, the buffer may not be updated, but the accumulated signal can still be subtracted. FIG. 57 shows an example of a notch filter of the DSP2904 by accumulating a replica of the noise for three cycles in each of the quiet times 5702, 5704, 5706, 5708 in a buffer and subtracting it from the noisy signal, according to some embodiments. Because the buffer contents 5710, 5712, 5714, 5716 match the noise data during quiet periods 5702, 5704, 5706, 5708 respectively, the noise can be more accurately modeled and, when subtracted, the noise content of the displayed signal can be significantly reduced.

[0342]

[0432] As each sample is added to the buffer, averaging can result in a filter with a peak at the power line frequency 5802 and all harmonics (5804, 5806, etc.). This allows selective accumulation of the power line frequency and all harmonics and rejection of all other frequencies, so that the notch filter of the DSP2904 subtracts only additive noise at a fixed frequency. Figure 58 shows an example of the result of a notch filter or buffer filter of the DSP2904, according to some embodiments. To generate the buffer filter shown in Figure 58, the buffer is updated, for example, by adding 5% new samples to the 95% accumulated value. In the specific context of an implementation, each new sample and other combined percentages of the accumulated value can be combined.

[0343]

[0433] 59 is a flow chart of a method 5900 of notch filtering noise from an input signal according to some embodiments. Method 5900 is described with reference to FIG. 29. However, method 5900 is not limited to that example embodiment.

[0344]

[0434] At 5902, the DSP2904 includes noise having a first harmonic frequency. and accessing an input signal having noise, the frequency of the noise in the input signal may be substantially constant.

[0345]

[0435] At 5904, the DSP 2904 determines quiet periods in the input signal. The DSP 2904 may determine the quiet periods by calculating a slope of the input signal. The DSP 2904 may then determine the presence of a quiet period based on the calculated slope being below a threshold.

[0346]

[0436] During quiet periods, the DSP 2904 stores samples of the noise of the input signal in a buffer at 5906. The size of the buffer may be based on the frequency of the noise in the input signal.

[0347]

[0437] As part of the storing, the DSP 2904 can average the samples of the input signal with corresponding samples of noise in the buffer to generate average samples. The DSP 2904 can then replace the corresponding samples of noise in the buffer with the average samples.

[0348]

[0438] At 5908, the DSP2904 subtracts the single cycle of noise in the buffer from the input signal to generate a filtered signal. The subtraction can remove the higher and second harmonic frequencies from the input signal while avoiding the introduction of transient responses (e.g., ringing) in the filtered signal. The first harmonic frequency can be 60 Hz and the second harmonic frequency can be 120 Hz or 180 Hz.

[0349]

[0439] At 5910, the DSP2904 repeats steps 5904-5908 to refine the filtered signal. As will be appreciated by those skilled in the art, the samples can be anywhere in a cycle. Furthermore, the samples need not constitute a single cycle. In other words, the DSP2904 can buffer multiple cycles of noise of the input signal.

[0350]

[0440] In some embodiments, the DSP 2904 can be based on a high pass filter. Some areas of the heart generate very low amplitude high frequency signals that may be of interest during cardiac procedures. Physicians often want these signals highlighted for their review in the presence of noise and other larger cardiac signals.

[0351]

[0441] This can be accomplished using a high pass filter. Figure 60 shows an example of a conventional high pass filter 6002, according to some embodiments. In this case, the 3db frequency 6004 of the conventional high pass filter may be approximately 200Hz to suppress low frequencies. Furthermore, since the frequencies of interest are often above the power line frequency (e.g., 60Hz), the conventional high pass filter approach may include placing a notch 6006 there to eliminate interference from possible large power line interference.

[0352]

[0442] However, a typical signal from an intracardiac catheter may contain high frequency signals from the conductive regions of the heart as well as sharp local spikes from various sources. Figure 61 shows an example of a signal that contains both high frequency signals from the conductive regions of the heart and sharp local spikes from various sources, according to some embodiments. As shown in Figure 61, there are sharp spikes 6102 that resemble local near-field impulses (e.g., QRS, local spikes, transient events, etc.) and short bursts 6104 of high frequency (e.g., 300 Hz) cardiac signals.

[0353]

[0443] Fig. 62 shows an example of the output resulting from filtering the signal of Fig. 61 using the high pass filter of Fig. 60, according to some embodiments. As shown in Fig. 62, the low frequency content (e.g., baseline fluctuations) is removed and the high frequency cardiac signal 6202 is highlighted as desired. However, the transient response of the high pass filter may leave an undesirable impulse (e.g., artifact) 6204 and some ringing in the output. In the composite and larger waveform, this impulse 6204 may be easily confused by a physician with the high frequency cardiac signal 6202. This is problematic for accurate diagnosis and treatment.

[0354]

[0444] In some embodiments, the DSP2904 can be based on a high pass filter that removes impulses while allowing high frequency signals of interest to pass. To remove impulses, the input signal can be monitored for large deviations and high signal slopes (e.g., derivatives). If these conditions are present, the output can be disabled for a period of time before and after their occurrence, so that the transient does not appear in the displayed waveform. Figure 63 shows an example of the output that results from filtering the signal of Figure 61 using a high pass filter that removes impulses 6302 while allowing high frequency cardiac signals 6304 of interest to pass, according to some embodiments.

[0355]

[0445] Figure 64 is a flow chart of a method 6400 for high-pass filtering noise from an input signal, according to some embodiments. The method 6400 is described with reference to Figure 29. However, the method 6400 is not limited to that example embodiment.

[0356]

[0446] In 6402, the DSP2904 accesses an input signal that includes noise and high frequency signals of interest. In applications of the DSP2904, rapid conduction tissue recognition filtering can be performed to, for example, identify Purkinje fibers, i.e., high isotropy / low anisotropy parts, from myocardial structures and preferential conduction pathways in diseased tissue. In such applications, the DSP2904 can access, for example, Purkinje signals, i.e., high frequency signals of interest, in the presence of noise. The DSP2904 can filter this input signal using a notch filter.

[0357]

[0447] Once artifacts are recognized in the signals of interest, they can be clearly introduced and characterized, allowing direct automation of filtering to be applied using these diagnosed signals as templates to subtract / filter or otherwise process the signals from the entirety of the retrieved electrogram. For example, the system can record signals with and without irrigation through the catheter, at constant catheter contact and catheter stability. This difference can represent artifacts, which can then be automatically characterized and used to create templates that allow the filtering and summing techniques of the system to remove the artifacts. As will be appreciated by those skilled in the art, such a system would be beneficial when employed in existing defibrillators as well as subcutaneous implantable cardioverter defibrillators (ICDs).

[0358]

[0448] In 6404, the DSP2904 high-pass filters the input signal to generate a filtered signal.

[0359]

[0449] At 6406, the DSP2904 isolates noise-related artifacts in the filtered signal from the high frequency signal of interest. For example, the DSP2904 can isolate the impulse response.

[0360]

[0450] The DSP2904 optimizes the input by calculating the slope of the filtered input. The DSP 2904 may then determine the presence of an artifact based on the calculated gradient exceeding a threshold. The DSP may characterize the artifact with an artifact template. The DSP 2904 may optionally select a filter based on the isolated artifact, such that the artifact template may be applied as a filter.

[0361]

[0451] At 6408, the DSP2904 disables the filtered signal for a period of time before and after the isolated artifact. The DSP2904 can optionally perform the disable using a selected filter. This disable can remove the isolated artifact and allow high frequency signals of interest to pass. The DSP2904 can buffer the filtered signal for a period of time before and after the isolated artifact.

[0362]

[0452] In some embodiments, the DSP 2904 can perform pattern (or signal characteristic) matching. The pattern matching of the cardiac signal can be based on some version of correlation. For example, the correlation can be a statistical correlation function or a mean absolute deviation.

[0363]

[0453] The correlation function (CF) can be specified by Equation 1:

number

[0364]

[0454] The mean absolute deviation function (MAD) can be specified by Equation 2:

number

[0365]

[0455] For surface ECGs, there may often be 12 leads in a set. For pace-matching applications, all 12 leads need to be correlated to all 12 leads of a reference beat. The reference beat may be a beat taken from when showing an abnormal beat and compared to a paced beat from a catheter during an electrophysiology procedure. In other cases, only a subset of the leads may need to be correlated. For correlation functions, a perfect match of shapes may be +1, exact opposites may be -1, and there may be no measure of amplitude similarity. For MAD functions, a perfect match may be 0, exact opposites may be 1, and amplitude differences may result in a difference in amplitude similarity. , a poorer match may result.

[0366]

[0456] For comparison of multiple leads, some measure of similarity may need to be established. This could be an average, a median, or an extension of Equation 1 or Equation 2 that adds the numerators and denominators for all leads in the set. Furthermore, a relatively larger weight could be given to leads with relatively larger amplitudes, or to certain ranges of heartbeats that represent features to be emphasized (e.g., Q waves).

[0367]

[0457] In all comparisons, the leads can be normalized to have 0 DC offset, since only the shape (and amplitude) is important in the comparison.

[0368]

[0458] In some embodiments, vertical calipers can be used to select a pattern (or signal characteristic). The vertical calipers can be a GUI selection widget. Figure 65 shows an example of a review window 6500 for selecting a range of data (usually one heart beat) using vertical calipers 6502, 6504, according to some embodiments.

[0369]

[0459] The selected pattern can then be saved as a reference heart beat (or known signal pattern). FIG. 66 illustrates an example of saving a selected pattern as a reference heart beat, according to some embodiments. The Save New Pattern window 6600 shown in FIG. 66 allows a user to view previously saved heart beats (e.g., known signal patterns) 6602 to determine whether the newly identified heart beat is unique enough to merit saving separately from the previously saved heart beats. Once a heart beat is stored, it can be given a unique name 6604, a color 6606, and / or a description (i.e., comments) 6608.

[0370]

[0460] When the user wishes to begin a search, he or she can do so by clicking on the Select Patterns button 6510 in the review window 6500 of FIG. This can open a window of selectable patterns to search. Figure 67 shows an example of a Select Patterns to Search window 6700 of selectable patterns to search, according to some embodiments. Window 6700 may display a scrollable list 6710 of all stored patterns. Check boxes 6720 to the left of each list item allow the user to select the associated pattern. Selections may remain valid until the user decides to change them. As the user clicks on each pattern in list 6710, a corresponding signal may be displayed below the list box in window 6730. Window 6730 may also display a field that allows the user to enter a confidence factor threshold (also referred to as pattern detection threshold 6740) that can be used to detect the pattern. For example, in FIG. 67, pattern detection threshold 6740 is set to 80%.

[0371]

[0461] After selecting the patterns to search and clicking OK 6750, the user can enable the search by clicking the Enable / Disable Patterns search button 6512 to start the search, which can be enabled in the review window 6500 shown in FIG. 65. After clicking this button, the search for patterns can be started and the heart beats that match the reference heart beat (e.g., have a confidence level equal to or greater than the selected confidence factor threshold) are displayed in the review window 6500. The found patterns can be displayed in two different modes in the review window 6500 of FIG. 65, namely, a summary view and a detailed view. As shown in the review window 6800 of FIG. 68, the user can click the button Summary or Detailed View to display the patterns. Buttons 6802 and Detail 6804 can be used to toggle between these two modes.

[0372]

[0462] In the Summary View, segments of the displayed signal in the Review Window that match a pattern may be highlighted in a color associated with each pattern. Multiple patterns may overlap the same segment of the signal. In the Summary View, the overlapping portions may be displayed in different colors to make the patterns more recognizable and distinguishable within each segment.

[0373]

[0463] FIG 68 shows an example of a pattern search summary view in the review window of FIG 65 with multiple matching patterns displayed, according to some embodiments. As shown in FIG 68, four portions 6806, 6808, 6810, 6812 of a surface ECG signal are highlighted in the review window 6800. In this example, the two portions 6806, 6808 on the left side are displayed in two colors (or line styles), which may mean that the patterns in these portions overlap. The two portions 6810, 6812 on the right side are displayed in the color assigned to pattern P1, which indicates that only the P1 pattern was found in those portions.

[0374]

[0464] FIG. 69 shows an example of the pattern search summary view 6900 in the review window of FIG. 68, where a single matching pattern is displayed but other patterns are hidden, according to some embodiments. When the matched pattern segments are displayed, a small window 6910 can be displayed on the right side. This window allows the user to show or hide the matched portion associated with each found pattern. In its initial state, all of the found patterns can be checked. When the user unchecks the checkboxes 6912, 6914 beside each pattern name, the corresponding highlighted portion is hidden. As shown in FIG. 69, the matched portions 6810, 6812 associated with pattern P1 6916 are hidden. Thus, the solid color portions 6810, 6812 of FIG. 68, which are on the right side and matched only with pattern P1, are not displayed in FIG. 69. However, the left portions 6806, 6808 where patterns P1 and P4 overlapped, are now displayed in FIG. 69 in the color associated with pattern P4 6918.

[0375]

[0465] In the detail view, pattern details can be shown one segment at a time. The detail view can be enabled by selecting detail 6804 in the review signal 6800 of FIG. 68. In the detail view, the actual pattern can be displayed above the matched segment using the color assigned to the pattern. FIG. 70 shows an example of a detail view for a signal in the review window of FIG. 65, according to some embodiments.

[0376]

[0466] As shown in FIG. 70, the detail view 7000 may show pattern details one segment at a time. For each portion, if multiple patterns overlap, the pattern with the highest confidence factor may be shown first. However, the user may select to see other overlapping patterns (e.g., having lower confidence values) by clicking on their associated checkboxes 7002, 7004 in the detail view list 7006. In this case, the signals displayed in the detail view 7000 may automatically change to reflect the newly selected pattern. For example, as shown in FIG. 70, pattern P1 7008 has the highest confidence value (e.g., 87.0%) and is therefore shown first.

[0377]

[0467] In the detailed view, you can view the confidence values ​​per lead using the horizontal bars in the Confidence Factor Per Lead table 7010, as shown in Figure 7. As shown in Table 70, above the bars, actual confidence values ​​may be provided. For example, lead I 7012 shows a confidence value of 79.6%. Confidence values ​​above a confidence level set by the user (e.g., when a retrieved pattern is selected) may be displayed in, for example, green, and values ​​below this threshold may be displayed in orange, visually indicating whether the confidence level for each individual lead meets the user's desired threshold. When the user clicks on any lead name in the per-lead confidence factor table 7010, the matched portions of the corresponding patterns and signals are displayed in the Pattern and Signal Traces (Pattern and Signal Traces) located below the per-lead confidence factor table 7010. ) window 7014. Below this window there may be two buttons that allow the user to change the time 7016 and amplitude scale 7018 for the displayed signal in order to accurately view the signal's shape details. If the selected time 7016 or amplitude scale 7018 makes the signal partially visible, scroll bars may be automatically displayed to allow the user to access any part of the signal.

[0378]

[0468] The detailed view 7000 may also highlight signal segments and associated matched patterns displayed using brackets 7020. This allows a user to easily identify the portion of the signal that is shown in the detailed view 7000. The match confidence factor 7022 for that pattern may also be shown alongside one of the brackets.

[0379]

[0469] 71 illustrates an example window 7100 with pattern match confidence values ​​provided by leads (confidence factor per lead 7102) according to some embodiments. As shown in FIG. 71, leads V1 7104 and V2 7106 are below the confidence threshold and are shown in orange.

[0380]

[0470] The disclosed system also allows for the use in pattern matching of the concept of creating templates for predetermined artifact generating events, as described for the method of Fig. 64. For example, the pattern of valve motion artifacts associated with unipolar signals collected above and below the valve and in the coronary arteries can be used to create a pattern template for the operator to immediately know whether the catheter is above the valve, below the valve, or in the coronary artery. When the coronary artery profile in the pattern template is met, the system can respond, for example, by not allowing energy delivery during the ablation procedure.

[0381]

[0471] Figure 72 is a flow chart of a method 7200 of pattern matching according to some embodiments. The method 7200 is described with reference to Figure 29. However, the method 7200 is not limited to that example embodiment.

[0382]

[0472] At 7202, the DSP 2904 accesses the input cardiac signal.

[0383]

[0473] At 7204, the DSP 2904 matches a portion of the input cardiac signal with a known signal pattern. The known signal pattern may be acquired during a previous or current patient treatment and stored in a pattern template. The known signal pattern may also be stored in a database.

[0384]

[0474] The DSP 2904 can match a portion of the input cardiac signal to a known signal pattern based on a correlation function. The DSP 2904 can match a portion of the input cardiac signal to a known signal pattern based on, for example, a mean absolute deviation (MAD) function. The DSP 2904 can also match a portion of the input cardiac signal to a known signal pattern based on a confidence value. It is also possible to match code patterns.

[0385]

[0475] The display module 2618 displays an indication of the degree of match at 7206. The indication of the degree of match may specify where cardiac pacing should be performed.

[0386]

[0476] Figure 73 is a flow chart of a method 7300 of pattern matching according to some embodiments. The method 7300 is described with reference to Figure 29. However, the method 7300 is not limited to that example embodiment.

[0387]

[0477] At 7302, the DSP 2904 accesses the input cardiac signal.

[0388]

[0478] At 7304, the DSP 2904 accesses the detection threshold.

[0389]

[0479] At 7306, the DSP 2906 matches a portion of the incoming cardiac signal to a known signal pattern based on a detection threshold. The known signal pattern may be acquired during a previous patient treatment or a current patient treatment. The known signal pattern may be stored in a database.

[0390]

[0480] The DSP 2904 can match a portion of the input cardiac signal to a known signal pattern based on a correlation function. The DSP 2904 can match a portion of the input cardiac signal to a known signal pattern based on, for example, a mean absolute deviation (MAD) function.

[0391]

[0481] The DSP2904 can match a portion of the input cardiac signal to a known signal pattern based on a weighted specific region of the known signal pattern. The DSP2904 can first match a portion of the input cardiac signal to the known signal pattern. The DSP2904 can determine a first confidence value based on the first match. The DSP2904 can second match the portion of the input cardiac signal to the known signal pattern. The DSP2904 can determine a second confidence value based on the second match. The DSP2904 can average the first confidence value and the second confidence value to create an average confidence value. The DSP2904 can then determine that the average confidence value is above a detection threshold.

[0392]

[0482] At 7308, the display module 2618 displays a highlighted portion of the input cardiac signal based on the matching. The display module 2618 may display the highlighted portion of the input cardiac signal based on a color associated with the known signal pattern, for example.

[0393]

[0483] In some embodiments, the DSP2904 can perform late potential and early excitation detection. By interpolating signal data from early excitation sites, displayed independent of normal and late potential filters, to signal data from detected late excitation sites, the system can infer sites of conduction delay. The sites (or regions) can be block highlighted by any compatible 3D mapping system, allowing the physician to guide catheter placement, record slow conduction at the sites, and target the sites for ablation. These features are very difficult, if not impossible, to achieve in systems that saturate when applying gain to small signals, and therefore slow conduction sites may remain essentially invisible to the physician.

[0394]

[0484] The embodiments herein interpolate data from early excitation sites with data from detected late excitation sites and display the data independently of normal and late potential filters. Such embodiments benefit from the high dynamic range of the system, which allows for real-time (e.g., live) and session playback detection of late potentials and pre-excitations in the main signal display window. By clicking on the "create and manage searches" button in the main signal display window, the user can create late potential or pre-excitation search criteria, launch searches, and manage existing searches.

[0395]

[0485] FIG. 74 shows an example of a search definition window 7400 for creating and managing searches for late potentials and pre-excitation, according to some embodiments. To add a late potential search to the main signal display window, a user can click on the "Add Late Potentials Search" button 7402 in the search definition window (Search Definitions window 7400 of FIG. 74). In response, a late potential detection configuration window can be displayed, allowing the user to define various search parameters. FIG. 75 shows an example of a late potential detection configuration window 7500 for defining various search parameters for late potentials, according to some embodiments.

[0396]

[0486] A user may create at least one pattern that performs a late potential search. A user may specify various late potential search parameters that allow for various types of searches. As shown in FIG. 75, a user may define one or more of the following parameters: a name for the search (7502), a selection of a heartbeat pattern to be used in the search (7504), a reference point for the start of the search (7506), a selection of an ECG lead to be used for heartbeat detection (7508), a selection of an intracardiac lead to be used for late potential detection (7510), a search interval using a start time and length from a pattern reference (7512), a heartbeat detection confidence threshold as a percentage (e.g., 80%) (7514), a selection of a late potential detection confidence threshold as a percentage (e.g., 80%) (7516), and a selection of a late potential amplitude threshold (e.g., 0.015 mV) (7518). As will be appreciated by those skilled in the art, a variety of other patterns may be defined by the user.

[0397]

[0487] Once all parameters are defined, the search can be launched. Once late potentials are detected, the signal display window can show the location of the late potentials along with their detection confidence. FIG. 76 shows an example signal display window 7600 showing the location of late potentials 7602, 7604, 7606, 7608, 7610 along with their detection confidence, according to some embodiments. The review window can also show all of the detected late potentials under a search results tab. The newly created late potential search can be listed in the search definition window (e.g., search definition window 7400 of FIG. 74). The newly created late potential search can be listed under the currently defined searches section in the search definition window.

[0398]

[0488] A user can add a pre-excitation search in a manner similar to the late potential search. A user can specify various pre-excitation search parameters that allow for different types of searches. The parameters can be similar to the late potential search parameters. The difference is that the search can occur at a defined search interval before the baseline. FIG. 77 shows an example of a pre-excitation detection configuration window 7700 that defines various search parameters (similar to those described in FIG. 75) for pre-excitation, according to some embodiments.

[0399]

[0489] Once all parameters are defined in the pre-excitation detection configuration window 7700, the search can be launched. Once pre-excitations are detected, the signal display window can show the location of the pre-excitations along with their detection confidence and length. 7 shows an example signal display window 7800 showing the locations of pre-excitations 7802, 7804, 7806 along with their detection confidence, according to some embodiments. The review window may also display all detected pre-excitations under a search results tab. Newly created pre-excitation searches may be listed in a search definition window (e.g., search definition window 7400 of FIG. 74). Newly created pre-excitation searches may be listed under a currently defined search section in the search definition window.

[0400]

[0490] A user can use the search definition window to manage already defined late potential and pre-excitation searches. Figure 79 shows an example of a search definition window 7900 for managing already defined late potential and pre-excitation searches, according to some embodiments.

[0401]

[0491] In the search definition window 7900, all active searches can be listed in the Currently Defined Searches window 7902, and the user can run, stop, delete, or modify them. If a search is stopped, the user can resume the execution of the search by clicking the "Run" button 7904. For example, as shown in FIG. 79, search EA1 is stopped 7906 and search LP1 is running 7908. In this case, the user can resume the execution of the EA1 search, stop the execution of the LP1 search 7910, or use other options (e.g., delete 7912 and modify 7914).

[0402]

[0492] Fig. 80 is a flow chart of a method 8000 for detecting early excitation or late potentials, according to some embodiments. Method 8000 is described with reference to Fig. 29. However, method 8000 is not limited to that example embodiment.

[0403]

[0493] At 8002, a first DSP 2904 accesses a first cardiac signal associated with a body surface lead.

[0404]

[0494] At 8004, the first DSP 2904 matches the heart beats of the first cardiac signal with the known cardiac pattern. The first DSP 2904 can match the heart beats of the first cardiac signal with the known cardiac pattern based on a correlation function. The first DSP 2904 can match the heart beats of the first cardiac signal with the known cardiac pattern based on, for example, a mean absolute deviation (MAD) function. The first DSP 2904 can match the heart beats of the first cardiac signal with the known cardiac pattern based on a confidence value. The confidence value can be user defined.

[0405]

[0495] At 8006, the second DSP 2904 searches for early excitation or late potentials in the second cardiac signal for a period of time before and after the matching heart beat, which may be a user-defined period of time.

[0406]

[0496] The second DSP 2904 can search the buffer containing the portion of the second cardiac signal for early excitation or late potentials. The second DSP 2904 can search for early excitation based on an amplitude threshold.

[0407]

[0497] Using the early excitation or late potentials, the system can interpolate signal data from a catheter at the site of the early excitation to signal data at the site of the late potential. The system can display the signal data independent of the normal and late potential filters. Using the interpolated signal data, the system can infer sites of conduction delays. The system can also use the interpolated signal data at a site in combination with a three-dimensional mapping system to guide the placement of additional catheters, record slow conduction at the site, or target the site for ablation. .

[0408]

[0498] In some embodiments, the display module 2618 can display one or more signals using a waterfall view (e.g., the waterfall view of FIGS. 37A and 37B). The waterfall view window can vertically stack heart beats that match a selected pattern of a given ECG lead and can show a user-selected intracardiac signal alongside each detected heart beat. The user-selected intracardiac signal can be shown at a user-defined interval relative to a reference point within the heart beat pattern.

[0409]

[0499] To set parameters for the waterfall view, the user must click on the “Create Waterfall View Window” button located on the Main Signal View toolbar. In response, a waterfall view configuration window can be displayed. FIG. 81 illustrates an example of a waterfall view configuration window 8100, according to some embodiments.

[0410]

[0500] As shown in FIG. 81 , the user can define one or more of the following parameters: The user can select a heartbeat pattern 8102 to search (e.g., from already saved heartbeat patterns used in the waterfall view). The user can define a reference point 8104 in the heartbeat pattern to be used for the display interval. If a reference point is not already selected, the user can add a reference point by clicking on the heartbeat pattern display window located below the list of heartbeat patterns. Similarly, the position of an existing reference point can be changed by clicking on the heartbeat pattern display window. The user can select a surface ECG lead 8106 for heartbeat detection. The user can define a display interval 8108 for the ECG lead (e.g., start point and length relative to the pattern reference point). The user can select an intracardiac channel 8110 for the search. The user can define a display interval 8112 for the intracardiac lead (e.g., start point and length relative to the pattern reference point). The user can also select a vertical scroll mode 8114, such as time or heartbeat.

[0411]

[0501] 82 shows an example of a waterfall view 8200 using time mode, according to some embodiments. When the vertical scroll mode 8114 is set to time mode, the matched signals can be continuously scrolled up by time. Thus, the time mode can show gaps 8202 between heartbeats when no heartbeats matching the selected pattern are detected. The time mode can show the last heartbeat timestamp 8204 in the bottom left corner of the window.

[0412]

[0502] When the vertical scroll mode 8114 is set to heartbeat mode, the automatic vertical scrolling of the waterfall view window can be disabled and the heartbeats can only be scrolled up if a new heartbeat matching the selected pattern is detected. Figure 83 shows an example of a waterfall view 8300 using heartbeat mode, according to some embodiments. In heartbeat mode, each individual beat can be time-stamped 8302.

[0413]

[0503] Once all of the parameters for the waterfall view have been defined by the user, the waterfall view window can display two signals side by side as shown in both Figures 82 and 83. The waterfall view window can display the signals using either time mode or heart rate mode. The names of the leads 8304, 8306 can be shown at the top of the window. The heart rate pattern name 8208 may also be shown alongside the ECG lead name 8206.

[0414]

[0504] For example, in the toolbar of the waterfall view window there may be buttons: a waterfall parameters button 8210 and a display parameters button 8212. The waterfall parameters button 8210 allows a user to adjust display parameters while the waterfall view window is open. For example, a user may change the display interval, vertical scroll mode, or any parameter, as would be understood by one of ordinary skill in the art.

[0415]

[0505] The user can disable this feature. FIG. 84 shows an example of a display parameters window 8400, according to some embodiments. The display parameters window 8400 allows the user to change various display parameters. For example, the user can adjust the zoom 8402, 8404 for each lead, and has the option to reset 8416, 8418 to default. The user can add 8406 or remove 8408 clipping. The user can change the color 8410, 8412 for each lead or a subset of leads. The user can disable 8414 fading of the displayed heart beats. In some embodiments, the displayed heart beats can fade as they move towards the upper portion of the waterfall view window.

[0416]

[0506] In some embodiments, the EP hardware system is capable of generating a clean unipolar signal according to some embodiments. The system can generate noise-free unipolar signals based on the fact that it has an ECG circuit board and multiple IC circuit boards that share substantially the same circuit configuration and components, and that the ECG circuit board processes the ECG signal with substantially the same path that each IC circuit board uses to process its corresponding IC signal. A single Wilson Coupled Electrode (WCT) signal can be used for the ECG circuit board and multiple IC circuit boards.

[0417]

[0507] In some embodiments, the EP hardware system can act as a central processing system for all other systems. The EP hardware system can include an ECG circuit board configured to receive an ECG signal, a plurality of IC circuit boards each configured to receive an IC signal, a communication interface communicatively coupled to a remote device, and a processor coupled to the ECG circuit board, the plurality of IC circuit boards, and the communication interface. The EP hardware system can act as a central processing system by having its processor receive feedback from the remote device via the communication interface and control the remote device based on the ECG signal, the IC signal, and feedback from the remote device via the communication interface.

[0418]

[0508] The EP hardware system can receive feedback from and control remote devices selected from the group consisting of, but not limited to, ultrasound machines, radio frequency (RF) generators, stimulators, 3D imaging devices, intracardiac echocardiography (ICE) machines, fluoroscopes, and defibrillators. As will be appreciated by those skilled in the art, the remote devices can be a variety of other types of devices. The EP hardware system can communicate with the remote devices using a communication protocol selected from the group consisting of, but not limited to, Digital Imaging and Communications in Medicine (DICOM), Ethernet, Universal Serial Bus (USB), and Institute of Electrical and Electronics Engineers (IEEE) 802.11. The device can communicate with a remote device via a communication interface coupled to the device. As will be appreciated by those skilled in the art, the EP hardware system can communicate with remote devices using a variety of other communication protocols.

[0419] Computer system implementation

[0509] Various embodiments may be implemented using one or more well-known computer systems, such as, for example, computer system 8500 shown in Figure 85. For example, one or more computer systems 8500 may be used to implement any of the embodiments discussed herein, as well as combinations and subcombinations thereof.

[0420]

[0510] The computer system 8500 may include one or more processors (also referred to as central processing units or CPUs), such as a processor 8504. The processor 8504 may be connected to a communications infrastructure or bus 8506.

[0421]

[0511] The computer system 8500 may also include user input / output devices 8503 , such as a monitor, keyboard, pointing device, etc., which may communicate with a communications infrastructure 8506 via a user input / output interface 8502 .

[0422]

[0512] One or more of the processors 8504 may be a graphics processing unit (GPU). In one embodiment, a GPU may be a processor that is a special-purpose electronic circuit designed to process mathematically intensive applications. GPUs may have a parallel structure that is efficient for parallel processing of large blocks of data, such as mathematically intensive data common in computer graphics applications, images, videos, etc.

[0423]

[0513] The computer system 8500 may also include a main or primary memory 8508, such as a random access memory (RAM). The main memory 8508 may include one or more levels of cache. The main memory 8508 may store control logic (e.g., computer software) and / or data.

[0424]

[0514] The computer system 8500 may also include one or more secondary storage devices or secondary memories 8510. The secondary memory 8510 may include, for example, a hard disk drive 8512 or a removable storage device or drive 8514. The removable storage drive 8514 may be a floppy disk drive, a magnetic tape drive, a compact disk drive, an optical storage drive, a tape backup device, or any other storage device / drive.

[0425]

[0515] The removable storage drive 8514 can interact with a removable storage unit 8518. The removable storage unit 8518 can include a computer usable or readable storage device on which computer software (control logic) or data is stored. The removable storage unit 8518 can be a floppy disk, magnetic tape, compact disk, DVD, optical storage disk, or any other computer storage device. The removable storage drive 8514 can read from or write to the removable storage unit 8518.

[0426]

[0516] The secondary memory 8510 may include other means, devices, components, instrumentalities, or other techniques that allow computer programs or other instructions or data to be accessed by the computer system 8500. Such means, devices, components, intermediaries or other techniques may include, for example, limbs. Removable storage units 8522 and interfaces 8520 may include a program cartridge and cartridge interface (such as found in video game devices), a removable memory chip (such as an EPROM or PROM) and associated sockets, a memory stick and USB port, a memory card and associated memory cart slot, or any other removable storage unit and associated interface.

[0427]

[0517] The computer system 8500 may further include a communication or network interface 8524. The communication interface 8524 may enable the computer system 8500 to communicate and interact with any combination of external devices, external networks, external entities, etc. (individually and collectively referred to by reference number 8528). For example, the communication interface 8525 may enable the computer system 8500 to communicate with external or remote devices 8528 via a communication path 8526, which may be wired or wireless (or a combination thereof) and may include any combination of a LAN, a WAN, the Internet, etc. Control logic or data may be transmitted to and from the computer system 8500 via the communication path 8526.

[0428]

[0518] The computer system 8500 may also be any of a personal digital assistant (PDA), a desktop workstation, a laptop or notebook computer, a netbook, a tablet, a smartphone, a smart watch or other wearable, an appliance, a part of the Internet-of-Things, or an embedded system, or any combination thereof, to name a few non-limiting examples.

[0429]

[0519] The computer system 8500 may be implemented in a variety of ways, including, but not limited to, remote or distributed cloud computing solutions; local or on-premise software ("on-premise" cloud-based solutions); "as a service" models (e.g., content as a service (CaaS), digital content as a service (DCaas), software as a service (SaaS), etc.); Managed software as a service (MSaa S), platform as a service (PaaS), desktop as a service (DaaS), framework as a service (FaaS), backend as a service (BaaS), mobile backend as a service (MBaaS), infrastructure as a service (infrastructure as a service) (IaaS, etc.); or The network may be a client or a server accessing or hosting any application or data through any delivery paradigm, including hybrid models involving any combination of services or delivery paradigms.

[0430]

[0520] Any applicable data structures, file formats and schemas in the computer system 8500 may include, but are not limited to, JavaScript Object Notation (JSON), Extensible Markup Language (XML), Yet Another Markup Language (YAM), L), Extensible Hypertext Markup Language (XHTML), Wireless Markup Language (WML), MessagePack, XML User Interface Language (XUL), or Alternatively, proprietary data structures, formats or schemas may be derived exclusively from standards, including, but not limited to, any other functionally similar representations, in any combination. or in combination with known or open standards.

[0431]

[0521] In some embodiments, a tangible, non-transitory apparatus or article of manufacture including a tangible, non-transitory computer usable or readable medium having control logic (software) stored thereon may also be referred to herein as a computer program product or program storage device. This includes, but is not limited to, a computer system 8500, a main memory 8508, a secondary memory 8510, and removable storage units 8518 and 8522, as well as a tangible article of manufacture embodying any combination of the above. Such control logic, when executed by one or more processing devices (such as computer system 8500), can cause such data processing devices to operate as described herein.

[0432]

[0522] Based on the teachings contained in this disclosure, it will be apparent to one of ordinary skill in the art how to make and use embodiments of the present disclosure using data processing devices, computer systems, or computer architectures other than those depicted in Figure 85. In particular, embodiments may operate with software, hardware, and / or operating system implementations other than those described herein.

[0433] conclusion

[0523] The EP recording system disclosed herein effectively removes noise and removes or isolates undesirable large signals while preserving the relevant components of the raw small signals, i.e., maintaining the integrity of the original information in the EP environment. Conventional EP systems may successfully filter out noise, but may also filter out the noisy signal components that the medical team wants to see. Conventional EP systems may also generate and introduce additional noise and undesirable artifacts that were not originally present in the raw signal due to well-intentioned software filtering algorithms. Conventional EP systems, even when utilizing modern noise reduction measures, are unable to effectively collect high fidelity, noise-free small signals in the presence of concurrent large signal procedures, such as defibrillation and ablation. This is because conventional EP systems do not have comprehensive signal collection and filtering solutions across the relevant frequency ranges, i.e., low (e.g., 0-100 Hz), mid (e.g., about 100 Hz to less than 300 kHz), and high (e.g., 300 kHz and above), and are unable to effectively process concurrent signals that differ by hundreds or thousands of orders of magnitude. In contrast, the EP recording system disclosed herein integrates and applies novel hardware circuitry, software methods and system topologies to remove undesired signals while preserving the original signal waveform across frequencies relevant to signals found in the EP environment.

[0434]

[0524] The disclosed EP system does not have to make the tradeoffs that conventional EP systems must make, but rather allows hardware and software aspects to work together to simultaneously (1) run amplifiers at high gain to look at small signals, (2) minimize destructive large signal filtering in hardware to look at large signals at the same time, thereby preventing both clipping and saturation, (3) process the signals by separating them from each other in independent displays, removing any remaining noise, and synchronizing the separated signals, and finally (4) allow the user to process and analyze both large and small signals in a manner that allows for precise time and event correlation of signal artifacts and events.

[0435]

[0525] The exemplary signal 2200 of FIGS. 22A and 22B illustrates these concepts and, after being collected, filtered and processed by the EP system disclosed herein, demonstrates an EC signal in the presence of large transients, ablation signals, defibrillation signals and EP environmental noise. 22A shows an improved visualization of G or IC cardiac signals. FIG. 22A illustrates the removal of noise from both small and large signals and the avoidance of clipping in the processing of large signals. Conventional EP systems provide a noisy cardiac signal 2203 and may artificially clip the signal 2202 to limit the amplitude of the displayed signal to avoid saturation effects. The disclosed EP system collects and clearly displays both weak 2214 and strong 2205 signals. With the disclosed EP system, no artificial clipping is required and the strong signal 2204 is fully defined (not clipped).

[0436]

[0526] 22B shows that the EP system can reveal low amplitude cardiac signals and associated random artifacts of minute components of the EP signal in the presence of noise and large signal processing. Window 2216 shows a noisy signal 2208 that includes both high and low amplitude minute components 2206 of the desired signal revealed by the disclosed EP system. In contrast, as shown in window 2218, conventional EP systems are not good at revealing both low and high amplitude minute components of the desired signal. With a noisier signal, the conventional EP system can reveal the low amplitude minute components 2210 of the desired signal, but are more likely to be lost among the noise 2212. The high amplitude components 2211 of the desired signal may be lost due to artificial clipping in conventional EP systems.

[0437]

[0527] 22C shows that the disclosed EP system can remove 60 Hz noise 2220 without saturation or delayed recovery while preserving components 2222 of the 60 Hz signal that belong to the original waveform 2224. Specifically, components 2222 of the original waveform 2224 that simultaneously occur as artifacts 2220 are not lost. In other words, when a large signal is simultaneously superimposed on a small signal, the disclosed EP system can clearly identify, collect and process both.

[0438]

[0528] It should be understood that the Detailed Description section, and not any other section, is intended to be used to interpret the claims, and that the other sections set forth one or more exemplary embodiments contemplated by the inventor, but may not represent all exemplary embodiments, and thus are not intended to limit the scope of the disclosure or the appended claims in any way.

[0439]

[0529] While the present disclosure describes exemplary embodiments for exemplary fields and applications, it should be understood that the present disclosure is not limited thereto. Other embodiments and modifications thereto are possible and are within the scope and spirit of the present disclosure. For example, without limiting the generality of this paragraph, the embodiments are not limited to the software, hardware, firmware, or entities illustrated in the figures or described herein. Moreover, the embodiments (whether or not explicitly described herein) have significant utility for fields and applications beyond the examples described herein.

[0440]

[0530] The embodiments are described herein in terms of functional building blocks illustrating the implementation of the specified functions and their related aspects. The boundaries of these functional building blocks are arbitrarily defined herein for convenience of description. Alternative boundaries may be defined so long as the specified functions and relationships (or their equivalents) are appropriately performed. Alternative embodiments may also implement the functional blocks, steps, operations, methods, etc. using an order different from that described herein. The present disclosure also extends to methods relating to using or otherwise implementing the hardware and software features disclosed herein.

[0441]

[0531] References herein to "one embodiment," "an embodiment," "an exemplary embodiment," or similar phrases indicate that the described embodiment may include a particular feature, characteristic, or property, but not all embodiments may necessarily include that particular feature, structure, or property. Moreover, such phrases do not necessarily refer to the same embodiment. Moreover, if a particular feature, structure, or property is described in connection with an embodiment, it is within the knowledge of one of ordinary skill in the art to incorporate such feature, structure, or property in other embodiments, whether or not it is explicitly mentioned or described herein. Moreover, some embodiments may be described using the terms "coupled" and "connected," along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, some embodiments may be described using the terms "connected" or "coupled" to indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0442]

[0532] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. 1. A signal visualization system comprising: A memory, a first signal module including a first digital signal processor (DSP) configured to match heart beats in a first packet associated with the first cardiac signal with known signal characteristics; a second signal module including a second DSP configured to search for late potentials in a second packet associated with the second cardiac signal in response to the matching; a display module coupled to the first signal module and the second signal module, Displaying a portion of the first cardiac signal; displaying a portion of the second cardiac signal including the late potential in time synchronization with the displayed portion of the first cardiac signal based on the searching. A display module configured as above; a memory including: at least one processor coupled to the memory and configured to execute the first signal module, the second signal module, and the display module; A system comprising:

2. The display module comprises: Displaying the portion of the first cardiac signal side-by-side with the portion of the second cardiac signal. The system of claim 1 further configured to:

3. The display module comprises:

2. The system of claim 1, further configured to display the portion of the second cardiac signal that corresponds to the displayed portion of the first cardiac signal, wherein the portion of the first cardiac signal and the portion of the second cardiac signal are displayed vertically stacked.

4. 4. The system of claim 3, wherein the display module is further configured to adjust an offset of the first cardiac signal based on the known signal characteristics, thereby pinning the first cardiac signal to a baseline.

5. 1. A computer-implemented method for visualizing a signal, comprising: matching, by at least one processor executing a first digital signal processor (DSP) of the first signal module, heart beats in a first packet associated with the first cardiac signal to signal characteristics; searching, by the at least one processor executing a second DSP of a second signal module, for late potentials in a second packet associated with a second cardiac signal in response to the matching; displaying, by the at least one processor executing a display module coupled to the first signal module and the second signal module, a portion of the first cardiac signal; displaying, by the at least one processor executing the display module coupled to the first signal module and the second signal module, a portion of the second cardiac signal including the late potential based on the searching and time-synchronously with the displayed portion of the first cardiac signal; A method comprising:

6. The at least one processor executing the display module displays the first cardiac displaying the portion of the signal side-by-side with the portion of the second cardiac signal. The method of claim 5 further comprising:

7. displaying, by the at least one processor executing the display module, the portion of the second cardiac signal corresponding to the displayed portion of the first cardiac signal, wherein the portion of the first cardiac signal and the portion of the second cardiac signal are displayed vertically stacked. The method of claim 5 further comprising:

8. adjusting, by the at least one processor executing the display module, an offset of the first cardiac signal based on the known signal characteristics, thereby pinning the first cardiac signal to a baseline. The method of claim 7 further comprising:

9. When executed by at least one computing device, the at least one computing device matching, by a first digital signal processor (DSP) of the first signal module, heart beats in a first packet associated with the first cardiac signal with known signal characteristics; searching, by a second DSP of a second signal module, for late potentials in a second packet associated with the second cardiac signal in response to said matching; displaying a portion of the first cardiac signal with a display module coupled to the first signal module and the second signal module; displaying, by a display module coupled to the first signal module and the second signal module, a portion of the second cardiac signal including the late potential based on the retrieval and time-synchronously with the displayed portion of the first cardiac signal; A non-transitory computer-readable device having stored thereon instructions for performing operations including:

10. The operation, displaying, by the display module, the portion of the first cardiac signal and the portion of the second cardiac signal side-by-side; 10. The non-transitory computer readable device of claim 9, further comprising:

11. The operation, displaying, with the display module, the portion of the second cardiac signal that corresponds to the displayed portion of the first cardiac signal, the portion of the first cardiac signal and the portion of the second cardiac signal being displayed vertically stacked.

10. The non-transitory computer readable device of claim 9, further comprising:

12. The operation, adjusting, by the display module, an offset of the first cardiac signal based on the known signal characteristics, thereby pinning the first cardiac signal to a baseline. The non-transitory computer readable device of claim 11 , further comprising:

13. 1. A signal visualization system comprising: A memory, a first signal module including a first digital signal processor (DSP) configured to match heart beats in a first packet associated with the first cardiac signal with known signal characteristics; a second signal module including a second DSP configured to search for early excitation a period prior to the matching heart beat in the second cardiac signal; a display module coupled to the first signal module and the second signal module, Displaying a portion of the first cardiac signal; displaying a portion of the second cardiac signal including the pre-excitation in time synchronization with the displayed portion of the first cardiac signal based on the search. A display module configured as above; a memory including: at least one processor coupled to the memory and configured to execute the first signal module, the second signal module, and the display module; A system comprising:

14. The display module comprises: Displaying the portion of the first cardiac signal side-by-side with the portion of the second cardiac signal. The system of claim 13 further configured to:

15. The display module comprises:

14. The system of claim 13, further configured to display the portion of the second cardiac signal that corresponds to the displayed portion of the first cardiac signal, wherein the portion of the first cardiac signal and the portion of the second cardiac signal are displayed vertically stacked.

16. 16. The system of claim 15, wherein the display module is further configured to adjust an offset of the first cardiac signal based on the known signal characteristics, thereby pinning the first cardiac signal to a baseline.

17. 1. A computer-implemented method for visualizing a signal, comprising: matching, by at least one processor executing a first digital signal processor (DSP) of the first signal module, heart beats in a first packet associated with the first cardiac signal with known signal characteristics; searching, by the at least one processor executing a second DSP of a second signal module, for pre-excitation in a period prior to the matching heart beat in the second cardiac signal; displaying, by the at least one processor executing a display module coupled to the first signal module and the second signal module, a portion of the first cardiac signal; displaying, by the at least one processor executing a display module coupled to the first signal module and the second signal module, a portion of the second cardiac signal including the pre-excitation based on the searching and time-synchronously with the displayed portion of the first cardiac signal; A method comprising:

18. displaying, by the at least one processor executing the display module, the portion of the first cardiac signal and the portion of the second cardiac signal side-by-side.

20. The method of claim 17, further comprising:

19. displaying, by the at least one processor executing the display module, the portion of the second cardiac signal corresponding to the displayed portion of the first cardiac signal, wherein the portion of the first cardiac signal and the portion of the second cardiac signal are displayed vertically stacked.

20. The method of claim 17, further comprising:

20. The at least one processor executing the display module detects the known signal. adjusting an offset of the first cardiac signal based on signal characteristics, thereby pinning the first cardiac signal to a baseline.

20. The method of claim 19, further comprising:

21. When executed by at least one computing device, the at least one computing device matching, by a first digital signal processor (DSP) of the first signal module, heart beats in a first packet associated with the first cardiac signal with known signal characteristics; searching, by a second DSP of the second signal module, for pre-excitation in a period prior to the corresponding heart beat in the second cardiac signal; displaying a portion of the first cardiac signal with a display module coupled to the first signal module and the second signal module; displaying, by a display module coupled to the first signal module and the second signal module, a portion of the second cardiac signal including the pre-excitation based on the searching and time-synchronously with the displayed portion of the first cardiac signal; A non-transitory computer-readable device having stored thereon instructions for performing operations including:

22. The operation, displaying, by the display module, the portion of the first cardiac signal and the portion of the second cardiac signal side-by-side; 22. The non-transitory computer readable device of claim 21, further comprising:

23. The operation, displaying, with the display module, the portion of the second cardiac signal that corresponds to the displayed portion of the first cardiac signal, the portion of the first cardiac signal and the portion of the second cardiac signal being displayed vertically stacked.

22. The non-transitory computer readable device of claim 21, further comprising:

24. The operation, adjusting, by the display module, an offset of the first cardiac signal based on the known signal characteristics, thereby pinning the first cardiac signal to a baseline.

24. The non-transitory computer readable device of claim 23, further comprising:

25. 1. A computer-implemented method comprising: accessing, with at least one processor, a first cardiac signal associated with a body surface lead; matching, with the at least one processor, heart beats of the first cardiac signal with known signal patterns; searching, with the at least one processor, for early excitation or late potentials in the second cardiac signal a period before and after the coincident cardiac beat; A method comprising:

26. 26. The method of claim 25, wherein the period of time is a user-defined period of time.

27. The searching, searching, by the at least one processor, for the pre-excitation based on an amplitude threshold.

26. The method of claim 25, further comprising:

28. The searching, searching, by the at least one processor, a buffer including a portion of the second cardiac signal for the early excitation or the late potential.

26. The method of claim 25, further comprising:

29. The matching, matching, by the at least one processor, the heart beats of the first cardiac signal with the known signal pattern based on a correlation function.

26. The method of claim 25, further comprising:

30. The matching, matching, by the at least one processor, the beats of the first cardiac signal with the known signal pattern based on a mean absolute deviation (MAD) function.

26. The method of claim 25, further comprising:

31. The matching, matching, by the at least one processor, the heart beats of the first cardiac signal with the known signal pattern based on a confidence value.

26. The method of claim 25, further comprising:

32. The method of claim 31 , wherein the confidence value is user defined.

33. and interpolating, by said at least one processor, signal data from the catheter at the site of the early excitation to signal data at the site of the late potential.

26. The method of claim 25, further comprising:

34. Displaying, by the at least one processor, the signal data from the catheter independent of a late potential filter.

34. The method of claim 33, further comprising:

35. estimating, by the at least one processor, a site of conduction delay between the site of the early excitation and the site of the late potential.

34. The method of claim 33, further comprising:

36. When executed by at least one computing device, the at least one computing device accessing a first cardiac signal associated with a body surface lead; matching the heart rate of the first cardiac signal with a known signal pattern; searching for early excitation or late potentials in the second cardiac signal a period before and after the coincident heart beat; A non-transitory computer-readable device having stored thereon instructions for performing operations including:

37. 37. The non-transitory computer readable device of claim 36, wherein the period of time is a user-defined period of time.

38. The searching, detecting said pre-excitation based on an amplitude threshold; 37. The non-transitory computer readable device of claim 36, further comprising:

39. The searching, detecting a buffer including a portion of the second cardiac signal for the early excitation or the late potential; Searching 37. The non-transitory computer readable device of claim 36, further comprising:

40. The matching, matching the heart rate of the first cardiac signal with the known signal pattern based on a correlation function.

37. The non-transitory computer readable device of claim 36, further comprising:

41. The matching, Matching the beats of the first cardiac signal with the known signal pattern based on a mean absolute deviation (MAD) function.

37. The non-transitory computer readable device of claim 36, further comprising:

42. The matching, Matching the heart beats of the first cardiac signal with the known signal pattern based on a confidence value.

37. The non-transitory computer readable device of claim 36, further comprising:

43. 43. The non-transitory computer readable device of claim 42, wherein the confidence value is user defined.

44. The operation, Interpolating signal data from the catheter at the site of the pre-excitation to signal data at the site of the late potential.

37. The non-transitory computer readable device of claim 36, further comprising:

45. The operation, 45. The non-transitory computer readable device of claim 44, further comprising displaying the signal data from the catheter independent of a lagging potential filter.

46. The operation, Inferring a site of conduction delay between said site of early excitation and said site of late potential.

45. The non-transitory computer readable device of claim 44, further comprising:

47. 1. A computer-implemented method for filtering noise from an input signal, comprising: accessing, by at least one processor, the input signal having a first harmonic frequency and having the noise; determining, by the at least one processor, periods of quiescence in the input signal; storing, by the at least one processor, samples of the noise in the input signal in a buffer during the quiet periods; subtracting, by the at least one processor, the sample from a single cycle of the noise in the buffer from the input signal to generate a filtered signal, the subtraction removing the first and second harmonic frequencies from the input signal and avoiding the introduction of transient responses in the filtered signal; and repeating, by the at least one processor, the determining, storing, and subtracting to refine the filtered signal; A method comprising:

48. The determining step comprises: calculating, by said at least one processor, a gradient of said input signal; determining, by the at least one processor, that the gradient is below a threshold, thereby determining the presence of the quiescent period; 48. The method of claim 47, further comprising:

49. The storing comprises: averaging, by the at least one processor, samples of the input signal with corresponding samples of the noise of the input signal in the buffer to create average samples; replacing, by the at least one processor, the corresponding samples of the noise of the input signal in the buffer with the average samples; 48. The method of claim 47, further comprising:

50. 48. The method of claim 47, wherein the first harmonic frequency is 60 Hertz and the second harmonic frequency is 120 Hertz or 180 Hertz.

51. 48. The method of claim 47, wherein the frequency of the noise in the input signal is substantially constant.

52. 52. The method of claim 51, wherein the size of the buffer is based on the frequency of the noise in the input signal.

53. When executed by at least one computing device, the at least one computing device accessing an input signal having a first harmonic frequency and having noise; determining periods of quiet in the input signal; storing samples of the noise in the input signal in a buffer during the quiet periods; subtracting the sample from a single cycle of the noise in the buffer from the input signal to generate a filtered signal, the subtraction removing the first and second harmonic frequencies from the input signal and avoiding the introduction of transient responses in the filtered signal; and repeating the determining, storing, and subtracting to refine the filtered signal; and A non-transitory computer-readable device having stored thereon instructions for performing operations including:

54. The determining step comprises: Calculating a slope of the input signal; 54. The non-transitory computer readable device of claim 53, further comprising: determining that the gradient is below a threshold, thereby determining the presence of the quiescent period.

55. The storing comprises: averaging samples of the input signal with corresponding samples of the noise of the input signal in the buffer to produce average samples; replacing the corresponding samples of the noise of the input signal in the buffer with the average samples; 54. The non-transitory computer readable device of claim 53, further comprising:

56. 54. The non-transitory computer readable device of claim 53, wherein the first harmonic frequency is 60 Hertz and the second harmonic frequency is 120 Hertz or 180 Hertz.

57. 54. The non-transitory computer readable device of claim 53, wherein the frequency of the noise in the input signal is substantially constant.

58. 54. The non-transitory computer readable device of claim 53, wherein a size of the buffer is based on the frequency of the noise in the input signal.

59. 1. A computer-implemented method for filtering noise from an input signal, comprising: accessing, by at least one processor, the input signal including the noise and minimal high frequency signals; high-pass filtering, by the at least one processor, the input signal to generate a filtered signal; isolating, with the at least one processor, the noise related artifacts in the filtered signal from high frequency signals of the interest; disabling, by the at least one processor, the filtered signal for a period of time before and after the isolated artifact, the disabling removing the isolated artifact and allowing high frequency signals of interest to pass; A method comprising:

60. filtering, by the at least one processor, the input signal using a notch filter.

60. The method of claim 59, further comprising:

61. isolating the artifact, calculating, by the at least one processor, a gradient of the filtered input signal; determining, by the at least one processor, that the gradient exceeds a threshold, thereby determining the presence of the artifact; 60. The method of claim 59, further comprising:

62. isolating the artifact, characterizing, by the at least one processor, the artifact in an artifact template, wherein the nulling comprises applying the artifact template as the selected filter across the isolated artifact in the filtered signal.

60. The method of claim 59, further comprising:

63. 60. The method of claim 59, wherein accessing the input signal including the noise and a high frequency signal of the subject further comprises accessing a Purkinje signal.

64. 60. The method of claim 59, wherein accessing the input signal including the noise and the high frequency signal of interest results from performing rapid conducting tissue recognition filtering.

65. 60. The method of claim 59, wherein isolating the artifacts further comprises isolating, by the at least one processor, an impulse response.

66. buffering, by the at least one processor, the filtered signal for the period of time before and after the isolated artifact.

60. The method of claim 59, further comprising:

67. selecting, by the at least one processor, a filter based on the isolated artifact; and applying, by the at least one processor, the selected filter to nullify the isolated signal in the filtered signal; 60. The method of claim 59, further comprising:

68. When executed by at least one computing device, the at least one computing device accessing an input signal including noise and a high frequency signal of interest; high pass filtering the input signal to generate a filtered signal; isolating the noise related artifacts in the filtered signal from high frequency signals of interest; and Disabling the filtered signal for a period of time before and after the isolated artifact, the disabling removing the isolated artifact and allowing high frequency signals of interest to pass; A non-transitory computer-readable device having stored thereon instructions for performing operations including:

69. The operation, filtering the input signal using a notch filter; 69. The non-transitory computer readable device of claim 68, further comprising:

70. The isolating comprises: Calculating a gradient of the filtered input signal; determining that the gradient exceeds a threshold, thereby determining the presence of the artifact; 69. The non-transitory computer readable device of claim 68, further comprising:

71. The isolating comprises: characterizing the artifact in an artifact template, wherein the nulling applies the artifact template as the selected filter across the isolated artifact in the filtered signal.

69. The non-transitory computer readable device of claim 68, further comprising:

72. 69. The non-transitory computer readable device of claim 68, wherein accessing the input signal including the noise and a high frequency signal of the subject further comprises accessing a Purkinje signal.

73. 69. The non-transitory computer readable device of claim 68, wherein accessing the input signal including the noise and the high frequency signal of interest results from performing rapid conducting tissue recognition filtering.

74. 69. The non-transitory computer readable device of claim 68, wherein isolating the artifacts further comprises isolating an impulse response.

75. The operation, Buffering the filtered signal for the period of time before and after the isolated artifact.

69. The non-transitory computer readable device of claim 68, further comprising:

76. The operation, selecting a filter based on the isolated artifact; applying the selected filter to nullify the isolated signal in the filtered signal; 69. The non-transitory computer readable device of claim 68, further comprising:

77. 1. A computer-implemented method comprising: accessing, by at least one processor, an input cardiac signal; matching, with the at least one processor, a portion of the input cardiac signal with a known signal pattern; displaying, by the at least one processor, an indication of the extent of the match; and A method comprising:

78. 78. The method of claim 77, wherein the known signal patterns are captured during a previous or current patient treatment and stored in a pattern template.

79. 78. The method of claim 77, wherein the known signal patterns are stored in a database.

80. The matching, matching, by the at least one processor, the portion of the input cardiac signal with the known signal pattern based on a correlation function.

78. The method of claim 77, further comprising:

81. The matching, matching, by the at least one processor, the portion of the input cardiac signal with the known signal pattern based on a mean absolute deviation (MAD) function.

78. The method of claim 77, further comprising:

82. The matching, matching, by the at least one processor, the portion of the input cardiac signal with the known signal pattern based on a confidence value.

78. The method of claim 77, further comprising:

83. 78. The method of claim 77, wherein the indication of the degree of match specifies where cardiac pacing should be delivered.

84. When executed by at least one computing device, the at least one computing device Accessing an input cardiac signal; matching a portion of the input cardiac signal with a known signal pattern; displaying an indication of the degree of match; and A non-transitory computer-readable device having stored thereon instructions for performing operations including:

85. 85. The non-transitory computer readable device of claim 84, wherein the known signal patterns are captured during a previous or current patient treatment and stored in a pattern template.

86. 85. The non-transitory control system of claim 84, wherein the known signal patterns are stored in a database. A computer readable device.

87. The matching, matching the portion of the input cardiac signal with the known signal pattern based on a correlation function.

85. The non-transitory computer readable device of claim 84, further comprising:

88. The matching, Matching the portion of the input cardiac signal with the known signal pattern based on a mean absolute deviation (MAD) function.

85. The non-transitory computer readable device of claim 84, further comprising:

89. The matching, matching the portion of the input cardiac signal with the known signal pattern based on a confidence value.

85. The non-transitory computer readable device of claim 84, further comprising:

90. 85. The non-transitory computer readable device of claim 84, wherein the indication of the degree of match specifies where cardiac pacing should be delivered.

91. 1. A computer-implemented method, comprising: accessing, by at least one processor, an input cardiac signal; accessing, by the at least one processor, a detection threshold; matching, by the at least one processor, a portion of the input cardiac signal with a known signal pattern based on the detection threshold; displaying, by the at least one processor, a highlighted portion of the input cardiac signal based on the matching; and A method comprising:

92. 92. The method of claim 91, wherein the known signal pattern is acquired during a previous patient treatment or a current patient treatment.

93. 92. The method of claim 91, wherein the known signal patterns are stored in a database.

94. The matching, matching, by the at least one processor, the portion of the input cardiac signal with the known signal pattern based on a correlation function.

92. The method of claim 91, further comprising:

95. The matching, matching, by the at least one processor, the portion of the input cardiac signal with the known signal pattern based on a mean absolute deviation (MAD) function.

92. The method of claim 91, further comprising:

96. The matching, a first matching, by the at least one processor, the portion of the input cardiac signal to the known signal pattern; determining, by the at least one processor, a first confidence value based on the first match; The at least one processor performs a step of converting a portion of a second input signal into the known signal pattern. and second matching the first line with the second line. determining, by the at least one processor, a second confidence value based on the second match; and averaging, by the at least one processor, the first confidence value and the second confidence value to create an average confidence value; determining, by the at least one processor, that the average confidence value is above the detection threshold; 92. The method of claim 91, further comprising:

97. The displaying Displaying, by the at least one processor, the highlighted portion of the input cardiac signal based on a color associated with the known signal pattern.

92. The method of claim 91, further comprising:

98. The matching, matching, by the at least one processor, the portion of the input cardiac signal with the known signal pattern based on weighted specific regions of the known signal pattern.

92. The method of claim 91, further comprising:

99. When executed by at least one computing device, the at least one computing device Accessing an input cardiac signal; Accessing a detection threshold; matching a portion of the input cardiac signal with a known signal pattern based on the detection threshold; displaying a highlighted portion of the input cardiac signal based on the matching; and A non-transitory computer-readable device having stored thereon instructions for performing operations including:

100. 100. The non-transitory computer readable device of claim 99, wherein the known signal pattern is captured during a prior patient treatment or a current patient treatment.

101. 100. The non-transitory computer readable device of claim 99, wherein the known signal patterns are stored in a database.

102. The matching, matching the portion of the input cardiac signal with the known signal pattern based on a correlation function.

100. The non-transitory computer readable device of claim 99, further comprising:

103. The matching, Matching the portion of the input cardiac signal with the known signal pattern based on a mean absolute deviation (MAD) function.

100. The non-transitory computer readable device of claim 99, further comprising:

104. The matching, first matching the portion of the input cardiac signal with the known signal pattern; determining a first confidence value based on the first match; second matching a portion of a second input signal with the known signal pattern; determining a second confidence value based on the second match; and averaging the first confidence value and the second confidence value to create an average confidence value; determining that the average confidence value is above the detection threshold; 100. The non-transitory computer readable device of claim 99, further comprising:

105. The displaying Displaying the highlighted portion of the input cardiac signal based on a color associated with the known signal pattern.

100. The non-transitory computer readable device of claim 99, further comprising:

106. The matching, matching the portion of the input cardiac signal with the known signal pattern based on a weighted region of the known signal pattern.

100. The non-transitory computer readable device of claim 99, further comprising:

107. 1. A system for generating a noise-free unipolar signal, comprising: an electrocardiogram (ECG) circuit board configured to process ECG signals; a plurality of intracardiac (IC) circuit boards, each IC circuit board configured to process a corresponding IC signal; Equipped with the ECG circuit board and the IC circuit boards share substantially the same circuitry and components; The system wherein the ECG circuit board processes the ECG signal using substantially the same path that each IC circuit board uses to process its corresponding IC signal.

108. 108. The system of claim 107, wherein a single Wilson Coupled Electrode (WCT) signal is used for the ECG circuit board and the multiple IC circuit boards.

109. 1. A system for performing electrophysiology (EP) processing, comprising: an electrocardiogram (ECG) circuit board configured to process ECG signals; a plurality of intracardiac (IC) circuit boards, each IC circuit board configured to process a corresponding IC signal; a communication interface communicatively coupled to the remote device; coupled to the ECG circuit board, the plurality of IC circuit boards and the communication interface; receiving feedback from the remote device via the communication interface; Controlling the remote device based on the ECG signal, each corresponding IC signal, and the feedback from the remote device via the communication interface. a processor configured to: A system comprising:

110. 110. The system of claim 109, wherein the remote device is selected from the group consisting of an ultrasound device, a radio frequency (RF) generator, a stimulator, a three-dimensional imaging device, an intracardiac echocardiography (ICE) device, an X-ray fluoroscope, and a defibrillator.

111. 110. The system of claim 109, wherein the communication interface is coupled to the remote device using a communication protocol selected from the group consisting of Digital Imaging and Communications in Medicine (DICOM), Ethernet, Universal Serial Bus (USB), and Institute of Electrical and Electronics Engineers (IEEE) 802.11.

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