Method for fault-tolerant operation of processing unit and of processing assembly, circuit configuration, and computing unit
The method for fault-tolerant operation of processing units with multiple sub-processing units addresses the vulnerability to hardware errors by determining an adaptive sub-word for continued operation with reduced accuracy, preventing complete shutdown of hardware accelerators and ensuring continued functionality in safety-critical applications.
Patent Information
- Application Number
- JP2024151951
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-09-06
- Filing Date
- 2024-09-04
- Publication Date
- 2025-03-18
AI Technical Summary
Highly integrated hardware accelerators used in computationally intensive applications like artificial intelligence and neural networks are vulnerable to hardware errors, leading to potential complete shutdowns of processing assemblies.
A method for fault-tolerant operation of a processing unit with multiple sub-processing units, where an adaptive sub-word is determined from the input word to be processed, allowing continued operation with reduced accuracy, thereby avoiding complete shutdown of the processing assembly.
Enables continued operation of processing units with reduced accuracy, preventing complete shutdown of hardware accelerators and ensuring continued functionality in safety-critical applications like autonomous driving.
Smart Images
Figure 2025037844000001_ABST
Abstract
Description
[Technical field]
[0001] The invention relates to a method for fault-tolerant operation of a processing unit with a plurality of sub-processing units, a circuit arrangement for its implementation, a method for fault-tolerant operation of a processing assembly and a computing unit. [Background technology]
[0002] For computationally intensive computer applications, for example in the field of artificial intelligence or neural networks, dedicated hardware accelerators in the form of integrated circuits may be used. Such hardware accelerators may include a number of processing units that perform frequently occurring elementary operations, such as multiplication and addition operations. High computation speeds are achieved, among other things, by parallelized execution in a number of processing units. To keep the energy consumption and cost of such hardware accelerators low, integrated circuits may be made with as small a structural size as possible, but these integrated circuits are relatively vulnerable to hardware errors. Not only temporary errors, such as bit flips, may occur, but also permanent errors, for example based on variations in the manufacturing process or based on aging processes. Summary of the Invention [Problem to be solved by the invention]
[0003] According to the invention, a method for fault-tolerant operation of a processing unit, a circuit arrangement for its implementation, a method for fault-tolerant operation of a processing assembly and a computing unit for its implementation are proposed with the features of the independent claims. Advantageous configurations are the subject of the dependent claims and the following description. [Means for solving the problem]
[0004] The invention provides a method for the operation of a processing unit with several sub-processing units, in the case of the presence of an error in one sub-processing unit or in the processing unit, for an input word to be processed, which is defined for processing in a first arithmetic mode of the processing unit, to determine from this input word an adaptive partial word suitable for processing in at least one sub-processing unit functioning without error, to determine an adaptive input word from this adaptive partial word, and to process the adaptive input word in a second arithmetic mode of the processing unit to determine an adaptive output word. The invention allows further operation of the processing unit with reduced accuracy, which can avoid a complete shutdown of a processing assembly (e.g. a hardware accelerator) which includes a malfunctioning processing unit as well as generally a large number of other (error-free) processing units. This is particularly advantageous in safety-related applications, for example in the case of control algorithms providing autonomous driving functions for automobiles using neural networks.
[0005] Starting from the fact that each sub-processing unit is configured to process one or more partial words and to determine a result partial word therefrom (in a manner defined by circuit technology). Starting from a processing unit configurable for several arithmetic methods, which processing unit is configured to determine an output word from the result partial word depending on the respectively configured arithmetic method. The processing unit is configured to process an input word, whereby partial words of the input word are processed, which are arranged in an interval of the input word and are processed in a sub-processing unit corresponding to said interval. That is to say, corresponding to several sub-processing units and corresponding to several intervals of the input word, at least one input word, in particular all input words, have several partial words. Correspondingly, the term partial word can be understood in particular in the sense of a proper partial word (for at least one of the input words) (i.e. as a proper part of the input word, i.e. one partial word is not the same as the input word). These partial words of one input word are disjoint.
[0006] The second calculation method differs from the first calculation method in particular.
[0007] According to one embodiment, to determine whether an error is present in a sub-processing unit, each sub-processing unit is checked to see if it does not function without error and / or at least one sub-processing unit that functions without error is determined.
[0008] The recognition that an error exists in one sub-processing unit or processing unit can be made by a suitable error recognition algorithm. Such an error recognition algorithm can, for example, make the processing unit process one or more sets of predefined input words whose output words are known and compare the resulting words obtained in this processing with the known output words in order to recognize the error. By suitable selection of the predefined input words, it is possible to largely limit the error to (at least) one specific sub-processing unit or to determine for each sub-processing unit whether it functions without error. The predefined input words can, for example, be selected such that the output words depend only on the correct functioning of one sub-processing unit. A sub-processing unit is determined or classified as functioning without error if no errors are found in it, i.e. if this sub-processing unit does not function incorrectly.
[0009] If there is no error in a sub-processing unit or in the processing unit, the operation of the processing unit is carried out in particular as specified, i.e. using all sub-processing units, in which case the input word is used as is and processed in the first arithmetic method.
[0010] According to one embodiment, the processing units implement a mathematical operation depending on the operation scheme, which includes or is the formation of a product of an input word or a product of partial words of an input word, each of the sub-processing units being configured for determining the product of two respective partial words of the input word as a result partial word, this mathematical operation being in particular a multiply-add operation. Since a multiplication often occurs in particular within the scope of a multiply-add operation, for example in scalar products or matrix operations used in neural networks, the corresponding processing units perform this multiplication at high speed and, if multiple processing units are used, in parallel. The term "multiply-add operation" (or multiply-accumulate operation) means a multiply-add operation in which two factors are multiplied together and the product of both factors is added to the respective summand.
[0011] According to one embodiment, forming an adaptive partial word for each input word comprises rounding the input word to a relatively significant part having a bit width corresponding to the bit width of the respective adaptive partial word to be formed and using this relatively significant part as the respective adaptive partial word, thereby performing the operation with reduced precision.
[0012] According to one embodiment, the rounding is performed towards zero. This procedure is of use in certain applications (for example in neural networks) since for a large number of input words the distribution of these input words is preserved, i.e. no distortion of the distribution of the rounded values with respect to the original value occurs. Rounding towards zero means that for a positive value to be rounded, the smallest possible value closest to this value to be rounded is selected as the rounded value, and for a negative value to be rounded, the largest possible value closest to this value to be rounded is selected as the rounded value. This means that for a binary value to be rounded to a certain number of bits, for positive values the most significant bits of this value are kept according to a certain number and the least significant bits (i.e. bits with less significance than a certain number of most significant bits) are truncated, and for negative values the least significant bits are truncated and 1 is added to the most significant bit (i.e. from bit 1 to the least significant bit of a certain number of most significant bits of the value to be rounded).
[0013] According to one embodiment, a bit shift operation is performed to map the adaptation output word to the adaptation result word, whereby the significance of the adaptation result part word and thus the adaptation output word can be corrected, said correction being dependent on at least one sub-processing unit functioning without error being used.
[0014] According to one embodiment, the first operation mode is the processing of the input word with a first bit width, in particular with the entire bit width, and the second operation mode is the processing of the input word with a second bit width, which is smaller than the first bit width, in particular with an integer fraction of the first bit width. For example, the first operation mode may correspond to a multiplication or multiply-and-add operation, in which the input word as a whole, i.e. with the entire bit width, is understood as a respective numerical value, which are multiplied together and the products are possibly added together. The second operation mode may correspond to a multiplication or multiply-and-add operation, in which in this example partial words of the input word, for example with half or a quarter of the entire bit width, are understood as respective (independent) numerical values, which are multiplied together and the products are possibly added together, thus obtaining a number of results corresponding to the number of partial words in an input word.
[0015] The circuit arrangement according to the invention comprises a processing unit and a control assembly, the processing unit having a number of sub-processing units, each of which is configured for processing one or more partial words and for determining a result partial word thereon, the processing unit (2) being configurable for a number of arithmetic schemes and configured for processing partial words of an input word arranged in an interval of the input word in the sub-processing unit corresponding to said interval and for determining an output word from the result partial words determined thereby in dependence on the respectively configured arithmetic scheme. The control assembly (or control unit) is configured for implementing the method according to the invention.
[0016] According to one embodiment, the control assembly has a control circuit configured to generate at least one first configuration signal for configuring the processing unit, the at least one first configuration signal configuring the processing unit according to (or in) one of the computational schemes. The control circuit may also possibly perform a decision as to whether one of the sub-processing units functions without error or erroneously.
[0017] According to one embodiment, the control assembly has an adaptation circuit configured to receive an input word to be processed and, based thereon, to form an adapted input word corresponding to at least one second configuration signal.
[0018] In one form, the control circuitry is configured to generate at least one second configuration signal to form the adaptation input word using the adaptation partial word. The adaptation circuitry may also implement, among other things, a rounding operation of the input word to determine the adaptation partial word.
[0019] According to one embodiment, the control assembly comprises a bit shift circuit, which is configured to shift the adaptive output word of the processing unit by a certain number of bits to obtain the adaptive result word. In one embodiment, this number of bits is configurable according to a third configuration signal. In one embodiment, the control circuit is configured to generate the third configuration signal depending on at least one error-free functioning sub-processing unit. This allows the bit position of the adaptive output word to be corrected only if this has not already been done in the processing unit.
[0020] In a method according to the invention for fault-tolerant operation of a processing assembly comprising a number of processing units as described above, a number of input words are defined for processing in a first computing method in processing units of the number of processing units assigned to these input words, and if an error is present in at least one processing unit of the number of processing units, the processing of the input words assigned to the at least one processing unit in which the error is present is performed by the method according to the invention for fault-tolerant operation of processing units, and the processing of the input words assigned to the processing units in which no error is present is performed in the first computing method.
[0021] A computing unit according to the invention comprises such a processing assembly and a control unit, the control unit being configured for implementing the method according to the invention for fault-tolerant operation of the processing assembly.
[0022] Further advantages and features of the present invention will be apparent from the description of the invention and the accompanying drawings.
[0023] The invention is illustrated diagrammatically in the drawings on the basis of an exemplary embodiment and is explained below with reference to the drawings. [Brief description of the drawings]
[0024] [Figure 1] FIG. 2 illustrates an exemplary processing unit and preceding and following functional blocks according to one embodiment. [Diagram 2] FIG. 2 is a flow diagram of a method for fault-tolerant operation of a processing unit according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0025] FIG. 1 illustrates an exemplary processing unit 2 and preceding and following functional blocks according to one embodiment.
[0026] The processing unit 2 is configured, for example, to perform multiply-add operations on binary values, and both full-width and half-width processing are supported. In full-width processing, the illustrated processing unit performs the following calculations for input values or words a, b, each having n bits (n being an even number greater than zero, e.g. 8, 16, 32 or another even number):
[0027]
number
[0028] We use the notation usual in information science, where
[0029]
number
[0030] The variable to the left of the operator
[0031]
number
[0032] The result of the expression on the right side of the
[0033]
number
[0034] The formula on the right side of may involve the variable itself, i.e. it is assigned a new value that may depend on the old value. That is, the variable c is, according to the formula above, the cumulative sum of the products of the input words a and b, for example, as several successive input words a and b are processed and their products are added together.
[0035] In half-width processing, partial words of the input word, each of which is n / 2 bits, are used, in which case the processing unit performs the following calculations for an input value or word a consisting of partial words a1, a0 and an input value or word b consisting of partial words b1, b0:
[0036]
number
[0037]
number
[0038] The variables c1 and c0 are formed independently of each other.
[0039] Regardless of the desired bit width, calculations by the processing units are initially performed at the partial word level, i.e. starting with partial words of bit width n / 2 bits. To calculate the full bit width, the partial results are combined.
[0040]
number
[0041] and
[0042]
number
[0043] where a0, a1, b0, and b1 each have n / 2 bits;
[0044]
number
[0045] applies.
[0046] 2i Multiplication by corresponds to a left shift of each binary bit by i bits (where the bit order increases to the left). That is, in terms of whole bit width operations, each multiplication by a power of 2 is realized in circuit terms by a left shift (where a zero bit is inserted from the right and the bit order or importance increases from right to left).
[0047] The processing unit 2 comprises sub-processing units 40, 41, 42, 43 arranged for determining the above-mentioned products of partial words of the input word, one sub-processing unit each being provided for determining a1·b1, a1·b0, a0·b1 and a0·b0. The partial words of the input word are for example read via input registers 32, 34 of the processing units. The products of the partial words determined by the sub-processing units 40, 41, 42, 43 are called result partial words. For example, the first sub-processing unit 40 determines the product a0·b0 as the result partial word, the second sub-processing unit 41 determines the product a1·b0 as the result partial word, the third sub-processing unit 42 determines the product a0·b1 as the result partial word and the fourth sub-processing unit 43 determines the product a1·b1 as the result partial word.
[0048] From these partial result words, the processing unit 2 can determine the result to be output, called output word. This is done in a configurable manner, i.e. which partial result words are used to determine the output word and how the partial result words are combined are configurable, for example by means of a (first) configuration signal 12 transmitted via corresponding control lines. In this respect, several configuration possibilities or operation methods are generally set in terms of circuit technology. The configurability, for the illustrated exemplary processing unit 2, is, inter alia, full bit-width processing and half bit-width processing.
[0049] Generally speaking, the processing unit has a number of sub-processing units and is configurable for different operation or processing schemes (for example full bit-width and half bit-width processing in the illustrated processing unit). Each sub-processing unit processes partial words of the input word in a predefined manner to determine a respective result partial word. From the result partial word, an output word is determined depending on the operation scheme, i.e. the output word depends on the operation scheme that forms the output word from the result partial word. For the same input word, different operation schemes generally result in different output words (except for special input words).
[0050] A processing unit with four sub-processing units in a 2x2 arrangement is shown by way of example, in which the input word is divided into two partial words each. In general, the processing unit may have a different number of sub-units and / or the input word may be divided into a different number of partial words, independent of each other, corresponding to the number and arrangement of the sub-units. Correspondingly, further or other possibilities may also exist for processing the input word or determining the output word from the result partial word (corresponding to various arithmetic modes). For example, 16 sub-processing units may be provided in a 4x4 arrangement, in which three arithmetic modes are defined, in particular, full bit width processing, half bit width processing, and quarter bit width processing (for example, if the input word has a bit width of 32 bits, 1x32 bit processing, 2x16 bit processing, and 4x8 bit processing).
[0051] In the case of processing with half bit width, only the result partial words of the second sub-processing unit 41 and the third sub-processing unit 42 are used, which result partial words correspond to the partial word products a1·b0 and a0·b1. These products are added to the partial words c1, c0 independently of each other as explained above. The partial words c1, c0 are stored, for example, in the output register 36 or in an accumulation register, and the partial words c1, c0 are considered as independent values, i.e. the partial words of the output word are two values. The accumulation operation is symbolically suggested in the figure. It also generally starts from the fact that several input words are processed successively, i.e. the respective partial word products a1·b0 and a0·b1 are successively added to the partial words c1, c0 in the output register 36. The output register 36 is initially reset (before the addition) to a certain value, in particular to zero.
[0052] In case of processing at the full bit width, the result partial words of all sub-processing units 40, 41, 42, 43 are used, which correspond to the partial word products a0·b0, a1·b0, a0·b1 and a1·b1. These products are added to the output word, which here is a single value as a whole, taking into account their respective significance, as explained above. The output word may also be stored in the output register 36 or in an accumulation register, where it may be added together if several input word pairs are consecutive.
[0053] If one sub-processing unit stops, another one that still functions without error can still be used for calculations, for example in the figure the fourth sub-processing unit 43 does not function without error, while the other three sub-processing units 40, 41, 42 function without error.
[0054] In such a situation, the input words 51, 52 that are to be processed with the entire bit width can be processed with reduced precision. For this purpose, a sub-processing unit that functions without error, here for example the first sub-processing unit 40, is determined and forms from the input words 51, 52 adapted partial words called adaptive partial words 61, 62, which are suitable for processing by the sub-processing unit 40 that functions without error. In this case, words called adaptive input words 63, 64 are formed, which subsume the adaptive partial words 61, 62, and which are arranged in a position in the adaptive input words 63, 64 so that the adaptive input words 63, 64 are processed by the sub-processing unit 40 that functions without error. In the example shown (the first sub-processing unit 40 is used), this is the lower n / 2 bits of the adaptive input words 63, 64, respectively. If other functional sub-processing units are used, the adaptation partial words 61, 62 are arranged in correspondingly other positions in the adaptation input words 63, 64. For example, the most significant n / 2 bits of the input words 51, 52 are used as adaptation partial words 61, 62, so that the adaptation partial words 61, 62 are arranged in a power of 2 (e.g.
[0055]
number
[0056] or
[0057]
number
[0058] ), it is the same as the rounded value of the input words 51 and 52.
[0059] The bits of the adaptation input words 63, 64 in the interval where no adaptation sub-words 61, 62 exist (in the example shown, the upper n / 2 bits of the adaptation input words 63, 64) can have any value and / or can be set to any value (e.g., zero) since they are not incorporated into the adaptation result word 54 where this interval is ultimately determined.
[0060] The formation of the adaptation partial words 61, 62 from the input words 51, 52 and the formation of the adaptation input words 63, 64 from the adaptation partial words 61, 62 is carried out, inter alia, by a functional block called adaptation circuit 4 which is arranged before the processing unit 2. The adaptation circuit 4 can be configured by means of a (second) configuration signal 14 transmitted via the corresponding control lines. This configuration defines how the adaptation circuit 4 maps the input words 51, 52 to the adaptation input words 63, 64, i.e. how the adaptation partial words 61, 62 are formed from the input words 51, 52 and on the basis of which the adaptation input words 63, 64 are formed. In the absence of errors, i.e. if all sub-processing units 40, 41, 42, 43 function without errors, the input words 51, 52 are directly mapped to the adaptation input words 63, 64.
[0061] For processing, the adaptive input words 63, 64 are read in, for example via the input registers 32, 34, as explained above. During processing, an adaptive result partial word is determined by the first sub-processing unit 40, which functions without error, and this adaptive result partial word is added to the value in the output register 36, the processing unit 2 being configured for this in an appropriate one of the arithmetic modes (configurability), in particular here for half-bit-width processing, so that the adaptive result partial word is added to the lower bits of the output register 36 (if several input words are processed in succession). The word formed in this way can be called an adaptive output word 66.
[0062] Generally speaking, for an input word that is defined for or intended to be processed in a first arithmetic scheme (here full bit width), an adaptive input word is formed that is processed in a second arithmetic scheme different from the first arithmetic scheme (here half bit width), for which inter alia the adaptation circuit is configured for forming an adaptive input word from the input word and the processing circuit is configured for the second arithmetic scheme, i.e. configured to perform processing in the second arithmetic scheme in order to form an adaptive output word.
[0063] In particular, since the adaptive output word is formed in the second arithmetic mode (half the bit width) instead of the originally defined first arithmetic mode (full bit width), it may occur that the position or place of the partial words of the adaptive output word does not correspond to the position or place that would have been present if the processing had been carried out in the first arithmetic mode. To correct this, the bits of the adaptive output word 66 can be shifted to the left by a certain number of bits, with bits of value 0 being inserted from the right to determine a result word called adaptive result word 54. Bits that are pushed to the left beyond the bit width of the adaptive output word or result word (i.e. moved to a position where their place goes beyond the most significant bit of the adaptive output word or result word) are discarded or cut. The number of bits to be shifted is determined in such a way that the mapping of the input word 51, 52 to the adaptive partial words 61, 62 or the adaptive input word 63, 64 is offset and corrected. This shifting is carried out in particular by a functional block called a bit shift circuit 6 or bit shift circuit downstream of the processing unit 2. The bit shifting circuit 6 can be configured by a (third) configuration signal 16 transmitted via a corresponding control line, so that the bit shifting circuit 6 performs a shift of a certain number of bits. If the processing unit 2 contains an internal bit shifting unit (not shown), this shift of a certain number of bits can be partly or completely performed already within the processing unit 2, for example already shifting the adaptation result partial word.
[0064] In summary, the procedure described results in calculations being performed with reduced precision (ie, with less significant bits) and therefore the adapted result word has a relatively low precision.
[0065] Among other things, a control circuit 10 is provided, which commands the above-mentioned steps, i.e. supplies input words 51, 52 to the processing unit 2 or the adaptation circuit 4 and generates configuration signals 12, 14, 16 for the processing unit 2, the adaptation circuit 4 and possibly the bit-shifting circuit 6. The control circuit 10 together with the adaptation circuit 4 and possibly the bit-shifting circuit 6 form a control assembly. The control assembly thus formed is configured for carrying out the method according to the invention for fault-tolerant operation of a processing unit, for example as described below.
[0066] The control assembly (or control unit) together with the processing unit forms a fault-tolerant circuit arrangement corresponding to the method. A single control circuit 10 can be provided for a number of processing units and corresponding upstream and downstream functional blocks. Correspondingly, this circuit arrangement can include a number of processing units and corresponding upstream and downstream functional blocks. A number of processing units or a number of processing units form a processing assembly. The computing unit can include a processing assembly and a control unit and is configured to perform the method for fault-tolerant operation of the processing units in one or more processing units of the processing assembly in which an error is identified, for input words to be processed in a first computing manner, and to perform processing in the first computing manner for processing units of the processing assembly in which no error is identified.
[0067] 2 shows a flow diagram of a method for fault-tolerant operation of a processing unit according to one embodiment. As mentioned above, the method may be implemented by a control assembly having, among other things, a control circuit, an adaptation circuit, and possibly a bit shifting circuit.
[0068] In an optional step 100, it is determined that an error exists in one of the sub-processing units of the processing unit, i.e. that this processing unit does not function without errors and thus the operation performed by this processing unit leads to an incorrect result. In this regard, inter alia, each sub-processing unit is checked whether it does not function without errors (or functions incorrectly). This can be done, for example, by performing a calculation by the processing unit with suitable predefined input values or input words whose result is known. If the calculated result does not match the known result, an error is inferred. The predefined input values are, for example, selected so that only one sub-processing unit is involved in the calculation.
[0069] Step 100 or the checks contained therein can be carried out, for example, regularly or at specific times (e.g. at start-up of a circuit arrangement which includes the processing unit). Alternatively or additionally, step 100 can also be indicated after it has been established that the processing unit does not function without errors, for example within the context of a check of the functionality of the processing unit. Step 100 then serves to determine that the error is caused by one sub-processing unit and not by another functional element of the processing unit.
[0070] In optional step 110, at least one sub-processing unit is determined to function without error. In this regard, a procedure can be followed similar to the test in step 100, whereby a sub-processing unit is determined to function without error if it is not found to function incorrectly, i.e. if the result calculated for a given input value matches a known result.
[0071] The presence of an error in one sub-processing unit and / or information about which one or which sub-processing units function without error may already be known from previous tests and may be stored, for example, in a memory of the control circuit. Correspondingly, step 100 or step 110 may possibly be omitted.
[0072] From now on, it is assumed that a processing circuit is provided for a first arithmetic scheme for the input word to be processed, and that the processing circuit is capable of being erroneous due to the presence of an error.
[0073] In step 120, an adaptation input word is formed from the input word to be processed. An adaptation partial word is determined from the input word to be processed. The adaptation partial word is suitable for processing in at least one error-free functioning sub-processing unit and has, for example, a corresponding bit width. An adaptation input word is then formed, which respectively includes at least one adaptation partial word. At least one adaptation partial word is inserted into at least one section of the respective adaptation input word that corresponds to at least one error-free functioning sub-processing unit, i.e. in the section in which at least one partial word is located that is processed by the respective error-free functioning sub-processing unit. Step 120 can be performed, for example, in that the input word to be processed is transmitted to an adaptation circuit, which is controlled to form the adaptation input word, in which case, inter alia, the adaptation circuit is configured by a second configuration signal.
[0074] The adaptive partial words are formed, inter alia, by rounding the input word to be processed. The number of significant digits in the rounding is selected according to the bit width of the adaptive partial word (for example the same as the bit width of the adaptive partial word or the same as the bit width of the adaptive partial word excluding the sign bit, etc.). The significant digits after the rounding are respectively used as the adaptive partial word, and the invalid digits after the rounding are truncated, which can be considered as a rescaling by the corresponding power of 2 (and truncation of the decimal point).
[0075] The bits of the adaptation input word in the interval in which no adaptation sub-word is located may have any value or may be set to a specific value, for example zero.
[0076] In step 130, the processing unit is instructed to process the adaptive input word in a second arithmetic scheme (which is different from the first arithmetic scheme). In particular, the processing unit is configured (by the first configuration signal) for the second arithmetic scheme. Processing of the adaptive input word in the second arithmetic scheme results in an adaptive output word.
[0077] For example, an adaptation input word is transmitted to an input register of a processing unit and processing is started (after configuration to the second arithmetic method) by a control signal and / or in response to a clock signal. The adaptation partial words are arranged in sections of the adaptation input word that correspond to at least one error-free functioning sub-processing unit, so that the adaptation partial words are processed by the at least one error-free functioning sub-processing unit, whereby one or more adaptation result partial words are determined and an adaptation output word is obtained from the adaptation result partial words. This may include, inter alia, a corresponding configuration of the processing units with the first configuration signal.
[0078] In step 140, an adaptation result word is determined from the adaptation output word. Step 140 comprises one or more sub-steps or sub-operations performed by the processing unit and / or one or more sub-steps or sub-operations performed after the processing by the processing unit. The sub-operations performed by the processing unit are in particular sub-operations performed to perform the mathematical operation implemented by the processing unit. In the case of a multiply-add operation (as in FIG. 1), this is for example a summation of the adaptation result sub-words. Depending on the circumstances, a bit-shift operation may also be performed by the processing unit. By executing the sub-operations performed by the processing unit, an adaptation output word is obtained, for example in an output register of the processing unit. The sub-operations performed after the processing by the processing unit are in particular at least one bit-shift operation corresponding to at least one error-free functioning sub-processing unit. That is, at least one bit shift operation for compensating the mapping of the input word to be processed onto the adaptation input word and thus the position of the adaptation partial word in the adaptation input word, which has been changed with respect to its original position (i.e. position), if this has not already been done by the partial operations performed by the processing unit. The at least one bit shift operation is performed, for example, by a bit shift circuit configured for this purpose by a third configuration signal. The bit shift operation acts on the adaptation output word to move its bits (whereby zeros can be inserted to the right or to the left, depending on which direction the bit shift operation is performed) in order to obtain an adaptation result word. [Explanation of symbols]
[0079] 2 Processing Unit 4 Applicable circuits 6-bit shift circuit 10 Control circuit 12 First configuration signal 14 Second configuration signal 16 Third configuration signal 32, 34 Input Registers 36 Output Registers 40, 41, 42, 43 Sub-processing unit 51, 52 Input word 54 Adaptation Result Words 61, 62 Adaptation Part Word 63, 64 adaptive input words 66 adaptive output words 100. Step of determining whether an error exists in one of the sub-processing units (43). 110. Step of determining at least one sub-processing unit (40) that functions without error. 120 forming an adaptive input word (63, 64) in which the adaptive partial word is placed 130 processing the adaptive input word (63, 64) with a second of the plurality of algorithms 140 Mapping the adapted output word (66) to an adapted result word (54)
Claims
1. A method for fault-tolerant operation of a processing unit (2) with a number of sub-processing units (40, 41, 42, 43), each of which is configured for processing one or more partial words and for determining result partial words thereon, said processing unit (2) being configurable for a number of arithmetic schemes and configured for processing partial words of an input word arranged in an interval of said input word in the sub-processing unit corresponding to said interval and for determining an output word from the result partial words determined thereby in dependence on the respectively configured arithmetic scheme, If an error is present in one sub-processing unit (43) or in the processing unit, for an input word (51, 52) to be processed that is defined for processing by the processing unit in a first operation mode of the plurality of operation modes, - determining (120) from said input word (51, 52) to be processed adaptive partial words (61, 62) suitable for processing in at least one error-free functioning sub-processing unit (40) and forming an adaptive input word (63, 64) in which said adaptive partial words are located in intervals corresponding to said at least one error-free functioning sub-processing unit (40); - processing (130) said adaptive input words (63, 64) by said processing unit with a second of said plurality of algorithms to determine adapted output words (66); The method includes:
2. 2. The method of claim 1, further comprising the step of checking for each sub-processing unit (40, 41, 42, 43) whether it does not function without errors, and / or determining (110) said at least one sub-processing unit (40) that functions without errors, in order to determine (100) the presence of an error in one sub-processing unit (43).
3. 3. The method according to claim 1 or 2, wherein the processing unit implements a mathematical operation that depends on the arithmetic scheme, the mathematical operation being or comprising forming a product of the input word or forming a product of the partial words of the input word, and each of the sub-processing units (40, 41, 42, 43) is configured for determining a product of respectively two partial words of the input word as a result partial word, and the mathematical operation is in particular a multiply-add operation.
4. 4. The method according to claim 1, wherein the forming (120) of the adaptive partial words for each input word comprises rounding the input word (51, 52) to be processed to a relatively significant part having a bit-width corresponding to the bit-width of the adaptive partial word (61, 62) to be formed, respectively, and using the relatively significant part as the respective adaptive partial word.
5. The method of claim 4 , wherein the rounding is toward zero.
6. The method of any one of claims 1 to 5, wherein a bit shift operation is performed to map (140) the adapted output word (66) of the processing unit into an adapted result word (54).
7. 7. The method according to claim 1, wherein the first computational scheme is processing of the input words in a first bit-width, in particular in the entire bit-width, and the second computational scheme is processing of the input words in a second bit-width, the second bit-width being smaller than the first bit-width, in particular being an integer fraction of the first bit-width.
8. A circuit arrangement including a processing unit (2) and a control assembly, said processing unit (2) having a number of sub-processing units (40, 41, 42, 43), each of which is configured for processing one or more partial words and for determining a result partial word thereon, said processing unit (2) being configurable for a number of arithmetic schemes and configured for processing partial words of an input word arranged in an interval of said input word in said sub-processing unit corresponding to said interval and for determining an output word from the result partial words determined thereby in dependence on said respectively configured arithmetic schemes, The control assembly is configured to perform the method according to any one of claims 1 to 7. Circuit configuration.
9. 9. The circuit arrangement of claim 8, wherein the control assembly comprises a control circuit (10), the control circuit (10) being configured to generate at least one first configuration signal (12) for configuring the processing unit (2), the at least one first configuration signal (12) configuring the processing unit according to one of the arithmetic schemes.
10. A circuit arrangement as claimed in claim 8 or 9, wherein the control assembly comprises an adaptation circuit (4) configured to receive an input word to be processed and, on the basis of which, to form the adaptive input word in accordance with at least one second configuration signal (14), and dependent on claim 9, the control circuit (10) is configured to generate the at least one second configuration signal (14), whereby the adaptive input word is formed using the adaptation partial words (61, 62).
11. A circuit arrangement according to any one of claims 8 to 10, wherein the control assembly comprises a bit shift circuit (6) configured for shifting the adaptation output word (66) of the processing unit (2) by a number of bits to obtain an adaptation result word (54), in particular the number of bits being configurable corresponding to a third configuration signal (16), and depending on claim 9, the control circuit (10) is configured for generating the third configuration signal (16) depending on the at least one error-free functioning sub-processing unit (40).
12. A method for fault-tolerant operation of a processing assembly comprising a number of processing units (2), each processing unit (2) having a number of sub-processing units (40, 41, 42, 43), each sub-processing unit being configured for processing one or more partial words and for determining result partial words thereon, each processing unit (2) being configurable for a number of arithmetic schemes and configured for processing partial words of an input word arranged in an interval of said input word in said sub-processing unit corresponding to said interval and for determining an output word from the result partial words determined thereby in dependence on said respectively configured arithmetic scheme, a number of input words are defined for processing in a first algorithm in a processing unit of said number of processing units (2) assigned to said input words; If an error is present in at least one processing unit of said multiple processing units, the processing of the input word assigned to said at least one processing unit in which an error is present is performed by a method according to any one of claims 1 to 7, the input words assigned to the processing units in which no errors exist are processed in the first arithmetic scheme; method.
13. a processing assembly comprising a number of processing units (2), each processing unit (2) having a number of sub-processing units (40, 41, 42, 43), each sub-processing unit being configured for processing one or more partial words and for determining a result partial word thereon, each sub-processing unit (2) being configurable for a number of arithmetic schemes, the processing assembly being configured for processing partial words of an input word arranged in an interval of the input word in the sub-processing unit corresponding to the interval and for determining an output word from the result partial words determined thereby in dependence on the respectively configured arithmetic scheme; A control unit configured to perform the method according to claim 12; A computation unit including: