Charge pump circuit and pll circuit

Abstract

To provide a charge pump circuit that is low-noise, can suppress an increase in installation area, and can suppress an increase in design man-hours.SOLUTION: A charge pump circuit according to an embodiment includes a current source, a first current mirror circuit having an input terminal connected to the current source, a second current mirror circuit having an input terminal connected to an output terminal of the first current mirror circuit, a third current mirror circuit having an input terminal connected to a first output terminal of the second current mirror circuit, a first switch having a first terminal connected to a second output terminal of the second current mirror circuit, and an output terminal connected to an output terminal of the third current mirror circuit and a second terminal of the first switch via a first node.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The embodiments relate to a charge pump circuit and a PLL circuit. [Background technology]

[0002] A PLL (Phase Locked Loop) circuit is known as a circuit for generating a signal synchronized with a reference frequency. The PLL circuit includes a charge pump (CP) circuit. In the PLL circuit, the charge pump circuit converts an error signal (voltage) detected by a phase detector into a current signal, for example. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-57751 A Summary of the Invention [Problem to be solved by the invention]

[0004] A charge pump circuit that is low-noise, can suppress an increase in installation area, and can suppress an increase in design man-hours. [Means for solving the problem]

[0005] A charge pump circuit according to an embodiment includes a current source, a first current mirror circuit having an input terminal connected to the current source, a second current mirror circuit having an input terminal connected to an output terminal of the first current mirror circuit, a third current mirror circuit having an input terminal connected to a first output terminal of the second current mirror circuit, a first switch having a first terminal connected to a second output terminal of the second current mirror circuit, and an output terminal connected to an output terminal of the third current mirror circuit and a second terminal of the first switch via a first node. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing a configuration of a PLL circuit according to an embodiment. [Diagram 2] FIG. 2 is a circuit diagram showing the configuration of a charge pump circuit and a loop filter circuit according to the embodiment. [Diagram 3] FIG. 3 is a waveform diagram showing a first example of waveforms of various signals applied in a setup operation in the PLL circuit according to the embodiment. [Figure 4] FIG. 4 is a waveform diagram showing a second example of waveforms of various signals applied in a setup operation in the PLL circuit according to the embodiment. [Diagram 5] FIG. 5 is a timing chart showing an example of the states of signals applied during a current source period and a current sink period and the magnitudes of various currents in the charge pump circuit according to the embodiment. [Figure 6] FIG. 6 is a circuit diagram showing an example of a current path in a current discharge period of the charge pump circuit and the loop filter according to the embodiment. [Figure 7] FIG. 7 is a circuit diagram showing an example of a current path in a current sink period of the charge pump circuit and the loop filter according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings. In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. When it is not necessary to distinguish between elements represented by reference numerals containing the same letters, these elements are referred to by reference numerals containing only letters.

[0008] In the following description, when a first element is "connected" to another second element, it includes the first element being indirectly connected to the second element through an intermediate element that is always or selectively conductive, or directly connected to the second element without an intermediate element.

[0009] In the following description, a state in which both ends of a switch are electrically connected via a switch is referred to as an on state, and a state in which both ends of a switch are not electrically connected via a switch is referred to as an off state.

[0010] 1. Configuration 1.1 PLL circuit FIG. 1 is a block diagram showing an example of a configuration of a PLL (Phase Locked Loop) circuit according to an embodiment.

[0011] 1, the PLL circuit 1 includes a modulator (MOD) 2, a divider (DIV) 3, a phase frequency detector (PFD) 4, a charge pump circuit (CP) 5, a loop filter (LF) 6, and a voltage controlled oscillator (VCO) 7. The PLL circuit 1 outputs an output signal Fout in response to an input signal Fin and a division ratio Fc. The input signal Fin is, for example, a signal having a certain frequency.

[0012] The modulator 2 is, for example, a delta-sigma modulator. The modulator 2 performs delta-sigma modulation based on a frequency-divided signal Fn input from the frequency divider 3 and a frequency-division ratio Fc, which is an input signal from an external source (not shown), and outputs a frequency-division control signal to the frequency divider 3.

[0013] The frequency divider 3 generates a frequency-divided signal Fn by dividing the frequency of the output signal Fout fed back from the voltage-controlled oscillator 7 based on the frequency-division control signal input from the modulator 2. The frequency divider 3 outputs the frequency-divided signal Fn to the modulator 2 and the phase frequency comparator 4. The frequency-divided signal Fn is, for example, a signal having the same frequency as Fin.

[0014] The phase frequency comparator 4 outputs a boost signal UP and a step-down signal DN to the charge pump circuit 5 based on an input signal Fin from an external source (not shown) and a frequency-divided signal Fn input from the frequency divider 3. The boost signal UP and the step-down signal DN are, for example, pulse signals whose pulse widths are determined according to the phase difference between the input signal Fin and the frequency-divided signal Fn. Specifically, for example, the phase frequency comparator 4 sets the boost signal UP or the step-down signal DN to an “H” (high) level during the period after one of the pulses of the input signal Fin and the frequency-divided signal Fn falls and before the other pulse falls.

[0015] The charge pump circuit 5 supplies a current Icp to the loop filter 6 for a period corresponding to the pulse width of the voltage-up signal UP and voltage-down signal DN from the phase frequency comparator 4. In the following description, the direction in which the current Icp flows from the charge pump circuit 5 to the loop filter 6 side is defined as a positive direction, and the current Icp flowing in the positive direction is denoted as +Icp. The direction in which the current Icp flows from the loop filter 6 to the charge pump circuit 5 side is defined as a negative direction, and the current Icp flowing in the negative direction is denoted as -Icp.

[0016] The loop filter 6 charges and discharges electric charges according to the direction of the current Icp received from the charge pump circuit 5, and converts the current into a DC voltage. The loop filter 6 outputs the converted voltage Vctrl to the voltage-controlled oscillator 7.

[0017] The voltage controlled oscillator 7 outputs an output signal Fout having a frequency corresponding to the magnitude of the voltage Vctrl received from the loop filter 6. The output signal Fout is, for example, a signal having a frequency different from that of Fin. The output signal Fout is also output to the frequency divider 3.

[0018] 1.2 Charge pump circuit configuration Next, the configuration of the charge pump circuit 5 of the PLL circuit 1 according to the embodiment will be described with reference to Fig. 2. Fig. 2 is a circuit diagram showing an example of the configuration of the charge pump circuit and the loop filter according to the embodiment.

[0019] The charge pump circuit 5 includes a current source 10, transistors 20, 21, 22, 23, 24, 25, 26, 27, 28, and 29, switches 40, 41, 42, and 43, resistors 50 and 51, and a charge pump output terminal Cout. The charge pump circuit 5 controls switching between the on state and the off state of each of the switches 40, 41, 42, and 43 based on an input from the phase frequency comparator 4. In response to this switching, a current Icp is output from the charge pump output terminal Cout to the loop filter 6.

[0020] The transistors 20, 21, 22, 23, 24, 25, 26, 27, 28, and 29 include, for example, metal oxide semiconductor field effect transistors (MOSFETs). The transistors 20, 21, 26, 27, 28, and 29 include, for example, N-type MOSFETs. The transistors 22, 23, 24, and 25 include, for example, P-type MOSFETs.

[0021] The current source 10 has an input terminal to which a voltage Vdd is supplied, and an output terminal connected to a node N1. The voltage Vdd is a power supply voltage that drives the charge pump circuit 5. The current source 10 outputs a reference current Iref to the node N1.

[0022] The transistor 20 has a drain terminal and a gate terminal connected to the node N1, and a source terminal supplied with a voltage Vss. The voltage Vss is a ground voltage that serves as a reference potential when the charge pump circuit 5 operates, and is, for example, 0 V. The supply of the voltage Vss is also referred to as being grounded.

[0023] The transistor 21 has a drain terminal connected to the node N2, a source terminal to which the voltage Vss is supplied, and a gate terminal connected to the node N1. The transistor 21 has, for example, the same gate length and gate width as the transistor 20.

[0024] The transistors 20 and 21 constitute a current mirror C1. The current mirror C1 is constituted by, for example, an N-type MOSFET.

[0025] The transistor 22 has a drain terminal and a gate terminal connected to the node N2, and a source terminal to which a voltage Vdd is supplied. The transistor 22 has a gate length and a gate width that are both about twice as large as those of the transistor 20, for example.

[0026] The transistor 23 has a drain terminal connected to the node N3, a source terminal to which a voltage Vdd is supplied, and a gate terminal connected to the node N2. The transistor 23 has, for example, about twice the gate length and about four times the gate width of the transistor 20.

[0027] The transistor 24 has a drain terminal connected to the node N4, a source terminal to which a voltage Vdd is supplied, and a gate terminal connected to the node N2. The transistor 24 has, for example, about twice the gate length and about 40 times the gate width of the transistor 20.

[0028] The transistor 25 has a drain terminal connected to the node N5, a source terminal to which a voltage Vdd is supplied, and a gate terminal connected to the node N2. The transistor 25 has, for example, about twice the gate length and about eight times the gate width of the transistor 20.

[0029] The transistors 22, 23, 24, and 25 constitute a current mirror C2. The current mirror C2 is constituted by, for example, a P-type MOSFET.

[0030] The transistor 26 has a drain terminal and a gate terminal connected to the node N3, and a source terminal supplied with a voltage Vss. The transistor 26 has a gate length equal to that of the transistor 20 and a gate width that is about one-fourth that of the transistor 20, for example.

[0031] The transistor 27 has a drain terminal connected to the node N6, a source terminal to which the voltage Vss is supplied, and a gate terminal connected to the node N3. The transistor 27 has a gate length equivalent to that of the transistor 20 and a gate width approximately 2.5 times that of the transistor 20.

[0032] The transistors 26 and 27 constitute a current mirror C3. The current mirror C3 is constituted by, for example, an N-type MOSFET.

[0033] Transistor 28 has a drain terminal connected to node N7, a source terminal to which voltage Vss is supplied, and a gate terminal connected to node N5. Transistor 28 has, for example, about four times the gate length and about eight times the gate width of transistor 20.

[0034] The transistor 29 has a drain terminal and a gate terminal connected to the node N5, and a source terminal to which a voltage Vss is supplied. The transistor 29 has, for example, a gate length that is about four times larger and a gate width that is about 32 times larger than that of the transistor 20.

[0035] The transistors 28 and 29 constitute a current mirror C4. The current mirror C4 is constituted by, for example, an N-type MOSFET.

[0036] The current mirrors C1 and C2, C2 and C3, and C2 and C4 are connected to each other. That is, the current mirror C3 passes a current obtained by mirroring the reference current Iref through the current mirrors C1 and C2 to the transistor 27. The current mirror C4 passes a current obtained by mirroring the reference current Iref through the current mirrors C1 and C2 to the transistor 28.

[0037] The switches 40, 41, 42, and 43 include, for example, transistors. The switches 40, 41, 42, and 43 control whether to connect (turn on) or disconnect (turn off) both ends based on the boost signal UP, UP, the step-down signal DN, or DN input from the phase frequency comparator 4. The boost signal UP is an inverted signal of the boost signal UP. The step-down signal DN is an inverted signal of the step-down signal DN. In the following description, when each signal is at the “H” level, it means that a voltage higher than the threshold voltage of the transistor is applied to the gate of the corresponding transistor. When a signal is at the “L” (Low) level, it means that a voltage lower than the threshold voltage of the transistor is applied to the gate of the corresponding transistor.

[0038] The switch 40 includes, for example, a P-type MOSFET. A first terminal of the switch 40 is connected to the node N4, and a second terminal of the switch 40 is connected to the resistor 50. For example, the switch 40 is turned off when the boost signal UP is at an “H” level, and is turned on when the boost signal UP is at an “L” level.

[0039] The switch 41 includes, for example, a P-type MOSFET. A first end of the switch 41 is connected to a node N4, and a second end of the switch 41 is connected to a node N7. For example, the switch 41 is turned off when the boost signal UP is at an “H” level, and is turned on when the boost signal UP is at an “L” level.

[0040] The boost signals UP and UP received by the switches 40 and 41, respectively, are inverted signals, so the switches 40 and 41 can be regarded as one SPDT (Single Pole Double Throw) switch. That is, when the boost signal UP is at the “H” level, the transistor 24 and the charge pump output terminal Cout are electrically connected, and when the boost signal UP is at the “L” level, the transistor 24 and the resistor 50 are electrically connected.

[0041] The switch 42 includes, for example, an N-type MOSFET. A first end of the switch 42 is connected to the node N6, and a second end of the switch 42 is connected to the node N7. For example, the switch 42 is turned on when the step-down signal DN is at an “H” level, and is turned off when the step-down signal DN is at an “L” level.

[0042] The switch 43 includes, for example, an N-type MOSFET. A first terminal of the switch 43 is connected to the node N6, and a second terminal of the switch 43 is connected to the resistor 51. For example, the switch 43 is turned on when the step-down signal DN is at an “H” level, and is turned off when the step-down signal DN is at an “L” level.

[0043] The step-down signals DN and DN received by the switches 42 and 43, respectively, are inverted signals, so the switches 42 and 43 can be regarded as one SPDT switch. That is, when the step-down signal DN is at the “H” level, the transistor 27 and the charge pump output terminal Cout are electrically connected, and when DN is at the “L” level, the transistor 27 and the resistor 51 are electrically connected.

[0044] The resistor 50 is a pull-down resistor. One end of the resistor 50 is connected to the second end of the switch 40, and the other end is grounded.

[0045] The resistor 51 is a pull-up resistor. One end of the resistor 51 is connected to the second end of the switch 43, and the other end of the resistor 51 is supplied with a voltage Vdd.

[0046] The charge pump output terminal Cout is connected to the node N7 and outputs a current Icp to the loop filter 6.

[0047] The loop filter 6 includes resistors 60 and 61, capacitors 70, 71, and 72, and a loop filter output terminal Lout.

[0048] One end of the resistor 60 is connected to the charge pump output terminal Cout, and the other end is connected to the loop filter output terminal Lout.

[0049] The resistor 61 has one end connected to the charge pump output terminal Cout and one end of the resistor 60, and the other end connected to the capacitor .

[0050] One end of the capacitor 70 is connected to the other end of the resistor 61, and the other end is grounded.

[0051] The capacitor 71 has one end connected to the charge pump output terminal Cout, one end of the resistor 60, and one end of the resistor 61, and the other end grounded.

[0052] The capacitor 72 has one end connected to the loop filter output terminal Lout and the other end of the resistor 60, and the other end grounded.

[0053] The capacitors 70, 71, and 72 are charged when the current Icp is discharged from the charge pump circuit 5, and are discharged when the current Icp is absorbed by the charge pump circuit 5.

[0054] The loop filter output terminal Lout is connected to the other end of the resistor 60 and one end of the capacitor 72 , and outputs a voltage Vctrl to the voltage controlled oscillator 7 .

[0055] 2. Operation of PLL circuit Next, the operation of the PLL circuit according to the embodiment will be described.

[0056] 2.1 Setup Operation In the charge pump circuit 5, a setup operation is first performed until the phase is locked. In the setup operation, the charge pump circuit 5 operates to reduce the phase difference between the reference input signal Fin and the frequency-divided signal Fn. FIG. 3 is a waveform diagram showing a first example of the waveforms of various signals applied in the setup operation in the PLL circuit according to the embodiment. FIG. 4 is a waveform diagram showing a second example of the waveforms of various signals applied in the setup operation in the PLL circuit according to the embodiment. In FIGS. 3 and 4, the input signal Fin, the frequency-divided signal Fn, the step-up signal UP, and the step-down signal DN are shown as the various signals. The first example shows a case where the phase of the frequency-divided signal Fn lags behind that of the input signal Fin. The second example shows a case where the phase of the frequency-divided signal Fn leads that of the input signal Fin.

[0057] In the setup operation, the phase frequency comparator 4 compares the phase of the input signal Fin with the phase of the frequency-divided signal Fn, and outputs the voltage-boosting signal UP and the voltage-dropping signal DN to the charge pump circuit 5. In the following description, during periods not specifically mentioned, both the voltage-boosting signal UP and the voltage-dropping signal DN are at the “L” level.

[0058] For example, as shown in Fig. 3, when the phase of the frequency-divided signal Fn lags behind the input signal Fin, the phase frequency comparator 4 sets the boost signal UP to "H" level for a period corresponding to the phase shift. Specifically, the boost signal UP is set to "H" level during the period Tu from the falling edge of the input signal Fin to the falling edge of the frequency-divided signal Fn. During this period, the step-down signal DN remains at "L" level.

[0059] When the charge pump circuit 5 receives the "H" level boost signal UP and the "L" level step-down signal DN, it turns on the switches 41 and 43 and turns off the switches 40 and 42. At this time, the current Iup flows and the current Idn does not flow. Also, the current Ioffset flows. Since the magnitude of the current Iup is sufficiently larger than the current Ioffset, the current Icp has a positive value. In other words, the charge pump circuit 5 outputs the current Icp.

[0060] When the charge pump circuit 5 outputs the current Icp, electric charges are stored in the capacitors 70, 71, and 72 in the loop filter 6. That is, the capacitors 70, 71, and 72 are in a charged state. As a result, the voltage Vctrl applied to the loop filter output terminal Lout increases. Depending on the length of time during which the voltage Vctrl is increasing, the frequency of the output signal Fout increases, that is, the frequency of the frequency-divided signal Fn also increases.

[0061] For example, as shown in Fig. 4, when the phase of the frequency-divided signal Fn is ahead of the input signal Fin, the phase frequency comparator 4 sets the step-down signal DN to "H" level for a period according to the phase shift. Specifically, the step-down signal DN is set to "H" level during the period Td from the falling edge of the frequency-divided signal Fn to the falling edge of the input signal Fin. During this period, the step-up signal UP remains at "L" level.

[0062] When the charge pump circuit 5 receives the voltage-up signal UP at the "L" level and the voltage-down signal DN at the "H" level, it turns on the switches 40 and 42 and turns off the switches 41 and 43. At this time, the current Iup does not flow, but the current Idn does. Also, the current Ioffset flows. Therefore, the current Icp has a negative value. In other words, the charge pump circuit 5 sinks the current.

[0063] When the charge pump circuit 5 absorbs the current Icp, the charges stored in the capacitors 70, 71, and 72 in the loop filter 6 are released. That is, the capacitors 70, 71, and 72 are in a discharged state. As a result, the voltage Vctrl applied to the loop filter output terminal Lout decreases. Depending on the length of time during which the voltage Vctrl is decreasing, the frequency of the output signal Fout decreases, that is, the frequency of the frequency-divided signal Fn also decreases.

[0064] When the input signal Fin and the frequency-divided signal Fn are in phase with each other after the setup operation, the PLL circuit 1 is in a steady state. In the steady state, the PLL circuit 1 is "locked." When the PLL circuit 1 is locked, for example, the PLL circuit 1 can steadily output a desired output signal Fout.

[0065] 2.2 Exhalation and suction actions When the PLL circuit 1 is locked, the charge pump circuit 5 sources and sinks the current Icp for each period of the input signal Fin, thereby outputting an output signal Fout with a substantially constant frequency. This operation will be described in detail below with reference to FIGS.

[0066] FIG. 5 is a timing chart showing an example of the state of the applied signal and the magnitude of various currents in the charge pump circuit 5 according to the embodiment. Part (a) of FIG. 5 shows the state of the boost signal UP. Part (b) of FIG. 5 shows the fluctuation of the current Iup flowing through the switch 41. Part (c) of FIG. 5 shows the fluctuation of the current Ioffset flowing through the transistor 28. Part (d) of FIG. 5 shows the fluctuation of the current Icp flowing through the charge pump output terminal Cout. FIG. 6 is a circuit diagram showing an example of a current path in a current discharge period of the charge pump circuit according to the embodiment. FIG. 7 is a circuit diagram showing an example of a current path in a current sink period of the charge pump circuit according to the embodiment. The current discharge period corresponds to the period from time t1 to time t2 in FIG. 5. The current sink period corresponds to the period from time t2 to time t3 in FIG. 5. The period from time t1 to time t3 corresponds to the period T of the input signal Fin.

[0067] First, the operation of the charge pump circuit 5 and the loop filter 6 during the current discharge period will be described with reference to Figs. 5 and 6. During the current discharge period, a voltage step-up signal UP at "H" level and a voltage step-down signal DN at "L" level are input. As a result, the switches 41 and 43 are in the ON state, and the switches 40 and 42 are in the OFF state. At this time, the current Iup flows at I1 (>0). Also, the current Ioffset continues to flow at I2 (>0). Therefore, the magnitude of the current Icp is I1-I2. The current I1 flows a current sufficiently larger than the current I2 (for example, 10 times), so the current Icp has a positive value (I1-I2>0). That is, during this period, the charge pump circuit 5 discharges a current.

[0068] When the charge pump circuit 5 outputs the current Icp, electric charges are stored in the capacitors 70, 71, and 72 in the loop filter 6. That is, the capacitors 70, 71, and 72 are in a charged state. As a result, the voltage Vctrl applied to the loop filter output terminal Lout increases.

[0069] Next, the operation of the charge pump circuit 5 and the loop filter 6 during the current sink period will be described with reference to Figures 5 and 7. During the current discharge period, the voltage step-up signal UP and voltage step-down signal DN are input at "L" level. This causes the switches 40 and 43 to be in the on state, and the switches 41 and 42 to be in the off state. Therefore, the current Iup does not flow. Meanwhile, the current Ioffset continues to flow at I2, so the magnitude of the current Icp becomes a negative value -I2. That is, during this period, the charge pump circuit 5 sinks the current Icp.

[0070] When the charge pump circuit 5 draws in the current Icp, the charges stored in the capacitors 70, 71, and 72 are released in the loop filter 6. That is, the capacitors 70, 71, and 72 are in a discharged state. As a result, the voltage Vctrl applied to the loop filter output terminal Lout decreases.

[0071] The amount of charge flowing as current Iup over period T is equal to the amount of charge flowing as current Ioffset. That is, the area of ​​hatched region A in part (b) of Fig. 5 is equal to the area of ​​hatched region B in part (c) of Fig. 5. Therefore, the sum of the charges stored in capacitors 70, 71, and 72 at the start of the cycle t1 is equal to the sum of the charges stored in capacitors 70, 71, and 72 at the end of the cycle t3.

[0072] Through the above cycle, the voltage Vctrl generated by the loop filter 6 fluctuates and is output to the voltage controlled oscillator 7, which then outputs the output signal Fout. In this way, the PLL circuit 1 maintains a steady state.

[0073] 3. Effects of this embodiment The configuration according to the present embodiment makes it possible to provide a charge pump circuit that is low-noise, can suppress an increase in the installation area, and can suppress an increase in the number of design steps.

[0074] In the charge pump circuit according to this embodiment, the current mirrors C3 and C4 are connected to the current mirror C1 via the current mirror C2. That is, the sizes of the current mirrors C1, C3, and C4 are configured independently. With this configuration, when the transistors constituting the current mirror are increased in size to reduce noise, the number of transistors that must be increased in size can be reduced. This allows the transistors that do not contribute to the superposition of noise to be reduced in size (not increased in size). Therefore, compared to a charge pump circuit with a structure in which the current mirror is shared, the charge pump circuit according to this embodiment allows the entire circuit to be reduced in size.

[0075] It is known that when a charge pump circuit outputs a current Icp, noise such as flicker noise and thermal noise originating from transistors and current sources is mixed in. Noise is undesirable because it deteriorates the quality of the transmitted signal and increases the possibility of outputting an unintended signal. In addition, in a current mirror circuit in a charge pump circuit, noise generated in a mirror source transistor may be superimposed on the current flowing through a mirror destination transistor depending on the mirror ratio. Therefore, in the process of passing through the current mirror circuit, noise originating from multiple transistors may be superimposed, resulting in large noise.

[0076] A known method for reducing noise in a charge pump circuit is to increase the size of the transistors and the current flowing through them, thereby suppressing flicker noise that increases inversely proportional to the current. However, increasing the size of the transistors also increases the installation area of ​​the charge pump circuit. In addition, in order to match the current flowing through the circuit to a predetermined value, it is necessary to adjust the gate length and gate width within the current mirror. Therefore, when one of the transistors constituting a current mirror is enlarged to reduce noise, the other transistors constituting the same current mirror may also be enlarged in the same way. For these reasons, there is a problem that it is difficult to reduce the size of a charge pump circuit.

[0077] With the configuration according to this embodiment, it is possible to reduce noise by canceling out the noise superimposed on the charge cycle and the discharge cycle in the signal output when the PLL circuit 1 is locked.

[0078] During a charging cycle, a current +Icp flowing in a positive direction through the charge pump output terminal Cout is output as a mirror of the reference current Iref. The current +Icp reflects the characteristics of the circuit connected from the current source 10 that outputs the reference current Iref via the transistors 20, 21, 22, and 24. Therefore, noise originating from the current source 10 and the transistors 20, 21, 22, and 24 is superimposed on the current +Icp.

[0079] On the other hand, in the discharge cycle, the current -Icp flowing in the negative direction through the charge pump output terminal Cout is also output by mirroring the reference current Iref. The current -Icp reflects the characteristics of the circuit connected from the current source 10 that outputs the reference current Iref via the transistors 20, 21, 22, 25, 28, and 29. Therefore, noise originating from the current source 10 and the transistors 20, 21, 22, 25, 28, and 29 is superimposed on the current -Icp.

[0080] Since the currents +Icp and -Icp are opposite-direction signals, the noise superimposed on both of them is cancelled out. That is, when the PLL circuit 1 is locked, the noise originating from the current source 10 and the transistors 20, 21, and 22 can be ignored. Also, when the PLL circuit 1 is locked, the switch 42 is rarely turned on. Therefore, the noise originating from the transistors 23, 26, and 27 can be ignored.

[0081] From the above, the source of the noise superimposed on the signal output from the loop filter 6 is limited to the transistors 24, 25, 28, and 29. This noise can be reduced by making the transistors 24, 25, 28, and 29 larger than the other transistors.

[0082] Furthermore, in the configuration according to this embodiment, the transistors 20, 21, 22, 23, 26, and 27 can be made smaller because noise is not superimposed on the signal output from the loop filter 6. As a result, the increase in the installation area of ​​the entire charge pump circuit can be suppressed, and the charge pump circuit can be made smaller.

[0083] Furthermore, with the configuration according to this embodiment, the charge pump circuit can be configured without using amplifiers, switches, etc. in the current sink operation. This eliminates the need for complex control, and reduces the number of simulation steps. This makes it possible to reduce the size of the charge pump circuit and to suppress an increase in the number of design steps. This allows the charge pump circuit and the PLL circuit to be produced efficiently.

[0084] 4.Other As a modification of this embodiment, a configuration is possible in which the transistors 20, 21, 26, 27, 28, and 29 include P-type MOSFETs, and the transistors 22, 23, 24, and 25 include N-type MOSFETs. In this case, the voltage Vss is applied to the terminal to which the voltage Vdd is applied in this embodiment, and the voltage Vdd is applied to the terminal to which the voltage Vss is applied. In addition, the direction in which the reference current Iref of the current source 10 flows is reversed.

[0085] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0086] 1...PLL circuit 2. Modulator 3...Frequency divider 4...Phase frequency comparator 5. Charge pump circuit 6…Loop filter 7…Voltage-controlled oscillator 10…Current source 20, 21, 22, 23, 24, 25, 26, 27, 28, 29…Transistors 40, 41, 42, 43…Switch 50, 51, 60, 61…Resistance 70, 71, 72...Capacitor Cout: Charge pump output terminal Lout: Loop filter output terminal

Claims

1. A current source; a first current mirror circuit having an input connected to the current source; a second current mirror circuit having an input terminal connected to the output terminal of the first current mirror circuit; a third current mirror circuit having an input terminal connected to the first output terminal of the second current mirror circuit; a first switch having a first terminal connected to the second output terminal of the second current mirror circuit; an output terminal connected to an output end of the third current mirror circuit and a second end of the first switch via a first node; A charge pump circuit comprising:

2. the first current mirror circuit and the third current mirror circuit each include a transistor having a first conductivity type; the second current mirror circuit includes a transistor having a second conductivity type different from the first conductivity type; 2. The charge pump circuit of claim 1.

3. The first current mirror circuit includes: a first transistor having a drain and a gate connected to the current source through a second node; a second transistor having a gate connected to the second node and a drain connected to an input terminal of the second current mirror circuit via a third node; Including, The second current mirror circuit includes: a third transistor including a drain and a gate connected to the third node; a fourth transistor having a drain connected to the input terminal of the third current mirror circuit via a fourth node and a gate connected to the third node; a fifth transistor having a drain connected to the first end of the first switch and a gate connected to the third node; Including, The third current mirror circuit includes: a sixth transistor having a drain and a gate connected to the fourth node; a seventh transistor having a drain connected to the first node and a gate connected to the fourth node; Including, 3. The charge pump circuit according to claim 2.

4. a fourth current mirror circuit having an input terminal connected to the third output terminal of the second current mirror circuit; a second switch having a first end connected to the output end of the fourth current mirror circuit and a second end connected to the first node; Further comprising:

2. The charge pump circuit of claim 1.

5. the first current mirror circuit, the third current mirror circuit, and the fourth current mirror circuit each include a transistor having a first conductivity type; the second current mirror circuit includes a transistor having a second conductivity type different from the first conductivity type; 5. The charge pump circuit according to claim 4.

6. The first current mirror circuit includes: a first transistor having a drain and a gate connected to the current source through a second node; a second transistor having a gate connected to the second node and a drain connected to an input terminal of the second current mirror circuit via a third node; Including, The second current mirror circuit includes: a third transistor including a drain and a gate connected to the third node; a fourth transistor having a drain connected to the input terminal of the third current mirror circuit via a fourth node and a gate connected to the third node; a fifth transistor having a drain connected to the first end of the first switch and a gate connected to the third node; an eighth transistor having a drain connected to the input terminal of the fourth current mirror circuit via a fifth node and a gate connected to the third node; Including, The third current mirror circuit includes: a sixth transistor having a drain and a gate connected to the fourth node; a seventh transistor having a drain connected to the first node and a gate connected to the fourth node; Including, The fourth current mirror circuit includes: a ninth transistor having a drain and a gate connected to the fifth node; a tenth transistor having a drain connected to the first end of the second switch and a gate connected to the fifth node; Including, 6. The charge pump circuit according to claim 5.

7. A charge pump circuit according to any one of claims 1 to 6; a phase frequency comparator connected to the charge pump circuit; a loop filter connected to the charge pump circuit; a voltage controlled oscillator connected to the loop filter; a frequency divider connected to the phase frequency comparator and the voltage controlled oscillator; 2. A PLL circuit comprising:

8. The charge pump circuit includes: When the first switch is in an on state, a first current is output to the loop filter via the output terminal; When the first switch is in an off state, a second current is input from the loop filter via the output terminal. It was configured as follows:

8. The PLL circuit according to claim 7.

9. in a first state, a total amount of charge based on the first current output from the charge pump circuit to the loop filter over one period of a signal input to the phase frequency comparator is substantially equal to a total amount of charge based on the second current input from the loop filter to the charge pump circuit over the period; 9. The PLL circuit according to claim 8.

Images