Semiconductor device

Abstract

To suppress oscillation.SOLUTION: A semiconductor device includes a first substrate 10a where a first electrode 13a, a second electrode 11a, and a third electrode 12a are provided, a second substrate 10b where a fourth electrode 13b, a fifth electrode 11b, and a sixth electrode 12b are provided and that is disposed beside the first substrate in a first direction, a first transistor 100 having a drain connected to the first electrode, a gate connected to the second electrode, and a source connected to the third electrode, a second transistor 100 having a drain connected to the fourth electrode, a gate connected to the fifth electrode, and a source connected to the sixth electrode, a first wire 30 connecting the second electrode and the fifth electrode while meandering in a second direction, and a second wire 31 connecting the third electrode and the sixth electrode while meandering in the second direction.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Power modules are known as semiconductor devices that achieve high output. A power module is configured as a single package in which multiple power semiconductors are integrated. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 4142539 Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides a semiconductor device capable of suppressing oscillations within the device. [Means for solving the problem]

[0005] The semiconductor device of the embodiment includes a first substrate having a first electrode, a second electrode, and a third electrode spaced apart from one another; a second substrate having a fourth electrode, a fifth electrode, and a sixth electrode spaced apart from one another and arranged side by side with the first substrate in a first direction; a first transistor provided on an upper surface of the first electrode and having a drain connected to the first electrode, a gate connected to the second electrode, and a source connected to the third electrode; a second transistor provided on an upper surface of the fourth electrode and having a drain connected to the fourth electrode, a gate connected to the fifth electrode, and a source connected to the sixth electrode; a first wiring that connects the second electrode and the fifth electrode in a meandering manner in a second direction intersecting the first direction; and a second wiring that connects the third electrode and the sixth electrode in a meandering manner in the second direction. [Brief description of the drawings]

[0006] [Figure 1]FIG. 1 is a circuit diagram showing an example of a circuit configuration of a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a plan view showing a configuration of an insulating substrate in a semiconductor device according to an embodiment. [Diagram 3] FIG. 3 is a cross-sectional view taken along line A1-A2 in FIG. [Figure 4] FIG. 2 is a plan view showing a configuration of a gate wiring and a source sense wiring included in a semiconductor device according to an embodiment. [Diagram 5] 5 is a cross-sectional view taken along line B1-B2 in FIG. 4. [Figure 6] 1 is a perspective view showing a meandering portion of an upper gate wiring and an upper source sense wiring included in a semiconductor device according to an embodiment; [Figure 7] 1 is a circuit diagram showing an example of a circuit configuration of an upper arm portion of a semiconductor device 1 according to an embodiment. [Figure 8] 1 is a circuit diagram showing an example of a circuit configuration of an upper arm portion of a semiconductor device 1 according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are given a common reference symbol. When multiple components having a common reference symbol are to be distinguished from one another, a subscript is added to the common reference symbol. When no particular distinction is required between multiple components, only the common reference symbol is added to the multiple components, and no subscript is added. Here, the subscript is not limited to a subscript or a superscript, but includes, for example, a lowercase alphabet added to the end of a reference symbol, and an index indicating an array.

[0008] The semiconductor device according to one embodiment is a power module, and is applied to, for example, a power conversion device for a railway vehicle, an industrial device for a renewable energy power generation system, or the like.

[0009] 1. Circuit configuration of semiconductor device First, an example of a circuit configuration of the semiconductor device 1 will be described with reference to Fig. 1. Fig. 1 is a circuit diagram showing an example of the circuit configuration of the semiconductor device 1.

[0010] 1, the semiconductor device 1 includes an upper arm portion UA ​​including a plurality of transistors connected in parallel, and a lower arm portion LA including a plurality of transistors connected in parallel. The upper arm portion UA ​​and the lower arm portion LA are connected in series.

[0011] The upper arm portion UA ​​includes a transistor Tr10a provided above an insulating substrate 10a and a transistor Tr10b provided above an insulating substrate 10b. The transistors Tr10a and Tr10b are connected in parallel. Hereinafter, when either the insulating substrates 10a or 10b is not limited, it will be referred to as "insulating substrate 10". Furthermore, when either the transistors Tr10a or Tr10b is not limited, it will be referred to as "transistor Tr10".

[0012] A plurality of transistors Tr10a may be provided above the insulating substrate 10a. In this case, the plurality of transistors Tr10a are connected in parallel. Similarly, a plurality of transistors Tr10b may be provided above the insulating substrate 10b. In this case, the plurality of transistors Tr10b are connected in parallel. The upper arm portion UA ​​may have three or more insulating substrates 10.

[0013] The lower arm portion LA includes a transistor Tr20a provided above the insulating substrate 20a and a transistor Tr20b provided above the insulating substrate 20b. The transistors Tr20a and Tr20b are connected in parallel. Hereinafter, when either the insulating substrates 20a or 20b is not limited, it will be referred to as "insulating substrate 20". Furthermore, when either the transistors Tr20a or Tr20b is not limited, it will be referred to as "transistor Tr20".

[0014] A plurality of transistors Tr20a may be provided above the insulating substrate 20a. In this case, the plurality of transistors Tr20a are connected in parallel. Similarly, a plurality of transistors Tr20b may be provided above the insulating substrate 20b. In this case, the plurality of transistors Tr20b are connected in parallel. The lower arm portion LA may have three or more insulating substrates 20.

[0015] The transistors Tr10a, Tr10b, Tr20a, and Tr20b are, for example, n-channel Metal Oxide Semiconductor (MOS) transistors.

[0016] The drains of the transistors Tr10a and Tr10b are commonly connected to a positive terminal P. A positive voltage is applied to the positive terminal P from the outside.

[0017] The gates of the transistors Tr10a and Tr10b are commonly connected to an upper gate terminal HG via an upper gate wiring. A gate signal voltage for controlling the transistors Tr10a and Tr10b is applied to the upper gate terminal HG. An inductance Lg10 is provided between the gate of the transistor Tr10a and the gate of the transistor Tr10b. In other words, one end of the inductance Lg10 is connected to the gate of the transistor Tr10a, and the other end of the inductance Lg10 is connected to the gate of the transistor Tr10b. The inductance Lg10 is a parasitic inductance in the upper gate wiring between the gate of the transistor Tr10a and the gate of the transistor Tr10b.

[0018] The sources of the transistors Tr10a and Tr10b are commonly connected to an upper source sense terminal HSS via an upper source sense wiring. The upper source sense terminal HSS is used to sense (monitor) the source voltages of the transistors Tr10a and Tr10b. An inductance Lss10 is provided between the source of the transistor Tr10a and the source of the transistor Tr10b. In other words, one end of the inductance Lss10 is connected to the source of the transistor Tr10a, and the other end of the inductance Lss10 is connected to the source of the transistor Tr10b. The inductance Lss10 is a parasitic inductance in the upper source sense wiring between the source of the transistor Tr10a and the source of the transistor Tr10b. For example, the coupling coefficient between the inductance Lss10 and the inductance Lg10 is k1.

[0019] The sources of the transistors Tr10a and Tr10b are commonly connected to the output terminal AC and the drains of the transistors Tr20a and Tr20b.

[0020] The gates of the transistors Tr20a and Tr20b are commonly connected to a lower gate terminal LG via a lower gate wiring. A gate signal voltage for controlling the transistors Tr20a and Tr20b is applied to the lower gate terminal LG. An inductance Lg20 is provided between the gate of the transistor Tr20a and the gate of the transistor Tr20b. In other words, one end of the inductance Lg20 is connected to the gate of the transistor Tr20a, and the other end of the inductance Lg20 is connected to the gate of the transistor Tr20b. The inductance Lg20 is a parasitic inductance in the lower gate wiring between the gate of the transistor Tr20a and the gate of the transistor Tr20b.

[0021] The sources of the transistors Tr20a and Tr20b are commonly connected to a lower source sense terminal LSS via a lower source sense wiring. The lower source sense terminal LSS is used to sense (monitor) the source voltages of the transistors Tr20a and Tr20b. An inductance Lss20 is provided between the source of the transistor Tr20a and the source of the transistor Tr20b. In other words, one end of the inductance Lss20 is connected to the source of the transistor Tr20a, and the other end of the inductance Lss20 is connected to the source of the transistor Tr20b. The inductance Lss20 is a parasitic inductance in the lower source sense wiring between the source of the transistor Tr20a and the source of the transistor Tr20b. For example, the coupling coefficient between the inductance Lss20 and the inductance Lg20 is k2.

[0022] The sources of the transistors Tr20a and Tr20b are commonly connected to a negative terminal N. A voltage lower than that applied to the positive terminal P is applied to the negative terminal N.

[0023] Hereinafter, when either the upper gate wiring or the lower gate wiring is not specified, it will be referred to as a "gate wiring." Furthermore, when either the upper source sense wiring or the lower source sense wiring is not specified, it will be referred to as a "source sense wiring."

[0024] 2. Structure of Semiconductor Device 2.1 Structure on the top surface of the insulating substrate First, an example of the configuration of the semiconductor device 1 will be described with reference to Fig. 2. Fig. 2 is a plan view showing the configuration of insulating substrates 10a, 10b, 20a, and 20b.

[0025] In the following description, the direction in which the upper arm portion UA ​​and the lower arm portion LA are arranged side by side on the upper surface of the base substrate 2 is referred to as the X direction. The direction that intersects with the X direction and in which the insulating substrates 10a and 10b are arranged side by side on the upper surface of the base substrate 2 is referred to as the Y direction. The direction that intersects with the X and Y directions is referred to as the Z direction. In addition, in the Z direction, the surface of the insulating substrate 10 on which the semiconductor chip 100 is arranged is referred to as the upper surface, and the opposing surface is referred to as the lower surface. The same applies to the base substrate 2 and the semiconductor chip 100.

[0026] As shown in FIG. 2, the semiconductor device 1 includes a base substrate 2, insulating substrates 10a, 10b, 20a, and 20b, gate electrodes 11a, 11b, 21a, and 21b, source electrodes 12a, 12b, 22a, and 22b, drain electrodes 13a, 13b, 23a, and 23b, and a plurality of semiconductor chips 100.

[0027] The base substrate 2 is a support for the semiconductor device 1. The base substrate 2 has a flat plate shape. The semiconductor device 1 can be fixed to an external device via the base substrate 2. The base substrate 2 can include a conductor (e.g., copper) for electrically connecting to the external device.

[0028] The insulating substrates 10a, 10b, 20a, and 20b are insulating substrates that support the semiconductor chip 100. Electrodes are provided on both sides of the insulating substrates 10a, 10b, 20a, and 20b. The insulating substrates 10a, 10b, 20a, and 20b are, for example, ceramic substrates. The insulating substrates 10a, 10b, 20a, and 20b include a conductor (for example, copper) for electrically connecting the upper electrode and the lower electrode. The insulating substrates 10a, 10b, 20a, and 20b are provided on the upper surface of the base substrate 2. An upper arm portion UA ​​configuration is provided on the upper surfaces of the insulating substrates 10a and 10b. In addition, a lower arm portion LA configuration is provided on the upper surfaces of the insulating substrates 20a and 20b.

[0029] First, the configuration on the upper surface of insulating substrate 10a will be described.

[0030] A gate electrode 11a, a source electrode 12a, and a drain electrode 13a are provided on the upper surface of the insulating substrate 10a. The gate electrode 11a, the source electrode 12a, and the drain electrode 13a are arranged on the upper surface of the insulating substrate 10a at a distance from each other. The shapes of the gate electrode 11a, the source electrode 12a, and the drain electrode 13a are arbitrary.

[0031] The gate electrode 11a includes a connection portion 14a that is connected to an upper gate wiring.

[0032] The source electrode 12a includes a connection portion 15a connected to the upper source sense wiring and a connection portion 16a connected to the output terminal AC.

[0033] The drain electrode 13a includes a connection portion 17a that is connected to the positive electrode terminal P.

[0034] In the example shown in FIG. 2, four semiconductor chips 100 are arranged on the drain electrode 13a. Note that there may be one or more semiconductor chips 100 on the drain electrode 13a. The semiconductor chip 100 is an n-channel MOS transistor. The semiconductor chip 100 on the drain electrode 13a corresponds to the transistor Tr10a described with reference to FIG. 1. A drain terminal is provided on the lower surface of the semiconductor chip 100, and a gate terminal and a source terminal are provided on the upper surface. The drain terminal of the semiconductor chip 100 is electrically connected to the drain electrode 13a. The gate terminal of the semiconductor chip 100 is connected to the gate electrode 11a via one wire WL. The source terminal of the semiconductor chip 100 is connected to the source electrode 12a via three wires WL. Note that the number of wires WL connecting the gate terminal and gate electrode 11a of the semiconductor chip 100 and the number of wires WL connecting the source terminal and source electrode 12a of the semiconductor chip 100 are arbitrary.

[0035] Next, the configuration on the upper surface of insulating substrate 10b will be described.

[0036] A gate electrode 11b, a source electrode 12b, and a drain electrode 13b are provided on the upper surface of the insulating substrate 10b. The gate electrode 11b, the source electrode 12b, and the drain electrode 13b are arranged spaced apart from each other on the upper surface of the insulating substrate 10b. The shapes of the gate electrode 11b, the source electrode 12b, and the drain electrode 13b are arbitrary.

[0037] The gate electrode 11b includes a connection portion 14b that is connected to an upper gate wiring.

[0038] The source electrode 12b includes a connection portion 15b connected to the upper source sense wiring and a connection portion 16b connected to the output terminal AC.

[0039] The drain electrode 13b includes a connection portion 17b that is connected to the positive terminal P.

[0040] In the example shown in FIG. 2, four semiconductor chips 100 are arranged on the drain electrode 13b. Note that there may be one or more semiconductor chips 100 on the drain electrode 13b. The semiconductor chip 100 on the drain electrode 13b corresponds to the transistor Tr10b described with reference to FIG. 1. The drain terminal of the semiconductor chip 100 is electrically connected to the drain electrode 13b. The gate terminal of the semiconductor chip 100 is connected to the gate electrode 11b via one wire WL. The source terminal of the semiconductor chip 100 is connected to the source electrode 12b via three wires WL.

[0041] Next, the configuration on the upper surface of the insulating substrate 20a will be described.

[0042] A gate electrode 21a, a source electrode 22a, and a drain electrode 23a are provided on the upper surface of the insulating substrate 20a. The gate electrode 21a, the source electrode 22a, and the drain electrode 23a are arranged spaced apart from each other on the upper surface of the insulating substrate 20a. The gate electrode 21a, the source electrode 22a, and the drain electrode 23a may have any shape.

[0043] The gate electrode 21a includes a connection portion 24a that is connected to the lower gate wiring.

[0044] The source electrode 22a includes a connection portion 25a connected to the lower source sense wiring and a connection portion 26a connected to the negative terminal N.

[0045] The drain electrode 23a includes a connection portion 27a that is connected to the output terminal AC.

[0046] In the example shown in FIG. 2, four semiconductor chips 100 are arranged on the drain electrode 23a. Note that there may be one or more semiconductor chips 100 on the drain electrode 23a. The semiconductor chip 100 on the drain electrode 23a corresponds to the transistor Tr20a described with reference to FIG. 1. The drain terminal of the semiconductor chip 100 is electrically connected to the drain electrode 23a. The gate terminal of the semiconductor chip 100 is connected to the gate electrode 21a via one wire WL. The source terminal of the semiconductor chip 100 is connected to the source electrode 22a via three wires WL.

[0047] Next, the configuration on the upper surface of the insulating substrate 20b will be described.

[0048] A gate electrode 21b, a source electrode 22b, and a drain electrode 23b are provided on the upper surface of the insulating substrate 20b. The gate electrode 21b, the source electrode 22b, and the drain electrode 23b are arranged spaced apart from each other on the upper surface of the insulating substrate 20b. The gate electrode 21b, the source electrode 22b, and the drain electrode 23b may have any shape.

[0049] The gate electrode 21b includes a connection portion 24b that is connected to the lower gate wiring.

[0050] The source electrode 22b includes a connection portion 25b connected to the lower source sense wiring and a connection portion 26b connected to the negative terminal N.

[0051] The drain electrode 23b includes a connection portion 27b that is connected to the output terminal AC.

[0052] In the example shown in FIG. 2, four semiconductor chips 100 are arranged on the drain electrode 23b. Note that there may be one or more semiconductor chips 100 on the drain electrode 23b. The semiconductor chip 100 on the drain electrode 23b corresponds to the transistor Tr20b described with reference to FIG. 1. The drain terminal of the semiconductor chip 100 is electrically connected to the drain electrode 23b. The gate terminal of the semiconductor chip 100 is connected to the gate electrode 21b via one wire WL. The source terminal of the semiconductor chip 100 is connected to the source electrode 22b via three wires WL.

[0053] 2.2 Cross-sectional structure of semiconductor device Next, an example of a cross-sectional configuration of the semiconductor device 1 will be described with reference to Fig. 3. Fig. 3 is a cross-sectional view taken along line A1-A2 in Fig. 2.

[0054] 3, a lower electrode 18a is provided on the lower surface of the insulating substrate 10a. The lower electrode 18a can be electrically connected to either the source electrode 12a or the drain electrode 13a. Solder 3 is provided between the upper surface of the base substrate 2 and the lower electrode 18a. In other words, the lower electrode 18a (insulating substrate 10a) is fixed onto the upper surface of the base substrate 2 by the solder 3.

[0055] A gate electrode 11a, a source electrode 12a, and a drain electrode 13a are provided on the upper surface of the insulating substrate 10a. A mounting material 200 is provided between the upper surface of the drain electrode 13a and the semiconductor chip 100. In other words, the semiconductor chip 100 is fixed (bonded) onto the upper surface of the drain electrode 13a by the mounting material 200. The mounting material 200 is made of a conductive material. For example, solder is used for the mounting material 200. Note that a sintered material that is difficult to melt (for example, any of copper, silver, lead, tin-copper compound, tin-silver compound, or tin-nickel compound) may be used instead of solder. In that case, a pressure sintered material with excellent pressure resistance may be used.

[0056] The drain terminal provided on the lower surface of the semiconductor chip 100 is electrically connected to the drain electrode 13a via a mounting material. The gate terminal provided on the upper surface of the semiconductor chip 100 is electrically connected to the gate electrode 11a via a wire WL. In addition, the source terminal provided on the upper surface of the semiconductor chip 100 is electrically connected to the source electrode 12a via a wire WL.

[0057] 2.3 Configuration of gate wiring and source sense wiring Next, an example of the configuration of the gate wiring and the source sense wiring will be described with reference to Fig. 4 to Fig. 6. Fig. 4 is a plan view showing the configuration of the gate wiring and the source sense wiring. Fig. 5 is a cross-sectional view taken along line B1-B2 in Fig. 4. Fig. 6 is a perspective view showing the meandering portion MP of the upper gate wiring 30 and the upper source sense wiring 31. In the example shown in Fig. 4, reference symbols of components not connected to the gate wiring or the source sense wiring are omitted for the sake of simplicity.

[0058] As shown in FIG. 4, the semiconductor device 1 includes an upper gate wiring 30, an upper source sense wiring 31, a lower gate wiring 40, and a lower source sense wiring 41.

[0059] The upper gate wiring 30 is connected to the connection portion 14a of the gate electrode 11a provided on the upper surface of the insulating substrate 10a and the connection portion 14b of the gate electrode 11b provided on the upper surface of the insulating substrate 10b. One end of the upper gate wiring 30 is connected to the upper gate terminal HG. The upper gate wiring 30 has a meandering portion MP provided in a wiring portion connecting the connection portion 14a and the connection portion 14b. That is, the meandering portion MP is provided in a wiring portion connecting the insulating substrates. In other words, the upper gate wiring 30 connects the gate electrode 11a and the gate electrode 11b while meandering in the X direction. The meandering portion MP of the upper gate wiring 30 extends in the Y direction while repeatedly folding back in the X direction. In other words, the meandering portion MP includes a plurality of first portions extending in the X direction and a plurality of second portions extending in the Y direction. The plurality of first portions and the plurality of second portions are alternately connected in series one by one. The folding back direction of the wiring in the meandering portion MP is arbitrary. For example, the upper gate wiring 30 may be folded back in the Y direction or in the Z direction. The number of times the wiring is folded back in the meandering portion MP is arbitrary. Furthermore, the upper gate wiring 30 may have a zigzag shape in the meandering portion MP. The parasitic inductance of the upper gate wiring 30 in the meandering portion MP corresponds to the inductance Lg10 described with reference to FIG. 1.

[0060] The upper source sense wiring 31 is connected to the connection portion 15a of the source electrode 12a provided on the upper surface of the insulating substrate 10a and the connection portion 15b of the source electrode 12b provided on the upper surface of the insulating substrate 10b. One end of the upper source sense wiring 31 is connected to the upper source sense terminal HSS. The upper source sense wiring 31 has a meandering portion MP provided in a wiring portion connecting the connection portion 15a and the connection portion 15b. In other words, the upper source sense wiring 31 connects the source electrode 12a and the source electrode 12b while meandering in the X direction. The wiring shape of the meandering portion MP of the upper source sense wiring 31 is approximately the same as the wiring shape of the meandering portion MP of the upper gate wiring 30. Note that when it is expressed as approximately the same, it may include manufacturing variations of the semiconductor device 1. The parasitic inductance at the meandering portion MP of the upper source sense wiring 31 corresponds to the inductance Lss10 described using FIG. 1.

[0061] As shown in FIG. 5, the upper source sense wiring 31 is disposed above the upper gate wiring 30 in the Z direction. Furthermore, as shown in FIG. 6, the meandering portion MP of the upper source sense wiring 31 is disposed above the meandering portion MP of the upper gate wiring 30. That is, the meandering portion MP of the upper source sense wiring 31 is disposed parallel to the meandering portion MP of the upper gate wiring 30. In other words, the upper gate wiring 30 and the upper source sense wiring 31 meander so as to be parallel to each other in the Z direction. That is, in a top view from the Z direction, the upper gate wiring 30 and the upper source sense wiring 31 meander so as to overlap with each other while being spaced apart. The distance between the upper gate wiring 30 and the upper source sense wiring 31 in the Z direction is defined as H. It is preferable that the distance H is 2 mm or less in order to increase (approach 1) the coupling coefficient k1 between the inductance Lg10 and the inductance Lss10.

[0062] Next, the lower gate wiring 40 and the lower source sense wiring 41 will be described.

[0063] As shown in FIG. 4, the lower gate wiring 40 is connected to the connection portion 24a of the gate electrode 21a provided on the upper surface of the insulating substrate 20a and the connection portion 24b of the gate electrode 21b provided on the upper surface of the insulating substrate 20b. One end of the lower gate wiring 40 is connected to the lower gate terminal LG. The lower gate wiring 40 has a meandering portion MP provided in a wiring portion connecting the connection portion 24a and the connection portion 24b, similar to the upper gate wiring 30. In other words, the lower gate wiring 40 connects the gate electrode 21a and the gate electrode 21b while meandering in the X direction. The meandering portion MP of the lower gate wiring 40 extends in the Y direction while repeatedly folding back in the X direction. The parasitic inductance in the meandering portion MP of the lower gate wiring 40 corresponds to the inductance Lg20 described with reference to FIG. 1.

[0064] The lower source sense wiring 41 is connected to the connection portion 25a of the source electrode 22a provided on the upper surface of the insulating substrate 20a and the connection portion 25b of the source electrode 22b provided on the upper surface of the insulating substrate 20b. One end of the lower source sense wiring 41 is connected to the lower source sense terminal LSS. The lower source sense wiring 41 has a meandering portion MP provided in a wiring portion connecting the connection portion 25a and the connection portion 25b, similar to the upper source sense wiring 31. In other words, the lower source sense wiring 41 connects the source electrode 22a and the source electrode 22b while meandering in the X direction. The wiring shape of the meandering portion MP of the lower source sense wiring 41 is approximately the same as the wiring shape of the meandering portion MP of the lower gate wiring 40. The parasitic inductance in the meandering portion MP of the lower source sense wiring 41 corresponds to the inductance Lss20 described with reference to FIG. 1.

[0065] Similar to the upper arm portion UA, the meandering portion MP of the lower source sense wiring 41 is disposed above the meandering portion MP of the lower gate wiring 40. In other words, the lower gate wiring 40 and the lower source sense wiring 41 meander so as to be parallel in the Z direction. That is, in a top view from the Z direction, the lower gate wiring 40 and the lower source sense wiring 41 meander so as to overlap while being spaced apart. As with the upper gate wiring 30 and the upper source sense wiring 31, the distance H between the lower gate wiring 40 and the lower source sense wiring 41 in the Z direction is preferably set to 2 mm or less in order to increase (approach 1) the coupling coefficient k2 between the inductance Lg20 and the inductance Lss20.

[0066] 3. Effect of meandering section on semiconductor device characteristics Next, the influence of the meandering portion MP of the gate wiring and the source sense wiring on the characteristics of the semiconductor device 1 will be described with reference to Figures 7 and 8. Figures 7 and 8 are circuit diagrams showing an example of the circuit configuration of the upper arm portion UA ​​of the semiconductor device 1. In the example shown in Figures 7 and 8, the circuit diagram of the lower arm portion LA is omitted for the sake of simplicity of explanation. Note that the semiconductor device 1 is also affected by the circuit of the lower arm portion LA in the same way as the circuit of the upper arm portion UA.

[0067] First, the influence of the meandering portion MP of the upper gate wiring 30 and the upper source sense wiring 31 on the oscillation of the semiconductor device 1 (upper arm portion UA) will be described.

[0068] 7, the inductance Lg10 becomes impedance for the oscillation loop indicated by the thick solid line. Since the inductance Lg10 increases due to the meandering portion MP of the upper gate wiring 30, oscillation is suppressed. At this time, the inductance Lss10 also increases due to the meandering portion MP of the upper source sense wiring 31. However, since no oscillation current flows through the inductance Lss10, no mutual inductance is generated.

[0069] Next, the effect on the switching speed of the semiconductor device 1 will be described.

[0070] As shown in FIG. 8, the inductance Lg10 and the inductance Lss10 are in opposite phase with respect to the gate signal loop indicated by the thick solid line. Therefore, the inductance Lg10 is cancelled out by the mutual inductance between the inductances Lg10 and Lss10. In this embodiment, the meandering portion MP of the upper source sense wiring 31 is arranged in parallel with the meandering portion MP of the upper gate wiring 30, so that the coupling coefficient k1 increases. That is, the mutual inductance increases, and the cancellation amount of the inductance Lg10 increases. Therefore, the delay in the switching speed of the semiconductor device 1 due to the increase in the inductance Lg10 is suppressed.

[0071] With the configuration according to this embodiment, it is possible to provide a semiconductor device 1 capable of suppressing oscillation within the device.

[0072] For example, in a module equipped with multiple insulating substrates, the length of the source wiring connecting the insulating substrates (between transistors connected in parallel) tends to be long. This increases the source inductance between the insulating substrates, making oscillation more likely to occur during switching. Increasing the gate inductance between the insulating substrates is an effective countermeasure against oscillation. However, when the gate inductance increases, the performance of the semiconductor device decreases due to substrate variations in transistor switching and reduced switching speed.

[0073] In contrast, with the configuration according to this embodiment, the semiconductor device 1 can be provided with a meandering portion MP at the portion connecting the insulating substrates of the gate wiring and the source sense wiring. This increases the gate inductance between the insulating substrates, thereby suppressing oscillation.

[0074] Furthermore, with the configuration according to this embodiment, the semiconductor device 1 can arrange the meandering portion MP of the source sense wiring and the meandering portion MP of the gate wiring in parallel between the insulating substrates. This can increase the mutual inductance between the gate inductance and the source inductance. In the gate signal loop, the source inductance and the gate inductance can be in opposite phase. This can cancel out the gate inductance by the mutual inductance in the gate signal loop. Therefore, it is possible to suppress a decrease in switching speed due to an increase in gate inductance.

[0075] 4. Modifications, etc. The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0076] Furthermore, in the above embodiments, "connection" also includes a state in which something else, such as a transistor or a resistor, is interposed between them and indirectly connected.

[0077] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0078] 1...Semiconductor device 2...Base board 3…Solder 10, 10a, 10b, 20, 20a, 20b...insulating substrate 11a, 11b, 21a, 21b...gate electrodes 12a, 12b, 22a, 22b...Source electrodes 13a, 13b, 23a, 23b...Drain electrodes 14a, 14b, 24a, 24b, 15a, 15b, 25a, 25b, 16a, 16b, 26a, 26b, 17a, 17b, 27a, 27b... Connections 18a...Bottom electrode 30…Upper gate wiring 31…Upper source sense wiring 40…Lower gate wiring 41…Lower source sense wiring 100…Semiconductor chips 200…Mounting material HG…Upper gate terminal HSS: Upper source sense terminal LA: Lower arm part LG…Lower gate terminal Lg10, Lg20, Lss10, Lss20...Inductance LSS: Lower source sense terminal MP: meandering section Tr10a, Tr10b, Tr20a, Tr20b...Transistors UA: Upper arm part WL…Wire

Claims

1. a first substrate on which a first electrode, a second electrode, and a third electrode are provided spaced apart from one another; a second substrate, which is arranged next to the first substrate in a first direction and in which a fourth electrode, a fifth electrode, and a sixth electrode are provided spaced apart from each other; a first transistor provided on an upper surface of the first electrode, the first transistor having a drain connected to the first electrode, a gate connected to the second electrode, and a source connected to the third electrode; a second transistor provided on an upper surface of the fourth electrode, the second transistor having a drain connected to the fourth electrode, a gate connected to the fifth electrode, and a source connected to the sixth electrode; a first wiring that connects the second electrode and the fifth electrode while meandering in a second direction that intersects with the first direction; a second wiring that connects the third electrode and the sixth electrode in a meandering manner in the second direction; Equipped with Semiconductor device.

2. the first wiring and the second wiring meander in a third direction intersecting the first direction so as to be parallel to each other; The semiconductor device according to claim 1 .

3. The distance between the first wiring and the second wiring is 2 mm or less. The semiconductor device according to claim 1 .

4. the first wiring includes a plurality of first portions extending in the first direction and a plurality of second portions extending in the second direction; The plurality of first portions and the plurality of second portions are alternately connected in series, The semiconductor device according to claim 1 .

5. a third substrate on which a seventh electrode, an eighth electrode, and a ninth electrode are provided so as to be spaced apart from one another; a fourth substrate, on which a tenth electrode, an eleventh electrode, and a twelfth electrode are provided spaced apart from one another, and which is arranged next to the third substrate in the first direction; a third transistor provided on an upper surface of the seventh electrode, the third transistor having a drain connected to the seventh electrode, a gate connected to the eighth electrode, and a source connected to the ninth electrode; a fourth transistor provided on an upper surface of the tenth electrode, the fourth transistor having a drain connected to the tenth electrode, a gate connected to the eleventh electrode, and a source connected to the twelfth electrode; a third wiring that connects the eighth electrode and the eleventh electrode in a meandering manner in the second direction; a fourth wiring that connects the ninth electrode and the twelfth electrode in a meandering manner in the second direction; Further comprising: The semiconductor device according to claim 1 .

6. the third transistor and the fourth transistor are connected in series with the first transistor and the second transistor; The semiconductor device according to claim 5 .

7. the third wiring and the fourth wiring meander in a third direction intersecting the first direction so as to be parallel to each other; The semiconductor device according to claim 5 .

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