Semiconductor device

Abstract

To provide a semiconductor device with improved reliability.SOLUTION: A semiconductor device includes at least one or more first transistors and at least one or more second transistors each having a first end connected to a first node and a second end connected to a second node, at least one or more third transistors and at least one or more fourth transistors each having a first end connected to the second node and a second end connected to a third node, a fifth transistor provided between a gate end of the at least one or more first transistors and the second node, a sixth transistor provided between a gate end of the at least one or more second transistors and the second node, a seventh transistor provided between a gate end of the at least one or more third transistors and the third node, and an eighth transistor provided between a gate end of the at least one or more fourth transistors and the third node.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] A power module is known as a semiconductor device that realizes high output. A power module is configured as a single package in which multiple power semiconductor elements are mounted. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 7157046 Summary of the Invention [Problem to be solved by the invention]

[0004] The reliability of the semiconductor device is improved. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes at least one or more first transistors and at least one or more second transistors, each having a first end connected to a first node and a second end connected to a second node, at least one or more third transistors and at least one or more fourth transistors, each having a first end connected to the second node and a second end connected to a third node, a fifth transistor provided corresponding to the at least one or more first transistors and having a first end connected to a gate terminal of the at least one or more first transistors and a second end connected to the second node, a sixth transistor provided corresponding to the at least one second transistor and having a first terminal connected to a gate terminal of the at least one second transistor and a second terminal connected to the second node; a seventh transistor provided corresponding to the at least one third transistor and having a first terminal connected to a gate terminal of the at least one third transistor and a second terminal connected to the third node; and an eighth transistor provided corresponding to the at least one fourth transistor and having a first terminal connected to a gate terminal of the at least one fourth transistor and a second terminal connected to the third node. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a circuit diagram showing an example of a circuit configuration of a semiconductor device according to an embodiment. [Diagram 2] 1 is a plan view showing a configuration of a semiconductor device according to an embodiment; [Diagram 3] 3 is a cross-sectional view taken along line III-III in FIG. 2, showing an example of a cross-sectional structure of the semiconductor device according to the embodiment. [Figure 4] FIG. 11 is a plan view showing a configuration of a semiconductor device according to a first modified example. [Diagram 5] FIG. 11 is a plan view showing a configuration of a semiconductor device according to a second modification. [Figure 6] FIG. 13 is a plan view showing a configuration of a semiconductor device according to a third modification. [Figure 7]7 is a cross-sectional view taken along line VII-VII in FIG. 6, showing an example of a cross-sectional structure of a semiconductor device according to a third modified example. [Figure 8] FIG. 13 is a plan view showing a configuration of a semiconductor device according to a fourth modification. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. The dimensions and ratios of the drawings are not necessarily the same as those in reality. In the following description, components having substantially the same functions and configurations are given the same reference numerals. When elements having similar configurations are to be particularly distinguished from each other, different letters or numbers may be added to the end of the same reference numerals.

[0008] 1. Embodiment A semiconductor device according to an embodiment will be described.

[0009] The semiconductor device according to the embodiment is a power module, and is applied to, for example, a power conversion device for a railway vehicle, or an industrial device for a renewable energy power generation system.

[0010] The configuration of the semiconductor device according to the embodiment will be described.

[0011] The circuit configuration of the semiconductor device according to the embodiment will be described with reference to Fig. 1. Fig. 1 is a circuit diagram showing an example of the circuit configuration of the semiconductor device according to the embodiment. In the example of Fig. 1, a semiconductor device 1 includes a plurality of transistors TU, TL, TCU, and TCL as internal semiconductor elements. In the following description, when the plurality of transistors TU, TL, TCU, and TCL are not to be distinguished from one another, each of the plurality of transistors TU, TL, TCU, and TCL is also simply referred to as a transistor T.

[0012] The transistors T are MOS (Metal-Oxide-Semiconductor) transistors. The transistors T are n-type transistors. Each transistor T is, for example, a transistor selected from a MOS transistor using silicon carbide (SiC), a MOS transistor using silicon (Si), and a transistor using gallium nitride (GaN). Each transistor T may be, for example, an IGBT (Insulated-Gate Bipolar Transistor). The drain-source breakdown voltage of each of the transistors TCU and TCL is, for example, higher than the gate-source breakdown voltage of each of the transistors TU and TL. The drain-source breakdown voltage of each of the transistors TCU and TCL is, for example, about 30V. In the embodiment, the number of the transistors TU, the number of the transistors TL, the number of the transistors TCU, and the number of the transistors TCL are each two or more. In FIG. 1, the circuit configuration is simplified, and only one of each of the transistors TU, TL, TCU, and TCL is shown.

[0013] A plurality of transistors TU are connected in parallel between a node P and a node AC (Alternating Current). The node P is an input terminal of the semiconductor device 1. In the circuit configuration of the semiconductor device 1, the node P has, for example, a positive polarity. The node AC is an output terminal of the semiconductor device 1. The node AC is connected to a monitor terminal, as described later. Each transistor TU has a drain terminal connected to the node P, a source terminal connected to the node AC, and a gate terminal connected to a node GU. The node GU is a control terminal. In the following description, each transistor TU is also referred to as an upper semiconductor element.

[0014] Each of the multiple transistors TCU is connected between the gate terminals of the multiple transistors TU and the source terminals of the multiple transistors TU. More specifically, each transistor TCU has a drain terminal connected to the gate terminals (node ​​GU) of the multiple transistors TU, a source terminal connected to the source terminals (node ​​AC) of the multiple transistors TU, and a gate terminal connected to a node GCU. The node GCU is a control terminal. In the following description, each transistor TCU is also referred to as an upper clamp element.

[0015] The multiple transistors TL are connected in parallel between a node AC and a node N. The node N is an input terminal of the semiconductor device 1. In the circuit configuration of the semiconductor device 1, the node N has, for example, negative polarity. As will be described later, the node N is connected to a monitor terminal different from the monitor terminal connected to the node AC. Each transistor TL has a drain terminal connected to the node AC, a source terminal connected to the node N, and a gate terminal connected to a node GL. The node GL is a control terminal. In the following description, each transistor TL is also referred to as a lower semiconductor element.

[0016] Each of the transistors TCL is connected between the gate terminals of the transistors TL and the source terminals of the transistors TL. More specifically, each transistor TCL has a drain terminal connected to the gate terminals (node ​​GL) of the transistors TL, a source terminal connected to the source terminals (node ​​N) of the transistors TL, and a gate terminal connected to a node GCL. The node GCL is a control terminal. In the following description, each transistor TCL is also referred to as a lower clamp element.

[0017] With the above-described configuration, the semiconductor elements inside the semiconductor device 1 can be controlled by a voltage supplied from outside the semiconductor device 1. For example, different signals are input from the outside to the nodes GU, GL, GCU, and GCL, respectively.

[0018] More specifically, when transistor TU is turned on and transistor TL is turned off, for example, an "H (High)" level signal is supplied to nodes GU and GCL, and an "L (Low)" level signal is supplied to nodes GL and GCU. Also, when transistor TU is turned off and transistor TL is turned on, for example, an "L" level signal is supplied to nodes GU and GCL, and an "H" level signal is supplied to nodes GL and GCU.

[0019] Next, the structure of the semiconductor device 1 according to the embodiment will be described.

[0020] First, the planar structure of the semiconductor device 1 according to the embodiment will be described with reference to Fig. 2. Fig. 2 is a plan view showing the configuration of the semiconductor device according to the embodiment.

[0021] The semiconductor device 1 further includes an insulating member 10, and conductors 21, 22, 23, 24, 25, 26, 27, 28a, 28b, 31, 32, 33, 34, 35, and 36. The semiconductor device 1 further includes a base substrate not shown in FIG.

[0022] The insulating member 10 is provided on a base substrate. The base substrate is a support having a flat portion. The base substrate includes, for example, copper or ceramics. The insulating member 10 includes, for example, resin or ceramics. The resin is, for example, polyphenylene sulfide (PPS). In the following, the structure of the semiconductor device 1 will be described using an X direction in a plane parallel to the base substrate and the upper surface of the insulating member 10, a Y direction perpendicular to the X direction in the plane, and a Z direction perpendicular to the plane.

[0023] The conductors 21, 22, 23, 24, and 25 are provided on the insulating member 10. The conductors 21, 22, 23, 24, and 25 are provided apart from each other. Each of the conductors 21, 22, 23, 24, and 25 has a portion extending along the X direction, for example. The portion of the conductor 22 extending along the X direction, the portion of the conductor 21 extending along the X direction, the portion of the conductor 23 extending along the X direction, the portion of the conductor 24 extending along the X direction, and the portion of the conductor 25 extending along the X direction are arranged along the Y direction, for example, in this order. In the following description, the side where the portion of the conductor 22 extending in the X direction is arranged among the portions of the conductors 22 and 25 extending in the X direction is referred to as one end side in the Y direction. Moreover, among the portions of the conductors 22 and 25 extending in the X direction, the side on which the portion of the conductor 25 extending in the X direction is located is referred to as the other end side in the Y direction. The conductors 21, 23, and 24 each further have a portion extending in the Y direction. The portion of the conductor 23 extending in the Y direction and the portions of the conductors 21 and 24 extending in the Y direction are located at different ends along the X direction. In the following description, among the portions of the conductors 21, 23, and 24 extending in the Y direction, the side on which the portion of the conductor 23 extending in the Y direction is located is referred to as one end side in the X direction. Moreover, among the portions of the conductors 21, 23, and 24 extending in the Y direction, the side on which the portions of the conductors 21 and 24 extending in the Y direction are located is referred to as the other end side in the X direction.

[0024] A plurality of transistors TU are arranged in the X direction on the upper surface of the portion of the conductor 21 extending along the X direction. The plurality of transistors TU are arranged, for example, at substantially equal intervals in the X direction. FIG. 2 shows an example in which nine transistors TU are arranged. Hereinafter, three transistors TU on one end side of the nine transistors TU are also referred to as transistors TU1. Also, three transistors TU on one end side of the six transistors TU other than the three transistors TU1 are also referred to as transistors TU2. Also, three transistors TU on the other end side of the nine transistors TU are also referred to as transistors TU3. The drain end of each transistor TU is provided on the lower surface of the transistor TU. The source end and gate end of each transistor TU are provided on the upper surface of the transistor TU. The drain end of each transistor TU is electrically connected to the conductor 21. The source end of each transistor TU is electrically connected to the conductor 23 via a wire. The gate end of each transistor TU is electrically connected to the conductor 22 via a wire.

[0025] 2 and the following description, the semiconductor device 1 includes three transistors TU1, three transistors TU2, and three transistors TU3, but is not limited to this. The number of transistors TU1, the number of transistors TU2, and the number of transistors TU3 may be one, two, or four or more.

[0026] A plurality of transistors TCU are arranged in the X direction on the upper surface of the portion of the conductor 22 extending along the X direction. The plurality of transistors TCU are arranged, for example, at substantially equal intervals in the X direction. FIG. 2 shows an example in which three transistors TCU are arranged. Hereinafter, the three transistors TCU are also referred to as transistors TCU1, TCU2, and TCU3 from one end side to the other end side in the X direction. The transistors TCU1, TCU2, and TCU3 correspond to the transistors TU1, TU2, and TU3, respectively. The drain end of each transistor TCU is provided on the lower surface of the transistor TCU. The source end and the gate end of each transistor TCU are provided on the upper surface of the transistor TCU. The drain end of each transistor TCU is electrically connected to the conductor 22. The gate end of each transistor TCU is connected to the node GCU. The source end of the transistor TCU1 is electrically connected to the source end of each transistor TU1 via a wire. The source terminal of the transistor TCU2 is electrically connected to the source terminal of each of the transistors TU2 via a wire, and the source terminal of the transistor TCU3 is electrically connected to the source terminal of each of the transistors TU3 via a wire.

[0027] The multiple transistors TCU are arranged so as to reduce variation in the length of the wires electrically connecting the source terminal of each transistor TCU to the source terminal of the transistor TU corresponding to that transistor TCU. For example, the multiple transistors TCU are arranged so that the average value of the length along the extension direction of the wires connecting the source terminal of each transistor TCU to the source terminals of the multiple transistors TU corresponding to that transistor TCU is approximately equal.

[0028] 2 and the following description, the semiconductor device 1 includes three transistors TCU, but is not limited to this. The number of transistors TCU may be two, or four or more. Each transistor TCU is only required to be electrically connected to the source terminal of at least one transistor TU among the multiple transistors TU.

[0029] A plurality of transistors TL are arranged in the X direction on the upper surface of the portion of the conductor 23 extending along the X direction. The plurality of transistors TL are arranged, for example, at substantially equal intervals in the X direction. FIG. 2 shows an example in which nine transistors TL are arranged. Hereinafter, three transistors TL on one end side of the nine transistors TL in the X direction are also referred to as transistors TL1. Also, three transistors TL on one end side of the six transistors TL excluding the three transistors TL1 are also referred to as transistors TL2. Also, three transistors TL on the other end side of the nine transistors TL in the X direction are also referred to as transistors TL3. The drain end of each transistor TL is provided on the lower surface of the transistor TL. The source end and gate end of each transistor TL are provided on the upper surface of the transistor TL. The drain end of each transistor TL is electrically connected to the conductor 23. The source end of each transistor TL is electrically connected to the conductor 24 via a wire. The gate end of each transistor TL is electrically connected to the conductor 25 via a wire.

[0030] 2 and the following description, the semiconductor device 1 includes three transistors TL1, three transistors TL2, and three transistors TL3, but is not limited to this. The number of transistors TL1, the number of transistors TL2, and the number of transistors TL3 may be one, two, or four or more.

[0031] A plurality of transistors TCL are arranged in the X direction on the upper surface of the portion of the conductor 25 extending along the X direction. The plurality of transistors TCL are arranged, for example, at substantially equal intervals in the X direction. FIG. 2 shows an example in which three transistors TCL are arranged. Hereinafter, the three transistors TCL are also referred to as transistors TCL1, TCL2, and TCL3 from one end side to the other end side in the X direction. The transistors TCL1, TCL2, and TCL3 correspond to the transistors TL1, TL2, and TL3, respectively. The drain end of each transistor TCL is provided on the lower surface of the transistor TCL. The source end and the gate end of each transistor TCL are provided on the upper surface of the transistor TCL. The drain end of each transistor TCL is electrically connected to the conductor 25. The gate end of each transistor TCL is connected to the node GCL. The source end of the transistor TCL1 is electrically connected to the source end of each transistor TL1 via a wire. The source terminal of the transistor TCL2 is electrically connected to the source terminal of each of the transistors TL2 through a wire, and the source terminal of the transistor TCL3 is electrically connected to the source terminal of each of the transistors TL3 through a wire.

[0032] The transistors TCL are arranged so that the wires electrically connecting the source terminal of each transistor TCL to the source terminal of the transistor TL corresponding to the transistor TCL have a small variation in length. The transistors TCL are arranged so that the average lengths of the wires connecting the source terminal of each transistor TCL to the source terminals of the transistors TL corresponding to the transistor TCL along the extending direction are approximately equal to each other.

[0033] 2 and the following description, the semiconductor device 1 includes three transistors TCL, but is not limited thereto. The number of transistors TCL may be two, or four or more. Each transistor TCL is only required to be electrically connected to the source terminal of at least one transistor TL among the multiple transistors TL.

[0034] In the embodiment, the transistors TU and TL are arranged such that the configuration of each transistor TU is similar to the configuration of each transistor TL when viewed from above. More specifically, the gate terminal of each transistor TU is arranged, for example, closer to one end in the Y direction than the source terminal of the transistor TU. Also, the gate terminal of each transistor TL is arranged, for example, closer to one end in the Y direction than the source terminal of the transistor TL.

[0035] The other end of conductor 26 along the X direction is electrically connected to a portion of conductor 21 extending in the Y direction. Conductor 26 functions as node P. In other words, conductor 26 is a positive polarity input terminal.

[0036] The other end of the conductor 27 along the X direction is electrically connected to a portion of the conductor 24 extending in the Y direction. The conductor 27 functions as a node N. In other words, the conductor 27 is a negative polarity input terminal.

[0037] The conductors 28a and 28b are electrically connected at one end in the X direction to a portion of the conductor 23 extending in the Y direction. The conductors 28a and 28b function as a node AC. In other words, the conductors 28a and 28b are output terminals.

[0038] The conductors 31, 32, 33, 34, 35, and 36 are provided on the insulating member 10, similarly to the conductors 21, 22, 23, 24, and 25. The conductor 31 is electrically connected to the conductor 22 via a wire. The conductor 31 functions as a node GU. That is, the conductor 31 corresponds to the control terminals of the plurality of transistors TU. The conductor 32 is electrically connected to the conductor 23 via a wire. The conductor 32 functions as a monitor terminal SSH connected to the node AC. The conductor 33 is electrically connected to the conductor 25 via a wire. The conductor 33 functions as a node GL. That is, the conductor 33 corresponds to the control terminals of the plurality of transistors TL. The conductor 34 is electrically connected to the conductor 24 via a wire. The conductor 34 functions as a monitor terminal SSL connected to the node N. The conductor 35 is electrically connected to the gate terminals of the plurality of transistors TCU, respectively, via a wire. The conductor 36 is electrically connected to the gate terminals of the plurality of transistors TCL, respectively, via wires.

[0039] Next, a cross-sectional structure of the semiconductor device 1 according to the embodiment will be described with reference to Fig. 3. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 2, showing an example of the cross-sectional structure of the semiconductor device according to the embodiment.

[0040] The semiconductor device 1 further includes, for example, a heat dissipation member HS.

[0041] The heat dissipation member HS is a heat sink. The heat dissipation member HS is provided, for example, on the entire lower surface of the base substrate B used as the support body described above. The heat dissipation member HS has a relatively large surface area due to the unevenness of the lower surface. The heat dissipation member HS includes, for example, copper or ceramics. The heat dissipation member HS may be formed integrally with the base substrate B.

[0042] Each transistor TU is provided on the upper surface of the conductor 21 via an adhesive member 41. The adhesive member 41 physically and electrically connects the drain end of each transistor TU to the conductor 21.

[0043] Each transistor TCU is provided on the upper surface of the conductor 22 via an adhesive member 43. The adhesive member 43 physically and electrically connects the drain terminal of each transistor TCU to the conductor 22.

[0044] Each transistor TL is provided on the upper surface of the conductor 23 via an adhesive member 42. The adhesive member 42 physically and electrically connects the drain end of each transistor TL to the conductor 23.

[0045] Each transistor TCL is provided on the upper surface of the conductor 25 via an adhesive member 44. The adhesive member 44 physically and electrically connects the drain terminal of each transistor TCL and the conductor 25.

[0046] According to the embodiment, it is possible to improve the reliability of the semiconductor device 1. Hereinafter, the improvement in reliability of the semiconductor device 1 according to the embodiment will be described.

[0047] In the semiconductor device 1 according to the embodiment, the source terminal of the transistor TCU1 is electrically connected to the source terminal of one or more transistors TU1. The source terminal of the transistor TCU2 is electrically connected to the source terminal of one or more transistors TU2. The source terminal of the transistor TCL1 is electrically connected to the source terminal of one or more transistors TL1. The source terminal of the transistor TCL2 is electrically connected to the source terminal of one or more transistors TL2. With this configuration, it is possible to suppress an increase in impedance of the wiring between the gate terminal and the source terminal of the upper semiconductor element via the upper clamp element and the wiring between the gate terminal and the source terminal of the lower semiconductor element via the lower clamp element, compared to a case in which the semiconductor device includes only one upper clamp element and one lower clamp element. This can improve the effect of suppressing malfunction.

[0048] Supplementally, in a semiconductor device including an upper semiconductor element and a lower semiconductor element, when one of the two types of semiconductor elements is turned on, a transient gate current flows through the other semiconductor element, and the voltage at the gate end of the other semiconductor element may rise. As a result, when controlling only one semiconductor element to be turned on, the other semiconductor element may also be turned on. In such a case, in order to suppress the rise in the voltage at the gate end, for example, one upper clamp element and one lower clamp element are provided in each of the upper semiconductor element and the lower semiconductor element. The source end of one upper clamp element is electrically connected to each of the source ends of all the upper semiconductor elements. In addition, the source end of one lower clamp element is electrically connected to each of the source ends of all the lower semiconductor elements. In such a case (in the case of the comparative example), for example, as the number of semiconductor elements increases, the length of the wiring between the upper clamp element and the upper semiconductor element, and the length of the wiring between the lower clamp element and the lower semiconductor element may become longer. This causes a problem of increasing impedance in the wiring between the gate terminal and the source terminal of the upper semiconductor element and the wiring between the gate terminal and the source terminal of the lower semiconductor element, which causes a problem of reducing the effect of the clamp element in suppressing the voltage rise at the gate terminal.

[0049] According to the embodiment, the semiconductor device 1 includes a plurality of transistors TCU and a plurality of transistors TCL. This makes it possible to suppress an increase in the length of the wiring between the upper clamp element and the upper semiconductor element, and the length of the wiring between the lower clamp element and the lower semiconductor element. That is, by distributing the plurality of transistors TCU and the plurality of transistors TCL, respectively, it is possible to suppress an increase in the length of the wiring in each of the transistors TCU and TCL. Therefore, it is possible to suppress an increase in impedance of the wiring between the gate terminal and the source terminal of the upper semiconductor element and the wiring between the gate terminal and the source terminal of the lower semiconductor element through the clamp element.

[0050] Moreover, according to the embodiment, the increase in size of the semiconductor device 1 can be suppressed compared to the comparative example. Supplementally, according to the embodiment, the number of upper clamp elements relative to the number of upper semiconductor elements and the number of lower clamp elements relative to the number of lower semiconductor elements can be increased compared to the comparative example. This makes it possible to suppress an increase in the on-resistance of each of the upper clamp elements and the lower clamp elements. Therefore, compared to the comparative example, the increase in size of each of the upper clamp elements and the lower clamp elements can be suppressed. Therefore, the increase in size of the semiconductor device 1 is suppressed.

[0051] 2. Variations Next, a semiconductor device according to a modification will be described below. In the following, the description of the same configuration as the embodiment will be omitted, and the configuration different from the embodiment will be mainly described.

[0052] 2.1 First modified example In the embodiment, the multiple transistors TU and TL are arranged such that the configuration of each transistor TU and the configuration of each transistor TL are similar when viewed from above, but this is not limited to the above. The multiple transistors TU and TL may be arranged such that the configuration of each transistor TU and the configuration of each transistor TL are symmetrical in the Y direction.

[0053] The configuration of the semiconductor device 1 according to the first modification will be described with reference to Fig. 4. Fig. 4 is a plan view showing the configuration of the semiconductor device according to the first modification. Note that the configurations of the multiple transistors TU, TL, TCU, and TCL, the insulating member 10, and the conductors 21, 22, 23, 24, 25, 26, 27, 28a, 28b, 31, 32, 33, 34, 35, and 36 according to the first modification are similar to those of the embodiment, except for the configuration of each transistor TL.

[0054] 4, in the first modification, the gate end of each transistor TL is disposed, for example, on the other end side in the Y direction than the source end of the transistor TL. As a result, the source end and gate end of each transistor TU and the source end and gate end of each transistor TL are disposed symmetrically in the Y direction.

[0055] The first modified example also provides the same effects as the embodiment.

[0056] 2.2 Second variant In the embodiment and the first modified example, the source terminal of the transistor TCL is directly connected to the source terminal of the transistor TL, but this is not limiting. The source terminal of the transistor TCL and the source terminal of the transistor TL may be indirectly connected via a conductor.

[0057] The configuration of the semiconductor device 1 according to the second modification will be described with reference to Fig. 5. Fig. 5 is a plan view showing the configuration of the semiconductor device according to the second modification. Note that the configurations of the transistors TU, TL, TCU, and TCL, the insulating member 10, and the conductors 21, 22, 23, 24, 25, 26, 27, 28a, 28b, 31, 32, 33, 34, 35, and 36 according to the second modification are the same as those according to the embodiment, except for the connection between the source end of the transistor TCL and the source end of the transistor TL.

[0058] 5, in the second modification, the source terminal of each transistor TCL is connected by a wire to the conductor 24. As a result, the source terminal of the transistor TCL is indirectly connected to the source terminal of the transistor TL via the wire and the conductor 24.

[0059] The lengths or average values ​​of the wires connecting each of the multiple transistors TCL to the conductor 24 are approximately equal.

[0060] The second modified example also provides the same effects as those of the embodiment and the first modified example.

[0061] 2.3 Third variant In the embodiment, the first modification, and the second modification, the case where the plurality of transistors TCU and TCL are vertical transistors has been shown, but this is not limited thereto. The semiconductor device may have the plurality of transistors TCU and TCL each being a horizontal transistor. In the following, the configuration of the semiconductor device according to the third modification will be mainly described with respect to the configuration different from the semiconductor device according to the embodiment, the first modification, and the second modification.

[0062] The configuration of the semiconductor device 1 according to the third modification will be described with reference to Fig. 6 and Fig. 7. Fig. 6 is a plan view showing the configuration of the semiconductor device according to the third modification. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 6, showing an example of the cross-sectional structure of the semiconductor device according to the third modification.

[0063] The configurations of the transistors TU and TL, the insulating member 10, and the conductors 21, 22, 23, 24, 25, 26, 27, 28a, 28b, 31, 32, 33, 34, 35, and 36 in the third modified example are similar to those in the embodiment. In the following, the configurations of the transistors TCU and TCL will be mainly described.

[0064] The transistors TCU and TCL in the third modification are horizontal transistors. That is, the source terminal, drain terminal, and gate terminal of each of the transistors TCU and TCL are provided on the upper surface of the transistor. The drain terminal of each transistor TCU is connected to the conductor 22 by, for example, a wire. The drain terminal of each transistor TCL is connected to the conductor 25 by, for example, a wire.

[0065] 7, each transistor TCU is provided on the upper surface of the conductor 22 via an adhesive member 51. The adhesive member 51 is an insulator that physically connects the lower surface of each transistor TCU and the conductor 22.

[0066] Each transistor TCU is provided on the upper surface of the conductor 25 via an adhesive member 52. The adhesive member 52 is an insulator that physically and electrically connects the drain end of each transistor TCU and the conductor 25.

[0067] The third modified example also provides the same effects as those of the embodiment, the first modified example, and the second modified example.

[0068] 2.4 Fourth variant In the third modification, the transistors TCU and TCL are mounted on a conductor via an insulator, but the present invention is not limited to this. Instead of the insulator, the transistors TCU and TCL may be mounted via an adhesive material similar to that of the transistors TU and TL.

[0069] The configurations of the multiple transistors TU, TL, TCU, and TCL, the insulating member 10, and the conductors 21, 22, 23, 24, 25, 26, 27, 28a, 28b, 31, 32, 33, 34, 35, and 36 according to the fourth modification are similar to those according to the third modification, except for the arrangement of the multiple TCUs and TCLs. In the following, the arrangement of the multiple TCUs and TCLs will be mainly described.

[0070] In the fourth modified example, the plurality of transistors TCU are provided on the upper surface of the conductor 23. The plurality of transistors TCL are provided on the upper surface of the conductor 24. Although not shown, the plurality of transistors TCU and TCL are mounted on the upper surfaces of the conductors 23 and 24 via adhesive members similar to the adhesive members 41 to 44 in the embodiment. The lower surface of each of the plurality of transistors TCU is at the same potential as the source terminal of the transistor TU or is an insulator. The lower surface of each of the plurality of transistors TCL is at the same potential as the source terminal of the transistor TL or is an insulator.

[0071] The fourth modified example also provides the same effects as those of the embodiment, the first modified example, the second modified example, and the third modified example.

[0072] Moreover, according to the fourth modification, the transistors TCU are mounted on the upper surface of the conductor 23 connected to the node AC and the source terminals of the transistors TU, and the transistors TCL are mounted on the upper surface of the conductor 24 connected to the node N and the source terminals of the transistors TL, so that the transistors can be mounted on the upper surfaces of the conductors without using an insulator as an adhesive member, thereby preventing the manufacturing process from becoming complicated.

[0073] 3. Other In the above-mentioned embodiment, first modification, second modification, third modification, and fourth modification, the number of wires connecting one configuration to another configuration may be one or more, and the number of wires is not limited. In addition, the wires included in the configuration of the semiconductor device 1 according to the embodiment, first modification, second modification, third modification, and fourth modification may be replaced with other conductors. For example, the wires in the embodiment, first modification, second modification, third modification, and fourth modification may be replaced with conductors such as ribbons and lead frames.

[0074] In addition, in the second, third, and fourth modified examples, as in the embodiment, an example in which the configuration of each transistor TU and the configuration of each transistor TL are similar when viewed from above have been shown, but this is not limited to this. Although not shown, in the second, third, and fourth modified examples, as in the first modified example, the source end and gate end of each transistor TU and the source end and gate end of each transistor TL may be arranged symmetrically in the Y direction.

[0075] In addition, in the first, third, and fourth modified examples, as in the embodiment, an example has been shown in which the source terminal of each transistor TCL is directly connected to the source terminal of the transistor TL via a wire, but this is not limited to this. Although not shown, in the first, third, and fourth modified examples, the source terminal of each transistor TCL may be indirectly connected via the conductor 24, as in the second modified example. That is, the source terminal of each transistor TCL may be connected to the conductor 24 by a wire, and thereby connected to the source terminal of the transistor TL.

[0076] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0077] 1...semiconductor device, 10...insulating member, 21, 22, 23, 24, 25, 26, 27, 28a, 28b, 31, 32, 33, 34, 35, 36...conductor, 41, 42, 43, 44, 51, 52...adhesive member, TU, TL, TCU, TCL...transistor, B...base substrate, HS...heat dissipation member.

Claims

1. at least one or more first transistors and at least one or more second transistors, each having a first end connected to a first node and a second end connected to a second node; at least one or more third transistors and at least one or more fourth transistors, each having a first end connected to the second node and a second end connected to a third node; a fifth transistor provided corresponding to the at least one first transistor, the fifth transistor having a first terminal connected to a gate terminal of the at least one first transistor and a second terminal connected to the second node; a sixth transistor provided corresponding to the at least one second transistor, the sixth transistor having a first terminal connected to a gate terminal of the at least one second transistor and a second terminal connected to the second node; a seventh transistor provided corresponding to the at least one third transistor, the seventh transistor having a first terminal connected to a gate terminal of the at least one third transistor and a second terminal connected to the third node; an eighth transistor provided corresponding to the at least one fourth transistor, the eighth transistor having a first terminal connected to a gate terminal of the at least one fourth transistor and a second terminal connected to the third node; A semiconductor device comprising:

2. The semiconductor device includes: the at least one or more first transistors and the at least one or more second transistors are each a plurality of transistors; The semiconductor device according to claim 1.

3. a second terminal of the fifth transistor is electrically connected to the second terminal of each of the at least one or more first transistors via a plurality of first conductors; a second terminal of the sixth transistor is electrically connected to the second terminal of each of the at least one second transistors via a plurality of second conductors; 3. The semiconductor device according to claim 2.

4. The average length of the first conductors is approximately equal to the average length of the second conductors.

4. The semiconductor device according to claim 3.

5. each of the first conductors and the second conductors is a wire, a ribbon, or a lead frame; 4. The semiconductor device according to claim 3.

6. The semiconductor device includes: the at least one or more third transistors and the at least one or more fourth transistors are each a plurality of transistors; The semiconductor device according to claim 1.

7. a second terminal of the seventh transistor is electrically connected to the second terminal of each of the at least one or more third transistors via a plurality of first conductors; a second terminal of the eighth transistor is electrically connected to the second terminal of each of the at least one or more fourth transistors via a plurality of second conductors; 7. The semiconductor device according to claim 6.

8. The average length of the first conductors is approximately equal to the average length of the second conductors.

8. The semiconductor device according to claim 7.

9. Each of the first transistor, the second transistor, the third transistor, and the fourth transistor is a MOS transistor using silicon carbide (SiC), a MOS transistor using silicon (Si), an IGBT using silicon carbide (SiC), an IGBT using silicon (Si), or a transistor using gallium nitride (GaN). The semiconductor device according to claim 1.

10. Each of the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor is a MOS transistor using silicon (Si) or a transistor using gallium nitride (GaN), and is a vertical transistor or a horizontal transistor. The semiconductor device according to claim 1.

11. a gate terminal of each of the at least one or more first transistors and a gate terminal of each of the at least one or more second transistors are connected to a fourth node; a gate terminal of each of the at least one or more third transistors and a gate terminal of each of the at least one or more fourth transistors are connected to a fifth node; The semiconductor device according to claim 1.

12. The gate terminal of the fifth transistor and the gate terminal of the sixth transistor form a sixth node. Connected to a gate terminal of the seventh transistor and a gate terminal of the eighth transistor are connected to a seventh node; The semiconductor device according to claim 11.

13. the fourth node, the fifth node, the sixth node, and the seventh node are each a control terminal that receives a signal from an external source; The semiconductor device according to claim 12.

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