Semiconductor device and manufacturing method for the same

Abstract

To provide a semiconductor device in which the degree of freedom in circuit design is high and a manufacturing method for the same.SOLUTION: A manufacturing method for a semiconductor device includes steps of: forming a first electrode on an aluminum nitride layer of a substrate where a silicon carbide layer, the aluminum nitride layer, and a gallium nitride layer are stacked in this order, and forming an extraction electrode inside the gallium nitride layer and the aluminum nitride layer; removing the silicon carbide layer in a region including a range right below the first electrode and a range right below the extraction electrode; forming a second electrode facing the first electrode and connected to the extraction electrode, in the region; forming an insulating film covering the second electrode; and forming a metal film on a lower surface of the silicon carbide layer and on a lower surface of the insulating film.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The embodiments relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] In a semiconductor device in which an MMIC (Monolithic Microwave Integrated Circuit) is formed, a HEMT (High Electron Mobility Transistor) and a MIM (Metal-Insulator-Metal) capacitor may be mounted together on a single semiconductor substrate. In such a semiconductor device, there is a demand for improved freedom in circuit design. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-117066 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiments is to provide a semiconductor device with high degree of freedom in circuit design and a manufacturing method thereof. [Means for solving the problem]

[0005] A manufacturing method of a semiconductor device according to an embodiment includes the steps of forming a first electrode on an aluminum nitride layer of a substrate having a silicon carbide layer, an aluminum nitride layer, and a gallium nitride layer stacked in that order, and forming an extraction electrode in the gallium nitride layer and the aluminum nitride layer, removing the silicon carbide layer in a region including the area directly below the first electrode and the area directly below the extraction electrode, forming a second electrode in the region facing the first electrode and connected to the extraction electrode, forming an insulating film covering the second electrode, and forming a metal film on a lower surface of the silicon carbide layer and on a lower surface of the insulating film.

[0006] The semiconductor device of the embodiment comprises a silicon carbide layer having a through portion, an aluminum nitride layer arranged on the silicon carbide layer, a gallium nitride layer arranged on the aluminum nitride layer, a first electrode arranged in a first portion of the area directly above the through portion, a lead-out electrode arranged in a second portion of the area directly above the through portion and penetrating the gallium nitride layer and the aluminum nitride layer, a second electrode arranged in a region including the area directly below the first electrode within the through portion and connected to the lead-out electrode, an insulating film covering the second electrode, and a metal film arranged on a lower surface of the insulating film and on a lower surface of the silicon carbide layer. [Brief description of the drawings]

[0007] [Figure 1] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first embodiment. [Diagram 2] 2A to 2C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Diagram 3] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 4A to 4C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Diagram 5] 5A to 5C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6]6A to 6C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view showing the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a plan view showing the semiconductor device according to the first embodiment. [Figure 9] 9A to 9C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment. [Figure 10] 10A to 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing the semiconductor device according to the second embodiment. [Figure 12] 12A to 12C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the third embodiment. [Figure 13] 13A to 13C are cross-sectional views showing a method for manufacturing a semiconductor device according to the third embodiment. [Figure 14] FIG. 14 is a cross-sectional view showing a semiconductor device according to the third embodiment. [Figure 15] 15A to 15C are cross-sectional views showing a method for manufacturing a semiconductor device according to the fourth embodiment. [Figure 16] 16A to 16C are cross-sectional views showing a method for manufacturing a semiconductor device according to the fourth embodiment. [Figure 17] FIG. 17 is a cross-sectional view showing a semiconductor device according to the fourth embodiment. [Figure 18] FIG. 17 is a cross-sectional view showing a semiconductor device according to the fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] <First embodiment> In this embodiment, a method for manufacturing a semiconductor device provided with an MMIC in which a HEMT and a MIM are integrated, and a configuration of the manufactured semiconductor device will be described. Note that a description of the HEMT will be omitted.

[0009] 1 to 6 are cross-sectional views showing a method for manufacturing a semiconductor device according to this embodiment. FIG. 7 is a cross-sectional view showing the semiconductor device according to this embodiment. FIG. 8 is a plan view showing the semiconductor device according to the present embodiment. Note that each figure is schematic and has been appropriately emphasized and simplified, and the same applies to other figures described later.

[0010] (Method of manufacturing a semiconductor device) First, a wafer 10 is prepared as shown in Fig. 1. In the wafer 10, a silicon carbide layer (hereinafter referred to as "SiC layer 11"), an aluminum nitride layer (hereinafter referred to as "AlN layer 12"), a gallium nitride layer (hereinafter referred to as "GaN layer 13"), and an aluminum gallium nitride layer (AlGaN layer, not shown) are laminated in this order. The wafer 10 may be prepared by fabrication or may be provided by receiving it from another party.

[0011] An area where a HEMT is to be formed and an area where a MIM is to be formed are set on the wafer 10. In the area where the MIM is to be formed, the AlGaN layer is removed. As a result, the GaN layer 13 becomes the top layer of the wafer 10, as shown in Figure 1. On the other hand, in the area where the HEMT is to be formed, the AlGaN layer is left.

[0012] 2, etching is performed from the front surface 10a side of the wafer 10 to remove a portion of the GaN layer 13. This forms a through portion 15 in the GaN layer 13. The through portion 15 penetrates the GaN layer 13 in the thickness direction. In addition, a portion of the GaN layer 13 is removed, and then the AlN layer 12 directly below it is removed to form a through portion 16. The through portion 16 penetrates the GaN layer 13 and the AlN layer 12 in the thickness direction.

[0013] 3, a metal is embedded in through portion 15 to form a surface electrode 21. A metal is embedded in through portion 16 to form an extraction electrode 22. Surface electrode 21 penetrates GaN layer 13, and its lower surface contacts upper surface 12a of AlN layer 12. Extraction electrode 22 penetrates GaN layer 13 and AlN layer 12, and its lower surface contacts SiC layer 11.

[0014] 4, etching is performed from the back surface 10b side of the wafer 10 to remove the SiC layer 11 in the region including the region directly below the front surface electrode 21 and the region directly below the extraction electrode 22. As a result, a through portion 17 is formed in the back surface 10b of the wafer 10. The through portion 17 penetrates the SiC layer 11 in the thickness direction, and at the bottom of the through portion 17, the lower surface 12b of the AlN layer 12 and the lower surface of the extraction electrode 22 are exposed.

[0015] 5, a back electrode 23 is formed on a part or the entire bottom surface of the through portion 17. The upper surface of the back electrode 23 contacts the lower surface 12b of the AlN layer 12 and the lower surface of the extraction electrode 22. In this manner, the back electrode 23 is connected to the extraction electrode 22. In this specification, "connection" means electrical connection.

[0016] 6, an insulating film 25 is formed on the entire back surface 10b of the wafer 10. The insulating film 25 is formed of, for example, silicon nitride (SiN). The insulating film 25 is also formed on the inner surface of the through portion 17 and covers the back surface electrode 23.

[0017] 7, a metal film 26 is formed on the entire back surface 10b of the wafer 10. The metal film 26 is continuously formed on the lower surface of the SiC layer 11 and the lower surface of the insulating film 25. The metal film 26 covers the insulating film 25 and is separated from the back surface electrode 23 via the insulating film 25. The wafer 10 is then diced into individual pieces. In this manner, the semiconductor device 1 according to this embodiment is manufactured.

[0018] 2, it is preferable that the through-hole 16 reaches the SiC layer 11, but a small amount of the AlN layer 12 may be left at the bottom of the through-hole 16. In this case, when the through-hole 17 is formed in the SiC layer 11 in the step shown in FIG. 5, the lower surface 12b of the AlN layer 12 is slightly removed to expose the lower surface of the extraction electrode 22.

[0019] (Semiconductor Device) As shown in Figures 7 and 8, the semiconductor device 1 of this embodiment includes a SiC layer 11, an AlN layer 12, a GaN layer 13, a front surface electrode 21, an extraction electrode 22, a back surface electrode 23, an insulating film 25, and a metal film 26.

[0020] A through portion 17 is provided in the SiC layer 11. The AlN layer 12 is disposed on the SiC layer 11. The GaN layer 13 is disposed on the AlN layer 12. An AlGaN layer (not shown) may be provided on the GaN layer 13. The surface electrode 21 is disposed in a part of the region directly above the through portion 17, penetrates the GaN layer 13, and contacts the upper surface 12a of the AlN layer 12. The extraction electrode 22 is disposed in another part of the region directly above the through portion 17, and penetrates the GaN layer 13 and the AlN layer 12.

[0021] The back electrode 23 is disposed at the bottom of the through portion 17, contacts the lower surface 12b of the AlN layer 12 directly below the front electrode 21, and is connected to the extraction electrode 22. The insulating film 25 is disposed on the lower surface of the SiC layer 11 and on the inner surface of the through portion 17, and covers the back electrode 23. The insulating film 25 is made of, for example, SiN. The metal film 26 is disposed continuously on the lower surface of the SiC layer 11 and the lower surface of the insulating film 25, and covers the insulating film 25.

[0022] In this embodiment, the front surface electrode 21 is in contact with the upper surface 12a of the AlN layer 12, and the back surface electrode 23 is in contact with the lower surface 12b of the AlN layer 12. The front surface electrode 21 faces the back surface electrode 23 via the AlN layer 12, thereby forming an MIM capacitor 31. The back surface electrode 23 of the MIM capacitor 31 is led out to the front surface side of the semiconductor device 1 via an extraction electrode 22. The AlN layer 12 functions as a dielectric layer of the MIM capacitor 31. A ground potential (GND) is applied to the metal film 26. The back surface electrode 23 of the MIM capacitor 31 is insulated from the metal film 26 by an insulating film 25.

[0023] (effect) In the semiconductor device 1 according to this embodiment, the AlN layer 12 is used as the dielectric layer of the MIM capacitor 31. Since aluminum nitride (AlN) has a high dielectric constant, it is possible to ensure the thickness of the AlN layer 12 to realize the necessary withstand voltage while achieving a high capacitance in the MIM capacitor 31. As a result, it is possible to miniaturize the MIM capacitor 31 while ensuring the required capacitance. In addition, by using the AlN layer 12 included in the wafer 10 as the dielectric layer of the MIM capacitor 31, the manufacturing cost of the semiconductor device 1 can be reduced.

[0024] In addition, since the back electrode 23 of the MIM capacitor 31 is insulated from the metal film 26, any potential can be applied to the back electrode 23 even when a reference potential, for example, a ground potential, is applied to the metal film 26. As a result, the degree of freedom in circuit design of the semiconductor device 1 is improved.

[0025] If the back electrode 23 is not provided and the metal film 26 is used as the back electrode of the MIM capacitor 31, the potential of the back electrode of the MIM capacitor 31 is fixed to a reference potential, for example, a ground potential, resulting in low freedom of circuit design.

[0026] <Second embodiment> This embodiment differs from the first embodiment in that a laminated film made of an AlN layer 12 and a GaN layer 13 is used as the dielectric layer of the MIM capacitor. 9 and 10 are cross-sectional views showing a method for manufacturing a semiconductor device according to this embodiment. FIG. 11 is a cross-sectional view showing the semiconductor device according to this embodiment.

[0027] (Method of manufacturing a semiconductor device) First, as shown in FIG. 1, a wafer 10 is prepared. 9, etching is performed from the front surface 10a side of the wafer 10 to remove a part of the GaN layer 13 and a part of the AlN layer 12. This forms the through portion 16. The through portion 16 penetrates the GaN layer 13 and the AlN layer 12 in the thickness direction to reach the SiC layer 11. In this embodiment, the through portion 15 is not formed.

[0028] 10, a surface electrode 21 is formed on the GaN layer 13. In addition, a metal is embedded in the through portion 16 to form an extraction electrode 22. Next, steps similar to those shown in FIGS. 4 to 7 are carried out.

[0029] 11, through-holes 17 are formed in the SiC layer 11, a back electrode 23 is formed on the bottom surface of the through-hole 17, and an insulating film 25 and a metal film 26 are formed on the entire back surface 10b of the wafer 10. Thereafter, the wafer 10 is diced to manufacture the semiconductor device 2.

[0030] (Semiconductor Device) 11 , in the semiconductor device 2 according to this embodiment, a front surface electrode 21 is disposed on a GaN layer 13. The front surface electrode 21 faces a back surface electrode 23 via a laminated film made of an AlN layer 12 and a GaN layer 13, thereby forming an MIM capacitor 32. The back surface electrode 23 of the MIM capacitor 32 is led out to the front surface side via an extraction electrode 22. The laminated film made of the AlN layer 12 and the GaN layer 13 functions as a dielectric layer of the MIM capacitor 32.

[0031] (effect) In this embodiment, a laminated film consisting of an AlN layer 12 and a GaN layer 13 is used as the dielectric layer of the MIM capacitor 32, so that the withstand voltage of the MIM capacitor 32 is higher than that of the semiconductor device 1 according to the first embodiment. Other than the above, the manufacturing method, configuration, and effects of this embodiment are the same as those of the first embodiment.

[0032] <Third embodiment> This embodiment is different from the second embodiment in that the thickness of the GaN layer 13 constituting the MIM capacitor is adjusted. 12 and 13 are cross-sectional views showing a method for manufacturing a semiconductor device according to this embodiment. FIG. 14 is a cross-sectional view showing the semiconductor device according to this embodiment.

[0033] (Method of manufacturing a semiconductor device) First, as shown in FIG. 1, a wafer 10 is prepared. 12, etching is performed from the front surface 10a side of wafer 10 to remove a portion of GaN layer 13. This forms a recess 18 in GaN layer 13. A portion of GaN layer 13 remains on the bottom surface of recess 18.

[0034] At this time, thickness t1 of GaN layer 13 to be left directly below recess 18 is determined according to the balance between the withstand voltage and capacitance of the MIM capacitor to be formed. Also, a part of GaN layer 13 and a part of AlN layer 12 are removed to form penetrating portion 16. Penetrating portion 16 penetrates GaN layer 13 and AlN layer 12 in the thickness direction to reach SiC layer 11.

[0035] 13, a metal is embedded in the recess 18 to form a surface electrode 21. Also, a metal is embedded in the through portion 16 to form a lead electrode 22. Next, steps similar to those shown in FIGS. 4 to 7 are carried out.

[0036] As a result, as shown in FIG. 14, a through-hole 17 is formed in the SiC layer 11, a back surface electrode 23 is formed on the bottom surface of the through-hole 17, and an insulating film 25 and a metal film 26 are formed on the entire back surface 10b of the wafer 10. Thereafter, the semiconductor device 3 is manufactured by dicing the wafer 10.

[0037] (Semiconductor device) As shown in FIG. 14, in the semiconductor device 3 according to the present embodiment, the surface electrode 21 is disposed in the recess 18 of the GaN layer 13. For this reason, the thickness t1 of the portion located directly below the surface electrode 21 in the GaN layer 13 is smaller than the thickness t2 of the portion excluding the region directly below the surface electrode 21 in the GaN layer. That is, t1 < t2. Therefore, the distance between the surface electrode 21 and the back surface electrode 23 is smaller than the thickness of the stacked film composed of the AlN layer 12 and the GaN layer 13.

[0038] Then, the surface electrode 21 faces the back surface electrode 23 through a part of the AlN layer 12 and the GaN layer 13, thereby forming a MIM capacitor 33. The back surface electrode 23 of the MIM capacitor 33 is drawn out to the surface side through the lead-out electrode 22. The stacked film composed of a part of the AlN layer 12 and the GaN layer 13 functions as a dielectric layer of the MIM capacitor 33.

[0039] (Effect) In the present embodiment, by adjusting the thickness t1 of the GaN layer 13 remaining in the region directly below the recess 18, the balance between the breakdown voltage and the capacitance of the MIM capacitor 33 can be controlled. The manufacturing method, configuration, and effects other than those described above in the present embodiment are the same as those in the first embodiment.

[0040] <Fourth Embodiment> This embodiment is different from the first embodiment in that the GaN layer 13 is used for the dielectric layer of the MIM capacitor. FIGS. 15 and 16 are cross-sectional views showing a method of manufacturing a semiconductor device according to the present embodiment. FIG. 17 is a cross-sectional view showing the semiconductor device according to the present embodiment.

[0041] (Method of manufacturing a semiconductor device) First, as shown in FIG. 1, a wafer 10 is prepared. 9, etching is performed from the front surface 10a side of the wafer 10 to form the through-holes 16. In this embodiment, the through-holes 15 are not formed. 10, a surface electrode 21 is formed on the GaN layer 13. Also, an extraction electrode 22 is formed in the through portion 16.

[0042] 4 is then performed. That is, etching is performed from the back surface 10b side of the wafer 10 to remove a part of the SiC layer 11. As a result, a through portion 17 is formed in the SiC layer 11. At the bottom of the through portion 17, the lower surface 12b of the AlN layer 12 and the lower surface of the extraction electrode 22 are exposed.

[0043] 15, a portion of the AlN layer 12 is removed in the region directly below the front surface electrode 21 at the bottom surface of the through portion 17. This forms a through portion 19 in the AlN layer 12. The through portion 19 penetrates the AlN layer 12 in the thickness direction. At the bottom of the through portion 19, the lower surface 13b of the GaN layer 13 is exposed.

[0044] 16, a back electrode 23 is formed on a part or the whole of the bottom surface of the through portion 17. The back electrode 23 is also formed inside the through portion 19. As a result, the back electrode 23 is in contact with the lower surface 13b of the GaN layer 13. The back electrode 23 faces the front electrode 21 via the GaN layer 13, and is connected to the extraction electrode 22.

[0045] Next, steps similar to those shown in FIGS. 6 and 7 are carried out. 17, an insulating film 25 and a metal film 26 are formed over the entire back surface 10b of the wafer 10. Thereafter, the wafer 10 is diced to manufacture the semiconductor device 4.

[0046] (Semiconductor Device) 17, in the semiconductor device 4 according to this embodiment, the back electrode 23 penetrates the AlN layer 12 and contacts the lower surface 13b of the GaN layer 13. Meanwhile, the front surface electrode 21 contacts the upper surface 13a of the GaN layer 13. In this manner, the front surface electrode 21 faces the back surface electrode 23 via the GaN layer 13, thereby forming an MIM capacitor 34. The GaN layer 13 functions as a dielectric layer of the MIM capacitor 34.

[0047] (effect) In this embodiment, a GaN layer 13 is used as a dielectric layer of the MIM capacitor 34. Depending on the characteristics required of the MIM capacitor, such an MIM capacitor 34 may be preferable. Other than the above, the manufacturing method, configuration, and effects of this embodiment are the same as those of the first embodiment.

[0048] <Fifth embodiment> This embodiment is different from the fourth embodiment in that the thickness of the GaN layer 13 constituting the MIM capacitor is adjusted. FIG. 18 is a cross-sectional view showing the semiconductor device according to this embodiment.

[0049] (Method of manufacturing a semiconductor device) First, as shown in FIG. 1, a wafer 10 is prepared. 12, a recess 18 is formed in the GaN layer 13. At this time, a thickness t1 of the GaN layer 13 to be left directly under the recess 18 is determined according to the balance between the withstand voltage and the capacitance of the MIM capacitor to be formed. In addition, a through portion 16 is formed to penetrate the GaN layer 13 and the AlN layer 12.

[0050] 13, a surface electrode 21 is formed in the recess 18. Also, an extraction electrode 22 is formed in the through portion 16. Next, a process similar to that shown in FIG. 4 is carried out to form a through-hole 17 on the back surface 10b of the wafer 10. As shown in FIG.

[0051] Next, a process similar to that shown in FIG. 15 is carried out to form a through portion 19 in the AlN layer 12 at the bottom surface of the through portion 17. Next, steps similar to those shown in FIG. 16, FIG. 6 and FIG. 7 are carried out.

[0052] 18, an insulating film 25 and a metal film 26 are formed on the entire back surface 10b of the wafer 10. Thereafter, the wafer 10 is diced to manufacture the semiconductor device 5.

[0053] (Semiconductor Device) 18, in the semiconductor device 5 according to this embodiment, the front surface electrode 21 is disposed in the recess 18. Therefore, the thickness t1 of the GaN layer 13 left directly below the recess 18 is smaller than the thickness t2 of the GaN layer 13 excluding the region directly below the front surface electrode 21.

[0054] The front surface electrode 21 faces the back surface electrode 23 via the GaN layer 13 disposed directly below the recess 18, thereby forming an MIM capacitor 35. The GaN layer 13 disposed directly below the recess 18 functions as a dielectric layer for the MIM capacitor 32.

[0055] (effect) In this embodiment, the balance between the breakdown voltage and the capacitance of MIM capacitor 35 can be controlled by adjusting the thickness t1 of GaN layer 13 that remains directly under recess 18. Other manufacturing methods, configurations, and effects of this embodiment are similar to those of the first embodiment.

[0056] According to the embodiment described above, it is possible to realize a semiconductor device with a high degree of freedom in circuit design and a method for manufacturing the same.

[0057] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims.

[0058] The present invention includes the following aspects.

[0059] (Appendix 1) forming a first electrode on the aluminum nitride layer of a substrate having a silicon carbide layer, an aluminum nitride layer, and a gallium nitride layer stacked in this order, and forming extraction electrodes in the gallium nitride layer and the aluminum nitride layer; removing the silicon carbide layer in a region including a region directly below the first electrode and a region directly below the extraction electrode; forming a second electrode in the region opposite to the first electrode and connected to the extraction electrode; forming an insulating film covering the second electrode; forming a metal film on a lower surface of the silicon carbide layer and on a lower surface of the insulating film; A method for manufacturing a semiconductor device comprising the steps of:

[0060] (Appendix 2) The step of forming the first electrode and the extraction electrode includes: forming a through-portion in the gallium nitride layer; forming the first electrode in the through portion; 2. A method for manufacturing a semiconductor device according to claim 1, comprising:

[0061] (Appendix 3) 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the first electrode and the extraction electrode, the first electrode is formed on the gallium nitride layer.

[0062] (Appendix 4) The step of forming the first electrode and the extraction electrode includes: forming a recess in the gallium nitride layer; forming the first electrode in the recess; 2. A method for manufacturing a semiconductor device according to claim 1, comprising:

[0063] (Appendix 5) After the step of removing the silicon carbide layer, the method further includes the step of forming a through portion in the aluminum nitride layer directly below the first electrode, 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the second electrode, the second electrode is also formed inside the through portion.

[0064] (Appendix 6) 6. The method for manufacturing a semiconductor device according to claim 5, wherein in the step of forming the first electrode and the extraction electrode, the first electrode is formed on the gallium nitride layer.

[0065] (Appendix 7) The step of forming the first electrode and the extraction electrode includes: forming a recess in the gallium nitride layer; forming the first electrode in the recess; 6. A method for manufacturing a semiconductor device according to claim 5, comprising the steps of:

[0066] (Appendix 8) a silicon carbide layer having a through-portion; an aluminum nitride layer disposed on the silicon carbide layer; a gallium nitride layer disposed on the aluminum nitride layer; a first electrode disposed in a first portion directly above the through portion; an extraction electrode disposed in a second portion directly above the through portion and penetrating the gallium nitride layer and the aluminum nitride layer; a second electrode that is disposed in a region including a region directly below the first electrode in the through-hole and is connected to the extraction electrode; an insulating film covering the second electrode; a metal film disposed on a lower surface of the insulating film and on a lower surface of the silicon carbide layer; A semiconductor device comprising:

[0067] (Appendix 9) 9. The semiconductor device according to claim 8, wherein the second electrode is in contact with a lower surface of the aluminum nitride layer in a region directly below the first electrode.

[0068] (Appendix 10) 10. The semiconductor device according to claim 9, wherein the first electrode penetrates the gallium nitride layer and contacts an upper surface of the aluminum nitride layer.

[0069] (Appendix 11) 10. The semiconductor device of claim 9, wherein the first electrode is disposed on the gallium nitride layer.

[0070] (Appendix 12) 9. The semiconductor device according to claim 8, wherein the second electrode penetrates the aluminum nitride layer in a region directly below the first electrode and contacts a lower surface of the gallium nitride layer.

[0071] (Appendix 13) 13. The semiconductor device according to claim 11, wherein a thickness of a portion of the gallium nitride layer located directly below the first electrode is thinner than a thickness of a portion of the gallium nitride layer other than the region directly below the first electrode. [Explanation of symbols]

[0072] 1, 2, 3, 4, 5 Semiconductor device, 10 wafers 10a surface 10b back side 11 SiC layer 12 AlN layer 12a Top side 12b Bottom side 13 GaN layer 13a Top side 13b Bottom side 15 Penetration 16 Penetration 17 Penetration 18 Recess 19 Penetration 21 Surface electrode 22 Extraction electrode 23 Back electrode 25 Insulating film 26 Metal Film 31, 32, 33, 34, 35 MIM capacitors t1, t2: Thickness of GaN layer 13

Claims

1. forming a first electrode on the aluminum nitride layer of a substrate having a silicon carbide layer, an aluminum nitride layer, and a gallium nitride layer stacked in this order, and forming extraction electrodes in the gallium nitride layer and the aluminum nitride layer; removing the silicon carbide layer in a region including a region directly below the first electrode and a region directly below the extraction electrode; forming a second electrode in the region opposite to the first electrode and connected to the extraction electrode; forming an insulating film covering the second electrode; forming a metal film on a lower surface of the silicon carbide layer and on a lower surface of the insulating film; A method for manufacturing a semiconductor device comprising the steps of:

2. The step of forming the first electrode and the extraction electrode includes: forming a through-portion in the gallium nitride layer; forming the first electrode in the through portion; The method for manufacturing a semiconductor device according to claim 1 , comprising:

3. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the first electrode and the extraction electrode, the first electrode is formed on the gallium nitride layer.

4. The step of forming the first electrode and the extraction electrode includes: forming a recess in the gallium nitride layer; forming the first electrode in the recess; The method for manufacturing a semiconductor device according to claim 1 , comprising:

5. After the step of removing the silicon carbide layer, the method further includes the step of forming a through portion in the aluminum nitride layer directly below the first electrode, 2 . The method for manufacturing a semiconductor device according to claim 1 , wherein in the step of forming the second electrode, the second electrode is also formed inside the through portion.

6. 6. The method for manufacturing a semiconductor device according to claim 5, wherein in the step of forming the first electrode and the extraction electrode, the first electrode is formed on the gallium nitride layer.

7. The step of forming the first electrode and the extraction electrode includes: forming a recess in the gallium nitride layer; forming the first electrode in the recess; The method for manufacturing a semiconductor device according to claim 5 , further comprising the steps of:

8. a silicon carbide layer having a through-portion; an aluminum nitride layer disposed on the silicon carbide layer; a gallium nitride layer disposed on the aluminum nitride layer; A first electrode disposed in a first portion directly above the through portion; an extraction electrode disposed in a second portion directly above the through portion and penetrating the gallium nitride layer and the aluminum nitride layer; a second electrode that is disposed in a region including a region directly below the first electrode in the through-hole and is connected to the extraction electrode; an insulating film covering the second electrode; a metal film disposed on a lower surface of the insulating film and on a lower surface of the silicon carbide layer; A semiconductor device comprising:

9. The semiconductor device according to claim 8 , wherein the second electrode is in contact with a lower surface of the aluminum nitride layer in a region directly below the first electrode.

10. The semiconductor device according to claim 9 , wherein the first electrode penetrates the gallium nitride layer and contacts an upper surface of the aluminum nitride layer.

11. The semiconductor device according to claim 9 , wherein the first electrode is disposed on the gallium nitride layer.

12. The semiconductor device according to claim 8 , wherein the second electrode penetrates the aluminum nitride layer in a region directly below the first electrode and contacts a lower surface of the gallium nitride layer.

13. 13. The semiconductor device according to claim 11, wherein a thickness of the portion of the gallium nitride layer located directly below the first electrode is thinner than a thickness of the portion of the gallium nitride layer other than the region directly below the first electrode.

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