Quantum device and method for manufacturing the same

Abstract

To connect a laminated substrate of a quantum device and a wiring component to each other without passing through a wire bonding step.SOLUTION: A quantum device that utilizes a quantum state includes a quantum chip 1, a wiring component 3 having a wiring layer 2, and a laminated substrate 4 that is arranged such that at least a surface of the wiring component 3 on which the quantum chip 1 is mounted is exposed. The wiring layer 5 of the laminated substrate 4 and the wiring layer 2 of the wiring component 3 are connected to each other by an integral conductor pattern 6, and the wiring layer 2 of the wiring component 3 and the wiring layer 5 of the laminated substrate 4 are connected to each other by the integral conductor pattern 6. Although wire bonding is not required to connect the wiring layer 2 and the wiring layer 5, thermal stress between the wiring component 3 and the laminated substrate 4 can be prevented.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to quantum devices and methods for fabricating the same. [Background technology]

[0002] Patent Document 1 discloses a quantum device in which a quantum chip is mounted on an interposer, the interposer is embedded in a base substrate (e.g., a PCB (Print circuit board)), and the circuit conductors of the base substrate and the circuit conductors of the interposer are connected by bonding wires. This quantum device suppresses thermal stress caused by the difference in the thermal expansion coefficient of the materials that make up each component (for example, between the Si (silicon) that makes up the interposer and the organic material that makes up the PCB), thereby stabilizing the electrical connections at the contact points and maintaining the quality of the signal transmission. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2022-002238 Summary of the Invention [Problem to be solved by the invention]

[0004] In the above Patent Document 1, since bonding wires are used to connect the interposer and base substrate, in addition to the process of providing a conductor layer on the surface of the base substrate and interposer, and processing this conductor layer to form a predetermined circuit pattern by patterning using processes such as sputtering, vapor deposition, electroless plating, electrolytic plating, etc., a process for connection using the bonding wires, i.e., a process using a wire bonder, which is different from the process of processing the conductor layer to form a predetermined conductor pattern, is required. In addition, with bonding wires, impedance matching is difficult because the connection is made up of separate wires, and the spacing between wires for signal and ground circuits cannot be maintained at the desired distance. Impedance matching is particularly important at high frequencies on the order of GHz (gigahertz) and above. Therefore, the quantum device described in Patent Document 1 requires separate manufacturing equipment using equipment for performing an additional bonding process, which increases the manufacturing equipment costs and poses the problem of suppressing degradation of signal characteristics in the high frequency band.

[0005] An object of the present invention is to simplify the process required for connecting an interposer and a base substrate of a quantum device. [Means for solving the problem]

[0006] In order to solve the above problems, the present invention proposes the following means. A quantum device according to a first aspect of the present invention is a quantum device that utilizes a quantum state, and is characterized in that it comprises a quantum chip, a wiring component having a wiring layer, and a laminated substrate installed so that at least the surface of the wiring component on which the quantum chip is mounted is exposed, and the wiring layer of the laminated substrate and the wiring layer of the wiring component are connected by an integral conductor pattern.

[0007] In addition, a second aspect of the present invention relates to a method for manufacturing a quantum device comprising a quantum chip, a wiring component having a wiring layer, and a laminated substrate arranged so that at least the surface of the wiring component on which the quantum chip is mounted is exposed, and is characterized in that it includes a step of embedding the wiring component in a recess of the laminated substrate, and a step of connecting the laminated substrate and the wiring component by an integrated conductor pattern. Effect of the Invention

[0008] According to the present invention, the process required for connecting the interposer of the quantum device to the base substrate can be simplified. [Brief description of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view showing an example of a minimum configuration of a quantum device according to the present invention. [Diagram 2] 1 is a cross-sectional view of a quantum device according to a first embodiment of the present invention. [Diagram 3] 1A and 1B are plan and cross-sectional views of a quantum device according to a first embodiment of the present invention, where (a) and (b) show an embodiment in which an interposer is mounted on a laminated substrate, and (a') and (b') show an embodiment in which a quantum device is mounted on an interposer. [Figure 4] FIG. 4 is a cross-sectional view of a quantum device according to a second embodiment of the present invention. [Diagram 5] FIG. 11 is a cross-sectional view of a quantum device according to a third embodiment of the present invention. [Figure 6] FIG. 11 is a cross-sectional view of a quantum device according to a fourth embodiment of the present invention. [Figure 7] FIG. 11 is a cross-sectional view of a quantum device according to a fifth embodiment of the present invention. [Figure 8] 13A and 13B show a quantum device according to a sixth embodiment of the present invention, in which (a) is a plan view and (b) is a cross-sectional view. [Figure 9] 9 is an enlarged view of the dotted line IX portion of the quantum device shown in FIG. 8, where (a') is a plan view of chamfering example 1 and (a") is a cross-sectional view of chamfering example 2, and (b') is a cross-sectional view of chamfering example 1 and (b") is a cross-sectional view of chamfering example 2. [Figure 10] 13A and 13B are plan views of quantum devices according to a seventh embodiment of the present invention, in which (a) is an example in which one quantum device is stacked on an interposer, and (b) is an example in which a plurality of quantum devices are stacked on an interposer. [Figure 11] 13A, 13B, and 13C are plan views of a quantum device according to an eighth embodiment of the present invention, showing first, second, and third modified examples of the range between the quantum device and an interposer, respectively. [Figure 12] 13A, 13B, and 13C are plan views of a quantum device according to a ninth embodiment of the present invention, showing first, second, and third modified examples of the arrangement of wiring components with respect to a quantum device and an interposer, respectively. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] A quantum device according to an example of a minimum configuration of the present invention will be described with reference to FIG. This quantum device is a quantum device that utilizes a quantum state, and is characterized in that it comprises a quantum chip 1, a wiring component 3 having a wiring layer 2, and a laminated substrate 4 arranged so that at least the surface of the wiring component 3 on which the quantum chip 1 is mounted is exposed, and that the wiring layer 5 of the laminated substrate 4 and the wiring layer 2 of the wiring component 3 are connected by an integral conductor pattern 6.

[0011] According to the above configuration, the wiring layer 2 of the wiring component 3 and the wiring layer 5 of the laminated substrate 4 are connected by an integral conductor pattern 6, so that the wiring layer 2 and the wiring layer 5 can be connected by using equipment generally employed in the manufacture of the laminated substrate 4, such as forming a predetermined circuit pattern using resist masking, without using wire bonding equipment. In each of the wiring layers 2, 5, the positional relationship between the signal and ground circuits is matched, so that impedance matching can be achieved.

[0012] In addition, a manufacturing method for a quantum device according to a second aspect of the present invention is a manufacturing method for a quantum device comprising a quantum chip 1, a wiring component 3 having a wiring layer 2, and a laminated substrate 4 arranged so that at least the surface of the wiring component 3 on which the quantum chip 1 is mounted is exposed, and is characterized in having a step of embedding the wiring component 3 in a recess 7 of the laminated substrate 4, and a step of connecting the laminated substrate 4 and the wiring component 3 by an integral conductor pattern 6.

[0013] According to the above configuration, by embedding the wiring component 3 in the recess 7 of the laminated substrate 4, the wiring layer 2 of the wiring component 3 and the wiring layer 5 of the laminated substrate 4 can be connected by an integrated conductor pattern 6. The connection between the wiring layer 2 and the wiring layer 5 can be achieved by using equipment commonly employed in the manufacture of laminated substrates 4, such as trimming, without using wire bonding equipment.

[0014] 2 and 3 show a first embodiment of the present invention. Reference numeral 10 denotes a quantum chip for performing quantum computing. The quantum computing refers to a function of processing data using quantum mechanical phenomena caused by quantum bits, and the quantum chip 10 has a configuration in which connection parts 12 (which do not necessarily have to be conductor layers forming a circuit pattern as long as they are conductors that can be connected to circuit elements in the quantum chip 10) are provided in a predetermined arrangement on the lower surface of the substrate 11. The connection parts 12 are preferably made of a superconducting material. More specifically, the substrate 11 is made of a material that is less deformed in a superconducting environment, such as silicon (Si), gallium arsenide (GaAs), sapphire, glass, etc. The connection portion 12 constituting the quantum bit circuit formed on the substrate 11 is made of niobium (Nb), niobium nitride such as niobium nitride, aluminum (Al), indium (In), lead (Pb), tin (Sn), rhenium (Re), palladium (Pd), titanium (Ti), titanium nitride, tantalum (Ta), tantalum nitride, or an alloy having superconductivity containing at least any of these. In this embodiment, the connecting portion 12 may have a metal layer of gold (Au), platinum (Pt), palladium (Pd) or the like formed on the surface as the metal of the connecting portion, in addition to the superconducting material.

[0015] The quantum chip 10 is mounted on a wiring component 20 that is connected to the connection portion 12 of the quantum chip 10, and the wiring component 20 is connected to a wiring layer 21 on the upper surface thereof by a bump 30 made of a conductor. The wiring component 20 is made of a material that has no difference in thermal expansion with the quantum chip 10 or has a difference as small as possible, such as silicon (Si), gallium arsenide (GaAs), sapphire, glass, or the like. The wiring layer 21 provided on one side (upper side in FIG. 3) of the wiring component 20 and used for connection with the quantum chip 10 is made of indium (In), niobium (Nb), niobium nitride such as niobium nitride, titanium (Ti), titanium nitride, tantalum (Ta), tantalum nitride, aluminum (Al), lead (Pb), tin (Sn), or a superconducting alloy containing at least one of these. A metal layer such as gold (Au), platinum (Pt), or palladium (Pd) may be formed on the surface.

[0016] The wiring component 20 is inserted into a recess 7 formed by recessing the top surface of the laminated substrate 40 (more specifically, penetrating only the first substrate 41 of a first substrate 41 and a second substrate 42 described below). In the illustrated example, the top surface of the wiring component 20 is configured so that the wiring component 20 and the laminated substrate 40 are on the same plane. The inner diameter of the recess 7 and the outer diameter of the wiring component 20 are set to a dimensional tolerance such that one of them is elastically deformed to an extent that there is a contact pressure that allows relative movement due to temperature changes, or a minute gap can be secured regardless of temperature changes. Furthermore, since the bottom surface of the wiring component 20 does not include the wiring layer 21, the base material thereof is exposed and is in direct contact with the top surface of the laminated substrate 40. The wiring component 20 essentially serves as an interposer between a conductor formed with the wiring density of the contact portion with the fine elements of the quantum chip 10 and the laminated substrate 40 having a wiring layer of a circuit pattern formed with a general wiring density.

[0017] The laminated substrate 40 has a basic configuration in which a first substrate 41 and a second substrate 42 made of insulating material are laminated, and the first substrate 41 and the second substrate 42 have wiring layers 43, 44, and 45 made of conductors forming a predetermined circuit pattern on their surfaces. The wiring layer 43 is covered with an insulating layer 46 formed of, for example, a solder resist or a passivation film, except for the connection portion with the quantum chip 10. The wiring layer 45 is covered with an insulating layer 47 formed of, for example, a solder resist or a passivation film, except for the connection portion with an external device.

[0018] The first substrate 41 has a first interlayer via 48 penetrating therethrough, and the first interlayer via 48 electrically connects the wiring layer 43 on the upper surface of the first substrate to the wiring layer 44. The second substrate 42 has a second interlayer via 49 penetrating therethrough, and the second interlayer via 49 electrically connects the wiring layer 44 between the first and second substrates 41, 42 to the wiring layer 45 on the lower surface of the second substrate 42. Furthermore, the second substrate 42 includes, on its lower surface, a wiring layer 45, a connector 50 having terminals in a predetermined arrangement for connecting the wiring component 20 to a circuit of an external device via the wiring layers 43, 44, and 45. In the first embodiment (similarly in other embodiments described later), the quantum chip 10 has two connection parts 12A and 12B, and the (first) connection part 12A is connected to the (first) connector 50 (50A) via the bump 30, wiring layer 21, wiring layer 43, first interlayer via 48, wiring layer 44, second interlayer via 49, and wiring layer 45, all of which are arranged on the left side of the center in Fig. 2, and the (second) connection part 12B is connected to the (second) connector 50 (50B) via the bump 30, wiring layer 21, wiring layer 43, first interlayer via 48, wiring layer 44, second interlayer via 49, and wiring layer 45, all of which are arranged on the right side of the center in Fig. 2. That is, the quantum chip 10 can individually transmit and receive data to and from devices connected to the first connector 50A and the second connector 50B.

[0019] The quantum chip 10 and the wiring component 20 are configured such that the wiring component 20 is placed in a recess 7 of the laminated substrate 40 as shown in FIG. 3(a), and the depth of the recess 7 and the thickness of the wiring component 20 are set so that their upper surfaces are flush with each other as shown in FIG. 3(b). On top of the wiring component 20 thus arranged on the laminated substrate 40, the quantum chip 10 is mounted, which has the same shape in a planar view (a shape in which the entire component is overlapping vertically) or, as shown in Figures 3(a') and (b'), has a slightly smaller shape in a planar view (a planar shape that overlaps part of the wiring component 20), and these are connected by the bumps 30.

[0020] The wiring layers 43, 44, 45 of the laminated substrate 40 are made of materials such as copper (Cu), aluminum (Al), etc., and are formed into a predetermined circuit pattern by means of sputtering, vapor deposition, electroless plating, electrolytic plating, etc. Specific methods for forming a layer of conductive material into a predetermined circuit pattern include a subtractive method using a resist applied to the surface as a mask, an additive method using plating, a SEMI additive method, and a lift-off method in which a pattern is formed by removing the applied resist. The insulating layers 46, 47 can be formed by known methods such as a method of forming an insulating layer using solder resist, or a method of selectively imparting insulation to some regions by passivation. The constituent material of the first substrate 41 and the second substrate 42 may be organic plastic alone or may contain inorganic or organic fillers, or may be a structure in which organic plastic is impregnated or laminated onto a reinforcing material such as glass cloth.

[0021] In the first embodiment having the above configuration, the wiring components 20 having the quantum chip 10 mounted thereon by bumps 30 are placed in the recesses 7 of the laminated substrate 40, and then the wiring layer 43 is formed across the wiring components 20 and the laminated substrate 40, thereby manufacturing a quantum device. Here, since the wiring layer 43 can be formed by the manufacturing method for forming a general circuit pattern as described above, a quantum device including the quantum chip 10 can be manufactured without a wire bonding process. In each wiring layer, the positional relationship between the signal and ground circuits is matched, so that impedance matching can be realized. Furthermore, since the wiring component 20 is housed in the recess 7 of the laminated substrate 40, the difference in thermal expansion and contraction between the wiring component 20 and the laminated substrate 40 due to the temperature changes necessary for the operation of a quantum device that utilizes the superconducting phenomenon is absorbed by the gap between the wiring component 20 and the recess 7, or by elastic deformation that does not cause excessive thermal stress, thereby preventing damage or deterioration of the quantum chip 10 and the wiring component 20.

[0022] A second embodiment of the present invention will be described with reference to Fig. 4. In the figure, components common to Figs. 2 and 3 are given the same reference numerals to simplify the description. In this second embodiment, the wiring component 20 has wiring layers 21, 22 on its front surface (the surface facing the quantum chip 10) and back surface (the opposite surface), and also has a connecting conductor 23 that penetrates the wiring component 20 and electrically connects the wiring layers 21, 22 on the front and back surfaces. Moreover, the wiring layer 22 on the back surface is connected to a wiring layer 45 on the back surface side of the second substrate 42 through a second interlayer via 49 .

[0023] In this second embodiment, the wiring component 20 is connected not only to the front surface of the first substrate 41 constituting the laminated substrate 40, but also to a wiring layer 44 between the first substrate 41 and the second substrate 42 via a connecting conductor 23, and is further connected to a wiring layer 45 on the rear surface side via a second interlayer via 49.

[0024] A third embodiment of the present invention will be described with reference to Fig. 5. In the figure, components common to Figs. 2, 3 and 4 are given the same reference numerals to simplify the description. In the third embodiment, a plurality of wiring layers 21, 24 and wiring layers 22, 25 are provided on the front and back surfaces of the wiring component 20, respectively, and the wiring layers 21, 24 are connected by a connection portion 26, and the wiring layers 22, 25 are connected by a connection portion 27. In this manner, by providing the wiring component 20 with a plurality of wiring layers 21, 24, 22, 25, it is possible to connect with the wiring layers 43, 44, 45 of the laminated substrate 40 at more points, and it is possible to wire and connect the quantum chip 10 and the device connected via the connector 50 with higher density. When facing a quantum bit circuit, measures are required to prevent energy loss in the quantum bit circuit, and if measures such as shielding by a ground circuit are insufficient, the characteristics will deteriorate, so it is preferable for the quantum chip 10 to be mounted on a separate component such as an interposer. In other words, in a quantum bit circuit (or more precisely, the resonators and couplers that make up the quantum bit), maintaining the quantum state for a long period of time is directly linked to performance. The time during which this quantum state is maintained is called the coherence time, and a long coherence time allows calculations to be continued until the correct answer is found, resulting in a high final accuracy rate. Furthermore, because the quantum state disappears when energy loss occurs, it is necessary to avoid placing dielectric materials that cause energy loss in and near the quantum circuit area. It is desirable to keep the substrate (silicon, sapphire, etc.) on which the circuit is mounted to a minimum, and to avoid placing it in an area larger than necessary. Therefore, since it is desirable to avoid placing a dielectric material close to the circuit surface of the quantum chip 10 having the quantum circuit, i.e., the surface on which the connection terminals are provided, in the case of a flip chip, it is necessary to avoid placing a dielectric material close to the surface on the wiring component 20 side. After mounting on wiring component 20, restrictions on the placement of a dielectric (insulating material) can be alleviated by configuring a shield by appropriately connecting to ground in a circuit on the wiring component 20 side. In addition, the shield configuration of wiring component 20 allows the use of a dielectric (insulating material) for laminated substrate 40.

[0025] A fourth embodiment of the present invention will be described with reference to Fig. 6. In the figure, the same components as those in Figs. 2, 3, 4 and 5 are given the same reference numerals to simplify the description. The fourth embodiment has a fillet 60 protruding from the upper surface of the laminated substrate 40. The fillet 60 is made of organic plastic or the like, like the laminated substrate 40, and is formed by integral molding with the laminated substrate 40 or by being fixed to the upper surface of the laminated substrate 40 by adhesion or the like. The fillet 60 has a gap penetrating vertically, and the space surrounded by this penetrating point and the laminated substrate 40 forms a recess 7 that accommodates the wiring component 20, and in a plan view has a contour shape (generally a square or rectangle) surrounding the periphery of the recess 7. One side of the fillet 60 has a wiring layer 61, which forms a predetermined circuit pattern and connects the wiring layer 43 on the upper surface of the laminated substrate 40 and the wiring layer 21 on the upper surface of the wiring component 20. The lower surface of the wiring component 20 arranged inside the fillet 60 is provided with an adhesive layer 28 made of a metal such as Ag (silver) that serves as a die bond or paste material, and this adhesive layer 28 adheres the wiring component 20 to the upper surface of the laminated substrate 40.

[0026] In the fourth embodiment, since the fillet 60 is provided on the upper surface of the laminated substrate 40, a recess 7 for accommodating the wiring component 20 can be provided on the upper surface of the laminated substrate 40 by using a flat standard substrate as the laminated substrate 40 and additionally attaching the fillet 60 to the upper surface thereof, and the laminated substrate 40 can be manufactured without using wire bonding equipment, as in the first to third embodiments. In addition, as the wiring layers 43-61-21 are formed across the surface of the laminated substrate 40 and the surface of the wiring component 20 and electrically connected, the wiring layer 61 between the wiring layers 21 and 46 can be supported from below by the fillet 60. For example, even if a difference in thermal expansion occurs between the laminated substrate 40, the fillet 60, and the wiring component 20, the wiring layer 61 can be reinforced to prevent disconnection.

[0027] A fifth embodiment of the present invention will be described with reference to Fig. 7. In the figure, components common to Figs. 2, 3, 4, 5 and 6 are given the same reference numerals to simplify the description. In the fifth embodiment, the wiring layer 21 on the lower surface of the wiring component 20 and the underlying wiring layers 43A, 43B of the laminated substrate 40 are connected by a connection portion 26 made of a metal bump. An underfill portion 29 is formed between the wiring layer 21 and the wiring layers 43A, 43B by injecting a synthetic resin.

[0028] In the fifth embodiment, by utilizing the two wiring layers 21, 25 on the front and back of the wiring component 20, connections with the wiring layers 43A, 43B, etc. of the laminated substrate 40 can be made at more connection points.

[0029] The adhesive layer 28, the underfill portion 29, and the fillet 60 are mainly made of an organic resin. Examples of the organic resin include epoxy resin, acrylic resin, urethane resin, styrene resin, polyimide, polyamide, and oxazole. For example, the fillet 60 and the adhesive layer 28 of the fourth embodiment may be made of the same organic resin, or the underfill portion 29 and the fillet 60 of the fifth embodiment may be made of the same organic resin and formed in the same manufacturing process, which is effective in simplifying the manufacturing process. These organic resins may be mixed with inorganic or organic fillers (reinforcing fibers) for the purposes of adjusting the thermal expansion coefficient to prevent warping, reducing shrinkage when the organic resin hardens, and preventing the occurrence and progression of cracks due to aging. Similarly, different types of organic resins may be mixed or laminated (bonded) together. Furthermore, the exposed surface of wiring component 20 and the terminal electrodes or wiring layers on the surface of laminated substrate 40 facing wiring component 20 may be electrically connected by printing with a conductive paste or by printing using an inkjet method. Furthermore, it goes without saying that the number of layers of the substrates constituting the laminated substrate 40, the number of wiring layers, and the number of connectors are not limited to those in the embodiment.

[0030] 8 and 9 show a sixth embodiment of the present invention. The quantum device of the sixth embodiment has a feature that can be applied to any of the first to fifth embodiments described above, and has a common configuration with the first to fifth embodiments except for the parts where the configuration is particularly detailed. In other words, the quantum device of the sixth embodiment can be implemented in combination with any of the first to fifth embodiments. 8(a) and 8(b), the wiring component 20 is disposed in a recess 7 of a laminated substrate 40. The wiring component 20 and the laminated substrate 40 are manufactured based on a predetermined dimensional tolerance, which allows the wiring component 20 and the laminated substrate 40 to slide relative to each other and reduces thermal stress caused by the difference in thermal contraction due to the temperature difference between the low temperature required for superconductivity and the room temperature during manufacturing. Furthermore, in the sixth embodiment, as shown as chamfering example 1 in Fig. 9(a')(b'), which is an enlarged view of portion IX in Fig. 8, a sloping chamfer 40a is applied to a recessed corner of a laminated substrate 40A, which is a modified example of the laminated substrate 40. Also, a sloping chamfer C that is the same or slightly longer is applied to the corresponding corner of the wiring component 20. That is, by forming the chamfer C, the two components can slide and move relative to each other more easily than in a sharp corner without a chamfer, and thermal stress is not likely to concentrate in that portion, making it possible to prevent chipping due to stress concentration. In other words, by forming chamfer C, it is possible to prevent the portion from chipping due to thermal stress, as compared to a sharp corner portion without chamfer. In detail, due to the presence of the chamfer C, the angle between an outer corner between one outer surface of the wiring component 20 and another outer surface perpendicular to the one outer surface, and an inner corner between one inner surface of the laminated substrate 40 and the other inner surface perpendicular to the one inner surface, is an obtuse angle larger than the perpendicular angle, making relative movement easier than in the case where the angles are perpendicular, and making it possible to prevent chipping due to the thermal stress described above.

[0031] 9(a")(b"), which is an enlarged view of portion IX in FIG. 8, shows chamfering example 2, in which a curved chamfer 40b with a predetermined radius of curvature is applied to the recessed corner of laminated substrate 40B, which is a modified example of laminated substrate 40. Similarly, a curved chamfer R with the same or a slightly smaller radius of curvature is applied to the corner of the corresponding wiring component 20. In other words, by forming the chamfer R, the two components can slide relative to each other more easily than if the corner were left sharp without being chamfered, and stress due to thermal expansion is less likely to concentrate in that area, making it possible to prevent chipping of the substrate, etc. In detail, the presence of the chamfer R makes relative movement easier than when the angle between an outer corner between one outer surface of the wiring component 20 and another outer surface perpendicular to the one outer surface, and an inner corner between one inner surface of the laminated substrate 40 and another inner surface perpendicular to the one inner surface, a larger obtuse angle than the perpendicular angle, and prevents chipping due to the thermal stress. Note that a configuration may be adopted in which the laminated substrates 40A, 40B in the area between the dashed line B and the wiring components 20A, 20B in Figures 9(b') and (b") (the area indicated by a roughly triangular shape in the same figure) are removed to prevent contact between the wiring components 20A, 20B and the laminated substrates 40A, 40B. The processing for forming the chamfer C or the chamfer R described in the sixth embodiment, or the processing for removing the area indicated by the dotted line B, or processing similar thereto, to avoid chipping of the corners of the wiring components 20A, 20B due to relative movement with respect to the inner surface of the laminated substrates 40A, 40B, are referred to as relief processing portions.

[0032] FIG. 10 shows a seventh embodiment of the present invention. The quantum device of arrangement example 1 shown in Figure 10(a) has a configuration in which a wiring component 20 having a roughly similar square shape is arranged approximately at the center of a laminated substrate 40 having a square shape in a planar view, and further, a square-shaped quantum chip 10A having an outline slightly smaller than that of the wiring component 20 is arranged approximately at the center of the wiring component 20. 10(b), a quantum device of Arrangement Example 2 has a configuration in which a substantially similar square-shaped wiring component 20 is arranged substantially at the center of a laminated substrate 40 that is square in plan view, and two rectangular quantum chips 10B are arranged line-symmetrically on the wiring component 20. The rectangular quantum chip 10B has a shape obtained by dividing a similar square slightly smaller than the wiring component 20 into two.

[0033] As shown in layout examples 1 and 2 of the seventh embodiment, a single quantum chip 10A may be provided on one wiring component 20, or multiple quantum chips 10A may be provided. When multiple quantum chips 10B are provided as shown in Fig. 10(b), these quantum chips 10B may be connected to each other by the wiring layer of the wiring component 20, or may be individually connected to the laminated substrate 40. Furthermore, the number of wiring components 20 mounted on one laminated substrate 40, or the number of quantum chips 10A mounted on one wiring component 20, is of course not limited to layout examples 1 and 2 shown in Figs. 10(a) and 10(b).

[0034] FIG. 11 shows an eighth embodiment of the present invention. The quantum device of layout example 3 shown in Figure 11(a) has a configuration in which a wiring component 20A with a roughly similar square shape is arranged approximately in the center of a laminated substrate 40 that is square in a planar view, and further, a square-shaped quantum chip 10A with a slightly smaller outline than the wiring component 20A is arranged approximately in the center of the wiring component 20A (substantially the same configuration as layout example 1 shown in Figure 10(a)). The quantum device of arrangement example 4 shown in Figure 11(b) has a configuration in which a wiring component 20B with a roughly similar square shape is arranged in approximately the center of a laminated substrate 40 that is square in a planar view, as shown by the dashed line in the same figure, and further, a quantum chip 10C with a roughly similar square shape and outline that is slightly larger than wiring component 20B and smaller than laminated substrate 40 is arranged on top of wiring component 20B. In this layout example 4, a conductor serving as a connection portion is arranged only in a region of the quantum chip 10C that overlaps with the wiring component 20B in a plan view. The quantum device of arrangement example 5 shown in Figure 11 (c) has a configuration in which a wiring component 20A with a roughly similar square shape is arranged approximately in the center of a laminated substrate 40 that has a square shape when viewed from above, and further, a quantum chip 10A with an identical square shape to the wiring component 20A is arranged on top of the wiring component 20A, and the quantum chip 10A and the wiring component 20A are arranged so that they are partially overlapping each other. In this layout example 5, a conductor serving as a connection portion is arranged only in a region of the quantum chip 10A that overlaps with the wiring component 20A in a plan view.

[0035] FIG. 12 shows a ninth embodiment of the present invention. 12(a) has a configuration in which rectangular split wiring components 20a and 20b, which are obtained by dividing a substantially similar square into two, are disposed substantially at the center of laminated substrate 40, which has a square shape in a plan view, and wiring component 20C, which as a whole has a substantially similar square shape to laminated substrate 40, is mounted. Quantum chip 10A is mounted on wiring component 20C so as to straddle split wiring components 20a and 20b.

[0036] 12(b) has a configuration in which square-shaped divided wiring components 20c, 20d, 20e, and 20f, which are obtained by dividing the square of the device into four parts, are arranged approximately at the center of laminated substrate 40, which has a square shape in a plan view, and wiring component 20D, which has an approximately similar square shape as laminated substrate 40, is mounted on the entire device. Quantum chip 10A is mounted on wiring component 20D so as to straddle divided wiring components 20c, 20d, 20e, and 20f. The quantum device of division example 2 shown in Fig. 12(c) has a configuration in which rectangular split wiring components 20a and 20b, which are obtained by dividing a substantially similar square into two, are disposed in the substantially center of a laminated substrate 40 having a square shape in a plan view, and a wiring component 20C, which is generally similar to the laminated substrate 40, is mounted on the laminated substrate 40. A rectangular quantum chip 10B is mounted on the wiring component 20C so as to straddle the split wiring components 20a and 20b. The rectangular quantum chip 10B has a shape obtained by dividing a similar square, which is slightly smaller than the wiring component 20, into two.

[0037] In the above division examples 1, 2, and 3, split wiring components 20a, 20b, or split wiring components 20c, 20d, 20e, and 20f are used as wiring component 20C or 20D. Therefore, compared to the case in which the wiring components are integrated as in the other embodiments, relative movement can be performed between split wiring components 20a, 20b, or between split wiring components 20c, 20d, 20e, and 20f. This relative movement can reduce thermal stress accompanying temperature changes compared to the case of an integrated configuration. Furthermore, by forming the quantum chip 10B in a rectangular shape obtained by dividing a given square shape into two, the relative movement between them is possible, and the thermal stress can be reduced compared to when the quantum chip 10B is integrally formed.

[0038] The shapes, number of divisions, and layout in a plan view of the laminated substrate, wiring components, and quantum devices are not limited to the examples of layout and division.

[0039] Although an embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to this embodiment, and design modifications and the like are also included within the scope of the present invention that does not deviate from the gist of the present invention.

[0040] A part or all of the above-described embodiments can be described as in the following supplementary notes, but are not limited to the aspects specified in the supplementary notes. (Appendix 1) A quantum device utilizing a quantum state, A quantum device comprising: a quantum chip; a wiring component having a wiring layer; and a laminated substrate arranged so that at least the surface of the wiring component on which the quantum chip is mounted is exposed, wherein the wiring layer of the laminated substrate and the wiring layer of the wiring component are connected by an integral conductor pattern. (Appendix 2) The wiring component is embedded in a laminated substrate. 2. The quantum device of claim 1. (Appendix 3) 3. The quantum device of claim 2, further comprising a recessed portion at least in one of an outer corner between one outer surface of the wiring component and another outer surface intersecting with the one outer surface, and an inner corner between one inner surface of the laminated substrate and another inner surface intersecting with the one inner surface. (Appendix 4) The conductor pattern is constituted by a part of the conductor layer on the surface of the laminated substrate. 4. The quantum device according to claim 1, (Appendix 5) 5. The quantum device according to claim 1, wherein the wiring component has a plurality of the wiring layers. (Appendix 6) 6. The quantum device according to claim 1, wherein the wiring component is provided with a core material and a through via that penetrates the core material. (Appendix 7) The quantum device described in any one of appendix 1 to 6, characterized in that the wiring component is formed by a plurality of divided wiring components arranged on the laminated substrate, and the quantum chip is arranged across the divided wiring components. (Appendix 8) A plurality of the quantum chips are arranged on a single wiring component. 8. The quantum device according to any one of claims 1 to 7. (Appendix 9) 9. The quantum device according to any one of claims 1 to 8, wherein the quantum chip is disposed so as to overlap, in whole or in part, with the wiring component in a plan view. (Appendix 10) The quantum chip is arranged so as to overlap with a plurality of the wiring components in a plan view. 10. The quantum device according to any one of claims 1 to 9. (Appendix 11) The laminated substrate has a plurality of wiring layers. 11. The quantum device according to any one of claims 1 to 10. (Appendix 12) The insulating layer of the laminated substrate is made of an organic material. 12. The quantum device according to any one of claims 1 to 11. (Appendix 13) 13. The quantum device according to any one of claims 1 to 12, wherein the laminated substrate includes a connector. (Appendix 14) the laminated substrate includes a plurality of connectors, some of which are connected to some circuits of the wiring component, and other connectors are connected to other circuits of the wiring component; 14. The quantum device of claim 13. (Appendix 15) A method for manufacturing a quantum device comprising: a quantum chip; a wiring component having a wiring layer; and a laminated substrate disposed so that at least a surface of the wiring component on which the quantum chip is mounted is exposed, the method comprising the steps of: embedding the wiring component in a recess of the laminated substrate; a step of connecting the laminated substrate and a wiring component by an integral conductor pattern; A method for manufacturing a quantum device comprising the steps of: [Industrial Applicability]

[0041] The present invention can be used in quantum device apparatus and the manufacture thereof. [Explanation of symbols]

[0042] 1. Quantum chip 2 wiring layers 3 Wiring components 4. Laminated substrate 5 wiring layer 6 Conductor Pattern 7 Recess 10. Quantum Chip 11 Substrate 12 wiring layer 20, 20A, 20B Wiring parts 21, 22, 24, 25 wiring layer 26, 27 Connection 28 Adhesive layer 29 Underfill section 30 Bump 40, 40A, 40B, 40C, 40D Laminated Board 41 First board 42 Second board 43, 44, 45 wiring layer 46, 47 Insulating layer 48 1st Layer Via 49 2nd Layer Via 50, 50A, 50B Connectors 60 Fillet 61 Wiring layer C Chamfer R chamfer

Claims

1. A quantum device utilizing a quantum state, A quantum device comprising: a quantum chip; a wiring component having a wiring layer; and a laminated substrate arranged so that at least the surface of the wiring component on which the quantum chip is mounted is exposed, wherein the wiring layer of the laminated substrate and the wiring layer of the wiring component are connected by an integral conductor pattern.

2. The wiring component is embedded in a laminated substrate. The quantum device of claim 1 .

3. 3. The quantum device of claim 2, further comprising a recessed portion at least in one of an outer corner between one outer surface of the wiring component and another outer surface intersecting with the one outer surface, and an inner corner between one inner surface of the laminated substrate and another inner surface intersecting with the one inner surface.

4. The conductor pattern is constituted by a part of the conductor layer on the surface of the laminated substrate. The quantum device of claim 1 .

5. The quantum device according to claim 1 , wherein the wiring component has a plurality of the wiring layers.

6. The wiring component is provided with a core material and a through via that penetrates the core material. The quantum device of claim 1 .

7. The wiring component is formed by a plurality of divided wiring components arranged on the laminated substrate, and the quantum chip is arranged across the divided wiring components. The quantum device of claim 1 .

8. A method for manufacturing a quantum device comprising: a quantum chip; a wiring component having a wiring layer; and a laminated substrate disposed so that at least a surface of the wiring component on which the quantum chip is mounted is exposed, the method comprising the steps of: embedding the wiring component in a recess of the laminated substrate; a step of connecting the laminated substrate and a wiring component by an integral conductor pattern; A method for manufacturing a quantum device comprising the steps of:

Images